A high current density triode and a method of manufacturing the same

Abstract

The application discloses a high-current-density triode and a preparation method thereof in the field of semiconductor devices. The main steps of the preparation method are as follows: after a collector region and part of a base region are epitaxially grown on a silicon carbide substrate in sequence, a pulsed laser deposition technology is used to form an aluminum gallium nitride zinc oxide core-shell heterostructure doped enhancement layer on the surface of the base region; after the growth of the base region is completed, an atomic layer deposition technology is used to generate an hafnium-zirconium co-doped barium strontium titanate interface passivation layer on the surface of the base region in situ; then, an emitter region is epitaxially grown and electrodes are made. The core-shell doped enhancement material is prepared by metal organic chemical vapor deposition to prepare an aluminum gallium nitride nanorod array core, and then a magnesium-silicon co-doped zinc oxide shell layer is coated on the surface of the core through a coprecipitation and high-temperature annealing process under a specific atmosphere. By introducing the inorganic functional layer, the application cooperatively optimizes carrier injection and transmission, so that the current density, working frequency and stability of the triode are significantly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to a high current density transistor and its fabrication method. Background Technology

[0002] As a core component of modern electronics, the continuous improvement of bipolar junction transistors (BJTs) performance is crucial for driving the development of fields such as high-frequency communication, high-speed computing, and power management. Current density is one of the core indicators for measuring transistor performance; higher current density means greater current drive capability within a smaller device size, thus contributing to improved integration density, switching speed, and power handling capabilities of integrated circuits. As the feature size of semiconductor devices continues to shrink, the physical limitations of traditional silicon-based materials in terms of carrier mobility and saturation velocity are becoming increasingly apparent, making it difficult to meet the requirements of next-generation electronic systems for extremely high operating frequencies and power densities. Therefore, industry and academia have turned their attention to compound semiconductor materials such as gallium arsenide (GaAs) and gallium nitride (GaN). While these materials possess excellent electronic properties, they still face many challenges in the actual fabrication of high-performance transistors, especially bipolar junction devices requiring high current injection. How to significantly improve the current density of devices without sacrificing other performance characteristics has become a crucial issue that urgently needs to be addressed in the field of semiconductor devices.

[0003] Currently, the mainstream technological approaches to achieving high current density mainly focus on two aspects: the introduction of new material systems and the optimization of device structures. On the one hand, by using narrow bandgap compound semiconductor materials with higher electron mobility, or by employing high-concentration doping or even superlattice structures in the channel, attempts are made to directly increase the concentration of carriers capable of conducting electricity. On the other hand, by finely designing the band structure of the emitter and base regions, such as by using graded composition or doping distribution, the carrier injection barrier is reduced. However, these traditional methods all have significant limitations. Simply increasing the doping concentration can lead to intensified carrier impurity scattering, which may actually decrease mobility and increase device capacitance, degrading high-frequency performance. Furthermore, complex bandgap engineering designs place almost stringent demands on the control precision of epitaxial growth, resulting in narrow process windows, high manufacturing costs, and difficulty in guaranteeing yield. More fundamentally, none of the above methods have effectively addressed the inherent defects present at the semiconductor material interfaces. At the heterojunction interface, lattice mismatch and chemical bond interruption introduce a large number of interface states. These interface states act as traps for charge carriers, severely hindering the efficient injection of charge carriers from the emitter region to the base region, which is a fundamental bottleneck limiting the improvement of current density. In addition, the presence of base resistance also weakens the effective driving voltage and generates unnecessary heat dissipation. Therefore, existing technologies often fall into a dilemma of trade-offs, making it difficult to achieve an ideal balance between current density, frequency characteristics, and process feasibility.

[0004] To fundamentally overcome the aforementioned bottlenecks, recent research trends indicate that innovating at the materials level—designing and fabricating novel thin-film materials with specific electrical functions—and integrating them as functional interface layers into traditional device structures, is a highly promising approach. These functional layers are not part of the active region, but rather actively modulate the interface band structure, defect state density, or carrier transport environment through their unique physicochemical properties. For example, materials with high dielectric constants can be used to shield interface charge scattering; while wide-bandgap materials with appropriate bandgap arrangements can be used to passivate interface dangling bonds. However, developing such functional materials faces significant challenges: they must be fully compatible with mainstream semiconductor processes, maintain structural and chemical stability during subsequent high-temperature epitaxy steps, and precisely control their electrical parameters (such as dielectric constant, defect density, and bandgap) to achieve the desired modulation effect. Currently, there is a lack of material systems and integration schemes that can simultaneously meet these stringent requirements and be specifically designed to address the specific physical problems in high-current-density transistors (i.e., the synergistic achievement of high injection efficiency and low base resistance). This leaves a clear technological gap and room for innovation for the proposal of this invention. Summary of the Invention

[0005] The purpose of this invention is to provide a high current density transistor and its fabrication method, which solves the interconnected technical problems encountered by existing bipolar junction transistors, especially compound semiconductor-based devices, in pursuing high current density, such as low carrier injection efficiency, large base region transport loss, and numerous heterojunction defects.

[0006] The present invention achieves the above objectives through the following technical solutions: A method for fabricating a high current density transistor, comprising the following steps: S1. Perform standard RCA cleaning and drying on the silicon carbide substrate; use metal-organic chemical vapor deposition to epitaxially grow an n+ type GaAs buffer layer and an n-type GaAs collector region on the substrate; use molecular beam epitaxy to epitaxially grow a p-type GaAs base region on the surface of the collector region; use pulsed laser deposition technology at a temperature of 500-600℃ to deposit aluminum gallium nitride-zinc oxide core-shell heterostructure doped reinforcement material on the surface of the p-type GaAs base region to form a base region doped reinforcement layer; S2. The remaining p-type GaAs base region is grown by molecular beam epitaxy. On the surface of the completed base region, atomic layer deposition is used with tetra(dimethylamino)hafnium, tetra(dimethylamino)zirconium, bis(cyclopentadienyl)barium, bis(cyclopentadienyl)strontium, and deionized water as precursors. Cyclic deposition is carried out at 295-305℃ to generate a hafnium-zirconium co-doped barium strontium titanate interface passivation layer in situ. Then, an n-type InGaP emitter region is epitaxially grown on the passivation layer by metal-organic chemical vapor deposition. The mesa is defined by photolithography and dry etching processes. The metal ohmic contact electrodes of the collector, base, and emitter are sequentially fabricated by electron beam evaporation and lift-off processes.

[0007] In this invention, the core of the high current density transistor fabrication mechanism lies in the precise integration of a core-shell heterostructure doped enhancement material and a hafnium-zirconium co-doped barium strontium titanate interface passivation material into key positions of a compound semiconductor bipolar junction transistor through a series of sequential thin-film deposition and micro / nano fabrication techniques. This reconstructs the carrier injection and transport paths of the device at the atomic and band level. The entire process begins with standard cleaning and epitaxial growth of the silicon carbide substrate. Cleaning removes surface contaminants and the native oxide layer, providing an atomically clean surface for high-quality epitaxy. First, a gallium arsenide buffer layer and collector region are grown using metal-organic chemical vapor deposition. The reaction mechanism involves the thermal decomposition and gas-phase chemical reaction of group III metal-organic compounds (such as trimethylgallium) and group V hydrides (such as arsine) on the high-temperature substrate surface, generating gallium arsenide, which is then epitaxially grown. Subsequently, a first thin base layer is grown using molecular beam epitaxy (MBE). This technique involves directly spraying a beam of atoms or molecules of gallium, arsenic, and carbon dopants (for p-type) onto a heated substrate surface in an ultra-high vacuum, achieving layer-by-layer epitaxial growth of single atoms and yielding extremely steep doping interfaces and high-quality crystals. Next, pulsed laser deposition (PLD) is used to deposit pre-synthesized core-shell heterostructure doped reinforcement nanoparticles onto the surface of this thin base layer. The mechanism involves using a high-energy pulsed laser to ablate the target material, causing it to instantly vaporize and ionize, forming a high-temperature, high-pressure plume plasma. This plasma expands forward and deposits as a film on the heated substrate surface. By precisely controlling the laser energy density and substrate temperature, it is possible to ensure that the nanoparticles spread on the substrate to form a continuous, dense, and ultrathin functional layer that maintains a certain orientation with the underlying semiconductor lattice without damaging the core-shell nanostructure. After this layer is embedded in the base region, the built-in polarization field and band modulation generated by the core-shell heterojunction and the internal "acceptor-donor pair" doping actively optimize the distribution and diffusion behavior of minority carriers in the base region. Subsequently, the remaining base region was grown again using molecular beam epitaxy, encapsulating the doped reinforcement layer within the base region near the collector junction. On the intact base region surface, a hafnium-zirconium co-doped barium strontium titanate interface passivation layer was grown using atomic layer deposition. This is a chemical process based on sequential self-confined surface reactions: organometallic precursor vapors of hafnium, zirconium, barium, and strontium, along with deionized water vapor, are cyclically introduced. Each precursor reaches saturation after reacting with hydroxyl groups on the substrate surface or the previous layer. Excess precursor is removed by purging with an inert gas before introducing the next reactant. This cyclic process allows for precise control of the film's chemical composition, thickness, and uniformity at the atomic scale. At the set reaction temperature, precursor molecules undergo chemical adsorption and decomposition reactions on the base region surface, gradually constructing a hafnium-zirconium co-doped barium strontium titanate film with a perovskite crystal structure. The synergistic doping of hafnium and zirconium ions effectively suppresses the formation of oxygen vacancies in the barium strontium titanate lattice, thereby significantly reducing the charge trap density in the film. This ultrathin high dielectric constant layer serves as an interface layer during subsequent emitter region epitaxy, effectively passivating interface states and reducing the carrier injection barrier.Subsequently, indium gallium phosphide (IGLP) emitter regions were epitaxially grown on top using metal-organic chemical vapor deposition (MOCVD). Despite the presence of an interface passivation layer, under suitable growth temperature and initial layer conditions, IGLP could still undergo three-dimensional island-like nucleation on top and eventually fuse into a continuous single-crystal thin film, forming a high-quality heterojunction. Subsequent photolithography and dry etching processes defined the surface structure through physicochemical means, achieving electrical isolation of the device. The final electron beam evaporation and stripping process involved heating and evaporating or sublimating metals such as gold, germanium, nickel, and zinc in a vacuum environment, causing their atoms to deposit on the semiconductor surface within the patterned window defined by the photoresist. After alloying heat treatment, low-resistance ohmic contact electrodes were formed. Through precise connection and reaction control of each step, the entire fabrication process ultimately constructed a transistor that integrated novel functional materials at key interfaces and regions. Its unique structure fundamentally improved carrier injection efficiency, reduced base transport losses, and enhanced interface stability, thereby achieving a leap in device current density and overall electrical performance.

[0008] According to a preferred embodiment of the present invention, in step S1, the thickness of the base region doped enhancement layer is 2-8 nm; the laser energy density used for pulsed laser deposition is 1.5-3.0 J / cm². 2 .

[0009] According to a preferred embodiment of the present invention, in step S2, the thickness of the interface passivation layer is 5-15 nm.

[0010] According to a preferred embodiment of the present invention, the preparation method of the aluminum gallium nitride-zinc oxide core-shell heterostructure doped reinforcement material includes: A1. Using trimethylgallium, trimethylaluminum, and ammonia as precursors, Al was grown on a sapphire substrate via metal-organic chemical vapor deposition. 0.25 Ga 0.75 N nanorod arrays; A2, the growing Al 0.25 Ga 0.75 An AlGaN nanorod array is immersed in hydrochloric acid and ultrasonically treated at 40-60°C to peel it off from the substrate, thus obtaining AlGaN nanorods; the AlGaN nanorods are then dispersed in ethylene glycol to obtain an AlGaN nanorod suspension. A3. Under continuous stirring and nitrogen protection, zinc acetate hexahydrate, magnesium acetate tetrahydrate and aminopropyltriethoxysilane were added sequentially to the AlGaN nanorod suspension; at the same time, an alkaline complexing solution composed of tetramethylammonium hydroxide, deionized water and ethylene glycol was added dropwise, and the reaction was carried out at 78-82℃. A4. After the reaction is complete, the product is collected by centrifugation, washed alternately with deionized water and ethanol, and finally dried under vacuum at 78-82℃ to obtain dried powder; the dried powder is annealed at 500-650℃ under an argon-oxygen mixed atmosphere.

[0011] In this invention, the preparation of the aluminum gallium nitride-zinc oxide core-shell heterostructure doped reinforcement material is a multi-step, precisely controllable chemical process. Its core mechanism lies in the controlled co-precipitation and hydrothermal reaction on a pre-fabricated one-dimensional aluminum gallium nitride nanostructure to epitaxially grow a magnesium and silicon co-doped zinc oxide shell, ultimately forming a core-shell nanoheterojunction with a unique band structure and doping distribution. First, an aluminum gallium nitride nanorod array is grown at high temperature using metal-organic chemical vapor deposition. This process involves the thermal decomposition of trimethylgallium and trimethylaluminum in a hydrogen carrier gas to produce gallium and aluminum atoms, which react with nitrogen atoms produced by the decomposition of simultaneously introduced ammonia gas. These atoms preferentially grow along a specific crystal orientation on a sapphire substrate, forming single-crystal nanorods with high crystal quality and uniform size. Subsequently, the nanorods were completely separated from the heterogeneous substrate by immersion in hydrochloric acid solution and thermal ultrasonic treatment. This process utilized the selective etching of the weakening layer at the substrate-nanorobot interface by hydrochloric acid and the physical exfoliation force generated by ultrasonic cavitation to obtain dispersed nanorods. This process also cleaned the nanorod surface, providing an active interface for subsequent coating reactions. The key shell growth step employed a co-precipitation method based on an alkaline complexing solution. A suspension of aluminum gallium nitride nanorods dispersed in ethylene glycol was mixed with zinc, magnesium, and silicon source precursors. Under continuous stirring and an inert atmosphere, a special alkaline solution prepared from tetramethylammonium hydroxide, deionized water, and ethylene glycol was slowly added dropwise. The alkaline solution acts as both a co-precipitant and a reaction medium, with a multi-faceted mechanism: tetramethylammonium hydroxide provides a stable, strongly alkaline environment, promoting the simultaneous hydrolysis of zinc acetate, magnesium acetate, and aminopropyltriethoxysilane to generate the corresponding metal hydroxides and silanol species; ethylene glycol, as a high-boiling-point solvent and a mild reducing agent, controls the reaction rate and prevents excessive particle aggregation; water molecules participate in the hydrolysis process. Under heating conditions, these hydrolysis products undergo adsorption, condensation, and dehydration reactions on the surface of aluminum gallium nitride nanorods, uniformly depositing an amorphous or microcrystalline zinc-magnesium-silicon composite hydroxide precursor shell through a heterogeneous nucleation mechanism. The siloxane species generated after the hydrolysis of aminopropyltriethoxysilane are effectively integrated into the growing shell matrix through the possible coordination of their terminal amino groups with the nanorod surface and metal ions, rather than forming a separate silica phase. This is crucial for achieving effective silicon doping. Finally, a medium-to-high temperature annealing process is performed in an argon-oxygen mixed atmosphere with precisely controlled oxygen partial pressure. This heat treatment process induces the complete decomposition, crystallization, and densification of the precursor shell. Driven by heat, the composite hydroxide is transformed into crystalline zinc oxide. Magnesium and silicon ions diffuse into the zinc oxide lattice, replacing some zinc ion lattice sites, and co-doping as acceptor and donor impurities, respectively, forming a semiconductor shell with a unique "acceptor-donor pair" doping mode. Simultaneously, the weakly oxidizing atmosphere effectively suppresses the generation of excessive intrinsic donor oxygen vacancies in the zinc oxide crystal due to oxygen deficiency, thereby ensuring that the doping effects of magnesium and silicon dominate and precisely controlling the Fermi level and conductivity characteristics of the shell.The annealing process also promotes the interdiffusion and chemical bonding of atoms at the core-shell interface, enhances the interfacial bonding force and carrier transport capacity, and ultimately yields a structurally stable core-shell heterogeneous nanomaterial with controllable doping.

[0012] According to a preferred embodiment of the present invention, in step A1, the growth temperature is 1095-1105℃ and the growth time is 30-40min.

[0013] According to a preferred embodiment of the present invention, in step A2, the ultrasonic treatment at 40-60°C is carried out for 30-60 minutes; the concentration of the hydrochloric acid is 1-3 mol / L.

[0014] According to a preferred embodiment of the present invention, in step A3, the reaction time at 78-82°C is 4-6 hours; the volume ratio of tetramethylammonium hydroxide, deionized water and ethylene glycol is 1:(1-2):(15-20).

[0015] According to a preferred embodiment of the present invention, in step A4, the annealing time at 500-650°C is 2-4 hours; the volume fraction of oxygen in the argon-oxygen mixed atmosphere is 3-5%.

[0016] The present invention also provides a high current density transistor prepared according to the above-described high current density transistor preparation method.

[0017] The beneficial effects of this invention are as follows: The high current density transistor and its fabrication method provided by this invention achieve a significant, multi-dimensional, and synergistic improvement in device performance by introducing two novel inorganic functional layers. The most significant effect is the breakthrough enhancement in current driving capability. Due to the integration of an aluminum gallium zinc oxide functional layer with a unique core-shell heterostructure and acceptor-donor pair co-doping in the base region, this layer effectively modulates the carrier distribution and transport environment within the base region, significantly reducing the scattering resistance encountered by minority carriers during transit in the base region, thereby greatly improving the base region transport factor. Simultaneously, the hafnium zirconium co-doped barium strontium titanate passivation layer grown in situ at the critical emitter-base region interface, with its extremely low interface state density and high dielectric properties, perfectly passivates interface defects, eliminates carrier traps, and efficiently shields the Coulomb scattering barrier, making the carrier injection process from the emitter region to the base region extremely smooth. The synergistic effect of these two layers of materials fundamentally optimizes the entire path of charge carriers from injection to collection, enabling the device to obtain a collector current much higher than that of traditional structures under the same bias voltage, achieving an order-of-magnitude increase in current density while maintaining an excellent current amplification factor.

[0018] Building upon the achievement of ultra-high current density, the high-frequency and power characteristics of the device in this invention are also significantly improved. The introduction of the interface passivation layer greatly reduces the parasitic capacitance of the emitter junction, while the base-doped enhancement layer optimizes the base resistance. Together, these two factors significantly shorten the carrier transit time and the circuit's charge-discharge time constant, thereby greatly increasing the device's cutoff frequency and maximum oscillation frequency, enabling it to handle higher-frequency amplification and switching applications. Furthermore, this performance improvement does not come at the expense of the device's thermal stability and power tolerance. Due to the excellent thermal stability and chemical inertness of the two functional layer materials, they maintain structural integrity and performance stability during subsequent high-temperature processes and long-term device operation. In particular, the strong suppression of oxygen vacancies in the interface passivation layer and the stress buffering effect of the core-shell structure jointly ensure that the device's key electrical parameters, such as current gain and turn-on voltage, do not drift significantly under harsh operating conditions such as high temperature and high current density. The reliability far exceeds that of conventional structure devices, laying a solid foundation for stable operation in high-power applications.

[0019] From the perspective of fabrication process and industrialization, the technical effects brought about by this invention are equally outstanding, demonstrating excellent feasibility and compatibility. The key technologies employed in the entire fabrication process, such as metal-organic chemical vapor deposition, molecular beam epitaxy, pulsed laser deposition, and atomic layer deposition, are all mature and mainstream processes in the semiconductor industry. This means that the innovative structure can be smoothly integrated into existing compound semiconductor production lines without disruptive equipment investment or process development. Particularly important is that the novel inorganic compounds constituting the two functional layers are synthesized entirely from commercially available high-purity chemicals, ensuring stable and reliable sources and controllable costs. The fabrication methods, whether it's the co-precipitation self-assembly of nano-core-shell structures or the in-situ atomic layer deposition of perovskite oxide films, all possess clear reaction pathways, well-defined process windows, and good reproducibility. This provides a solid process foundation for the patented technology to move from the laboratory to large-scale mass production. In summary, this invention not only achieves a triple leap in device performance in terms of current density, frequency, and reliability, but also ensures the feasibility and economy of the technology at the manufacturing level, possessing extremely high practical value and broad industrialization prospects. Detailed Implementation

[0020] The following detailed embodiments are only used to further illustrate this application and should not be construed as limiting the scope of protection of this application. Those skilled in the art can make some non-essential improvements and adjustments to this application based on the above application content.

[0021] Example 1 The preparation steps of aluminum gallium nitride-zinc oxide core-shell heterostructure doped reinforced materials are as follows: First, a 100mm diameter c-plane sapphire substrate was prepared and cleaned sequentially in an ultrasonic cleaner with acetone, isopropanol, and deionized water for 10 minutes each, followed by drying with high-purity nitrogen. The cleaned substrate was then placed into the reaction chamber of a metal-organic chemical vapor deposition (MOCVD) system. The trimethylgallium (TMG) source bottle was maintained at -10.0℃, and the trimethylaluminum (TMA) source bottle at 15.0℃. The reaction chamber pressure was set to 10.0 kPa, and the total hydrogen carrier gas flow rate was 10.0 SLM. The substrate was heated to 1100℃ and stabilized for 5 minutes. Then, trimethylgallium vapor (2.500 g) was introduced at a flow rate of 100 sccm; trimethylaluminum vapor (0.830 g) was introduced at a flow rate of 33 sccm; and high-purity ammonia was introduced simultaneously at a flow rate of 5000 sccm. Growth was carried out under these conditions for 35 minutes. After growth, the substrate was cooled to below 300℃ in an ammonia atmosphere and removed to obtain Al. 0.25 Ga 0.75AlGaN nanorod arrays were then grown on a substrate. The substrate with the nanorod array was immersed in 200 mL of 2.0 mol / L hydrochloric acid solution, and the solution was placed in a 50°C water bath and treated with a 300W ultrasonic processor for 45 min. After treatment, the upper suspension containing AlGaN nanorods was carefully aspirated with a pipette, and the precipitate was collected by centrifugation at 8000 rpm for 10 min, which was the AlGaN nanorods. The obtained nanorods were redispersed in 200 mL of ethylene glycol and stirred with a magnetic stirrer at 500 rpm for 30 min to form a homogeneous suspension. The entire suspension was then added to a three-necked flask equipped with a reflux condenser, a constant-pressure dropping funnel, and a nitrogen inlet. Under continuous nitrogen protection (flow rate 50 mL / min) and magnetic stirring at 300 rpm, 5.500 g of zinc acetate hexahydrate, 0.220 g of magnesium acetate tetrahydrate, and 0.150 g of aminopropyltriethoxysilane were added sequentially to a flask. Then, 20.0 mL of a 25% aqueous solution of tetramethylammonium hydroxide, 30.0 mL of deionized water, and 360.0 mL of ethylene glycol were mixed thoroughly in a beaker to prepare a coprecipitant. Using a constant-pressure dropping funnel, this coprecipitant was added dropwise to the reaction system at a constant rate of 1.50 mL / min for a total adding time of 4.0 h. After the addition was complete, the oil bath temperature of the reaction system was maintained at 80.0 °C, and the reaction was stirred for another 5.0 h. After the reaction was complete, the mixture was allowed to cool naturally to room temperature. The reaction product was transferred to a centrifuge tube and centrifuged at 10,000 rpm for 5 min, discarding the supernatant. The precipitate was washed three times with 50 mL of deionized water and twice with 50 mL of anhydrous ethanol, centrifuged under the same conditions after each wash. The resulting precipitate was transferred to a petri dish and placed in a vacuum drying oven at 80.0 °C and -0.1 MPa for 12 h to obtain the dried precursor powder. Finally, the precursor powder was evenly spread in an alumina ceramic boat and placed in the center of a tube furnace. A mixture of argon and oxygen (96:4 volume ratio) was introduced at a total flow rate of 2.0 L / min. The furnace temperature was increased from room temperature to 575 °C at a rate of 5.0 °C / min and maintained at this temperature for 3.0 h for annealing. After annealing, the heating power was turned off, and the sample was allowed to cool to below 80 °C in the continuously introduced mixed atmosphere before being removed, yielding the final aluminum gallium nitride-zinc oxide core-shell heterostructure doped reinforced material powder.

[0022] The fabrication steps for the high current density transistor are as follows: An n-type 4H-SiC substrate with a diameter of 100 mm and a resistivity of 0.02 Ω·cm is taken, cleaned and dried using a standard RCA process. It is then placed in a metal-organic chemical vapor deposition (MOCVD) system, and a 100 nm thick n+ type GaAs buffer layer is epitaxially grown at a growth rate of 1.0 μm / h under a pressure of 10.0 kPa and a temperature of 610 °C. The silane dopant flow rate is set to achieve a carrier concentration of 1 × 10⁻⁶. 19 cm -3 Subsequently, under the same pressure, the temperature was lowered to 580℃, and a 500nm thick n-type GaAs collector region was epitaxially grown at a growth rate of 1.5μm / h. The silane flow rate was adjusted to achieve a carrier concentration of 5×10⁻⁶. 16 cm -3 The sample was removed from the equipment and transferred to the molecular beam epitaxy (MBE) apparatus. The sample was heated to 580°C, with an arsenic beam pressure of 1.0 × 10⁻⁶. -5 Under Pa conditions, the gallium source furnace and carbon-doped source furnace were turned on, and a 15 nm thick p-type GaAs layer was epitaxially grown at a growth rate of 0.3 μm / h, with the carbon doping concentration controlled at 1 × 10⁻⁶. 19 cm -3 This layer serves as the initial base region. The sample is removed and transferred to a pulsed laser deposition apparatus. The previously prepared doped reinforcing material powder is pressed into a target with a diameter of 25.4 mm under a pressure of 300 MPa and mounted on the target stage. The sample is fixed on the heating stage, and the cavity vacuum is evacuated to 5.0 × 10⁻⁶. -5 Pa, then high-purity oxygen was introduced until the pressure reached 10.0 Pa. The sample stage temperature was raised to 550℃ and stabilized. A KrF excimer laser (wavelength 248 nm) was used, and the laser energy density was set to 2.2 J / cm². 2The pulse repetition frequency was 10 Hz, and the focused spot irradiated the rotating target. Deposition was stopped after 3000 pulses, forming a base region doped enhancement layer of approximately 5 nm thick on the surface of the initial p-type GaAs base region. The sample was then moved back into the molecular beam epitaxy (MBE) apparatus, and under the exact same growth conditions, an 85 nm thick p-type GaAs layer was grown epitaxially, bringing the total thickness of the entire p-type base region to 100 nm. After the base region growth was completed, the sample was placed in an atomic layer deposition (ALD) apparatus. The reaction chamber temperature was set to 300 °C. The temperatures of the tetradimethylaminohafnium precursor tank were set to 75 °C, the tetradimethylaminozirconium precursor tank to 75 °C, the dicyclopentadienylbarium precursor tank to 180 °C, the dicyclopentadienylstrontium precursor tank to 180 °C, and the water precursor tank to 20 °C. A deposition supercycle was defined as follows: a pulsed introduction of tetradimethylaminohafnium vapor into the cavity for 0.1 s, followed by purging with high-purity nitrogen for 10 s; a pulsed introduction of tetradimethylaminozirconium vapor for 0.1 s, followed by purging with nitrogen for 10 s; a pulsed introduction of dicyclopentadienylbarium vapor for 0.2 s, followed by purging with nitrogen for 15 s; a pulsed introduction of dicyclopentadienylstrontium vapor for 0.2 s, followed by purging with nitrogen for 15 s; and finally, a pulsed introduction of water vapor for 0.1 s, followed by purging with nitrogen for 20 s. This supercycle was repeated 150 times to grow a hafnium-zirconium co-doped barium strontium titanate interface passivation layer with a thickness of approximately 10 nm on the surface of the p-type GaAs substrate. The sample was then loaded into the metal-organic chemical vapor deposition apparatus for the third time. Under reaction pressure of 10.0 kPa and temperature of 600 °C, a 150 nm thick n-type InGaP emitter region was epitaxially grown on the passivation layer using trimethylindium, trimethylgallium, and phosphine as sources at a growth rate of 1.0 μm / h. Silane was used for doping to achieve a carrier concentration of 5 × 10⁻⁶. -19 cm -3 Following this, photolithography and etching were performed: positive photoresist was spin-coated onto the sample surface, and a stepper lithography machine was used to expose and define the stage pattern. After development, a photoresist mask was obtained. Inductively coupled plasma dry etching was used in a chlorine and argon gas mixture to sequentially etch the InGaP emitter region, the interface passivation layer, and the GaAs base region until the collector region was exposed, forming an isolation mesa. Residual photoresist was then removed using a stripper. Finally, electrode fabrication was performed: photoresist was spin-coated again onto the sample surface, and photolithography was used to define the electrode windows for the collector, base, and emitter. The sample was placed in an electron beam evaporation apparatus under a vacuum better than 5.0 × 10⁻⁶. -4Under the conditions of Pa, a 15 nm thick gold-germanium alloy, a 30 nm thick nickel layer, and a 200 nm thick gold layer were sequentially evaporated and deposited in the collector and emitter windows. In the base window, a 15 nm thick gold-zinc alloy, a 30 nm thick nickel layer, and a 200 nm thick gold layer were sequentially evaporated and deposited. After deposition, the sample was immersed in a special stripping solution, and the photoresist and excess metal on top were removed using ultrasonic assistance to form the metal electrode pattern. Finally, the device was rapidly annealed at 400 °C in a nitrogen atmosphere for 60 s to complete the ohmic contact alloying, ultimately yielding a high current density transistor.

[0023] Example 2 The specific implementation method is the same as in Example 1, except that the preparation steps of the aluminum gallium nitride-zinc oxide core-shell heterostructure doped reinforcement material are as follows: Prepare a c-plane sapphire substrate, clean and dry it, and then place it into the MOCVD reaction chamber. Maintain the trimethylgallium source bottle at -10.0℃ and the trimethylaluminum source bottle at 15.0℃. Set the reaction chamber pressure to 9.8 kPa and the total hydrogen carrier gas flow rate to 9.8 SLM. Heat the substrate to 1102℃ and stabilize for 5 min. Introduce trimethylgallium at a flow rate of 95 sccm (corresponding to a mass of 2.375 g); introduce trimethylaluminum at a flow rate of 31 sccm (corresponding to a mass of 0.794 g); and simultaneously introduce high-purity ammonia at a flow rate of 4900 sccm. After growth for 32 min, cool under an ammonia atmosphere to obtain Al. 0.25 Ga 0.75 AlGaN nanorod arrays were immersed in 190 mL of 1.8 mol / L hydrochloric acid and placed in a 45°C water bath for 38 min of ultrasonic treatment at 300 W. The supernatant was collected and centrifuged at 8000 rpm for 10 min to obtain AlGaN nanorod precipitate. The nanorods were dispersed in 190 mL of ethylene glycol and stirred for 30 min to form a suspension. Under nitrogen protection and stirring at 300 rpm, 5.000 g of zinc acetate hexahydrate, 0.200 g of magnesium acetate tetrahydrate, and 0.135 g of aminopropyltriethoxysilane were added sequentially to the suspension. The coprecipitant was prepared by mixing 15.0 mL of 25% tetramethylammonium hydroxide aqueous solution, 15.0 mL of deionized water, and 240.0 mL of ethylene glycol, and added dropwise at a rate of 1.20 mL / min for a total adding time of 3.75 h. After the addition was complete, the reaction system was maintained at 79.0°C and the reaction was stirred for another 4.5 h. After the reaction was completed and cooled, the precipitate was centrifuged and washed with deionized water and ethanol, respectively. The precipitate was then vacuum dried at 80.0℃ and -0.1MPa for 12 h. The precursor powder was placed in a tube furnace, and a mixture of argon and oxygen in a volume ratio of 96.5:3.5 was introduced at a total flow rate of 2.0 L / min. The temperature was increased to 520℃ at a rate of 4.0℃ / min, and annealed for 2.5 h. The furnace was then cooled to obtain the final powder.

[0024] The fabrication steps for the high current density transistor are as follows: An n-type 4H-SiC substrate is taken, cleaned and dried using RCA. A 100 nm thick n+ type GaAs buffer layer (doping concentration 1×10⁻⁶) is grown in an MOCVD apparatus at 9.8 kPa pressure and 605 °C. 19 cm -3 Subsequently, a 500 nm thick n-type GaAs collector region (doping concentration 5 × 10⁻⁶) was grown at 580 °C. 16 cm -3 Transferred to the MBE equipment, at 580℃ and an arsenic pressure of 1.0 × 10⁻⁶. -5 Under Pa, a 12 nm thick initial base region of p-type GaAs was grown (carbon doping concentration 1 × 10⁻⁶). 19 cm -3 The sample was removed and, in a PLD device, heated under a vacuum of 5.0 × 10⁻⁶. -5 Under conditions of Pa, oxygen pressure of 9.0 Pa, and sample stage temperature of 530℃, a laser energy density of 1.8 J / cm² was used. 2 At a frequency of 10 Hz, 2500 pulses were deposited to form a base region doped enhancement layer approximately 3 nm thick. The process was then repeated in MBE under the same conditions to grow an 88 nm thick p-type GaAs layer, resulting in a total base region thickness of 100 nm. In an ALD apparatus, with the chamber temperature set at 298 °C, using the same precursor and pulse sequence as in Example 1, a supercycle was repeated 120 times to grow an interface passivation layer approximately 7 nm thick. In an MOCVD apparatus, at a pressure of 9.8 kPa and a temperature of 598 °C, a 120 nm thick n-type InGaP emitter region (silicon doping concentration 5 × 10⁻⁶) was grown. 19 cm -3 The subsequent photolithography and dry etching were used to define the mesa, and gold-germanium-nickel-gold n-type electrodes and gold-zinc-nickel-gold p-type electrodes with the same structure as in Example 1 were fabricated using electron beam evaporation and lift-off processes. Finally, alloying annealing was performed to complete the device fabrication.

[0025] Example 3 The specific implementation method is the same as in Example 1, except that the preparation steps of the aluminum gallium nitride-zinc oxide core-shell heterostructure doped reinforcement material are as follows: Prepare a c-plane sapphire substrate, clean and dry it, and then place it in the MOCVD reaction chamber. Maintain the trimethylgallium source bottle at -10.0℃ and the trimethylaluminum source bottle at 15.0℃. Set the reaction chamber pressure to 10.2 kPa and the total hydrogen carrier gas flow rate to 10.2 SLM. Heat the substrate to 1098℃ and stabilize for 5 min. Introduce trimethylgallium at a flow rate of 105 sccm (corresponding to a mass of 2.625 g); introduce trimethylaluminum at a flow rate of 35 sccm (corresponding to a mass of 0.875 g); and simultaneously introduce high-purity ammonia at 5100 sccm. After growth for 38 min, cool under an ammonia atmosphere to obtain an Al0.25Ga0.75N nanorod array. Immerse the array in 210 mL of 2.2 mol / L hydrochloric acid, place it in a 55℃ water bath, and sonicate it with 300 W power for 50 min. The supernatant was collected and centrifuged at 8000 rpm for 10 min to obtain AlGaN nanorod precipitate. The nanorods were dispersed in 210 mL of ethylene glycol and stirred for 30 min to form a suspension. Under nitrogen protection and stirring at 300 rpm, 5.800 g of zinc acetate hexahydrate, 0.232 g of magnesium acetate tetrahydrate, and 0.160 g of aminopropyltriethoxysilane were added sequentially to the suspension. The coprecipitant was prepared by mixing 20.0 mL of 25% tetramethylammonium hydroxide aqueous solution, 40.0 mL of deionized water, and 380.0 mL of ethylene glycol, and added dropwise at a rate of 1.70 mL / min for a total adding time of 4.3 h. After the addition was complete, the reaction system was maintained at 81.0 °C and the reaction was stirred for another 5.5 h. After the reaction was completed and cooled, the precipitate was centrifuged and washed with deionized water and ethanol, respectively. The precipitate was then vacuum dried at 80.0 °C and -0.1 MPa for 12 h. The precursor powder was placed in a tube furnace, and a mixture of argon and oxygen in a volume ratio of 95.5:4.5 was introduced at a total flow rate of 2.0 L / min. The temperature was increased to 620 °C at a rate of 5.0 °C / min, and after annealing for 3.5 h, the furnace was cooled to obtain the final powder.

[0026] The fabrication steps for the high current density transistor are as follows: An n-type 4H-SiC substrate is taken, cleaned and dried using RCA. A 100 nm thick n+ type GaAs buffer layer (doping concentration 1×10⁻⁶) is grown in an MOCVD apparatus at 10.2 kPa pressure and 615 °C. 19 cm -3 Subsequently, a 500 nm thick n-type GaAs collector region (doping concentration 5 × 10⁻⁶) was grown at 580 °C. 16 cm -3 Transferred to the MBE equipment, at 580℃ and an arsenic pressure of 1.0 × 10⁻⁶. -5 Under Pa, an 18 nm thick initial base region of p-type GaAs was grown (carbon doping concentration 1×10⁻⁶). 19 cm -3The sample was removed and, in a PLD device, heated under a vacuum of 5.0 × 10⁻⁶. -5 Under conditions of Pa, oxygen pressure of 11.0 Pa, and sample stage temperature of 570℃, a laser energy density of 2.8 J / cm² was used. 2 At a frequency of 10 Hz, 3500 pulses were deposited to form a base region doped enhancement layer approximately 7 nm thick. The process was then repeated in MBE under the same conditions to grow a 92 nm thick p-type GaAs layer, resulting in a total base region thickness of 110 nm. In an ALD apparatus, with the chamber temperature set at 302 °C, using the same precursor and pulse sequence as in Example 1, a supercycle was repeated 180 times to grow an interface passivation layer approximately 13 nm thick. In an MOCVD apparatus, at a pressure of 10.2 kPa and a temperature of 602 °C, a 180 nm thick n-type InGaP emitter region (silicon doping concentration 5 × 10⁻⁶) was grown. 19 cm -3 The subsequent photolithography and dry etching were used to define the mesa, and gold-germanium-nickel-gold n-type electrodes and gold-zinc-nickel-gold p-type electrodes with the same structure as in Example 1 were fabricated using electron beam evaporation and lift-off processes. Finally, alloying annealing was performed to complete the device fabrication.

[0027] Comparative Example 1 The specific implementation method is the same as in Example 1, except that the fabrication steps of the high current density transistor are as follows: An n-type 4H-SiC substrate with the exact same specifications as in Example 1 is taken and subjected to the same RCA cleaning and drying. Under the same MOCVD equipment and process conditions, an n+ type GaAs buffer layer and an n-type GaAs collector region of the same thickness and doping concentration are grown. Subsequently, under the same MBE equipment and process conditions, a p-type GaAs base region with a total thickness of 100 nm is continuously epitaxially grown in one step, with the carbon doping concentration maintained at 1×10⁻⁶. 19 cm -3 No base region doped reinforcement layer was deposited during this process. After the base region growth was completed, a 10 nm thick hafnium zirconium co-doped barium strontium titanate interface passivation layer was grown on the exposed GaAs base region surface under the same ALD equipment and process conditions. Subsequent steps, including growing a 150 nm thick n-type InGaP emitter region in MOCVD, performing photolithography and dry etching to define the mesa, and fabricating and alloying identical metal electrodes by electron beam evaporation and lift-off, were completely consistent with those in Example 1.

[0028] Comparative Example 2 The specific implementation method is the same as in Example 1, except that the preparation steps of the aluminum gallium nitride-zinc oxide core-shell heterostructure doped reinforcement material are as follows: This comparative example only prepares pure zinc oxide target material. 5.500 g of zinc acetate hexahydrate was dissolved in 200 mL of ethylene glycol. Under stirring and nitrogen protection, an alkaline solution consisting of 10.0 mL of 25% tetramethylammonium hydroxide aqueous solution, 10.0 mL of deionized water, and 180.0 mL of ethylene glycol was added dropwise, and the reaction was carried out at 80 °C for 5 h. After the reaction, the mixture was centrifuged and washed, and then vacuum dried at 80 °C to obtain zinc hydroxide precursor powder. This powder was annealed in air at 575 °C for 3 h to obtain pure zinc oxide powder. The preparation steps of the high current density transistor are as follows: substrate preparation, buffer layer, collector region, and initial 15 nm thick p-type GaAs base region growth are exactly the same as in Example 1. Subsequently, under the same PLD deposition conditions (temperature 550 °C, oxygen pressure 10.0 Pa, laser energy density 2.2 J / cm²), the transistor was prepared. 2 Under the conditions described above, a pure zinc oxide layer of approximately 5 nm thickness was deposited using the target material pressed from the pure zinc oxide powder. Subsequently, the remaining 85 nm thick p-type GaAs base region was grown in the MBE. All process parameters and steps for subsequent interface passivation layer deposition, emitter region growth, mesa etching, and electrode fabrication were identical to those in Example 1.

[0029] Comparative Example 3 The specific implementation method is the same as in Example 1, except that the fabrication steps of the high current density transistor are as follows: An n-type 4H-SiC substrate with the same specifications as in Example 1 is taken and subjected to the same RCA cleaning and drying. Under the same MOCVD and MBE equipment and process conditions, an identical n+ type GaAs buffer layer, an n-type GaAs collector region, and a p-type GaAs base region with a total thickness of 100 nm (including a 15 nm initial layer, a 5 nm base region doped enhancement layer, and an 85 nm subsequent layer, the deposition process of which is exactly the same as in Example 1) are grown sequentially. After the base region growth is completed, no interface passivation layer is deposited, and the sample is directly placed into the MOCVD equipment. Under the same process conditions (pressure 10.0 kPa, temperature 600 °C), a 150 nm thick n-type InGaP emitter region is epitaxially grown directly on the exposed p-type GaAs base region surface, with the doping concentration maintained at 5 × 10⁻⁶. 19 cm -3 The parameters and steps of the subsequent photolithography, dry etching to define the mesa, and electrode fabrication processes are exactly the same as in Example 1.

[0030] Performance testing According to relevant national and industry standards, the high current density transistors prepared in Examples 1-3 and Comparative Examples 1-3 were subjected to performance testing using the following methods, which included the following steps: The saturation current density and transconductance were tested using an automated test system equipped with a semiconductor parameter analyzer. First, the device under test (DUT) was mounted on a temperature-controlled probe stage, and the probe stage substrate temperature was precisely set and stabilized at 25.0°C. The test employed a common-emitter configuration, controlled by the source measurement unit within the analyzer.

[0031] For the saturation current density test, a sequence test script is written and executed: First, the base current source is controlled to output a predetermined value starting from 0µA and increasing in 10µA steps until the collector current approaches saturation; at each fixed base current point, another voltage source is controlled to output a collector-emitter voltage that linearly scans from 0V to 3.0V with a scan step of 10mV, and the collector current value is recorded synchronously after a 10ms sampling delay at each voltage point; after the test is completed, the data is processed, the collector current at a collector-emitter voltage of 2.0V is extracted, and the saturation current density is calculated based on the effective emitter area of ​​the device, reported in milliamperes per millimeter (mA / mm).

[0032] For transconductance testing, in another test sequence, the collector-emitter voltage is fixed at 2.0V, and the voltage source is controlled to output a base-emitter voltage ranging from 0.6V to 1.2V in 1mV steps. The base current and collector current are measured simultaneously. The transconductance value is obtained by calculating the derivative of the collector current with respect to the base-emitter voltage (ΔIc / ΔVbe), and the unit is reported as millisiemens per millimeter (mS / mm).

[0033] The breakdown voltage test is performed on the same probe station. The base terminal of the device is kept open. The voltage applied between the collector and emitter is slowly increased in 50mV increments using a programmable voltage source. At the same time, the collector current is monitored with a high-precision ammeter. When the monitored collector current reaches 1mA, the test program automatically stops and records the voltage value at this time. This voltage is reported as the breakdown voltage, and the unit is volts (V).

[0034] The cutoff frequency and maximum oscillation frequency were tested on a microwave probe station using a vector network analyzer in conjunction with a ground-signal-ground type high-frequency probe. First, without any device placed on the probe, a comprehensive short-circuit-open-load-shoot-through calibration was performed using an impedance standard substrate within a frequency range of 100MHz to 50GHz to eliminate errors inherent in the test system. After calibration, the probes were attached to the input and output pads of the device, and a DC bias of Vce=2.0V and Ic=10mA was applied to the device using a DC bias probe. In continuous wave mode, with an intermediate frequency bandwidth of 1kHz, S-parameter scans were performed in 200MHz steps, with an average sampling of 64 times per frequency point. After obtaining the complete two-port S-parameter matrix, it was imported into circuit simulation software, and the measured data were fitted by constructing and optimizing the π-type small-signal equivalent circuit model of the device. From the fitted model, the curves of current gain and maximum available gain as a function of frequency are directly extracted. The frequency points corresponding to the two curves when the frequency drops to unity gain (0dB) are reported as the current gain cutoff frequency and the maximum oscillation frequency, respectively, with the unit being gigahertz (GHz).

[0035] The current gain attenuation rate was tested using a high-temperature reverse bias experiment. The packaged device was placed in a forced convection high and low temperature test chamber, and the chamber air temperature was raised to 150.0°C at a rate of 2°C per minute and stabilized. Then, a constant reverse bias voltage of 26V was applied between the collector and emitter of the device using a high-precision DC power supply, with the base left floating. This stress condition was continuously applied for 1000 hours. Before and after the stress test, the device was cooled to 25.0°C and its common-emitter DC current gain was accurately measured under the same DC test conditions (Vce=2.0V, Ic=100mA / mm). The attenuation rate was obtained by calculating the percentage decrease in gain value after stress relative to the initial value before stress, and the report unit is percentage (%).

[0036] Test results: Table 1: Test results of each embodiment and comparative example ; As can be seen from Table 1, the test data of Examples 1-3 have a comprehensive advantage over Comparative Examples 1-3, systematically demonstrating the synergistic effect of the two novel inorganic functional layers introduced in this invention, effectively solving the three core physical problems that restrict the realization of high current density in bipolar junction transistors.

[0037] First, addressing the bottleneck of low carrier injection efficiency, the extremely high saturation current density and transconductance values ​​in the examples provide direct evidence. Example 1 achieves a saturation current density of 1850 mA / mm, several times higher than the comparative example lacking any functional layer. This is primarily attributed to the contribution of the hafnium-zirconium co-doped barium strontium titanate interface passivation layer. This layer, grown in situ on the base region surface, exhibits extremely low interface state density and high dielectric properties, significantly reducing carrier trapping and barrier height at the emitter junction interface. This makes the electron injection process from the emitter region to the base region exceptionally efficient, directly translating into a significant improvement in driving capability.

[0038] Secondly, addressing the issue of high transport losses in the base region, the significant improvements in transconductance and cutoff frequency reveal the crucial role of the base region doped enhancement layer. The transconductances of Examples 1-3 all exceed 295 mS / mm, far higher than the comparative examples, directly reflecting the improved minority carrier transport efficiency within the base region. After the aluminum gallium nitride-zinc oxide core-shell heterostructure doped enhancement layer is embedded in the base region, its unique acceptor-donor pair co-doping mode modulates the local electric field and energy band at the nanoscale, optimizing the carrier distribution and diffusion path, effectively reducing the base region resistance and transit time. This not only enhances current handling capability but also directly translates into an excellent cutoff frequency of up to 112 GHz, resolving the contradiction that increasing doping concentration traditionally leads to frequency decrease.

[0039] Finally, regarding the reliability challenges posed by numerous defects at heterogeneous interfaces, the stable increase in breakdown voltage and the sharp decrease in current gain attenuation rate are decisive evidence. Especially under high electric field and high temperature stress, Comparative Example 3, lacking an interface passivation layer, exhibits the lowest breakdown voltage and a gain attenuation rate as high as 28.0%, indicating that interface defects lead to severe leakage and performance degradation. In contrast, the breakdown voltages of Examples 1-3 are all stable above 30V, and the attenuation rates are all below 5.2%. This fully demonstrates that hafnium-zirconium co-doping strongly suppresses oxygen vacancies, and the stable interface provided by the core-shell structure, together reducing the interface defect density to an extremely low level, thereby ensuring long-term stable operation of the device under harsh conditions such as high voltage and high temperature.

[0040] In summary, the superior performance of the embodiments is not the result of a single improvement, but rather the result of the innovations of the two functional materials in the two dimensions of physical interface and in vivo transport, and their synergistic effect: the interface passivation layer ensures the efficient injection starting point of charge carriers, while the base region enhancement layer ensures high-speed and low-loss transport of charge carriers in the bulk. The combined effect of the two fundamentally breaks through the technical dilemma of achieving high injection, low loss and high stability simultaneously.

[0041] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A method for fabricating a high current density transistor, characterized in that the steps include... include: S1. Perform standard RCA cleaning and dry the silicon carbide substrate; An n+ type GaAs buffer layer and an n-type GaAs collector region are epitaxially grown on a substrate using metal-organic chemical vapor deposition (MOCVD). A p-type GaAs base region is epitaxially grown on the surface of the collector region using molecular beam epitaxy (MBE). An aluminum gallium nitride-zinc oxide core-shell heterostructure doped reinforcement material is deposited on the surface of the p-type GaAs base region using pulsed laser deposition (PLD) at a temperature of 500-600℃ to form a base region doped reinforcement layer. S2. The remaining p-type GaAs base region is grown by molecular beam epitaxy. On the surface of the completed base region, atomic layer deposition is used with tetra(dimethylamino)hafnium, tetra(dimethylamino)zirconium, bis(cyclopentadienyl)barium, bis(cyclopentadienyl)strontium, and deionized water as precursors. Cyclic deposition is carried out at 295-305℃ to generate a hafnium-zirconium co-doped barium strontium titanate interface passivation layer in situ. Then, an n-type InGaP emitter region is epitaxially grown on the passivation layer by metal-organic chemical vapor deposition. The mesa is defined by photolithography and dry etching processes. The metal ohmic contact electrodes of the collector, base, and emitter are sequentially fabricated by electron beam evaporation and lift-off processes.

2. The method for fabricating a high current density transistor according to claim 1, characterized in that, In step S1, the thickness of the base region doped enhancement layer is 2-8 nm; the laser energy density used for pulsed laser deposition is 1.5-3.0 J / cm². 2 .

3. The method for fabricating a high current density transistor according to claim 1, characterized in that, In step S2, the thickness of the interface passivation layer is 5-15 nm.

4. The method for fabricating a high current density transistor according to claim 1, characterized in that, The preparation method of the aluminum gallium nitride-zinc oxide core-shell heterostructure doped and reinforced material includes: A1. Using trimethylgallium, trimethylaluminum, and ammonia as precursors, Al was grown on a sapphire substrate via metal-organic chemical vapor deposition. 0.25 Ga 0.75 N nanorod arrays; A2, the growing Al 0.25 Ga 0.75 An AlGaN nanorod array is immersed in hydrochloric acid and ultrasonically treated at 40-60°C to peel it off from the substrate, thus obtaining AlGaN nanorods; the AlGaN nanorods are then dispersed in ethylene glycol to obtain an AlGaN nanorod suspension. A3. Under continuous stirring and nitrogen protection, zinc acetate hexahydrate, magnesium acetate tetrahydrate and aminopropyltriethoxysilane were added sequentially to the AlGaN nanorod suspension; at the same time, an alkaline complexing solution composed of tetramethylammonium hydroxide, deionized water and ethylene glycol was added dropwise, and the reaction was carried out at 78-82℃. A4. After the reaction is complete, the product is collected by centrifugation, washed alternately with deionized water and ethanol, and finally dried under vacuum at 78-82℃ to obtain dried powder; the dried powder is annealed at 500-650℃ under an argon-oxygen mixed atmosphere.

5. The method for fabricating a high current density transistor according to claim 4, characterized in that, In step A1, the growth temperature is 1095-1105℃ and the growth time is 30-40 min.

6. The method for fabricating a high current density transistor according to claim 4, characterized in that, In step A2, the ultrasonic treatment at 40-60℃ takes 30-60 minutes; the concentration of the hydrochloric acid is 1-3 mol / L.

7. The method for fabricating a high current density transistor according to claim 4, characterized in that, In step A3, the reaction time at 78-82℃ is 4-6 hours; the volume ratio of tetramethylammonium hydroxide, deionized water and ethylene glycol is 1:(1-2):(15-20).

8. The method for fabricating a high current density transistor according to claim 4, characterized in that, In step A4, the annealing time at 500-650℃ is 2-4 hours; the volume fraction of oxygen in the argon-oxygen mixed atmosphere is 3-5%.

9. A high current density transistor, characterized in that, The high current density transistor is prepared by the method of preparation of the high current density transistor according to any one of claims 1-8.