A two-dimensional selenium-molybdenum disulfide-based inverter and a preparation method thereof

Abstract

The application discloses a kind of based on two-dimensional selenium-molybdenum disulfide inverter and preparation method, it is related to two-dimensional material device related technical field, wherein, inverter includes conductive substrate, insulating gate layer, P-type transistor and N-type transistor, insulating gate layer is located on the conductive substrate;Channel region in P-type transistor includes two-dimensional selenium, the P-type transistor is located on the insulating gate layer;Channel region in N-type transistor includes molybdenum disulfide, the N-type transistor is located on the insulating gate layer;Wherein, the drain of the P-type transistor and the N-type transistor are electrically connected with each other, constitute complementary metal oxide semiconductor, can solve the problems, such as high switching power consumption, poor air stability and high-performance P-type two-dimensional semiconductor material lack in complementary logic inverter based on two-dimensional material in prior art, resulting in integration difficulty.

Description

Technical Field

[0001] This invention relates to the field of two-dimensional material devices, and in particular to an inverter based on two-dimensional selenium-molybdenum disulfide and its preparation method. Background Technology

[0002] As the fundamental unit of complementary metal-oxide-semiconductor (CMOS) circuits, the performance of logic inverters directly affects the power consumption, speed, and integration density of digital integrated circuits. With the continuous miniaturization of semiconductor devices to the nanoscale, traditional silicon-based technologies face severe challenges such as short-channel effects, increased leakage current, and thermal budget limitations. Two-dimensional materials, due to their atomic-level thickness, absence of surface dangling bonds, excellent electrostatic control capabilities, and rich electrical properties, are considered ideal candidate material systems for constructing next-generation ultra-low-power, high-density logic devices. Transition metal chalcogenides (such as molybdenum disulfide, MoS2), as typical n-type two-dimensional semiconductors, have been extensively studied and applied in transistors and logic gates. However, high-performance, air-stable p-type two-dimensional semiconductors are scarce, and high-quality integration with n-type materials faces numerous challenges, severely hindering the development of all-two-dimensional CMOS circuits.

[0003] Currently, research on complementary logic inverters based on two-dimensional materials mainly focuses on finding suitable p-type materials or controlling the polarity of materials. For example, existing technology (Controllable P-Type Doping Strategy for High-Performance 2D Material Complementary Inverters. ACS Appl. Mater. Interfaces 2025, 17, 17018-17025.) discloses an inverter based on WSe2 / MoS2. This scheme achieves high voltage gain by controlling the oxidation of mechanically exfoliated WSe2 to make it exhibit p-type characteristics and forming a complementary circuit with MoS2. However, this scheme has significant shortcomings: firstly, its inverter switching power consumption is relatively high, with a minimum of about 0.256nW, which is difficult to meet the requirements of ultra-low power applications; secondly, it relies on the mechanical exfoliation method, which has low yield, poor repeatability, and uncontrollable size, and the additional oxidation post-processing step increases the process complexity and uncontrollable interface defects.

[0004] Another existing technology (Tunable Tribotronic Dual-Gate Logic Devices Based on 2D MoS2 and Black Phosphorus. Adv. Mater. 2018, 30, 1705088.) reports an inverter based on black phosphorus (BP) and MoS2. This device uses triboelectric potential instead of gate voltage to achieve logic functions, but it also has problems: First, black phosphorus is extremely prone to oxidation and degradation in air, and must rely on a top-deposited hafnium dioxide (HfO2) insulating layer for protection, which increases process complexity and thermal budget; second, its power consumption is still in the nW range (about 1nW), and the special triboelectric structure is not conducive to high-density integration.

[0005] Therefore, developing a two-dimensional semiconductor that combines intrinsic p-type characteristics, high air stability, and a suitable bandgap, and achieving low-damage, high-quality integration with mature n-type materials (such as MoS2), is key to constructing high-performance, low-power, and highly reliable all-two-dimensional CMOS inverters.

[0006] Two-dimensional selenium (2D Se), as an emerging single-element p-type semiconductor, shows great potential in low-power electronic devices due to its anisotropic structure composed of one-dimensional atomic chains, suitable band gap (approximately 1.6-2.0 eV), and theoretically extremely low off-state current. However, existing 2D selenium synthesis techniques face several bottlenecks, hindering its integration with materials such as MoS2 to construct logic devices. For example: Solution methods (as described in patent CN114988373B) typically require the use of large amounts of organic surfactants and solvents, resulting in complex processes and often yielding selenium nanosheets with thicknesses exceeding 100 nm, which is insufficient to meet the requirements of nanoscale devices for ultrathin channels.

[0007] High temperature and high pressure methods (as described in patent CN120485948A) require extreme synthesis conditions, have high thermal budgets and expensive equipment, and produce bulk crystals that cannot be directly used for device fabrication.

[0008] Etching thinning methods (as described in patent CN112028034A) obtain two-dimensional selenium by etching aluminum selenide with an acidic solution, but the lateral size of the product is usually less than 1 μm, which is difficult to be compatible with micro-nano fabrication processes, and the etching process may introduce contamination and defects.

[0009] Although some studies (such as Polarization - Sensitive Photodetectors Based on Anisotropic 2D Selenium and Its Multifunctional Applications. ACS Appl. Mater. Interfaces 2025, 17, 55074-55083.) have obtained high-quality two-dimensional selenium using physical vapor deposition and demonstrated its transistor characteristics, most of these works focus on single semiconductor devices or optoelectronic devices. They have not systematically addressed how to integrate two-dimensional selenium with another two-dimensional semiconductor (such as MoS2) into a high-performance, low-power complementary logic inverter using a low thermal budget and low-cost process. Furthermore, there is a lack of systematic evaluation and reporting on the key performance characteristics of this integrated device, such as power consumption and stability, under full logic functionality.

[0010] In summary, no existing technology discloses a complementary logic inverter based on two-dimensional selenium and molybdenum disulfide, and its fabrication method, that can simultaneously meet the requirements of ultra-low power consumption, high air stability, low thermal budget, low cost, and high process compatibility. Summary of the Invention

[0011] This invention provides an inverter based on two-dimensional selenium-molybdenum disulfide and its fabrication method, which can solve the problems of high switching power consumption, poor air stability, and integration difficulties caused by the lack of high-performance P-type two-dimensional semiconductor materials in the prior art complementary logic inverters based on two-dimensional materials.

[0012] To address the above problems, this invention provides an inverter based on two-dimensional selenium-molybdenum disulfide and its preparation method, comprising: Conductive substrate; An insulating gate layer is located on the conductive substrate; A P-type transistor, wherein the channel region includes two-dimensional selenium, and the P-type transistor is located on the insulating gate layer; An N-type transistor, wherein the channel region includes molybdenum disulfide, and the N-type transistor is located on the insulating gate layer; The drains of the P-type transistor and the N-type transistor are electrically connected to each other, forming a complementary metal-oxide-semiconductor system.

[0013] The present invention provides an inverter based on two-dimensional selenium-molybdenum disulfide, which, compared with the prior art, has the following beneficial effects, but is not limited to: Two-dimensional selenium has a suitable wide bandgap and extremely low off-state current. When combined with molybdenum disulfide, the switching power consumption of the inverter can be as low as 20pW at a low supply voltage of 0.5V, which is far lower than that of existing two-dimensional material inverters, meeting the core requirements of next-generation ultra-low power integrated circuits.

[0014] Two-dimensional selenium itself exhibits excellent air stability, eliminating the need for additional encapsulation protection. The two materials are integrated via van der Waals forces, resulting in an interface free of dangling bonds and minimal lattice mismatch, thus endowing the device with inherent stability and anti-interference capabilities. Furthermore, both materials are nanometer-thick, significantly reducing the space occupied in the vertical direction, which is beneficial for three-dimensional stacking and high-density integration.

[0015] Preferably, the conductive substrate is P-type doped, and the conductive substrate is configured as a common gate. The P-type transistor and the N-type transistor are provided with electrodes, including a ground electrode and an output electrode.

[0016] Preferably, the two-dimensional selenium is a single-crystal two-dimensional selenium nanosheet synthesized by physical vapor deposition. The molybdenum disulfide is configured as molybdenum disulfide nanosheets synthesized by chemical vapor deposition.

[0017] Preferably, the two-dimensional selenium nanosheets and the molybdenum disulfide nanosheets are disposed on the insulating gate layer at intervals.

[0018] Preferably, this application embodiment provides a preparation method for preparing the above-mentioned inverter, the preparation method comprising: S1. Provide a first substrate, place a selenium source in a first temperature zone under a protective gas, place the first substrate in a second temperature zone, and grow two-dimensional selenium nanosheets on the first substrate through a physical vapor deposition process; S2. Provide a second substrate, place a sulfur source in a third temperature zone, place the second substrate and a molybdenum source in a fourth temperature zone, and grow molybdenum disulfide nanosheets on the second substrate through a chemical vapor deposition process; S3. The two-dimensional selenium nanosheets and the molybdenum disulfide nanosheets are assembled onto the insulating gate layer of a target substrate by a transfer process to form a P-type transistor and an N-type transistor structure, and the drain regions of the P-type transistor and the N-type transistor are electrically connected to each other. S4. Fabricate metal electrodes on the assembled structure, and complete the fabrication of the inverter by combining them with a conductive substrate and an insulating gate layer.

[0019] The preparation method provided by this invention has, but is not limited to, the following beneficial effects compared to the prior art: The synthesis of two-dimensional selenium uses only a single selenium powder precursor, carried out under normal pressure and a hydrogen-containing protective atmosphere, with a maximum temperature not exceeding 380℃ and a substrate temperature as low as 120-150℃. This temperature is significantly lower than that of traditional semiconductor processes and the synthesis temperature of most two-dimensional materials, effectively reducing equipment requirements and energy consumption. In the synthesis of molybdenum disulfide, the growth temperature is controlled at 740-760℃ by adding sodium chloride flux. The synthesis of both materials can be completed in the same tube furnace by sequentially replacing the quartz tubes, greatly reducing equipment investment and process complexity.

[0020] The synthesis process is environmentally friendly and highly reproducible. The entire preparation process, especially the synthesis of two-dimensional selenium, does not require the use of strong acids, strong alkalis, or other toxic or corrosive organic solvents, avoiding complex liquid phase treatment and waste liquid recovery issues, thus demonstrating higher green safety. The physical vapor deposition and chemical vapor deposition processes employed are both precisely controllable techniques. The combination of dry / wet transfer strategies improves the success rate and positional accuracy of material transfer, facilitating controllable device fabrication and large-scale mass production.

[0021] Preferably, both the first substrate and the second substrate are silicon wafers.

[0022] Preferably, in S1, a dual-temperature zone tubular furnace is provided, wherein the first temperature zone is located upstream of the gas inlet of the dual-temperature zone tubular furnace, and the selenium source temperature is 340°C. The second temperature zone is located downstream of the gas inlet of the dual-temperature zone tube furnace, and the temperature of the first substrate is 120-150°C.

[0023] Preferably, in S2, the third temperature zone is located upstream of the gas inlet of the dual-temperature zone tubular furnace, and the sulfur powder temperature is 160°C. The fourth temperature zone is located downstream of the gas inlet of the dual-temperature zone tube furnace, and the second substrate temperature is 750°C.

[0024] Preferably, in S2, sodium chloride is added to the molybdenum source, and the growth temperature is 740°C to 760°C.

[0025] Preferably, in S3, the two-dimensional selenium nanosheets are transferred by dry transfer using polydimethylsiloxane, and the molybdenum disulfide nanosheets are transferred by wet transfer using polymethyl methacrylate. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the overall structure of an inverter based on two-dimensional selenium-molybdenum disulfide according to an embodiment of the present invention. Figure 2 This is a schematic diagram of a method for fabricating an inverter based on two-dimensional selenium-molybdenum disulfide according to an embodiment of the present invention. Figure 3 This is a schematic representation of the Raman spectral characterization of two-dimensional selenium in an embodiment of the present invention. Figure 4 This is a schematic diagram showing the thickness characterization of two-dimensional selenium using atomic force microscopy according to an embodiment of the present invention. Figure 5 This is a schematic diagram showing the Raman spectral characterization of molybdenum disulfide according to an embodiment of the present invention; Figure 6 This is a schematic diagram showing the atomic force microscopy thickness characterization of molybdenum disulfide according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the static voltage transfer characteristic curve of the two-dimensional selenium-molybdenum disulfide inverter according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the static power consumption curve of the two-dimensional selenium-molybdenum disulfide inverter according to an embodiment of the present invention; Figure 9 The diagram shows the pulse voltage dynamic response VT of the two-dimensional selenium-molybdenum disulfide inverter according to an embodiment of the present invention.

[0028] Explanation of reference numerals in the attached figures: 100, Conductive substrate; 200, Insulating gate layer; 300, P-type transistor; 310, External electrode; 400, N-type transistor; 500, Output electrode; 600, Ground electrode. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings showing multiple embodiments according to this application. It should be understood that the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments described in this application without creative effort will fall within the scope of protection of this application.

[0030] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing specific embodiments only and is not intended to limit this application; the terms "comprising," "including," "having," "containing," etc., in the description, claims, and accompanying drawings of this application are open-ended terms. Therefore, "comprising," "including," or "having" refers to, for example, a method or apparatus having one or more steps or elements, but is not limited to having only these one or more elements. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0031] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0032] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0033] It should be emphasized that when the term "comprising / including" is used in this specification, it is used to explicitly indicate the presence of the stated feature, integer, step, or component, but does not exclude the presence or addition of one or more other features, integers, steps, parts, or groups of features, integers, steps, or parts.

[0034] like Figure 1As shown in the figure, an inverter based on two-dimensional selenium-molybdenum disulfide and its fabrication method provided by an embodiment of the present invention includes a conductive substrate 100, an insulating gate layer 200, a P-type transistor 300, and an N-type transistor 400. The insulating gate layer 200 is located on the conductive substrate 100. The channel region of the P-type transistor 300 includes two-dimensional selenium, and the P-type transistor 300 is located on the insulating gate layer 200. The channel region of the N-type transistor 400 includes molybdenum disulfide, and the N-type transistor 400 is located on the insulating gate layer 200. The drains of the P-type transistor 300 and the N-type transistor 400 are electrically connected to each other, forming a complementary metal-oxide-semiconductor.

[0035] Specifically, the inverter of this invention connects the drain of a P-type transistor 300 and the drain of an N-type transistor 400 as the output electrode 500, the source of the P-type transistor 300 as the external electrode 310 for connecting to an external high-voltage power supply, and the source of the N-type transistor 400 as the ground electrode 600. Simultaneously, the P-type doped conductive substrate 100 serves as the common gate, thus achieving the signal inversion function. This structural design fully utilizes the intrinsic p-type characteristics of two-dimensional selenium and the n-type characteristics of molybdenum disulfide, and the complementary circuit formed by the two effectively reduces switching power consumption.

[0036] Meanwhile, two-dimensional selenium itself has good air stability and can exist stably in air without additional encapsulation protection, avoiding the increased complexity and cost caused by encapsulation processes, and also reducing the risk of introducing interface defects.

[0037] In this embodiment, the conductive substrate 100 is P-type doped and is configured as a common gate; electrodes are provided on the P-type transistor 300 and the N-type transistor 400, and the electrodes include a ground electrode 600, an output electrode 500, and an external electrode 310.

[0038] In this design, the source of the P-type transistor 300 is a single electrode, which serves as an external electrode 310 for connecting to a high-level external voltage V. ddThe drain of the N-type transistor 400 is connected to the drain of the P-type transistor 300, serving together as the output electrode 500. The source of the N-type transistor serves as the ground electrode 600. This structural design allows the input signal to simultaneously control the on / off states of both the P-type transistor 300 and the N-type transistor 400, thereby achieving the inverting logic function. Specifically, when the input is high, the N-type transistor 400 is on, the P-type transistor 300 is off, and the output is grounded, presenting a low level. When the input is low, the P-type transistor 300 is on, the N-type transistor 400 is off, and the output is connected to the power supply through the P-type transistor 300, presenting a high level. This complementary structure helps reduce static power consumption and improves the overall performance of the inverter.

[0039] In this embodiment, the two-dimensional selenium is configured as a single-crystal two-dimensional selenium nanosheet synthesized by physical vapor deposition; the molybdenum disulfide is configured as a molybdenum disulfide nanosheet synthesized by chemical vapor deposition.

[0040] Two-dimensional selenium nanosheets prepared by physical vapor deposition (PVD) exhibit excellent crystallinity, and their single-crystal structure effectively reduces grain boundary scattering, providing a good carrier transport channel for the P-type transistor 300. Meanwhile, molybdenum disulfide nanosheets synthesized by chemical vapor deposition (CVD) possess an atomically flat surface and controllable thickness, ensuring a high on / off ratio and low contact resistance for the N-type transistor 400. Both nanosheets are two-dimensional layered structures with natural van der Waals surfaces, allowing for low-damage integration with the insulating gate layer 200 via dry or wet transfer processes, avoiding the problems caused by lattice mismatch and interfacial stress in traditional heterogeneous integration.

[0041] In this embodiment, the two-dimensional selenium nanosheets and the molybdenum disulfide nanosheets are disposed on the insulating gate layer 200 at intervals.

[0042] This spacing effectively avoids mutual interference in the electrical properties of the two semiconductor materials, ensuring that the P-type transistor 300 and the N-type transistor 400 operate independently. It also provides ample operational space for subsequent electrode fabrication and device packaging, improving process compatibility and operability during device fabrication. Specifically, the spacing between the two-dimensional selenium nanosheets and the molybdenum disulfide nanosheets can be adjusted according to the actual device size and process requirements, generally controlled within the range of 1-5 μm. This satisfies electrical isolation requirements while minimizing the overall size of the inverter, facilitating high device integration.

[0043] This application provides a preparation method for fabricating an inverter, such as... Figure 2 As shown, the preparation method includes: S1. Provide a first substrate, place a selenium source in a first temperature zone under a protective gas, place the first substrate in a second temperature zone, and grow two-dimensional selenium nanosheets on the first substrate through a physical vapor deposition process; S2. Provide a second substrate, place a sulfur source in a third temperature zone, place the second substrate and a molybdenum source in a fourth temperature zone, and grow molybdenum disulfide nanosheets on the second substrate through a chemical vapor deposition process; S3. The two-dimensional selenium nanosheets and the molybdenum disulfide nanosheets are assembled onto the insulating gate layer 200 of a target substrate by a transfer process to form a structure of P-type transistor 300 and N-type transistor 400, and the drain regions of the P-type transistor 300 and the N-type transistor 400 are electrically connected to each other. S4. Prepare metal electrodes on the assembled structure, and complete the fabrication of the inverter by combining it with the conductive substrate 100 and the insulating gate layer 200.

[0044] The preparation method provided by this invention achieves heterogeneous integration of two-dimensional selenium and molybdenum disulfide through a stepwise growth and integration process, effectively reducing process complexity and thermal budget. First, steps S1 and S2 grow high-quality two-dimensional selenium and molybdenum disulfide nanosheets on independent substrates, respectively. This separate growth approach allows for independent processing of the growth parameters of the two materials, ensuring that their respective material properties are optimized without affecting each other. For example, when physical vapor deposition of two-dimensional selenium, precise control of the selenium source temperature and substrate temperature can yield single-crystal nanosheets with specific sizes and thicknesses; while in chemical vapor deposition of molybdenum disulfide, adjusting the sulfur source temperature, molybdenum source supply rate, and growth temperature allows for the control of the number of nanosheet layers and domain size.

[0045] In step S4, the metal electrodes are typically fabricated using electron beam evaporation or thermal evaporation to deposit the metal material, followed by photolithography and etching processes to define the electrode pattern. A good ohmic contact between the electrode and the two-dimensional semiconductor material is crucial for ensuring the device's electrical performance. In this method, the conductive substrate 100 is used as the common gate, which, together with the source and drain electrodes, forms the electrical circuit of the inverter, thus completing the fabrication of the entire device. This fabrication process eliminates the need for high-temperature epitaxy or complex ion implantation processes, significantly reducing equipment requirements and fabrication costs, while also avoiding the negative impact of high-temperature processes on the performance of two-dimensional materials.

[0046] In this embodiment of the application, both the first substrate and the second substrate are configured as silicon wafers.

[0047] Silicon wafers, as substrates, possess excellent chemical and thermal stability, providing a smooth surface support for the growth of two-dimensional selenium nanosheets and molybdenum disulfide nanosheets. Furthermore, silicon wafers are low-cost, readily available, and easy to process, facilitating subsequent transfer processes.

[0048] Furthermore, a silicon dioxide layer can be pre-grown on the surface of the silicon wafer. The insulating properties and smooth surface of silicon dioxide can reduce the interference of the substrate on the nanosheet growth process and improve the crystal quality and surface flatness of the nanosheet.

[0049] Before using silicon wafers as the first and second substrates, a carrier preparation is required. A silicon dioxide substrate obtained by dry oxidation is used as the deposition carrier, wherein the silicon dioxide thickness is 300 nm.

[0050] After the deposition of the substrate is completed, the silicon wafers are cleaned. First, the silicon wafers required for growth are ultrasonically cleaned sequentially at room temperature in acetone, isopropanol, ethanol, and deionized water, respectively, with each cleaning session lasting 20 minutes in the corresponding solution. Then, a nitrogen gun is used to blow away the deionized water from the surface of the silicon wafer after the final deionized water solution, thereby obtaining a clean silicon wafer.

[0051] In the embodiments of this application, keeping the silicon wafer surface clean helps to deposit two-dimensional selenium with high quality, single crystal and nanoscale thickness.

[0052] In this embodiment of the application, in S1, a dual-temperature zone tube furnace is provided. The first temperature zone is located upstream of the gas inlet of the dual-temperature zone tube furnace, and the selenium source temperature is 340°C. The second temperature zone is located downstream of the gas inlet of the dual-temperature zone tube furnace, and the first substrate temperature is 120-150°C.

[0053] The dual-temperature zone tube furnace design enables independent temperature control of the selenium source evaporation and nanosheet growth processes. In the upstream furnace temperature zone, the selenium source fully sublimates at 340°C to form selenium vapor, which is then transported downstream with the carrier gas. In the downstream furnace temperature zone, the first substrate is maintained at a lower temperature of 120-150°C, providing a suitable nucleation and growth environment for the selenium vapor.

[0054] This temperature gradient setting ensures effective evaporation of the selenium source while avoiding excessive substrate temperature that could lead to overgrowth or polycrystalline phenomena in the nanosheets. This is beneficial for obtaining two-dimensional selenium nanosheets with uniform size and controllable thickness.

[0055] In the above process, the reaction time was initially set to 120 minutes, with the heating and cooling rates maintained at 5-10 °C / min. Before the reaction, the furnace tube was purged with pure Ar gas for 20 minutes to remove most of the air, at a flow rate of 400 sccm. Finally, single-crystal two-dimensional selenium nanosheets were deposited and grown on a silicon substrate, with a thickness of approximately 12-22 nm and a two-dimensional lateral width of 3-30 μm. Figure 3 Raman spectral characterization of medium- and two-dimensional selenium showed distinct peak positions. Figure 4Atomic force microscopy revealed that the synthesized two-dimensional selenium was approximately 18.8 nm thick, both indicating the successful synthesis of high-quality, nanoscale-thickness two-dimensional selenium. After the reaction, two-dimensional selenium nanosheets were deposited on a silicon wafer.

[0056] In this embodiment, in S2, the third temperature zone is located upstream of the gas inlet of the dual-temperature zone tube furnace, and the sulfur powder temperature is 160°C; the fourth temperature zone is located downstream of the gas inlet of the dual-temperature zone tube furnace, and the second substrate temperature is 750°C.

[0057] The synthesis of molybdenum disulfide mainly adopts chemical vapor deposition. Its synthesis equipment is the same as that used for the synthesis of two-dimensional selenium. Only the quartz tube needs to be replaced to carry out the deposition operation, which greatly reduces the demand for and cost of the equipment.

[0058] First, similar to the two-dimensional selenium synthesis process, the substrate silicon wafer is cleaned, and the same tube furnace is used in both cases. However, the difference between two-dimensional selenium synthesis and molybdenum disulfide synthesis lies in the temperature and the precursor. In molybdenum disulfide, approximately 0.1 mg of molybdenum trioxide is used as the molybdenum source. In this embodiment, the purity of molybdenum trioxide is 99.5%. At the same time, approximately 0.1 mg of sodium chloride with a purity of 99.5% is mixed into the molybdenum source to effectively reduce the deposition temperature of the generated molybdenum disulfide. The molybdenum trioxide is reduced and sulfided by sulfur vapor (S) at high temperature, and is converted into the target product molybdenum disulfide through a chemical reaction.

[0059] In the embodiments of this application, the sulfur vapor is approximately 10 mg of sublimed sulfur with a purity of 99.9%.

[0060] In the above reaction process, specifically, sulfur powder is placed in the upstream temperature zone, i.e., the third temperature zone, with the temperature controlled at 160°C. The silicon wafer substrate and molybdenum source are placed in the downstream temperature zone, i.e., the fourth temperature zone, with the temperature controlled at 750°C. The polished surface of the silicon wafer is inverted and positioned approximately 2-5 mm above the center of the molybdenum source. The carrier gas flow rate is set to 50 sccm, and the heating and cooling rates are controlled at 8-10°C / minute.

[0061] Ultimately, atomically thick molybdenum disulfide nanosheets with a thickness between 0.6 and 5 nm and a two-dimensional lateral width of 30 to 100 μm were deposited and grown on the silicon substrate. Figure 5 The Raman spectrum of molybdenum disulfide in the sample shows a clear peak position. Figure 6 The atomic force microscopy results showed that the synthesized molybdenum disulfide was 0.7 nm thick, indicating that high-quality nanoscale monolayer molybdenum disulfide had been successfully synthesized.

[0062] In this embodiment, in step S3, the two-dimensional selenium nanosheets are transferred by dry transfer using polydimethylsiloxane, and the molybdenum disulfide nanosheets are transferred by wet transfer using polymethyl methacrylate.

[0063] In the above structure, in the transfer process step S3 of the inverter fabrication, a dry transfer of two-dimensional selenium nanosheets is first performed using polydimethylsiloxane (PPC) assisted: a PPC film is attached to the surface of a first substrate on which two-dimensional selenium is grown, and the two-dimensional selenium nanosheets are attached to the PPC at a pick-up temperature of 36°C. Then, a high-precision micro-nano transfer platform is used to align and attach the two-dimensional selenium nanosheets to the predetermined position on the target substrate under an optical microscope. After that, the temperature is raised to 100°C to soften the PPC and release the two-dimensional selenium nanosheets. Finally, the residual PPC is removed by soaking in acetone solution, thus completing the transfer of two-dimensional selenium.

[0064] Then, a silicon wafer with a two-dimensional molybdenum selenide-disulfide surface obtained after transfer was used for photoresist spin coating. The spin coating speed was set to a low speed of 600 rpm and a high speed of 3000 rpm, and the wafer was heated for 4 minutes to solidify the photoresist. The desired electrode pattern was then etched onto the photoresist using electron beam exposure, with an electrode width of 2-4 micrometers and a channel length of 2-5 micrometers. The wafer was then immersed in the developer for 16 seconds and in the fixer for 40 seconds.

[0065] Chromium 15nm and gold 50nm were deposited at a stable rate of 5Å / min by thermal evaporation, and then the device was subjected to a stripping process. The annealing process involves heating for 9 hours in an inert gas atmosphere at a temperature of 100°C to optimize the contact performance between the metal and the semiconductor, while preventing device performance degradation.

[0066] Next, a wet transfer of molybdenum disulfide nanosheets was performed using polymethyl methacrylate (PMMA) assisted method: a PMMA adhesive layer was spin-coated onto the surface of a second substrate on which molybdenum disulfide was grown; the silica layer on the back side of the substrate was removed by etching with hydrofluoric acid solution, causing the composite film of PMMA and molybdenum disulfide to float on the liquid surface; the film was retrieved using a target substrate and precisely aligned under an optical microscope, so that the molybdenum disulfide nanosheets and the transferred two-dimensional selenium nanosheets were placed side by side and without overlap on the insulating gate layer 200; finally, the PMMA adhesive layer was dissolved and removed with acetone, achieving the non-destructive transfer of the molybdenum disulfide nanosheets, thereby completing the integration of the P-type transistor 300 and the N-type transistor 400 materials.

[0067] The inverters manufactured through the above-described process steps can be subjected to corresponding performance tests in this application. The testing process is as follows: First, its static voltage transfer characteristic curve was tested to verify its NOT gate logic function. Based on the principle of complementary metal-oxide-semiconductor (CMOS) circuits, when the input signal is low (i.e., when a large negative gate voltage is applied), the P-type two-dimensional selenium transistor is turned on while the N-type molybdenum disulfide transistor is turned off. At this time, the output voltage depends on the high-level voltage of the external power supply, i.e., V. out =V dd Conversely, when the input signal is high, i.e., when a large positive gate voltage is applied, the molybdenum disulfide transistor is turned on while the two-dimensional selenium transistor is turned off, and the output voltage signal is the voltage to ground, i.e., V. out =0V, test results are as follows Figure 7 The diagram clearly illustrates this inverting voltage transfer relationship, confirming that the device possesses complete NOT gate functionality. A peak switching power consumption point can be observed near the switching voltage of the inverter of this invention, which can be calculated using P=I. dd ×V dd The device can be obtained at V dd At 0.5V, the peak switching power consumption is only about 20pW, such as Figure 8 As shown, this result directly proves that the inverter prepared in this invention has excellent characteristics of ultra-low power consumption.

[0068] To further characterize the dynamic input / output logic function of the device of this invention, a high voltage at the input / output electrodes is defined as representing a logic signal "1", and a low voltage as representing "0". It exhibits a long-term and stable NOT gate logic output function under a square wave pulse voltage input signal, such as... Figure 9 As shown, this indicates that the two-dimensional selenium-molybdenum disulfide logic inverter of the present invention has potential applications in future silicon-based integrated circuits with high integration, low power consumption and long-term stability.

[0069] The above-disclosed embodiments are merely a few specific examples of the present invention. However, the embodiments of the present invention are not limited thereto, and any variations that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. An inverter based on two-dimensional selenium-molybdenum disulfide, characterized in that, include: Conductive substrate (100); An insulating gate layer (200) is located on the conductive substrate (100); P-type transistor (300), the channel region including two-dimensional selenium, the P-type transistor (300) is located on the insulating gate layer (200); N-type transistor (400), the channel region including molybdenum disulfide, the N-type transistor (400) is located on the insulating gate layer (200); The drains of the P-type transistor (300) and the N-type transistor (400) are electrically connected to each other, forming a complementary metal-oxide-semiconductor.

2. The inverter based on two-dimensional selenium-molybdenum disulfide according to claim 1, characterized in that, The conductive substrate (100) is P-type doped, and the conductive substrate (100) is configured as a common gate. The P-type transistor (300) and the N-type transistor (400) are provided with electrodes, the electrodes including a ground electrode (600) and an output electrode (500).

3. The inverter based on two-dimensional selenium-molybdenum disulfide according to claim 1, characterized in that, The two-dimensional selenium is configured as a single-crystal two-dimensional selenium nanosheet synthesized by physical vapor deposition. The molybdenum disulfide is configured as molybdenum disulfide nanosheets synthesized by chemical vapor deposition.

4. An inverter based on two-dimensional selenium-molybdenum disulfide according to claim 3, characterized in that, The two-dimensional selenium nanosheets and the molybdenum disulfide nanosheets are disposed on the insulating gate layer (200) at intervals.

5. A method for preparing an inverter as described in any one of claims 1-4, characterized in that, Includes the following steps: S1. Provide a first substrate, place a selenium source in a first temperature zone under a protective gas, place the first substrate in a second temperature zone, and grow two-dimensional selenium nanosheets on the first substrate through a physical vapor deposition process; S2. Provide a second substrate, place a sulfur source in a third temperature zone, place the second substrate and a molybdenum source in a fourth temperature zone, and grow molybdenum disulfide nanosheets on the second substrate through a chemical vapor deposition process; S3. The two-dimensional selenium nanosheets and the molybdenum disulfide nanosheets are assembled onto the insulating gate layer (200) of a target substrate by a transfer process to form a structure of a P-type transistor (300) and an N-type transistor (400), and the drain regions of the P-type transistor (300) and the N-type transistor (400) are electrically connected to each other. S4. Prepare metal electrodes on the assembled structure, and complete the fabrication of the inverter by combining them with a conductive substrate (100) and an insulating gate layer (200).

6. The preparation method according to claim 5, characterized in that, Both the first substrate and the second substrate are configured as silicon wafers.

7. The preparation method according to claim 5, characterized in that, In S1, a dual-temperature zone tubular furnace is provided, the first temperature zone is located upstream of the gas inlet of the dual-temperature zone tubular furnace, and the selenium source temperature is 340°C. The second temperature zone is located downstream of the gas inlet of the dual-temperature zone tube furnace, and the temperature of the first substrate is 120-150°C.

8. The preparation method according to claim 7, characterized in that, In S2, the third temperature zone is located upstream of the gas inlet of the dual-temperature zone tubular furnace, and the temperature of the sulfur source is 160°C. The fourth temperature zone is located downstream of the gas inlet of the dual-temperature zone tube furnace, and the second substrate temperature is 750°C.

9. The preparation method according to claim 5, characterized in that, In S2, sodium chloride is added to the molybdenum source, and the growth temperature is 740°C to 760°C.

10. The preparation method according to claim 5, characterized in that, In S3, the two-dimensional selenium nanosheets are transferred by dry transfer using polydimethylsiloxane, and the molybdenum disulfide nanosheets are transferred by wet transfer using polymethyl methacrylate.

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