A photoelectric detector and a preparation method thereof

Abstract

The application discloses a photoelectric detector and a preparation method thereof. The photoelectric detector comprises a substrate, first grooves are arranged on both sides of the substrate along a first direction, a band gap of the substrate on a side where the first grooves are arranged is less than or equal to a band gap of germanium, a first conductive type doped region and a second conductive type doped region are respectively arranged in the two first grooves, a band gap of the first conductive type doped region and the second conductive type doped region is greater than or equal to a band gap of silicon, a first electrode is arranged on a side of the first conductive type doped region away from the substrate, and the first electrode is in contact with the first conductive type doped region, and a second electrode is arranged on a side of the second conductive type doped region away from the substrate, and the second electrode is in contact with the second conductive type doped region. The application can reduce a dark current of a device, ensure consistency of the device and enhance integrability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a photodetector and its fabrication method. Background Technology

[0002] In recent years, short-wave infrared (SWIR) photodetectors have received widespread attention in fields such as night vision, optical communication, and industrial inspection. To balance performance and process compatibility, silicon (Si) / germanium (Ge) heterojunction photodetectors have become a research hotspot. In existing technologies, Si / Ge heterojunction photodetectors primarily employ a vertical structure. However, in vertical heterojunction structures, due to Si / Ge interface defects and impurity diffusion, the devices are prone to high dark currents, limiting the signal-to-noise ratio under low-light conditions. Furthermore, the use of traditional global epitaxy and global doping processes in vertical structures makes it difficult to precisely control the doping concentration of each vertically positioned layer, resulting in limited device performance consistency. Simultaneously, vertical structures are difficult to integrate with complementary metal-oxide-semiconductor (CMOS) processes at high density, hindering device miniaturization and array formation. Summary of the Invention

[0003] This invention provides a photodetector and its fabrication method to solve the problems of high dark current, poor device performance consistency, and difficulty in achieving high-density integration with CMOS technology in current photodetectors.

[0004] In a first aspect, the present invention provides a photodetector, the photodetector comprising: Substrate; along a first direction, first grooves are provided at intervals on both sides of the substrate; along a second direction, the bandgap width of the substrate on the side with the first grooves is less than or equal to the bandgap width of germanium; the first direction is perpendicular to the second direction; The first conductivity type doped region and the second conductivity type doped region are located in two first grooves, respectively; the band gap of the first conductivity type doped region and the second conductivity type doped region are greater than or equal to the band gap of silicon; the first conductivity type and the second conductivity type are different. The first electrode is located on the side of the first conductivity type doped region away from the substrate and is in contact with the first conductivity type doped region; the second electrode is located on the side of the second conductivity type doped region away from the substrate and is in contact with the second conductivity type doped region.

[0005] Optionally, the substrate includes a germanium substrate or a germanium-on-insulator substrate; The germanium substrate on an insulator includes a silicon substrate layer, an insulating substrate layer, and a germanium substrate layer. The insulating substrate layer is located on one side of the silicon substrate layer, and the germanium substrate layer is located on the side of the insulating substrate layer away from the silicon substrate layer. Along a first direction, first grooves are provided on both sides of the germanium substrate layer at intervals.

[0006] Optionally, the thickness of the germanium substrate layer ranges from 500nm to 1000nm; the depth of the first groove ranges from 50nm to 500nm; and the width of the first groove ranges from 100nm to 1000nm.

[0007] Optionally, the first conductivity type doped region includes a first conductivity type silicon doped region, and the second conductivity type doped region includes a second conductivity type silicon doped region.

[0008] Optionally, the doping concentration of the first conductivity type doped region is 1*10. 18 cm -3 -5*10 19 cm -3 The doping concentration of the second conductivity type doped region is 1*10. 18 cm -3 -5*10 19 cm -3 .

[0009] Optionally, the photodetector further includes: a passivation layer; The passivation layer is located on one side of the substrate. Along the first direction, first through grooves are provided on both sides of the passivation layer at intervals. The first through grooves penetrate the passivation layer. The vertical projection of the two first through grooves on the substrate is located within the vertical projection of the two first grooves on the substrate. The first electrode and the second electrode are located on the side of the passivation layer away from the substrate corresponding to the two first grooves, and are located in the two first through grooves, respectively.

[0010] Secondly, the present invention provides a method for fabricating a photodetector, the method comprising: A substrate is provided, wherein a first groove is provided on both sides of the substrate along a first direction; and the bandgap width of the substrate on the side with the first groove is less than or equal to the bandgap width of germanium along a second direction; the first direction is perpendicular to the second direction. A first conductivity type doped region and a second conductivity type doped region are formed in the two first grooves, respectively, and the band gap of the first conductivity type doped region and the second conductivity type doped region is greater than or equal to the band gap of silicon. A first electrode is formed on the side of the first conductivity type doped region away from the substrate, and the first electrode is in contact with the first conductivity type doped region; A second electrode is formed on the side of the second conductivity type doped region away from the substrate, and the second electrode is in contact with the second conductivity type doped region.

[0011] Optionally, a substrate is provided, comprising: Germanium substrates are provided; Using photolithography and etching processes, a first groove is formed at intervals on both sides of the germanium substrate along a first direction; Alternatively, a substrate may be provided, including: A germanium-on-insulator substrate is provided, comprising a silicon substrate layer, an insulating substrate layer, and a germanium substrate layer, wherein the insulating substrate layer is located on one side of the silicon substrate layer, and the germanium substrate layer is located on the side of the insulating substrate layer away from the silicon substrate layer; Using photolithography and etching processes, first grooves are formed at intervals on both sides of the germanium substrate along a first direction.

[0012] Optionally, a first conductivity type doped region and a second conductivity type doped region are formed in the two first grooves, respectively, including: Selective epitaxy is used to form a first silicon region and a second silicon region in two first grooves, respectively; Selective doping is used to dope a first silicon region to form a silicon doped region of a first conductivity type, and a second silicon region to form a silicon doped region of a second conductivity type.

[0013] Optionally, a selective epitaxial growth process is used to form a first silicon region and a second silicon region in the two first grooves, respectively, including: Selective epitaxy is employed, and silane and / or propane are used as silicon precursors during the epitaxy process to form a first silicon region and a second silicon region in two first grooves, respectively.

[0014] Optionally, after forming a first conductivity type doped region and a second conductivity type doped region in the two first grooves respectively, the method further includes: Annealing is performed on the intermediate of the photodetector having doped regions of the first conductivity type and the second conductivity type. A passivation layer is formed on one side of the substrate. Along the first direction, first through grooves are provided at intervals on both sides of the passivation layer. The first through grooves penetrate the passivation layer. The vertical projections of the two first through grooves on the substrate are respectively located within the vertical projections of the two first grooves on the substrate. A first electrode is formed on the side of the first conductivity type doped region away from the substrate, including: A first electrode is formed on the side of the passivation layer away from the substrate corresponding to the first conductivity type doped region, and a first through-hole is formed in the first conductivity type doped region. A second electrode is formed on the side of the second conductivity type doped region away from the substrate, including: A second electrode is formed on the side of the passivation layer away from the substrate corresponding to the doped region of the second conductivity type, and in the first through-groove corresponding to the doped region of the second conductivity type.

[0015] The technical solution of this invention involves forming a first groove on one side of a substrate, within which a first conductivity type doped region and a second conductivity type doped region are respectively formed. This creates a lateral PIN structure comprised of the first conductivity type doped region, the second conductivity type doped region, and the substrate between the first and second conductivity type doped regions, thus forming a photodetector with a horizontal double heterojunction structure. The first and second conductivity type doped regions are positioned horizontally, reducing their contact area with the substrate in region I. This effectively reduces the impact of interface defects and impurity diffusion, allowing the band barrier of the heterojunction to play a dominant role. By suppressing carrier tunneling and reverse injection through the barrier, the dark current of the device can be effectively reduced, and the signal-to-noise ratio can be improved. This invention utilizes photolithography and other processes for selected area epitaxy and selected area doping to form the first and second conductivity type doped regions. This allows for precise control of the junction doping concentration and geometry. The doping in each region of the PIN structure does not affect each other, ensuring the consistency and reliability of device performance in a large-area array. This improves the overall stability and durability of the photodetector array, significantly increases photoelectric response efficiency, and enhances detection performance under low-light conditions. The technical solutions of this invention are beneficial for device miniaturization and high-density integration. Compared with the existing vertical structure, the horizontal heterojunction structure has lower substrate dependence, is more compatible with CMOS process, and can realize closely arranged photodetector arrays, which is beneficial for high-resolution imaging systems and low-power integrated applications.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a photodetector provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another photodetector provided in an embodiment of the present invention; Figure 3 This is a flowchart of a method for fabricating a photodetector provided in an embodiment of the present invention; Figures 4-5 This is a schematic diagram of some steps in the fabrication method of a photodetector provided in an embodiment of the present invention; Figure 6 This is a flowchart of another method for fabricating a photodetector provided in an embodiment of the present invention; Figures 7-9 This is a schematic diagram of some steps in another method for fabricating a photodetector provided in an embodiment of the present invention. Figure 10 This is a flowchart of another method for fabricating a photodetector provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of some steps in a method for fabricating a photodetector provided in an embodiment of the present invention. Figure 12 This is a flowchart of another method for fabricating a photodetector provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Figure 1 This is a schematic diagram of the structure of a photodetector provided in an embodiment of the present invention, as shown below. Figure 1As shown, the photodetector includes: a substrate 1; first grooves 10 spaced apart on both sides of the substrate 1 along a first direction X. Along a second direction Y, the bandgap of the substrate 1 on the side with the first grooves 10 is less than or equal to the bandgap of germanium. The first direction X is perpendicular to the second direction Y. A first conductivity type doped region 21 and a second conductivity type doped region 22 are respectively located within the two first grooves 10, and the bandgap of the first conductivity type doped region 21 and the second conductivity type doped region 22 is greater than or equal to the bandgap of silicon. The first conductivity type and the second conductivity type are different. A first electrode 31 and a second electrode 32 are present. The first electrode 31 is located on the side of the first conductivity type doped region 21 away from the substrate 1 and is in contact with the first conductivity type doped region 21. The second electrode 32 is located on the side of the second conductivity type doped region 22 away from the substrate 1 and is in contact with the second conductivity type doped region 22.

[0022] Specifically, the photodetector may include a substrate 1, which can be a single-layer substrate made of a single material. For example, substrate 1 may include a germanium substrate. Substrate 1 may also be a multilayer substrate formed by bonding two or more different materials through a specific process. For example, substrate 1 may include a germanium-on-insulator (GOI) substrate. Two horizontal first grooves 10 may be spaced apart on one side of substrate 1. The side of substrate 1 with the first grooves 10 can be an intrinsic semiconductor layer and can serve as an absorption layer. When the photodetector is working, the side of substrate 1 with the first grooves 10 can absorb photons. The bandgap of the side of substrate 1 serving as the absorption layer can be less than or equal to the bandgap of germanium, thereby enabling the side of substrate 1 serving as the absorption layer to absorb a wider range of short-wave infrared light.

[0023] The photodetector may further include a first conductivity type doped region 21 and a second conductivity type doped region 22, as well as a first electrode 31 and a second electrode 32. The conductivity type of the first conductivity type doped region 21 may include N-type or P-type, and the doping type of the second conductivity type doped region 22 may include P-type or N-type. When the doping type of the first conductivity type doped region 21 is N-type, the doping type of the second conductivity type doped region 22 is P-type; conversely, when the doping type of the first conductivity type doped region 21 is P-type, the doping type of the second conductivity type doped region 22 is N-type.

[0024] The first conductivity type doped region 21 and the second conductivity type doped region 22 can be respectively disposed within two horizontal first grooves 10, and the band gap of the semiconductor material of the first conductivity type doped region 21 and the second conductivity type doped region 22 can be greater than or equal to the band gap of silicon. The first conductivity type doped region 21, the second conductivity type doped region 22, and the substrate 1 between the first conductivity type doped region 21 and the second conductivity type doped region 22 can form a horizontal PIN structure. The first conductivity type doped region 21 can form a heterojunction with the substrate 1 of region I, and the second conductivity type doped region 22 can also form a heterojunction with the substrate 1 of region I, thereby forming a horizontal double heterojunction structure. In this embodiment of the invention, the band gap of the semiconductor material of the first conductivity type doped region 21 and the second conductivity type doped region 22 is set to be greater than or equal to the band gap of silicon, which can ensure that the first conductivity type doped region 21 and the second conductivity type doped region 22 basically do not absorb photons, thereby enabling the substrate 1 of region I to efficiently absorb photons. The first conductivity type doped region 21 and the second conductivity type doped region 22 can be formed by selective epitaxy and selective doping using processes such as photolithography. When the first conductivity type doped region 21 is doped, the doping process will not affect the substrate 1 of the horizontally set I region and the second conductivity type doped region 22. Similarly, when the second conductivity type doped region 22 is doped, the doping process will not affect the substrate 1 of the horizontally set I region and the first conductivity type doped region 21.

[0025] A first electrode 31 may be provided on the side of the first conductivity type doped region 21 away from the substrate 1. The first electrode 31 may be electrically connected to the first conductivity type doped region 21. A second electrode 32 may be provided on the side of the second conductivity type doped region 22 away from the substrate 1. The second electrode 32 may be electrically connected to the second conductivity type doped region 22. When the photodetector is working, the first electrode 31 and the second electrode 32 can be externally connected to a reverse bias voltage. The substrate 1 in region I can absorb short-wave infrared light. Photons penetrate into the interior of the substrate 1 in region I, thereby generating electron-hole pairs inside the substrate 1 in region I. Under the action of the strong electric field established by the external reverse bias voltage, electrons and holes are pulled towards the N-type doped region and the P-type doped region, respectively. For example, the first conductivity type doped region 21 is P-type doped and the second conductivity type doped region 22 is N-type doped. At this time, electrons are pulled towards the second conductivity type doped region 22 and holes are pulled towards the first conductivity type doped region 21, so that holes and electrons are collected by the first electrode 31 and the second electrode 32, respectively, thereby forming a detectable photocurrent in the external circuit.

[0026] The technical solution of this invention involves forming a first groove 10 on one side of a substrate 1, and then forming a first conductivity type doped region 21 and a second conductivity type doped region 22 within the first groove 10. This creates a lateral PIN structure formed by the first conductivity type doped region 21, the second conductivity type doped region 22, and the substrate 1 between the first and second conductivity type doped regions 21 and 22, thus forming a photodetector with a horizontal double heterojunction structure. The first conductivity type doped region 21 and the second conductivity type doped region 22 are arranged horizontally, reducing their contact area with the substrate 1 in region I. This effectively reduces the influence of interface defects and impurity diffusion, allowing the band barrier of the heterojunction to play a dominant role. By suppressing carrier tunneling and reverse injection through the barrier, the dark current of the device can be effectively reduced and the signal-to-noise ratio improved. This invention utilizes photolithography and other processes to perform selected-area epitaxy and selected-area doping to form a first conductivity type doped region 21 and a second conductivity type doped region 22. This allows for precise control of the junction doping concentration and geometry. The doping in each region of the PIN structure does not interfere with each other, ensuring consistent device performance and reliability in large-area arrays. This improves the overall stability and durability of the photodetector array, significantly enhances photoelectric response efficiency, and improves detection performance under low-light conditions. The technical solution of this invention facilitates device miniaturization and high-density integration. Compared to existing vertical structures, the horizontal heterojunction structure has lower substrate dependence, is more compatible with CMOS processes, and enables tightly packed photodetector arrays, which is beneficial for high-resolution imaging systems and low-power integrated applications.

[0027] The technical solutions of this invention provide effective technical support for SWIR photodetectors in applications such as high-performance optical imaging, night vision, optical communication, and industrial inspection. By reducing dark current, improving response speed, and enhancing integrability, this invention offers significant advantages in performance optimization, process controllability, and practical application value. In summary, this invention, through innovative horizontal double heterojunction design and precise local process control, overcomes the shortcomings of existing technologies in terms of high dark current, limited device integration, and insufficient process flexibility, achieving a high-performance, integrable, and arrayable short-wave infrared photodetector with significant technological advancement and application potential.

[0028] Optionally, based on the above embodiments, Figure 2 This is a schematic diagram of another photodetector provided in an embodiment of the present invention, as shown below. Figure 1 and Figure 2As shown, substrate 1 includes a germanium substrate or a germanium-on-insulator substrate 20. The germanium-on-insulator substrate 20 includes a silicon substrate layer 11, an insulating substrate layer 12, and a germanium substrate layer 13. The insulating substrate layer 12 is located on one side of the silicon substrate layer 11, and the germanium substrate layer 13 is located on the side of the insulating substrate layer 12 away from the silicon substrate layer 11. Along the first direction X, first grooves 10 are provided at intervals on both sides of the germanium substrate layer 13.

[0029] Specifically, the substrate 1 of the photodetector provided in this embodiment of the invention can be a single-layer germanium substrate or a germanium-on-insulator (GOI) substrate 20. The GOI substrate 20 can include a silicon substrate layer 11, an insulating substrate layer 12, and a germanium substrate layer 13. The insulating substrate layer 12 can include a silicon dioxide substrate layer. The germanium substrate layer 13 in the GOI substrate 20 can serve as an absorption layer. The germanium substrate layer 13 can be provided with two first grooves 10 at intervals. The first conductivity type doped region 21, the second conductivity type doped region 22, and the germanium substrate layer 13 between the first conductivity type doped region 21 and the second conductivity type doped region 22 can form a horizontal PIN structure, thereby forming a photodetector with a horizontal double heterojunction structure.

[0030] The substrate 1 of the photodetector provided in this embodiment of the invention may include a germanium-on-insulator substrate 20, which can provide effective electrical and thermal isolation for the device, significantly reduce the parasitic current of the device, improve the signal-to-noise ratio, and provide a basis for high-sensitivity detection.

[0031] Optionally, based on the above embodiments, refer to... Figure 2 The thickness of the germanium substrate 13 ranges from 500nm to 1000nm; the depth of the first groove 10 ranges from 50nm to 500nm; and the width of the first groove 10 ranges from 100nm to 1000nm.

[0032] Specifically, substrate 1 may include a germanium-on-insulator (GeOI) substrate 20. The thickness of the germanium substrate layer 13 of the GeOI substrate 20 can be set to 500nm-1000nm. The thickness design of the germanium substrate layer 13 takes into account both the requirements of light absorption efficiency and device structure control. The thickness setting of the germanium substrate layer 13 in this embodiment of the invention ensures that short-wave infrared light is fully absorbed in the germanium substrate layer 13, improving photoelectric conversion efficiency, while maintaining mechanical stability and process controllability during wafer processing. In addition, the GeOI substrate 20 can provide a high-quality insulating substrate layer 12, effectively reducing parasitic capacitance, which is conducive to the subsequent formation of horizontal double heterojunction structures and CMOS-compatible integration, laying the foundation for realizing high-performance, low dark current photodetectors.

[0033] Two horizontal first grooves 10 can be etched at intervals on one side of the germanium substrate 13 using photolithography and etching processes. These first grooves 10 are used to subsequently form a first conductivity type doped region 21 and a second conductivity type doped region 22. The placement of the first grooves 10 not only clearly defines the position and geometry of the first conductivity type doped region 21 and the second conductivity type doped region 22, but also provides precise spatial constraints for the selected area epitaxy and selected area doping processes, thereby achieving localized doping control. By forming the first grooves 10 on both sides of the germanium substrate 13, the influence of interface defects on the device's dark current can be effectively reduced, while ensuring the symmetry and uniformity of the horizontal double heterojunction, improving device performance consistency. Furthermore, the groove structure facilitates close contact between the doped region and the absorption layer, optimizing photoelectric carrier collection efficiency and laying the foundation for achieving high-response speed and low-noise photodetectors.

[0034] In this embodiment of the invention, the depth of the first groove 10 is set to 50nm-500nm, and the width of the first groove 10 is set to 100nm-1000nm. This ensures sufficient absorption of short-wave infrared light by the germanium substrate 13, improving photoelectric conversion efficiency, while also precisely defining the positions of the first conductivity type doped region 21 and the second conductivity type doped region 22, ensuring the geometric uniformity and symmetry of the horizontal double heterojunction. Simultaneously, the groove structure enhances the tight bonding between the first conductivity type doped region 21 and the second conductivity type doped region 22 and the germanium substrate 13, improving photocarrier collection efficiency and reducing interface defects and dark current. Furthermore, this size range is suitable for existing micro / nano fabrication processes, compatible with selected area epitaxy and selected area doping processes, providing controllability and flexibility for device arraying and CMOS integration.

[0035] In some embodiments of the present invention, the thickness of the germanium substrate 13 can be arbitrarily set, and can be less than 500 nm or greater than 1000 nm, without specific limitation. The depth of the first groove 10 can be less than 50 nm or greater than 500 nm, and the width of the first groove 10 can be less than 100 nm or greater than 1000 nm, without specific limitation.

[0036] Optionally, based on the above embodiments, refer to... Figure 1 and Figure 2 The first conductivity type doped region 21 includes a first conductivity type silicon doped region, and the second conductivity type doped region 22 includes a second conductivity type silicon doped region.

[0037] Specifically, silicon can be used as the material for both the first conductivity type doped region 21 and the second conductivity type doped region 22. The semiconductor materials of both regions have relatively wide band gaps, ensuring that they essentially do not absorb photons. This allows the substrate 1 in region I to efficiently absorb photons, avoiding ineffective absorption and optical losses by the first and second conductivity type doped regions 21 and 22, thereby improving the optical absorption efficiency and quantum efficiency of the device. Simultaneously, a PIN structure is constructed using mature silicon doping technology and its low dark current characteristics, and dark current is suppressed through a heterojunction band barrier, achieving a synergistic optimization of high responsivity and low noise.

[0038] In existing technologies, the heterojunction contact area in vertical structures is large, which significantly increases the total number of interface defects and the degree of impurity diffusion, introducing more recombination centers and leakage channels, leading to an increase in dark current. However, when the embodiments of the present invention use a smaller contact area, the influence of interface defects and impurity diffusion can be effectively reduced, allowing the band barrier of the heterojunction to play a dominant role. By suppressing carrier tunneling and reverse injection through the barrier, the dark current can be effectively suppressed.

[0039] Optionally, based on the above embodiments, refer to... Figure 1 and Figure 2 The doping concentration of the first conductivity type doped region 21 is 1*10. 18 cm -3 -5*10 19 cm -3 The doping concentration of the second conductivity type doped region 22 is 1*10. 18 cm -3 -5*10 19 cm -3 .

[0040] Specifically, the doping concentration of both the first conductivity type doped region 21 and the second conductivity type doped region 22 can be set to 1*10. 18 cm -3 -5*10 19 cm -3 Set the doping concentration to 1*10 18 cm -3 -5*10 19 cm -3 Within a certain range, it can effectively drive the separation of photogenerated carriers, improving photoelectric response efficiency, while avoiding excessive doping that could lead to carrier recombination and increased junction defects. The embodiments of this invention can effectively reduce dark current and maintain consistent device performance. Simultaneously, the doping concentration range takes into account CMOS process feasibility, providing controllability and reliability for large-area arrays and integrated applications.

[0041] Optionally, based on the above embodiments, refer to... Figures 1-2 The photodetector also includes a passivation layer 4. The passivation layer 4 is located on one side of the substrate 1, and along the first direction X, first through-grooves 40 are spaced apart on both sides of the passivation layer 4, penetrating the passivation layer 4. The vertical projections of the two first through-grooves 40 onto the substrate 1 lie within the vertical projections of the two first grooves 10 onto the substrate 1. The first electrode 31 and the second electrode 32 are respectively located on the side of the passivation layer 4 corresponding to the two first grooves 10 away from the substrate 1, and are respectively located within the two first through-grooves 40.

[0042] Specifically, a passivation layer 4 is disposed on one side of the substrate 1 and on the side of the first conductivity type doped region 21 and the second conductivity type doped region 22 away from the substrate 1. For example, the passivation layer 4 may include a silicon oxide passivation layer and / or a silicon nitride passivation layer. The passivation layer 4 can perform surface passivation to reduce interface state density and surface recombination, thereby improving device stability and lifetime. The passivation layer 4 may have two first through-channels 40, one located on the side of the first conductivity type doped region 21 away from the substrate 1, and the other located on the side of the second conductivity type doped region 22 away from the substrate 1. The first electrode 31 may be located on the side of the passivation layer 4 corresponding to the first conductivity type doped region 21 away from the substrate 1, and within the first through-channel 40 on the side of the first conductivity type doped region 21 away from the substrate 1. The first electrode 31 is electrically connected to the first conductivity type doped region 21. The second electrode 32 can be located on the side of the passivation layer 4 corresponding to the second conductivity type doped region 22 away from the substrate 1, and is located in the first through groove 40 on the side of the second conductivity type doped region 22 away from the substrate 1. The second electrode 32 is electrically connected to the second conductivity type doped region 22.

[0043] Figure 3 This is a flowchart of a method for fabricating a photodetector according to an embodiment of the present invention. Figures 4-5 This is a schematic diagram of some steps in a method for fabricating a photodetector provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the preparation method includes: S100: A substrate is provided, wherein a first groove is provided on both sides of the substrate along a first direction; and the bandgap width of the substrate on the side with the first groove is less than or equal to the bandgap width of germanium along a second direction; the first direction is perpendicular to the second direction.

[0044] Specifically, such as Figure 4As shown, a substrate 1 is first provided. Substrate 1 can be a single-layer substrate made of a single material; for example, substrate 1 may include a germanium substrate. Substrate 1 can also be a multilayer substrate formed by bonding two or more different materials through a specific process; for example, substrate 1 may include a germanium-on-insulator (GOI) substrate. Two horizontal first grooves 10 can be spaced apart on one side of substrate 1. The side of substrate 1 with the first grooves 10 can be an intrinsic semiconductor layer and can serve as an absorption layer. When the photodetector is working, the side of substrate 1 with the first grooves 10 can absorb photons. The bandgap of the side of substrate 1 serving as the absorption layer can be less than or equal to the bandgap of germanium, thereby enabling the side of substrate 1 serving as the absorption layer to absorb short-wave infrared light over a wider wavelength range.

[0045] S110: A first conductivity type doped region and a second conductivity type doped region are formed in the two first grooves respectively, and the band gap of the first conductivity type doped region and the second conductivity type doped region is greater than or equal to the band gap of silicon.

[0046] Specifically, such as Figure 5 As shown, a first conductivity type doped region 21 and a second conductivity type doped region 22 are then formed in the two first grooves 10, respectively. The conductivity type of the first conductivity type doped region 21 can include N-type or P-type, and the doping type of the second conductivity type doped region 22 can include P-type or N-type. When the doping type of the first conductivity type doped region 21 is N-type, the doping type of the second conductivity type doped region 22 is P-type; when the doping type of the first conductivity type doped region 21 is P-type, the doping type of the second conductivity type doped region 22 is N-type.

[0047] The first conductivity type doped region 21, the second conductivity type doped region 22, and the substrate 1 between the first conductivity type doped region 21 and the second conductivity type doped region 22 can form a horizontal PIN structure. The first conductivity type doped region 21 can form a heterojunction with the substrate 1 in region I, and the second conductivity type doped region 22 can also form a heterojunction with the substrate 1 in region I, thereby forming a horizontal double heterojunction structure. In this embodiment of the invention, the bandgap of the semiconductor material of the first conductivity type doped region 21 and the second conductivity type doped region 22 is set to be greater than or equal to the bandgap of silicon, which can ensure that the first conductivity type doped region 21 and the second conductivity type doped region 22 basically do not absorb photons, thereby enabling the substrate 1 in region I to efficiently absorb photons. The first conductivity type doped region 21 and the second conductivity type doped region 22 can be formed by selective epitaxy and selective doping using processes such as photolithography. When the first conductivity type doped region 21 is doped, the doping process will not affect the substrate 1 of the horizontally set I region and the second conductivity type doped region 22. Similarly, when the second conductivity type doped region 22 is doped, the doping process will not affect the substrate 1 of the horizontally set I region and the first conductivity type doped region 21.

[0048] S120: A first electrode is formed on the side of the first conductivity type doped region away from the substrate, and the first electrode is in contact with the first conductivity type doped region.

[0049] Specifically, such as Figure 1 As shown, a first electrode 31 is formed on the side of the first conductivity type doped region 21 away from the substrate 1, and the first electrode 31 can be electrically connected to the first conductivity type doped region 21.

[0050] S130: A second electrode is formed on the side of the second conductivity type doped region away from the substrate, and the second electrode is in contact with the second conductivity type doped region.

[0051] Specifically, such as Figure 1 As shown, a second electrode 32 is formed on the side of the second conductivity type doped region 22 away from the substrate 1, and the second electrode 32 can be electrically connected to the second conductivity type doped region 22.

[0052] The technical solution of this invention involves forming a first groove 10 on one side of a substrate 1, and forming a first conductivity type doped region 21 and a second conductivity type doped region 22 within the first groove 10. This forms a lateral PIN structure composed of the first conductivity type doped region 21, the second conductivity type doped region 22, and the substrate 1 between the first and second conductivity type doped regions 21 and 22, thus forming a photodetector with a horizontal double heterojunction structure. The first conductivity type doped region 21 and the second conductivity type doped region 22 are arranged horizontally, reducing their contact area with the substrate 1 in region I. This effectively reduces the influence of interface defects and impurity diffusion, allowing the band barrier of the heterojunction to play a dominant role. By suppressing carrier tunneling and reverse injection through the barrier, the dark current of the device can be effectively reduced and the signal-to-noise ratio improved. This invention utilizes photolithography and other processes to perform selected-area epitaxy and selected-area doping to form a first conductivity type doped region 21 and a second conductivity type doped region 22. This allows for precise control of the junction doping concentration and geometry. The doping in each region of the PIN structure does not interfere with each other, ensuring consistent device performance and reliability in large-area arrays, thereby improving the overall stability and durability of the photodetector array. The technical solution of this invention facilitates device miniaturization and high-density integration. Compared to existing vertical structures, the horizontal heterojunction structure has lower substrate dependence, is more compatible with CMOS processes, and enables tightly packed photodetector arrays, which is beneficial for high-resolution imaging systems and low-power integrated applications.

[0053] Optionally, based on the above embodiments, Figure 6 This is a flowchart of another method for fabricating a photodetector provided in an embodiment of the present invention. Figures 7-9 This is a schematic diagram of some steps in another method for fabricating a photodetector provided in this embodiment of the invention, as shown below. Figure 6 As shown, the preparation method includes: S200: Provide a germanium substrate; or, provide a germanium-on-insulator substrate, the germanium-on-insulator substrate comprising a silicon substrate layer, an insulating substrate layer and a germanium substrate layer, the insulating substrate layer being located on one side of the silicon substrate layer and the germanium substrate layer being located on the side of the insulating substrate layer away from the silicon substrate layer.

[0054] Specifically, such as Figure 4 and Figure 7 As shown, in fabricating a photodetector, a single-layer germanium substrate can be provided, or a germanium-on-insulator (GOI) substrate 20 can be provided. The GOI substrate 20 may include a silicon substrate layer 11, an insulating substrate layer 12, and a germanium substrate layer 13. The insulating substrate layer 12 may include a silicon dioxide substrate layer. The germanium substrate layer 13 in the GOI substrate 20 can serve as an absorption layer.

[0055] The thickness of the germanium substrate layer 13 of the germanium-on-insulator substrate 20 can be set to 500nm-1000nm. The thickness design of the germanium substrate layer 13 takes into account both the requirements of light absorption efficiency and device structure control. The thickness setting of the germanium substrate layer 13 in this embodiment of the invention ensures that short-wave infrared light is fully absorbed in the germanium substrate layer 13, improving photoelectric conversion efficiency, while maintaining mechanical stability and process controllability during wafer fabrication. In addition, the germanium-on-insulator substrate 20 can provide a high-quality insulating substrate layer 12, effectively reducing parasitic capacitance, which is conducive to the subsequent formation of horizontal double heterojunction structures and CMOS-compatible integration, laying the foundation for realizing high-performance, low dark current photodetectors.

[0056] S210: Using photolithography and etching processes, a first groove is formed at intervals on both sides of a germanium substrate along a first direction; or, using photolithography and etching processes, a first groove is formed at intervals on both sides of a germanium substrate layer along a first direction.

[0057] Specifically, such as Figure 4 and Figure 8 As shown, after providing a single-layer germanium substrate, a mask layer can be formed on the entire side of the germanium substrate. For example, the mask layer may include silicon oxide, silicon nitride, and / or photoresist, etc. Then, the mask layer is patterned using photolithography or other processes. The patterned mask layer can expose the area corresponding to the first groove 10. Then, the germanium substrate is etched using the mask layer as a mask to form the first groove 10. Alternatively, after providing a GOI substrate, a mask layer can be formed on the entire side of the germanium substrate layer 13 away from the silicon substrate layer 11. For example, the mask layer may include a silicon oxide layer, a silicon nitride layer, and / or a photoresist layer, etc. Then, the mask layer is patterned using photolithography or other processes. The patterned mask layer can expose the area corresponding to the first groove 10. Then, the germanium substrate layer 13 is etched using the mask layer as a mask to form the first groove 10.

[0058] Two horizontal first grooves 10 can be etched at intervals on one side of the germanium substrate 13 using photolithography and etching processes. These first grooves 10 are used to subsequently form first and second conductivity type doped regions. The placement of the first grooves 10 not only clearly defines the position and geometry of the first and second conductivity type doped regions but also provides precise spatial constraints for the selected epitaxial growth and selected doping processes, thereby achieving localized doping control. By forming the first grooves 10 on both sides of the germanium substrate 13, the influence of interface defects on the device's dark current can be effectively reduced, while ensuring the symmetry and uniformity of the horizontal double heterojunction, improving device performance consistency. Furthermore, the groove structure facilitates close contact between the doped regions and the absorption layer, optimizing photoelectric carrier collection efficiency and laying the foundation for achieving high-response speed and low-noise photodetectors.

[0059] S220: A first conductivity type doped region and a second conductivity type doped region are formed in the two first grooves respectively, and the band gap of the first conductivity type doped region and the second conductivity type doped region is greater than or equal to the band gap of silicon.

[0060] S230: A first electrode is formed on the side of the first conductivity type doped region away from the substrate, and the first electrode is in contact with the first conductivity type doped region.

[0061] S240: A second electrode is formed on the side of the second conductivity type doped region away from the substrate, and the second electrode is in contact with the second conductivity type doped region.

[0062] Optionally, based on the above embodiments, Figure 10 This is a flowchart of another method for fabricating a photodetector provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of some steps in a method for fabricating a photodetector provided in another embodiment of the present invention, as shown below. Figure 10 As shown, the preparation method includes: S300: A substrate is provided, wherein a first groove is provided on both sides of the substrate along a first direction; and the bandgap width of the substrate on the side with the first groove is less than or equal to the bandgap width of germanium along a second direction; the first direction is perpendicular to the second direction.

[0063] S310: Selective epitaxy process is used to form a first silicon region and a second silicon region in two first grooves respectively.

[0064] Specifically, such as Figure 11 As shown, after etching the substrate 1 to form the first groove 10, a selected area epitaxial growth process can be used to form a first silicon region 23 and a second silicon region 24 within the two first grooves 10, respectively. For example, a mask layer can be first formed on the side of the germanium substrate layer 13 away from the silicon substrate layer 11 and throughout the first groove 10. The mask layer may include a photoresist layer, a silicon oxide layer, and / or a silicon nitride layer, etc. Then, the mask layer is patterned using photolithography or other processes to remove the mask layer within the first groove 10. The first silicon region 23 and the second silicon region 24 are then epitaxially formed inside and outside the first grooves 10 using the mask layer as a mask; that is, the first silicon region 23 and the second silicon region 24 are grown through selected area epitaxy. This embodiment of the invention achieves precise positioning and high-quality junction formation of the first conductivity type doped region and the second conductivity type doped region through local epitaxial growth.

[0065] Optionally, silane (Si2H6) and / or propane (Si3H8) can be used as silicon precursors during epitaxy. In this embodiment of the invention, the first silicon region 23 and the second silicon region 24 in the first groove 10 are formed by selective epitaxial growth. During the epitaxy process, gas source materials such as Si2H6 and / or Si3H8 are selected as silicon precursors. The design consideration is to achieve low-temperature epitaxial growth, effectively avoid high temperature causing lattice damage or stress to the substrate 1 (germanium substrate layer 13) on the side where the first groove 10 is formed, thereby maintaining the crystal quality and photoelectric performance of the germanium substrate layer 13, ensuring the geometric accuracy and material integrity of the junction region, reducing interface defects, improving photoelectric response efficiency, and being compatible with CMOS technology. This provides a feasible path for miniaturization and array applications, and provides a reliable foundation for forming the first conductivity type doped region and the second conductivity type doped region of a high-performance horizontal double heterojunction.

[0066] S320: Selective doping is used to dope a first silicon region to form a silicon doped region of a first conductivity type, and a second silicon region to form a silicon doped region of a second conductivity type. The band gap of the first and second conductivity type doped regions is greater than or equal to the band gap of silicon.

[0067] Specifically, such as Figure 11 and Figure 9 As shown, a selective doping process is used to dope the first silicon region 23 to form a first conductivity type silicon doped region 21, and to dope the second silicon region 24 to form a second conductivity type silicon doped region 22. For example, a mask layer can be formed on the side of the germanium substrate 13 away from the silicon substrate 11, and on the sides of the first silicon region 23 and the second silicon region 24 away from the silicon substrate 11. The mask layer may include a photoresist layer, a silicon oxide layer, and / or a silicon nitride layer, etc. Then, the mask layer is patterned using photolithography or other processes. The patterned mask layer exposes the first silicon region 23 and the second silicon region 24. Using the mask layer as a mask, the first conductivity type is doped into the first silicon region 23, and the second conductivity type is doped into the second silicon region 24. This selective doping method is used to precisely form the P-type and N-type silicon regions of a horizontal double heterojunction. This step achieves fine adjustment of the electrical characteristics and geometry of the junction region through localized doping control.

[0068] In this embodiment of the invention, the absorption layer is a germanium absorption layer, and the doping region is a silicon doping region. This ensures that the first conductivity type doping region 21 and the second conductivity type doping region 22 basically do not absorb photons, thereby enabling the substrate 1 in region I to efficiently absorb photons. This avoids ineffective absorption and optical loss of photons by the first conductivity type doping region 21 and the second conductivity type doping region 22, thereby improving the optical absorption efficiency and quantum efficiency of the device. Simultaneously, a PIN structure is constructed using mature silicon doping technology and low dark current characteristics, and dark current is suppressed through the heterojunction band barrier, achieving synergistic optimization of high responsivity and low noise.

[0069] S330: A first electrode is formed on the side of the first conductivity type doped region away from the substrate, and the first electrode is in contact with the first conductivity type doped region.

[0070] S340: A second electrode is formed on the side of the second conductivity type doped region away from the substrate, and the second electrode is in contact with the second conductivity type doped region.

[0071] Optionally, based on the above embodiments, Figure 12 This is a flowchart of another method for fabricating a photodetector provided in an embodiment of the present invention, as shown below. Figure 12 As shown, the preparation method includes: S400: A substrate is provided, wherein a first groove is provided on both sides of the substrate along a first direction; and the bandgap width of the substrate on the side with the first groove is less than or equal to the bandgap width of germanium along a second direction; the first direction is perpendicular to the second direction.

[0072] S410: A first conductivity type doped region and a second conductivity type doped region are formed in the two first grooves respectively, and the band gap of the first conductivity type doped region and the second conductivity type doped region is greater than or equal to the band gap of silicon.

[0073] S420: Annealing is performed on the intermediate of the photodetector having a first conductivity type doped region and a second conductivity type doped region.

[0074] Specifically, such as Figure 5 and Figure 9 As shown, after doping is completed, the device is subjected to high-temperature annealing to activate the doping and repair lattice defects.

[0075] S430: A passivation layer is formed on one side of the substrate. Along the first direction, first through grooves are provided on both sides of the passivation layer at intervals. The first through grooves penetrate the passivation layer. The vertical projection of the two first through grooves on the substrate is located within the vertical projection of the two first grooves on the substrate.

[0076] Specifically, such as Figure 1 and Figure 2As shown, a passivation layer 4 is formed on one side of the substrate 1 and on the side of the first conductivity type doped region 21 and the second conductivity type doped region 22 away from the substrate 1. Exemplarily, the passivation layer 4 may include a silicon oxide passivation layer and / or a silicon nitride passivation layer. The passivation layer 4 can perform surface passivation to reduce interface state density and surface recombination, thereby improving device stability and lifetime.

[0077] The passivation layer 4 may be provided with two first through grooves 40. One first through groove 40 is located on the side of the first conductivity type doped region 21 away from the substrate 1, and the other first through groove 40 may be located on the side of the second conductivity type doped region 22 away from the substrate 1.

[0078] S440: A first electrode is formed on the side of the passivation layer away from the substrate corresponding to the first conductivity type doped region, and in the first through-groove corresponding to the first conductivity type doped region.

[0079] Specifically, such as Figure 1 and Figure 2 As shown, a passivation layer 4 corresponding to the first conductivity type doped region 21 is located on the side away from the substrate 1, and a first electrode 31 is formed in the first through-groove 40 corresponding to the first conductivity type doped region 21. The first electrode 31 is electrically connected to the first conductivity type doped region 21.

[0080] S450: A second electrode is formed on the side of the passivation layer away from the substrate corresponding to the doped region of the second conductivity type, and in the first through-groove corresponding to the doped region of the second conductivity type.

[0081] Specifically, such as Figure 1 and Figure 2 As shown, a passivation layer 4 corresponding to the second conductivity type doped region 22 is located on the side away from the substrate 1, and a second electrode 32 is formed in the first through-groove 40 corresponding to the second conductivity type doped region 22. The second electrode 32 is electrically connected to the second conductivity type doped region 22.

[0082] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0083] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A photodetector, characterized in that, include: Substrate; Along a first direction, first grooves are provided at intervals on both sides of the substrate; along a second direction, the bandgap width of the substrate on the side with the first groove is less than or equal to the bandgap width of germanium; the first direction is perpendicular to the second direction. A first conductivity type doped region and a second conductivity type doped region are respectively located within two first grooves; the band gap widths of the first conductivity type doped region and the second conductivity type doped region are greater than or equal to the band gap width of silicon; the first conductivity type is different from the second conductivity type. A first electrode and a second electrode, wherein the first electrode is located on the side of the first conductivity type doped region away from the substrate and is in contact with the first conductivity type doped region; and the second electrode is located on the side of the second conductivity type doped region away from the substrate and is in contact with the second conductivity type doped region.

2. The photodetector according to claim 1, characterized in that, The substrate includes a germanium substrate or a germanium-on-insulator substrate; The germanium substrate on an insulator includes a silicon substrate layer, an insulating substrate layer, and a germanium substrate layer. The insulating substrate layer is located on one side of the silicon substrate layer, and the germanium substrate layer is located on the side of the insulating substrate layer away from the silicon substrate layer. Along the first direction, the first groove is provided at intervals on both sides of the germanium substrate layer.

3. The photodetector according to claim 2, characterized in that, The thickness of the germanium substrate layer ranges from 500nm to 1000nm; the depth of the first groove ranges from 50nm to 500nm; and the width of the first groove ranges from 100nm to 1000nm.

4. The photodetector according to claim 1, characterized in that, The first conductivity type doped region includes a first conductivity type silicon doped region, and the second conductivity type doped region includes a second conductivity type silicon doped region.

5. The photodetector according to claim 1, characterized in that, The first conductive type doped region has a doping concentration of 1*10 18 cm -3 -5*10 19 cm -3 ; and the second conductive type doped region has a doping concentration of 1*10 18 cm -3 -5*10 19 cm -3 .

6. The photodetector according to claim 1, characterized in that, Also includes: passivation layer; The passivation layer is located on one side of the substrate. Along the first direction, first through grooves are provided on both sides of the passivation layer at intervals, and the first through grooves penetrate the passivation layer. The vertical projection of the two first through grooves on the substrate is located within the vertical projection of the two first grooves on the substrate. The first electrode and the second electrode are respectively located on the side of the passivation layer away from the substrate corresponding to the two first grooves, and are respectively located in the two first through grooves.

7. A method for fabricating a photodetector, characterized in that, include: A substrate is provided, wherein a first groove is provided at intervals on both sides of the substrate along a first direction; Along the second direction, the bandgap width of the substrate on the side where the first groove is provided is less than or equal to the bandgap width of germanium; the first direction is perpendicular to the second direction; A first conductivity type doped region and a second conductivity type doped region are respectively formed in the two first grooves, and the band gap of the first conductivity type doped region and the second conductivity type doped region is greater than or equal to the band gap of silicon. A first electrode is formed on the side of the first conductivity type doped region away from the substrate, and the first electrode is in contact with the first conductivity type doped region; A second electrode is formed on the side of the second conductivity type doped region away from the substrate, and the second electrode is in contact with the second conductivity type doped region.

8. The method for fabricating a photodetector according to claim 7, characterized in that, Provide a substrate, including: Germanium substrates are provided; Using photolithography and etching processes, the first groove is formed at intervals on both sides of the germanium substrate along the first direction; Alternatively, a substrate may be provided, including: A germanium-on-insulator substrate is provided, the germanium-on-insulator substrate comprising a silicon substrate layer, an insulating substrate layer and a germanium substrate layer, wherein the insulating substrate layer is located on one side of the silicon substrate layer and the germanium substrate layer is located on the side of the insulating substrate layer away from the silicon substrate layer; The first groove is formed at intervals on both sides of the germanium substrate along the first direction using photolithography and etching processes.

9. The method for fabricating a photodetector according to claim 7, characterized in that, A first conductivity type doped region and a second conductivity type doped region are respectively formed in the two first grooves, including: Using a selective epitaxial growth process, a first silicon region and a second silicon region are formed in the two first grooves, respectively; Selective doping is used to dope the first silicon region to form a silicon doped region of a first conductivity type, and to dope the second silicon region to form a silicon doped region of a second conductivity type.

10. The method for fabricating a photodetector according to claim 9, characterized in that, Using a selective epitaxial growth process, a first silicon region and a second silicon region are formed in the two first grooves, respectively, including: Selective epitaxy is employed, and silane and / or propane are used as silicon precursors during the epitaxy process to epitaxially form the first silicon region and the second silicon region in the two first grooves, respectively.

11. The method for fabricating a photodetector according to claim 7, characterized in that, After forming a first conductivity type doped region and a second conductivity type doped region in the two first grooves respectively, the method further includes: The intermediate of the photodetector having the first conductivity type doped region and the second conductivity type doped region is annealed. A passivation layer is formed on one side of the substrate. Along the first direction, first through grooves are provided at intervals on both sides of the passivation layer, and the first through grooves penetrate the passivation layer. The vertical projections of the two first through grooves on the substrate are respectively located within the vertical projections of the two first grooves on the substrate. A first electrode is formed on the side of the first conductivity type doped region away from the substrate, including: The first electrode is formed on the side of the passivation layer away from the substrate corresponding to the first conductivity type doped region, and in the first through-groove corresponding to the first conductivity type doped region; A second electrode is formed on the side of the second conductivity type doped region away from the substrate, including: The passivation layer corresponding to the second conductivity type doped region is located on the side away from the substrate, and the second electrode is formed in the first through-hole corresponding to the second conductivity type doped region.

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