Back contact solar cell, method of manufacturing the same, and photovoltaic module

Abstract

The application discloses a back contact solar cell, a preparation method thereof and a photovoltaic module. The back contact solar cell comprises a substrate, a back surface of the substrate is provided with a plurality of P regions, a plurality of N regions and interval regions between the P regions and the N regions, the P region comprises a first tunneling layer and a P-type doped polysilicon layer, the first tunneling layer is located between the P-type doped polysilicon layer and the substrate, and the minimum distance between the P-type doped polysilicon layer and the interval region adjacent to the P-type doped polysilicon layer is 0.5-5 microns along the arrangement direction of the P regions. Thus, direct contact between the P-type doped polysilicon layer and the N-type doped polysilicon layer can be at least reduced or even avoided, so that the problem of cell leakage can be alleviated or even avoided.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, specifically to back-contact solar cells, their fabrication methods, and photovoltaic modules. Background Technology

[0002] TBC cells are a combination of IBC cells (interdigitated back contact cells) and TOPCon cells (tunneling oxide passivated contact cells). They use a silicon substrate as the substrate and doped polycrystalline silicon as the doping layer. A tunneling oxide layer is deposited in the electrode region to suppress minority carriers from drifting to the surface and to transfer the grid lines to the back side of the substrate. They have the advantages of BC cells (no incident light shading) and TOPCon cells (excellent passivation effect).

[0003] The main feature of TBC batteries is the interdigitated electrode on the back: the doped layer is formed by the interdigitated distribution of p+ and n+ regions, whose main function is to separate and collect charge carriers. The p+ region is responsible for collecting holes, and the n+ region is responsible for collecting electrons. The collected charge carriers are then transferred to the positive and negative electrodes and form a path with the external load. Therefore, the p+ and n+ regions cannot be in direct contact. Otherwise, the collected charge carriers will directly contact each other at the doped layer level, forming a short circuit, which will prevent the charge carriers from being effectively collected and thus cause leakage.

[0004] TBC cells in related technologies are prone to leakage problems. Therefore, current TBC cells, their preparation methods, and photovoltaic modules still need improvement. Summary of the Invention

[0005] This application aims to at least partially alleviate or resolve at least one of the aforementioned problems.

[0006] In one aspect of this application, a back-contact solar cell is proposed. In some embodiments of this application, the back-contact solar cell includes a substrate, on the back side of which are disposed a plurality of alternating P-regions, a plurality of N-regions, and a spacer region located between the P-regions and the N-regions; each P-region includes a first tunneling layer and a P-type doped polycrystalline silicon layer, the first tunneling layer being located between the P-type doped polycrystalline silicon layer and the substrate, and along the arrangement direction of the plurality of P-regions, the minimum distance between the P-type doped polycrystalline silicon layer and its adjacent spacer region is 0.5 μm-5 μm. Therefore, direct contact between the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer can be reduced or even avoided to some extent, thereby alleviating or even avoiding the problem of cell leakage.

[0007] In some embodiments of this application, the thickness of the substrate at the P region is greater than the thickness of the substrate at the N region, and the height difference between the substrate surface at the P region and the substrate surface at the N region is 2.0 μm-2.8 μm.

[0008] In some embodiments of this application, the N-region includes a second tunneling layer and an N-type doped polysilicon layer. The second tunneling layer is located between the N-type doped polysilicon layer and the substrate. Along the arrangement direction of the plurality of N-regions, the minimum distance between the N-type doped polysilicon layer and its adjacent spacer region is 0.8 μm-5.3 μm. This helps to further reduce or even avoid direct contact between the P-type doped polysilicon layer and the N-type doped polysilicon layer.

[0009] In some embodiments of this application, the second tunneling layer comprises silicon oxide.

[0010] In some embodiments of this application, the thickness of the second tunneling layer is 1.65nm-2.25nm.

[0011] In some embodiments of this application, the doping element of the N-type doped polycrystalline silicon layer includes phosphorus.

[0012] In some embodiments of this application, the thickness of the substrate at the N region is greater than the thickness of the substrate at the spacer region, and the height difference between the substrate surface at the N region and the substrate surface at the spacer region is 2.3 μm-3.1 μm.

[0013] In some embodiments of this application, the back-contact solar cell satisfies at least one of the following conditions: the first tunneling layer comprises silicon oxide; the thickness of the first tunneling layer is 1.7 nm-2.3 nm; and the doping element of the P-type doped polycrystalline silicon layer includes boron.

[0014] In another aspect of this application, a method for fabricating the aforementioned back-contact solar cell is proposed. In some embodiments of this application, the method for fabricating the aforementioned back-contact solar cell includes: forming a first tunneling layer, a P-type doped polycrystalline silicon layer, and a first glass layer on the back side of a substrate; performing a first laser etching process to remove the first glass layer in the N-region and the spacer region; performing an etching process using a first alkaline solution to remove the P-type doped polycrystalline silicon layer, the first tunneling layer, and a portion of the substrate in the N-region and the spacer region; forming a second tunneling layer, an N-type doped polycrystalline silicon layer, and a second glass layer on the back side of the substrate; performing a second laser etching process to remove the second glass layer in the P-region and the spacer region; and performing an etching process using a second alkaline solution to remove the N-type doped polycrystalline silicon layer, the second tunneling layer, and a portion of the substrate in the spacer region in the P-region and the spacer region, wherein the thickness of the substrate removed by the second alkaline solution etching is greater than the thickness of the substrate removed by the first alkaline solution etching. This increases the lateral etching degree of the second alkaline solution, removing some of the doped polycrystalline silicon at the edge of the P-region, which helps to reduce or even avoid direct contact between the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer.

[0015] In some embodiments of this application, the difference between the thickness of the substrate removed by the second alkaline solution etching and the thickness of the substrate removed by the first alkaline solution etching is ≥0.3 μm. This is beneficial for further increasing the lateral etching degree of the second alkaline solution, thereby more effectively mitigating or even preventing battery leakage.

[0016] In some embodiments of this application, the etching process using the second alkaline solution satisfies at least one of the following conditions: the volume ratio of water, the first solute, and the texturing additive in the second alkaline solution is 470:(5 to 10):(6 to 14), the first solute includes at least one of sodium hydroxide and potassium hydroxide; the temperature of the second alkaline solution is 70°C-80°C; the etching time is 450s-650s; and the thickness of the substrate removed by etching is 2.3μm-3.1μm.

[0017] In some embodiments of this application, the etching process using the first alkaline solution satisfies at least one of the following conditions: the volume ratio of water, the second solute, and the polishing additive in the first alkaline solution is 450:(20 to 30):(3 to 10), the second solute includes at least one of sodium hydroxide and potassium hydroxide; the temperature of the first alkaline solution is 65°C to 75°C; the etching time is 200s to 300s; and the thickness of the substrate removed by etching is 2.0μm to 2.8μm.

[0018] In another aspect of this application, a photovoltaic module is proposed. In some embodiments of this application, the photovoltaic module includes the back-contact solar cell described above. Therefore, this photovoltaic module possesses all the features and advantages of the back-contact solar cell described above, which will not be repeated here. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This shows a partial flowchart of the fabrication process for back-contact solar cells in related technologies; Figure 2 This shows a partial flowchart of the fabrication process for back-contact solar cells in related technologies; Figure 3 The image shows a back-contact solar cell emitting light, according to related technologies. Figure 4 This shows a partial structural schematic diagram of a back-contact solar cell according to an embodiment of the present application; Figure 5 This shows a partial structural schematic diagram of a back-contact solar cell according to an embodiment of the present application; Figure 6A schematic diagram of the structure of a back-contact solar cell according to an embodiment of this application is shown.

[0020] Explanation of reference numerals in the attached figures: 10: Substrate; 11: Back side; 12: Front side; 20: First tunneling layer; 30: P-type doped polysilicon layer; 40: Second tunneling layer; 50: N-type doped polysilicon layer; 60: First electrode; 70: Second electrode; 80: Back film; 90: Front film; 1: P-region; 2: N-region; 3: Spacer region. Detailed Implementation

[0021] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0022] In related technologies, some process flows for the preparation of TBC can be referenced. Figure 1 and Figure 2 SiOx (silicon oxide), P-poly (P-type polycrystalline silicon), and BSG (borosilicate glass) are formed on the back side of Nc-Si (N-type crystalline silicon). Then, the BSG in the N-region and spacer regions on the back side is removed. Next, alkaline washing is used to remove the P-poly grown in the N-region and spacer regions on the back side. During this process, the alkaline solution reacts laterally, etching away the P-poly on the sides of the P-region (e.g., ...). Figure 1 As shown in the diagram, during the next process of high-temperature chemical vapor deposition + phosphorus diffusion to generate N-poly (N-type polycrystalline silicon), N-poly will grow on the side of the P-region, and the N-poly on the side of the P-region will be in direct contact with the P-poly. (Reference) Figure 2 The PSG (phosphosilicate glass) grown on the back P-region and spacer region is removed by laser, followed by wet etching of the P-region and spacer region. After laser and wet etching, the N-poly on the side of the P-region is not completely removed and is in direct contact with the P-poly in the P-region (e.g., ...). Figure 2 As shown in the figure, leakage current occurs. Figure 3 This is an image of a back-contact solar cell produced using this method, which exhibits significant leakage issues. During the related process, lateral corrosion (removing P-poly from the P-region side) is unavoidable in the wet alkaline reaction. The corroded area forms N-poly in subsequent high-temperature processes. If the N-poly from the P-region side is not completely removed during subsequent processing, P-poly and N-poly come into contact, resulting in leakage.

[0023] In this application, in order to at least alleviate or even solve the above problems to some extent, the minimum distance between the P-type doped polysilicon layer in the P region and the adjacent spacer region is set to 0.5μm-5μm, so as to reduce or even avoid the situation of N-type polysilicon remaining on the side of the P region, thereby alleviating or even avoiding the problem of battery leakage.

[0024] In one aspect of this application, a back-contact solar cell is provided. In some embodiments of this application, reference is made to... Figures 4 to 6 The back-contact solar cell includes a substrate 10, which has a back side 11 and a front side 12 disposed opposite to each other. The front side 12 is the side facing the sun during the use of the cell, and the back side 11 is the side facing away from the sun during the use of the cell.

[0025] refer to Figures 4 to 6 The back surface 11 of the substrate 10 is provided with a plurality of alternately distributed P regions 1, a plurality of N regions 2, and a spacer region 3 located between the P regions 1 and N regions 2. The spacer region 3 is used to separate the P regions 1 and N regions 2. Figure 4 and Figure 6 Each diagram shows only one P-region 1, one N-region 2, and one spacer region 3. The P-region 1 includes a first tunneling layer 20 and a P-type doped polysilicon layer 30. The first tunneling layer 20 is located between the P-type doped polysilicon layer 30 and the substrate 10, along the arrangement direction of the multiple P-regions 1 (e.g., ...). Figures 4 to 6 In the X direction (as shown), the minimum distance d1 between the P-type doped polysilicon layer 30 and its adjacent spacer region 3 is 0.5 μm-5 μm. For example, d1 can be 0.5 μm, 0.7 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc. Therefore, the relatively large distance between the P-type doped polysilicon layer and the spacer region can reduce or even avoid direct contact between the P-type doped polysilicon and N-type doped polysilicon on the P-region side, thus helping to alleviate or even avoid battery leakage problems.

[0026] In some embodiments of this application, the substrate 10 can be an N-type silicon substrate. The specific dimensions of the substrate are not particularly limited in this application, and those skilled in the art can select and set them according to actual needs.

[0027] In some embodiments of this application, the first tunneling layer 20 may include silicon oxide. Thus, the first tunneling layer has a certain tunneling function, allowing majority carriers to tunnel through while hindering minority carriers from passing through.

[0028] In some embodiments of this application, the thickness of the first tunneling layer 20 can be 1.7 nm to 2.3 nm, for example, the thickness of the first tunneling layer 20 can be 1.7 nm, 1.9 nm, 2.1 nm, 2.3 nm, etc. A thinner first tunneling layer is more conducive to the tunneling of majority carriers.

[0029] In this application, the thickness of the substrate and each film layer refers to the thickness of the substrate or film layer along the Y direction (e.g., ...). Figure 4 and Figure 6 The dimensions shown are on the diagram.

[0030] In some embodiments of this application, the doping element of the P-type doped polysilicon layer 30 may include boron. In some specific embodiments, the P-type doped polysilicon layer may be a boron-doped polysilicon layer.

[0031] In some embodiments of this application, reference is made to Figure 4 and Figure 6 The thickness of substrate 10 at P-region 1 is greater than the thickness of substrate 10 at N-region 2, and the height difference h1 between the surfaces of substrate 10 at P-region 1 and N-region 2 can be 2.0 μm-2.8 μm, for example, h1 can be 2.0 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, etc. This facilitates more effective isolation between the P-type doped polysilicon layer and the N-type doped polysilicon layer, thereby better preventing battery leakage. It should be noted that the difference in thickness between substrate 10 at P-region 1 and substrate 10 at N-region 2 is due to the height difference on the back surfaces of the substrates corresponding to the P-region and N-region regions.

[0032] In some embodiments of this application, reference is made to Figure 4 and Figure 6 N-region 2 includes a second tunneling layer 40 and an N-type doped polysilicon layer 50. The second tunneling layer 40 is located between the N-type doped polysilicon layer 50 and the substrate 10, along the arrangement direction of the plurality of N-regions 2 (e.g., Figure 4 and Figure 6 In the X direction (as shown), the minimum distance d2 between the N-type doped polysilicon layer 50 and its adjacent spacer region 3 can be 0.8 μm-5.3 μm. For example, d2 can be 0.8 μm, 1 μm, 1.5 μm, 2.5 μm, 3.5 μm, 4.2 μm, 5.3 μm, etc. This allows for more effective isolation between the P-type doped polysilicon layer and the N-type doped polysilicon layer, thus better preventing battery leakage.

[0033] In some embodiments of this application, the second tunneling layer 40 may include silicon oxide. Thus, the second tunneling layer has a certain tunneling function, allowing majority carriers to tunnel through while hindering minority carriers from passing through.

[0034] In some embodiments of this application, the thickness of the second tunneling layer 40 can be 1.65 nm to 2.25 nm. For example, the thickness of the second tunneling layer 40 can be 1.65 nm, 1.8 nm, 2.0 nm, 2.1 nm, 2.25 nm, etc. A thickness of the second tunneling layer within the above range is more conducive to the tunneling of majority carriers.

[0035] In some embodiments of this application, the doping element of the N-type doped polysilicon layer 50 may include phosphorus. In some specific embodiments, the N-type doped polysilicon layer 50 may be a phosphorus-doped polysilicon layer.

[0036] In some embodiments of this application, reference is made to Figure 4 and Figure 6 The thickness of substrate 10 at N-region 2 is greater than that at spacer region 3, and the height difference h2 between the surface of substrate 10 at N-region 2 and the surface of substrate 10 at spacer region 3 can be 2.3 μm-3.1 μm, for example, h2 can be 2.3 μm, 2.5 μm, 2.7 μm, 2.9 μm, 3.1 μm, etc. Therefore, during alkaline washing to remove N-type doped polysilicon from P-regions and N-regions, the degree of lateral etching can be increased, which helps ensure that there is no residual N-type doped polysilicon on the sides of the P-type doped polysilicon layer, thus further helping to prevent battery leakage.

[0037] In some embodiments of this application, reference is made to Figure 6 The back-contact solar cell may also include a first electrode 60 and a second electrode 70, wherein the first electrode 60 is located in the P region 1 and is in contact with the P-type doped polycrystalline silicon layer 30, and the second electrode 70 is located in the N region 2 and is in contact with the N-type doped polycrystalline silicon layer 50.

[0038] In some embodiments, the first electrode 60 and the second electrode 70 may both be silver electrodes.

[0039] In some embodiments, both the first electrode 60 and the second electrode 70 may include a main gate and a fine gate.

[0040] In some embodiments of this application, reference is made to Figure 6 The back contact solar cell may also include a back film 80, a first electrode 60 of P region 1 passing through the back film 80 and contacting the P-type doped polycrystalline silicon layer 30, and a second electrode 70 of N region 2 passing through the back film 80 and contacting the N-type doped polycrystalline silicon layer 50.

[0041] In some embodiments of this application, the back film 80 may include a back aluminum oxide layer and a back antireflective layer. In some specific embodiments, the thickness of the back aluminum oxide layer may be 4.2 nm to 4.4 nm.

[0042] In some embodiments of this application, the back antireflection layer may include multiple sub-layers. Specifically, along the direction away from the substrate, the back antireflection layer may include a first silicon nitride layer, a second silicon nitride layer, and a third silicon nitride layer stacked sequentially. The silicon nitride films are distinguished by their different refractive indices, and the thickness of each film is between 10nm and 30nm. The final overall film thickness is 78nm-90nm, and the refractive index is 2.07-2.17.

[0043] In some embodiments of this application, reference is made to Figure 6 The back-contact solar cell may also include a positive film 90, which is disposed on the front side 12 of the substrate 10. In some embodiments, the positive film 90 may include a front alumina layer and a front anti-reflection layer.

[0044] In some embodiments, the thickness of the front alumina layer can be 4.2 nm to 4.4 nm.

[0045] In some embodiments, the front antireflection layer may include multiple sub-layers. Specifically, along the direction away from the substrate, the front antireflection layer may include a fourth silicon nitride layer, a fifth silicon nitride layer, a sixth silicon nitride layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a first silicon oxide layer stacked sequentially. The difference between the silicon nitride and silicon oxynitride layers is their refractive index. The thickness of each layer is between 10 nm and 25 nm, and the final overall thickness of the layer is 70 nm to 80 nm, with a refractive index of 2.05 to 2.15.

[0046] In some embodiments of this application, the substrate in the spacer area and the front side of the substrate can be formed with a pyramidal textured surface, thereby improving the battery's light utilization efficiency.

[0047] In another aspect of this application, a method for fabricating the aforementioned back-contact solar cell is provided. In some embodiments of this application, the method for fabricating the aforementioned back-contact solar cell may include the following steps: S10: A first tunneling layer 20, a P-type doped polysilicon layer 30, and a first glass layer are formed on the back side 11 of the substrate 10.

[0048] In some embodiments, the first tunneling layer may be a silicon oxide layer, and the first glass layer may be a borosilicate glass layer (BSG layer).

[0049] In some embodiments of this application, a first tunneling layer (e.g., a silicon oxide layer) and a first polysilicon layer can be sequentially deposited on the back side of a substrate using LPCVD (low-pressure chemical vapor deposition). In some embodiments, the deposition time of the first tunneling layer can be 1000s-3000s, the deposition temperature can be 590℃-630℃, and the thickness of the formed first tunneling layer can be 1.7nm-2.3nm; the deposition time of the first polysilicon layer can be 11000s-13000s, the deposition temperature can be 550℃-570℃, and the thickness of the formed first polysilicon layer can be 250nm-350nm.

[0050] In some embodiments, after forming the first polysilicon layer, boron diffusion and oxidation processes can be performed. Boron diffusion can transform the first polysilicon layer into a P-type doped polysilicon layer, and oxidation can form a BSG layer on a portion of the P-type doped polysilicon layer away from the substrate. In some embodiments, the pre-crystallization temperature for boron diffusion is 950℃-980℃, and the crystallization time is 2500s-3000s; the diffusion temperature is 800℃-870℃, and the diffusion time is 300s-600s; the drive-through temperature is 930℃-960℃, and the drive-through time is 500s-800s; the oxidation temperature is 850℃-950℃, and the oxidation time is 3000s-3500s; the post-annealing temperature is 950℃-980℃, the thickness of the BSG layer is 55nm-65nm, and the sheet resistance is 100Ω / □-140Ω / □.

[0051] In some embodiments of this application, the substrate may be an N-type silicon substrate.

[0052] In some embodiments, the substrate may be double-sided polished before forming the first tunneling layer. In some embodiments, the specific steps of double-sided polishing are as follows: The N-type silicon substrate is double-sided polished in a wet alkaline polishing tank. The alkaline solution used is composed of H2O, NaOH, and polishing additives in a volume ratio of 450:30:5. The process time is 250s-400s, and the tank temperature of the wet alkaline polishing tank is 60℃-75℃.

[0053] S20: Perform the first laser etching process to remove the first glass layer of N region 2 and spacer region 3.

[0054] In some embodiments of this application, the first laser etching process can meet the following conditions: laser power of 40W-50W, overlap rate of 50%-60%, frequency of 500kHz-600kHz, and pulse width of 0.8μs-1.2μs.

[0055] The first laser etching process removes the first glass layer (BSG layer) of the N-region and the spacer region, while retaining the first glass layer of the P-region. During subsequent alkaline etching, the first glass layer of the P-region acts as a protector, preventing the P-type doped polysilicon layer in the P-region from being etched by the alkaline solution.

[0056] S30: The first alkaline solution is used for etching to remove the P-type doped polysilicon layer 30, the first tunneling layer 20 and part of the substrate 10 in N region 2 and spacer region 3.

[0057] In step S10, a first tunneling layer (silicon oxide layer), a P-type doped polysilicon layer, and a BSG layer are also formed on the front and side surfaces of the substrate. Before etching with the first alkaline solution, acid washing can be performed using a wet chain machine to remove the BSG on the front and side surfaces. In some embodiments, the tank temperature of the wet chain machine is 20℃-50℃, the overall process time is 50s-80s, and the chain machine has two acid tanks. The acid solution in the first acid tank is composed of H2O and HF in a volume ratio of 2:5, and the acid solution in the second acid tank is composed of H2O and HF in a volume ratio of 3:4.

[0058] The etching process is performed using a first alkaline solution, followed by alkaline washing using a wet tank machine to remove the P-type doped polysilicon layer and the first tunneling layer on the front and side surfaces, as well as the P-type doped polysilicon layer, the first tunneling layer, and part of the substrate in the N region and the spacer region.

[0059] In some embodiments of this application, the volume ratio of water, the second solute, and the polishing additive in the first alkaline solution can be 450:(20 to 30):(3 to 10). For example, the volume ratio of water, the second solute, and the polishing additive can be 450:25:7, 450:25:3, 450:25:10, 450:20:3, 450:20:10, 450:30:3, 450:30:10, etc. The second solute can include at least one of sodium hydroxide and potassium hydroxide. The above-mentioned alkaline solution has good etching performance and can etch doped polycrystalline silicon layers, tunneling layers, and part of the silicon substrate. The specific material of the polishing additive is not particularly limited in this application, and those skilled in the art can select it as needed.

[0060] In some embodiments of this application, the temperature of the first alkaline solution (i.e., the tank temperature of the wet etching process) can be 65°C-75°C. For example, the temperature of the first alkaline solution can be 65°C, 68°C, 70°C, 72°C, 75°C, etc. This can increase the etching rate to a certain extent, keep the etching rate within a suitable range, and help shorten the etching time.

[0061] In some embodiments of this application, the etching time of the first alkaline solution can be 200s-300s, for example, 200s, 230s, 250s, 280s, 300s, etc. This helps to control the etching depth within a reasonable range and reduce the degree of lateral corrosion.

[0062] In some embodiments of this application, the thickness of the substrate removed by the first alkaline etching can be 2.0 μm-2.8 μm, for example, 2.0 μm, 2.2 μm, 2.5 μm, 2.7 μm, 2.8 μm, etc. This ensures the removal of the P-type doped polysilicon layer in the N-region and the spacer region. Simultaneously, it at least partially reduces or even avoids the lateral etching of the P-type doped polysilicon layer in the P-region by the first alkaline solution, thereby reducing the risk of subsequent formation of an N-type doped polysilicon layer on the side of the P-type doped polysilicon layer, and thus helping to mitigate or even avoid battery leakage.

[0063] S40: A second tunneling layer 40, an N-type doped polysilicon layer 50, and a second glass layer are formed on the back side 11 of the substrate 10.

[0064] In some embodiments, the second tunneling layer may be a silicon oxide layer, and the second glass layer may be a phosphosilicate glass layer (PSG layer).

[0065] In some embodiments of this application, a second tunneling layer (e.g., a silicon oxide layer) and a second polysilicon layer can be sequentially deposited on the back side of a substrate using LPCVD (low-pressure chemical vapor deposition). In some embodiments, the deposition time of the second tunneling layer is 500s-1200s, the temperature is 590℃-630℃, and the thickness of the formed second tunneling layer is 1.65nm-2.25nm; the deposition time of the second polysilicon layer is 3500s-5000s, the deposition temperature is 605℃-620℃, and the thickness of the formed first polysilicon layer is 250nm-310nm.

[0066] In some embodiments, after forming the second polysilicon layer, phosphorus diffusion and oxidation processes can be performed. Phosphorus diffusion can transform the second polysilicon layer into an N-type polysilicon layer, and oxidation can form a PSG layer on a portion of the N-type doped polysilicon layer away from the substrate. In some embodiments, the diffusion temperature is 800℃-820℃, the diffusion time is 1200s-1500s, the drive temperature is 870℃-890℃, and the drive time is 800s-1200s; the oxidation temperature is 910℃-930℃, the oxidation time is 600s-900s, the thickness of the PSG layer is 45nm-55nm, and the sheet resistance is 20Ω / □-30Ω / □.

[0067] S50: Perform a second laser etching process to remove the second glass layer of P region 1 and spacer region 3.

[0068] A second laser etching process is performed to remove the second glass layer (PSG layer) of the P region and the spacer region, while retaining the second glass layer of the N region. During the subsequent etching process using alkaline solution, the second glass layer of the N region can play a protective role, preventing the N-type doped polysilicon layer of the N region from being etched by the alkaline solution.

[0069] S60: The second alkaline solution is used for etching to remove the N-type doped polysilicon layer 50, the second tunneling layer 40, and part of the substrate 10 of the spacer region 3 in P region 1 and spacer region 3.

[0070] In this application, the thickness of the substrate removed by the second alkaline solution etching is greater than the thickness of the substrate removed by the first alkaline solution etching. This increases the lateral etching degree of the second alkaline solution, removing part of the structure on the P-region side, ensuring that there is no N-type doped polysilicon on the P-region side, thereby avoiding leakage problems caused by direct contact between P-type and N-type doped polysilicon. Specifically, the shallow depth of the first alkaline etching reduces or even eliminates corrosion of the P-type doped polysilicon layer in the P-region. During subsequent N-type doped polysilicon deposition, the N-type doped polysilicon layer is less likely to deposit between the BSG layer and the first tunneling layer, thus mitigating or even preventing leakage caused by direct contact between P-type and N-type doped polysilicon. Even if a portion of the P-type doped polysilicon on the side of the P-region is etched away during the first alkaline etching process, N-type doped polysilicon directly contacts the P-type doped polysilicon on the side of the P-region during N-type doped polysilicon deposition. Since the depth of the second alkaline etching is greater than that of the first alkaline etching, the lateral corrosion of the second alkaline etching increases, which helps remove the N-type doped polysilicon directly in contact with the P-type doped polysilicon, thereby mitigating or even solving the battery leakage problem.

[0071] In some embodiments, the difference between the thickness of the substrate removed by the second alkaline etching and the thickness of the substrate 10 removed by the first alkaline etching can be ≥0.3 μm. This is more conducive to the complete removal of N-type doped polysilicon deposited on the sidewalls of P-type doped polysilicon, thereby better preventing battery leakage.

[0072] In step S40, a second tunneling layer (silicon oxide layer), an N-type doped polysilicon layer, and a PSG layer are also formed on the front and side surfaces of the substrate. Before etching with a second alkaline solution, the PSG on the front and side surfaces can be removed by acid washing using a wet chain machine. In some embodiments, the tank temperature of the wet chain machine is 20°C-50°C, the process time is 30s-60s, and the chain machine has one acid tank. The acid solution in the acid tank is composed of H2O and HF in a volume ratio of 3:4.

[0073] The etching process is performed using a second alkaline solution, followed by alkaline washing (texturing) using a tank-type machine to remove the N-type doped polysilicon layer and the first tunneling layer on the front and sides, the N-type doped polysilicon layer and the second tunneling layer on the back P region and the spacer region, as well as part of the substrate in the spacer region. At the same time, a pyramid textured surface is formed on the front side of the spacer region and the substrate.

[0074] In some embodiments of this application, the volume ratio of water, the first solute, and the texturing additive in the second alkaline solution can be 470:(5 to 10):(6 to 14). For example, the volume ratio of water, the first solute, and the texturing additive can be 470:6:11, 470:6:6, 470:6:14, 470:5:6, 470:5:14, 470:10:6, 470:10:14, etc. The first solute can include at least one of sodium hydroxide and potassium hydroxide. The above-mentioned alkaline solution has good etching performance and can remove the doped polycrystalline silicon layer, tunneling layer, and part of the silicon substrate, and form a pyramidal textured surface in the spaced area between the front and back sides of the substrate. The specific material of the texturing additive is not particularly limited in this application, and those skilled in the art can select it as needed.

[0075] In some embodiments of this application, the temperature of the second alkaline solution can be 70°C-80°C, for example, 70°C, 72°C, 75°C, 77°C, 80°C, etc. At the above temperatures, the second alkaline solution can maintain a suitable etching rate, which can improve the uniformity and etching effect of the etching process.

[0076] In some embodiments of this application, the etching time of the second alkaline solution can be 450s-650s, for example, 450s, 500s, 550s, 600s, 650s, etc. This is beneficial for increasing the etching depth, thereby increasing the degree of lateral etching, which is beneficial for removing the N-type doped polysilicon layer on the side of the P-type doped polysilicon layer, and thus helps to alleviate or even solve the problem of battery leakage.

[0077] In some embodiments of this application, the thickness of the substrate removed by the second alkaline etching can be 2.3 μm-3.1 μm, for example, the thickness of the substrate removed by the second alkaline etching can be 2.3 μm, 2.5 μm, 2.7 μm, 2.9 μm, 3.1 μm, etc. Therefore, the second alkaline etching depth is relatively large, which can increase the lateral etching degree of the second alkaline solution, remove part of the film layer on the side of the P-type doped polysilicon layer, and isolate the P-type doped polysilicon layer from the N-type doped polysilicon layer, thereby preventing battery leakage.

[0078] In some embodiments of this application, the method for preparing a back-contact solar cell may further include the steps of forming a positive film, a back film, and electrodes.

[0079] In some embodiments, aluminum oxide layers can be formed on both the front and back sides of the substrate using ALD (atomic layer deposition). In some specific embodiments, aluminum oxide layers can be deposited using a back-to-back dual-intercalation method, with an ALD process temperature of 300°C, a process time of 900 s, and an aluminum oxide layer thickness of 4.2 nm-4.4 nm.

[0080] In some specific embodiments, a back antireflection layer can be formed on the side of the back alumina layer away from the substrate. The deposition temperature of the back antireflection layer can be 530°C, and it can be divided into 3 layers. The order of deposition from the substrate outward is silicon nitride 1, silicon nitride 2, and silicon nitride 3. The silicon nitride layers are different in refractive index. The thickness of each layer is between 10nm and 30nm, and the final overall film thickness is between 78nm and 90nm, with a refractive index between 2.07 and 2.17.

[0081] In some specific embodiments, a front antireflection layer can be formed on the side of the front alumina layer away from the substrate. The deposition temperature of the front antireflection layer can be 540°C, and it can be divided into 6 layers. The deposition order from the substrate outward is silicon nitride 1, silicon nitride 2, silicon nitride 3, silicon oxynitride 1, silicon oxynitride 2, and silicon oxide. The difference between the silicon nitride and silicon oxynitride layers is their refractive index. The thickness of each layer is between 10nm and 25nm, and the final overall film thickness is between 70nm and 80nm, with a refractive index between 2.05 and 2.15.

[0082] In some embodiments of this application, a first electrode and a second electrode can be formed in the P-region and N-region, respectively, by screen printing. Specifically, metal gate lines can be formed on the back side by screen printing, and then sintered at high temperature to form ohmic contacts between the metal gate lines and the semiconductor (N-type doped polysilicon layer or P-type doped polysilicon layer) to collect and conduct current.

[0083] In some embodiments, the first and second electrodes can be formed on the back side by a three-pass printing method: the first pass prints the back side main grid with 9-24 main grids; the second pass prints the back side N-region fine grid with 150-250 fine grids and a fine grid height of 4μm-13μm; the third pass prints the back side P-region fine grid with 150-250 fine grids and a fine grid height of 4μm-13μm; the sintering peak temperature can be 680℃-750℃.

[0084] In summary, when fabricating back-contact solar cells using the method proposed in this application, the depth of the second alkaline etching treatment is greater than that of the first alkaline etching treatment. This increases the lateral etching depth of the second alkaline solution, ensuring that no N-type doped polysilicon remains on the sides of the P-type doped polysilicon layer in the P-region, thereby mitigating or even preventing cell leakage. Furthermore, by controlling the composition, temperature, and etching time of the alkaline solution, the etching depth can be better adjusted to ensure that the P-type doped polysilicon layer is isolated from the N-type doped polysilicon layer, thus preventing cell leakage.

[0085] In another aspect, this application proposes a photovoltaic module. In some embodiments of this application, the photovoltaic module includes the aforementioned back-contact solar cell. Therefore, this photovoltaic module is less prone to leakage problems.

[0086] In some embodiments of this application, the photovoltaic module may include one or more back-contact solar cells.

[0087] The present application will be described below through specific embodiments. Those skilled in the art will understand that the specific embodiments below are merely illustrative and do not limit the scope of the present application in any way. Furthermore, in the following embodiments, unless otherwise specified, the materials and equipment used are commercially available. If specific processing conditions and methods are not explicitly described in the later embodiments, conditions and methods known in the art can be used for processing.

[0088] Example 1 1. Double-sided polishing: The N-type silicon substrate is polished on both sides in a wet alkaline polishing tank. The alkaline solution used is composed of H2O, NaOH and polishing additives in a volume ratio of 450:30:5. The process time is 300s and the tank temperature of the wet alkaline polishing tank is 70℃. 2. LP1 (First Low-Pressure Chemical Vapor Deposition): The deposition time for the tunneling layer (silicon oxide layer) is 2000s, and the deposition temperature is 610℃; the deposition time for the polycrystalline silicon layer is 12000s, and the deposition temperature is 560℃. 3. Boron diffusion: The pre-crystallization temperature for boron diffusion is 960℃, and the crystallization time is 2700s; the diffusion temperature is 830℃, and the diffusion time is 400s; the advance temperature is 950℃, and the advance time is 600s; the oxidation temperature is 900℃, and the oxidation time is 3200s; the post-annealing temperature is 960℃; this step can form P-poly and BSG layers. 4. First laser etching process: Laser removal of BSG from the N-region and spacer region on the back side. The laser power is 45W, the overlap rate is 55%, the frequency is 550kHz, and the pulse width is 1μs. 5. P1 Cleaning: Acid washing is performed using a wet chain machine to remove BSG from the front and sides of the silicon substrate. The tank temperature of the wet acid tank chain machine is 30℃, and the overall process time is 60s. The chain machine has two acid tanks. The acid solution in the first acid tank is composed of H2O and HF in a volume ratio of 2:5, and the acid solution in the second acid tank is composed of H2O and HF in a volume ratio of 3:4. Alkali washing is performed using a wet alkaline washing machine to remove the P-poly and silicon oxide layers on the front and sides of the silicon substrate, as well as the P-poly, silicon oxide layers, and part of the silicon substrate in the N-region and spacer region. The tank temperature of the wet alkaline washing machine is 65℃, the process time is 200s, and the alkaline solution used for alkaline washing is composed of H2O, NaOH, and polishing additives in a volume ratio of 450:25:7.

[0089] 6. LP2 (Second Low Pressure Chemical Vapor Deposition): The deposition time for the tunneling layer (silicon oxide layer) is 800s and the temperature is 610℃; the deposition time for polycrystalline silicon is 4300s and the deposition temperature is 615℃.

[0090] 7. Phosphorus diffusion: diffusion temperature is 810℃, diffusion time is 1400s, propagation temperature is 880℃, propagation time is 1000s, oxidation temperature is 920℃, oxidation time is 750s; this step can form N-poly and PSG layers. 8. Second laser etching process: Laser removal of PSG from the P-region and the spacer region on the back side. The laser power is 45W, the overlap rate is 55%, the frequency is 550kHz, and the pulse width is 1μs. 9. P2 Cleaning: PSG on the front and sides of the silicon substrate is removed by a wet chain machine. The temperature of the chain machine tank is 35℃ and the process time is 45s. The chain machine has one acid tank, and the acid solution in the acid tank is composed of H2O and HF in a volume ratio of 3:4. The trough-type machine removes the front and side surfaces of the silicon substrate, as well as the N-poly layer in the P-region, the silicon oxide layer formed in step 6, the N-poly layer in the spacer region, the silicon oxide layer, and part of the substrate. At the same time, a pyramid textured surface is formed in the spacer region and the front surface. The alkaline solution for texturing is composed of H2O, NaOH, and texturing additives in a volume ratio of 470:6:11. The solution temperature is 70℃, and the process time is 450s.

[0091] After etching with an alkaline solution, an acid solution is used to remove the BSG in the P region and the PSG in the N region.

[0092] 10. ALD: Alumina layer is deposited by back-to-back double insertion; ALD process temperature is 300℃, and process time is 900s; 11. Front Anti-reflective Layer: The coating process temperature is 540℃, consisting of 6 layers. The deposition order from the silicon substrate outward is silicon nitride 1, silicon nitride 2, silicon nitride 3, silicon oxynitride 1, silicon oxynitride 2, and silicon oxide. The difference between the silicon nitride and silicon oxynitride layers is their refractive index. The thickness of each layer is between 10nm and 25nm, and the final overall film thickness is between 70nm and 80nm, with a refractive index between 2.05 and 2.15. 12. Backside Anti-reflection Layer: The coating process temperature is 530℃, consisting of 3 layers. The order of deposition from the silicon substrate outward is silicon nitride 1, silicon nitride 2, and silicon nitride 3. The silicon nitride layers differ in their refractive index. The thickness of each layer is between 10nm and 30nm, resulting in an overall film thickness between 78nm and 90nm and a refractive index between 2.07 and 2.17. 13. Screen Printing: Metal gate lines are formed on the back side using screen printing. After high-temperature sintering, the metal gate lines form ohmic contacts with the semiconductor to collect and conduct current. The process involves three printing passes: the first pass prints the main gate on the back side, with 9-24 gate lines; the second pass prints the fine gates in the N-region on the back side, with 150-250 gate lines and a gate height of 4μm-13μm; and the third pass prints the fine gates in the P-region on the back side, with 150-250 gate lines and a gate height of 4μm-13μm. The peak sintering temperature is 680℃-750℃.

[0093] Example 2 Example 2 prepared a battery using the same method as Example 1. The difference between Example 2 and Example 1 is that in step 5, the temperature of the wet alkaline polishing tank is 75°C and the process time is 300s; in step 9, the temperature of the alkaline solution used for texturing is 80°C and the process time is 650s.

[0094] Example 3 Example 3 prepared a battery using the same method as Example 1. The difference between Example 3 and Example 1 is that in step 5, the temperature of the wet alkaline polishing tank is 68°C and the processing time is 250s; in step 9, the temperature of the alkaline solution used for texturing is 76°C and the processing time is 550s.

[0095] Light emission tests on the batteries from each embodiment revealed that none of the batteries prepared in Examples 1-3 exhibited significant leakage. This indicates that by controlling parameters such as solution temperature and process time in the two alkaline washing steps, and ensuring that the lateral corrosion degree of the alkaline solution in step 9 is greater than that in step 5, the battery leakage problem can be improved. In Examples 1-3, the minimum distance between the P-type doped polycrystalline silicon layer and its adjacent spacer region was between 0.5 μm and 5 μm, and there was virtually no residual N-type doped polycrystalline silicon on the side of the P-type doped polycrystalline silicon layer.

[0096] In the description of this application, the terms "front", "back", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and do not require this application to be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0097] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," and "other embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples, without contradiction. Additionally, it should be noted that in this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0098] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A back-contact solar cell, characterized in that, The back-contact solar cell includes a substrate, and the back side of the substrate is provided with a plurality of alternating P regions, a plurality of N regions, and a spacer region located between the P regions and the N regions; The P-region includes a first tunneling layer and a P-type doped polysilicon layer. The first tunneling layer is located between the P-type doped polysilicon layer and the substrate. Along the arrangement direction of the plurality of P-regions, the minimum distance between the P-type doped polysilicon layer and its adjacent spacer region is 0.5 μm-5 μm.

2. The back-contact solar cell according to claim 1, characterized in that, The thickness of the substrate at the P region is greater than the thickness of the substrate at the N region, and the height difference between the substrate surface at the P region and the substrate surface at the N region is 2.0 μm-2.8 μm.

3. The back-contact solar cell according to claim 1, characterized in that, The N-region includes a second tunneling layer and an N-type doped polysilicon layer. The second tunneling layer is located between the N-type doped polysilicon layer and the substrate. Along the arrangement direction of the plurality of N-regions, the minimum distance between the N-type doped polysilicon layer and its adjacent spacer region is 0.8 μm-5.3 μm. Optionally, the second tunneling layer comprises silicon oxide; Optionally, the thickness of the second tunneling layer is 1.65 nm to 2.25 nm; Optionally, the doping element of the N-type doped polycrystalline silicon layer includes phosphorus.

4. The back-contact solar cell according to any one of claims 1-3, characterized in that, The thickness of the substrate in the N region is greater than the thickness of the substrate in the spacer region, and the height difference between the substrate surface in the N region and the substrate surface in the spacer region is 2.3 μm-3.1 μm.

5. The back-contact solar cell according to any one of claims 1-3, characterized in that, At least one of the following conditions must be met: The first tunneling layer comprises silicon oxide; The thickness of the first tunneling layer is 1.7 nm to 2.3 nm; The doping element of the P-type doped polycrystalline silicon layer includes boron.

6. A method for preparing a back-contact solar cell according to any one of claims 1-5, characterized in that, include: A first tunneling layer, a P-type doped polysilicon layer, and a first glass layer are formed on the back side of the substrate; Perform a first laser etching process to remove the first glass layer in the N-region and the spacer region; The first alkaline solution is used for etching to remove the P-type doped polysilicon layer, the first tunneling layer, and part of the substrate in the N-region and the spacer region. A second tunneling layer, an N-type doped polysilicon layer, and a second glass layer are formed on the back side of the substrate; A second laser etching process is performed to remove the second glass layer in the P-region and the spacer region; A second alkaline solution is used for etching to remove the N-type doped polysilicon layer, the second tunneling layer, and part of the substrate in the spacer region of the P-region and the spacer region. The thickness of the substrate removed by the second alkaline solution etching is greater than the thickness of the substrate removed by the first alkaline solution etching.

7. The method according to claim 6, characterized in that, The difference between the thickness of the substrate removed by the second alkaline etching solution and the thickness of the substrate removed by the first alkaline etching solution is ≥0.3μm.

8. The method according to claim 6, characterized in that, The etching process using the second alkaline solution satisfies at least one of the following conditions: In the second alkaline solution, the volume ratio of water, the first solute, and the texturing additive is 470:(5 to 10):(6 to 14), and the first solute includes at least one of sodium hydroxide and potassium hydroxide; The temperature of the second alkaline solution is 70℃-80℃; The etching time is 450s-650s; The thickness of the substrate removed by etching is 2.3 μm-3.1 μm.

9. The method according to any one of claims 6-8, characterized in that, The etching process using the first alkaline solution satisfies at least one of the following conditions: In the first alkaline solution, the volume ratio of water, the second solute, and the polishing additive is 450:(20 to 30):(3 to 10), and the second solute includes at least one of sodium hydroxide and potassium hydroxide; The temperature of the first alkaline solution is 65℃-75℃; The etching time is 200s-300s; The thickness of the substrate removed by etching is 2.0 μm-2.8 μm.

10. A photovoltaic module, characterized in that, Includes the back-contact solar cell according to any one of claims 1-5.

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