A chip with an arrayed reflecting structure and a method for manufacturing the same

Abstract

The application discloses a chip with an array type reflecting structure and a preparation method thereof, and belongs to the technical field of chip manufacturing. The chip with the array type reflecting structure comprises a chip layer, a metal column structure and a silicon nitride layer. The chip layer comprises independent pixel areas and non-pixel areas. The metal column structure is formed in the pixel areas of the chip layer and is arranged in a periodic array. The silicon nitride layer is formed on the upper surface of the non-pixel areas of the chip layer, and the upper surface of the silicon nitride layer has a triangular micropore structure arranged in a periodic array. The ytterbium layer is conformally covered on the upper surface of the silicon nitride layer. The chip with the array type reflecting structure constructs a micropore array with a nearly triangular cross section on the surface of the silicon nitride layer, can form a complete photonic band gap in a wide wave band range, and simultaneously realizes strong angle scattering of light. Compared with a traditional planar or circular hole type reflecting layer, the chip can significantly improve the light utilization rate.

Description

Technical Field

[0001] This invention belongs to the field of chip manufacturing technology, specifically relating to a chip with an array-type reflective structure and its fabrication method. Background Technology

[0002] In the rapid development of photonic chips and optoelectronic devices towards high performance, miniaturization, and integration, reflective structures, as core components for controlling light propagation paths and improving light utilization efficiency, directly determine the overall optoelectronic characteristics of the chip. They are widely used in the core structures of various optoelectronic devices such as photovoltaic chips, photodetector chips, and optical waveguide chips. Among these, silicon nitride (SiN) is a key component. x Thin films, with their unique optical and physical properties, have become the preferred material for constructing chip reflective structures.

[0003] SiN x SiN thin films possess a wide-band light transmission window, making them suitable for the ultraviolet to near-infrared operating wavelengths commonly used in photonic chips. Furthermore, their refractive index can be flexibly adjusted by controlling fabrication process parameters. They also offer advantages such as low optical loss, good chemical stability, and high compatibility with chip substrates, leading to their widespread application in photonic devices such as optical waveguides, antireflection layers, and surface passivation. Particularly in the bilayer or multilayer distributed Bragg reflector structures of photovoltaic chips and photodetector chips, SiN… x As a key reflective layer component, thin films can effectively reduce light reflection loss on the chip surface, significantly improve the light capture efficiency of the device, and thus optimize the photoelectric conversion performance of the chip, providing important support for the research and development of high-performance optoelectronic devices.

[0004] As the requirements for light utilization efficiency in photonic chips continue to increase, the reflective performance of reflective structures has become one of the key bottlenecks restricting breakthroughs in chip performance. Currently, SiN used in chip reflective structures in existing technologies... x The reflective layer typically employs a traditional planar structure or a circular aperture array structure. Planar SiN... x The limited reflection angle range of the reflective layer makes it difficult to achieve efficient reflection of wide-angle incident light, causing some incident light to escape from the chip and reducing light capture efficiency; while the circular aperture array structure of SiN x Due to the symmetry limitations of the aperture structure, the reflective layer lacks flexibility in adjusting its reflection spectrum, and its reflectivity in specific operating wavelength bands is insufficient to meet the application requirements of high-performance chips. Overall, the reflection effect is poor, failing to fully utilize the potential of SiN. x Optical advantages of thin films. Summary of the Invention

[0005] Therefore, the purpose of this invention is to provide a chip with an array-type reflective structure and a method for fabricating the same.

[0006] In a first aspect, the present invention provides a chip having an array-type reflective structure, comprising: Chip layer: includes independent pixel regions and non-pixel regions; Metal pillar structure: formed within the pixel region of the chip layer and arranged in a periodic array; Silicon nitride (SiN) x ) layer: formed on the upper surface of the non-pixel area of ​​the chip layer, the upper surface of the silicon nitride layer has a triangular micropore structure arranged in a periodic array; Ytterbium (Yb) layer: Conformally covers the upper surface of the silicon nitride layer (the ytterbium layer maintains the triangular microporous structure of the silicon nitride layer surface array).

[0007] Secondly, the present invention provides a method for fabricating a chip with an array-type reflective structure, comprising the following steps: S1: Prepare a chip with an array of metal pillars; prepare a silicon nitride layer on the upper surface of one side of the metal pillars of the chip; then spin-coat photoresist on the silicon nitride layer, and after exposure and development, expose the corresponding area of ​​the array of triangular micro-holes to be etched to obtain intermediate device 1. S2: The corresponding area of ​​the array of triangular micro-holes of intermediate device 1 is exposed and etched to form an array of triangular micro-holes on the silicon nitride layer; after etching, the photoresist is removed to obtain intermediate device 2. S3: Spin-coat photoresist onto the silicon nitride layer of intermediate device 2 until the entire surface is flat, and then expose and develop to form a photoresist pattern that exposes the pixel area; then etch the silicon nitride layer of the pixel area until the metal pillars of the pixel area are exposed, remove the photoresist, and obtain intermediate device 3; S4: Inkjet print photoresist onto the metal pillars in the 3-pixel area of ​​the intermediate device to protect the metal pillars; then, deposit a ytterbium layer on the entire surface of the device by magnetron sputtering. After deposition, remove the photoresist to obtain a chip with an array-type reflective structure.

[0008] Thirdly, the present invention provides a photovoltaic device, including the aforementioned chip with an array-type reflective structure.

[0009] Fourthly, the present invention provides an optoelectronic device, including the aforementioned chip having an array-type reflective structure.

[0010] Compared with the prior art, one or more of the above technical solutions can achieve at least one of the following beneficial effects: The chip with an array-type reflective structure of the present invention is based on silicon nitride (SiN). xThe surface of the layer is constructed with a near-triangular cross-section micro-aperture array, which can form a complete photonic bandgap over a wide wavelength range and achieve strong angular scattering of light. Compared with traditional planar or circular aperture reflective layers, it can significantly improve the light utilization rate. In addition, the present invention also deposits a ytterbium (Yb) metal layer on the surface of the micro-aperture array, which has both light conversion and light reflection characteristics. It can convert photons that are not effectively utilized into photons that can be absorbed again by the upper functional layer, realize the secondary utilization of light energy, and thus effectively improve the overall photoelectric conversion efficiency of the chip. Through the synergistic effect of the two special structural layers, the chip with the array-type reflective structure of the present invention has excellent optical performance and photoelectric conversion efficiency. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the chip with an array-type reflective structure in this invention.

[0012] Figure 2 This is a process flow diagram of step S1 in the method for preparing a chip with an array-type reflective structure in this invention.

[0013] Figure 3 This is a process flow diagram of step S2 in the method for preparing a chip with an array-type reflective structure in this invention.

[0014] Figure 4 This is a process flow diagram of step S3 in the method for preparing a chip with an array-type reflective structure in this invention.

[0015] Figure 5 This is a process flow diagram of step S4 in the method for preparing a chip with an array-type reflective structure in this invention. Detailed Implementation

[0016] To facilitate understanding of the present invention, the present invention will be described more fully and in detail below with reference to the accompanying drawings and preferred embodiments, but the scope of protection of the present invention is not limited to the following specific embodiments.

[0017] Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by those skilled in the art. The technical terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the invention.

[0018] As mentioned above, in a first aspect, the present invention provides a chip having an array-type reflective structure, comprising: Chip layer: includes independent pixel regions and non-pixel regions; Metal pillar structure: formed within the pixel region of the chip layer and arranged in a periodic array; Silicon nitride (SiN) x) layer: formed on the upper surface of the non-pixel area of ​​the chip layer, the upper surface of the silicon nitride layer has a triangular micropore structure arranged in a periodic array; Ytterbium (Yb) layer: Conformally covers the upper surface of the silicon nitride layer (the ytterbium layer maintains the triangular microporous structure of the silicon nitride layer surface array).

[0019] The chip of this invention with an array-type reflective structure is first made of SiN x As an optical substrate, a micro-aperture array with a tilted angle and near-triangular cross-section is constructed in the non-pixel area of ​​the chip to achieve photonic bandgap and strong scattering effects. This near-triangular cross-section micro-aperture array differs significantly in geometry from traditional circular and square aperture arrays, providing a wider scattering angle and higher local field enhancement within the same wavelength band, significantly improving the light capture and reflection efficiency of the chip's underlying layer. Furthermore, in the formed SiN... x On the surface of the triangular aperture structure, a Yb layer is deposited using magnetron sputtering. This utilizes the broadband conversion-luminescence properties and large absorption cross-section of Yb metal to achieve the absorption and re-emission of unused photons. Furthermore, the Yb metal layer directly covers the SiN... x The surface of the triangular hole wall can utilize SiN x The optical resonance effect of the triangular aperture array enhances performance while maintaining good chemical stability due to the inherent properties of the metal, effectively avoiding oxidation or migration problems. This invention proposes directly depositing a Yb layer onto microstructured SiN. x A reflective layer is used to achieve a complete technical solution of "light energy capture-conversion-reflection" closed loop, through which SiN... x The strong scattering and photonic bandgap characteristics of the near-triangular aperture array are synergistically combined with the light energy conversion function of the Yb layer metal to form a novel light reflection / conversion composite structure at the bottom of the chip. This structure can provide additional light energy recovery and reuse channels for subsequent upper functional layers of the chip (such as photodetector layers, photovoltaic layers, or optical modulation layers), effectively filling the technological gap in the field of efficient utilization of light energy at the bottom layer of current optical devices.

[0020] Preferably, the thickness of the silicon nitride layer is 300~350nm, including but not limited to: 300nm, 310nm, 320nm, 330nm, 340nm, 350nm, etc.; the thickness represents the height from the bottom to the top.

[0021] Preferably, the depth of the triangular microporous structure is 240~280nm, including but not limited to: 240nm, 250nm, 260nm, 270nm, 280nm, etc.

[0022] Preferably, the metal column is one of tungsten, copper, silver, or gold.

[0023] Preferably, the thickness of the ytterbium layer is 30~40nm, including but not limited to: 30nm, 31nm, 32nm, 33nm, 34nm, 35nm, 36nm, 37nm, 38nm, 39nm, 40nm, etc.

[0024] Secondly, the present invention provides a method for fabricating a chip with an array-type reflective structure, comprising the following steps: S1: Prepare a chip with an array of metal pillars; prepare a silicon nitride layer on the upper surface of one side of the metal pillars of the chip; then spin-coat photoresist on the silicon nitride layer, and after exposure and development, expose the corresponding area of ​​the array of triangular micro-holes to be etched to obtain intermediate device 1. S2: The corresponding area of ​​the array of triangular micro-holes of intermediate device 1 is exposed and etched to form an array of triangular micro-holes on the silicon nitride layer; after etching, the photoresist is removed to obtain intermediate device 2. S3: Spin-coat photoresist onto the silicon nitride layer of intermediate device 2 until the entire surface is flat, and then expose and develop to form a photoresist pattern that exposes the pixel area; then etch the silicon nitride layer of the pixel area until the metal pillars of the pixel area are exposed, remove the photoresist, and obtain intermediate device 3; S4: Inkjet print photoresist onto the metal pillars in the 3-pixel area of ​​the intermediate device to protect the metal pillars; then, deposit a ytterbium layer on the entire surface of the device by magnetron sputtering. After deposition, remove the photoresist to obtain a chip with an array-type reflective structure.

[0025] In the preparation method of the present invention, firstly, in SiN x Photoresist is deposited and patterned to preserve micropores in non-pixel areas and completely cover pixel areas. Subsequent processes include dry etching, resist removal, secondary photolithography, inkjet printing of photoresist-protected metal pillars, magnetron sputtering of the Yb layer, and removal of photoresist from pixel areas, precisely forming the target structure where the Yb layer is retained only on the hole array. This invention offers strong process compatibility, adapting to 2-inch, 4-inch, 6-inch, and 8-inch chips, and all processes (ICP-CVDSiN) are compatible. x The methods (including dual photolithography, dry etching, magnetron sputtering, and inkjet printing) all conform to CMOS standards and can be mass-produced on 4-inch, 6-inch, and 8-inch wafer lines without the need for additional high-cost dedicated equipment, significantly reducing process investment and yield risks. Third, the method of this invention uses inkjet printing to temporarily cover photoresist on metal pillars, which can form complete protection for the pixel area, effectively avoiding pixel damage caused by multiple photolithography or mask alignment in traditional processes, and improving the dimensional accuracy and electrical performance consistency of the pixel structure. Fourth, Yb metal is directly deposited on SiN... x Hole walls, using SiN xThe supporting role and chemical inert protection of the Yb metal layer prevent oxidation, migration, or peeling during subsequent high-temperature processing or deposition of upper functional layers (such as ALD, CVD), ensuring the optical performance and reliability of the device under long-term operating conditions. Fifth: The present invention offers high process flexibility. The aperture, aperture spacing, tilt angle, and Yb film thickness can be independently adjusted through process parameters such as photolithography resolution, RIE time, and sputtering power. This allows for precise matching of optical characteristics to different wavebands and device requirements (such as photoelectric detection, photovoltaics, optical modulation, etc.), providing greater design freedom compared to existing fixed structures. Sixth: The fabrication method of the present invention has lower costs. Compared to traditional multilayer metal / dielectric stacked high-reflectivity mirror solutions, this method requires only one layer of SiN. x One-step dry etching and one-layer Yb metal deposition significantly reduce material and process costs, while the simplified structure improves the overall process yield.

[0026] Preferably, in step S1, the method for preparing the silicon nitride layer is ICP-CVD deposition, and the specific process parameters are: deposition temperature of 70~80℃, including but not limited to: 70℃, 72℃, 75℃, 78℃, 80℃, etc.; ICP power of 350~400 Ω. W, including but not limited to: 350W, 360W, 370W, 380W, 390W, 400W, etc.; SiH4 and N2 flow rates are 6.8~7.2mL / min (including but not limited to: 6.8mL / min, 6.9mL / min, 7.0mL / min, 7.1mL / min, 7.2mL / min, etc.) and 6.3~6.7mL / min (including but not limited to: 6.3mL / min, 6.4mL / min, 6.5mL / min, 6.6mL / min, 6.7mL / min, etc.), respectively; working gas pressure is 5~10mtorr, including but not limited to: 5mtorr, 6mtorr, 7mtorr, 8mtorr, 9mtorr, 10mtorr, etc.; coating time is 25~30 min, including but not limited to: 25min, 26min, 27min, 28min, 29min, 30min, etc.

[0027] Preferably, in steps S1 and S3, the spin coating speed is 2000~3000 rpm, including but not limited to: 2000 rpm, 2200 rpm, 2500 rpm, 2800 rpm, 3000 rpm, etc.; the photoresist thickness is 2~3 μm, including but not limited to: 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, etc.; and the exposure dose is 120~180 mJ / cm. 2 Including but not limited to: 120mJ / cm 2 130mJ / cm 2 140mJ / cm2 150mJ / cm 2 160mJ / cm 2 170mJ / cm 2 180mJ / cm 2 The development time is 45-60 seconds, including but not limited to: 45 seconds, 50 seconds, 55 seconds, 60 seconds, etc.

[0028] Preferably, in step S2, the etching is performed using dry etching. The process parameters for dry etching are as follows: vacuum degree 10~20 mTorr, including but not limited to: 10 mTorr, 12 mTorr, 15 mTorr, 18 mTorr, 20 mTorr, etc.; etching power 120~140 W, including but not limited to: 120 W, 125 W, 130 W, 135 W, 140 W, etc.; etching gas is a mixture of CHF3 and O2, with CHF3 gas flow rate of 45~55 sccm, including but not limited to: 45 sccm, 48 sccm, 50 sccm, 52 sccm, 55 sccm, etc.; O2 gas flow rate of 8~11 sccm, including but not limited to: 8 sccm, 9 sccm, 10 sccm, 11 sccm, etc.; etching time 10~15 min, including but not limited to: 10 min, 11 min, 12 min, 13 min, 14 min, 15 min, etc.

[0029] Preferably, in steps S2 and S3, the method for removing photoresist is as follows: immerse the device in a photoresist remover solution and soak it at a temperature of 70~80℃ (including but not limited to: 70℃, 72℃, 75℃, 78℃, 80℃, 82℃, 85℃, etc.) for 10~30 min (including but not limited to: 10 min, 15 min, 20 min, 25 min, 30 min, etc.); then rinse it with an alcohol spray gun and finally purge it with a nitrogen gun.

[0030] Preferably, in step S3, the etching is performed using dry etching. The process parameters for dry etching are as follows: vacuum degree 10~20 mTorr, including but not limited to: 10 mTorr, 12 mTorr, 15 mTorr, 18 mTorr, 20 mTorr, etc.; etching power 120~140 W, including but not limited to: 120 W, 125 W, 130 W, 135 W, 140 W, etc.; etching gas is a mixture of CHF3 and O2, with CHF3 gas flow rate of 45~55 sccm, including but not limited to: 45 sccm, 48 sccm, 50 sccm, 52 sccm, 55 sccm, etc.; O2 gas flow rate of 8~11 sccm, including but not limited to: 8 sccm, 9 sccm, 10 sccm, 11 sccm, etc.; etching time 12~18 min, including but not limited to: 12 min, 13 min, 14 min, 15 min, 16 min, 17 min, 18 min, etc.

[0031] Preferably, in step S4, the magnetron sputtering is DC magnetron sputtering; the process parameters of DC magnetron sputtering are as follows: sputtering power is 100~200W, including but not limited to: 100W, 120W, 150W, 180W, 200W, etc.; the distance between the device and the target is set to 80~120mm, including but not limited to: 80mm, 90mm, 100mm, 110mm, 120mm, etc.; the working gas is argon, and the working gas flow rate is 40~60sccm, including but not limited to: 40sccm, 45sccm, 50sccm, 55sccm, 60sccm, etc.; the total system pressure is 0.5~1Pa, including but not limited to: 0.5Pa, 0.6Pa, 0.7Pa, 0.8Pa, 0.9Pa, 1.0Pa, etc.; the device temperature is 25~80℃, including but not limited to: 25℃, 30℃, 40℃, 50℃, 60℃, 70℃, 80℃, etc.

[0032] Thirdly, the present invention provides a photovoltaic device, including the aforementioned chip with an array-type reflective structure.

[0033] Fourthly, the present invention provides an optoelectronic device, including the aforementioned chip having an array-type reflective structure.

[0034] A chip with an array-type reflective structure is shown in the schematic diagram of this invention. Figure 1 ;include: The chip layer includes independent pixel regions and non-pixel regions; within the pixel regions are periodically arranged arrays of metal pillars; a silicon nitride layer is formed on the upper surface of the non-pixel regions of the chip layer, and the upper surface of the silicon nitride layer has a periodically arranged array of triangular micropores; a ytterbium layer conformally covers the upper surface of the silicon nitride layer. The fabrication process flow diagram of the chip with the array-type reflective structure of this invention can be seen. Figures 2-5 For specific preparation methods, please refer to the examples.

[0035] Example 1 S1: The process flow diagram for this step is as follows: Figure 2 As shown, the specific steps are as follows: Prepare a chip with an array of tungsten pillars; prepare a 320nm thick silicon nitride layer on the upper surface of one side of the tungsten pillars of the chip using an ICP-CVD coating machine (specific process parameters are: coating temperature 75℃, ICP power 380 W, SiH4 and N2 flow rates 7.0mL / min and 6.5mL / min respectively, working gas pressure 8.5mtorr, coating time 27min); then spin-coat a 2.5μm thick photoresist layer on the silicon nitride layer at 2500rpm, and after pre-baking (115℃ for 70s), apply a photoresist at 150mJ / cm². 2 Expose with the exposure dose, bake after baking (115℃ for 70s), soak in developer for 50s, spin dry at 5800rpm for 18s after development, expose the position of the array of triangular micro-holes to be etched, and obtain intermediate device 1. S2: The process flow diagram for this step is as follows: Figure 3 As shown, the specific steps are as follows: A RIE etching machine is used to dry etch the array of triangular micro-holes in intermediate device 1 (the dry etching process parameters are: vacuum degree 15 mTorr, etching power 130 W, etching gas is a mixture of CHF3 and O2, CHF3 gas flow rate 50 sccm, O2 gas flow rate 10 sccm, etching time 13 min, and etching depth 260 nm), forming an array of triangular micro-holes on the silicon nitride layer. After etching, the device is placed in a photoresist remover solution and immersed at 75°C for 20 min to remove the photoresist. Then, it is rinsed with an alcohol spray gun and purged with a nitrogen gun to obtain intermediate device 2.

[0036] S3: The process flow diagram for this step is as follows: Figure 4 As shown, the specific steps are as follows: A 2.5 μm thick layer of photoresist is spin-coated onto the silicon nitride layer of intermediate device 2 at 2500 rpm until the entire surface is smooth. After pre-baking (115℃ for 70 s), a photoresist is applied at 150 mJ / cm². 2The device is exposed to the specified exposure dose, then baked (115℃ for 70s), and then immersed in developer for 50s. After development, it is spun dry at 5800rpm for 18s to form a photoresist pattern that exposes the pixel area. Then, the silicon nitride layer in the pixel area is dry etched using a RIE etching machine (the dry etching process parameters are: vacuum degree of 15mTorr, etching power of 130W, etching gas is a mixture of CHF3 and O2, CHF3 gas flow rate of 50sccm, O2 gas flow rate of 10sccm, and etching time of 15min) until the tungsten pillars in the pixel area are exposed. The device is then placed in a photoresist remover and immersed at 75℃ for 20min to remove the photoresist. It is then rinsed with an alcohol spray gun and finally purged with a nitrogen gun to obtain intermediate device 3.

[0037] S4: The process flow diagram for this step is as follows Figure 5 As shown, the specific steps are as follows: Inkjet printing of photoresist is performed on the tungsten pillars in the 3-pixel region of the central device to protect the tungsten pillars; then, a 35nm thick ytterbium layer is deposited on the entire surface of the device by magnetron sputtering (process parameters: sputtering power 150W, device-target distance 100mm, working gas argon, working gas flow rate 50sccm, system total pressure 0.8Pa, device temperature 50℃). After deposition, the device is immersed in a photoresist remover solution at 75℃ for 20 minutes to remove the photoresist; then, it is rinsed with an alcohol spray gun and finally purged with a nitrogen gun to obtain a chip with an array-type reflective structure.

[0038] Comparative Example 1 Compared with Example 1, this comparative example does not have an array of triangular microporous structures and a ytterbium layer. The preparation method is as follows: Prepare a chip with an array of tungsten pillars; deposit a 320 nm thick silicon nitride layer on the upper surface of one side of the tungsten pillars using an ICP-CVD coating machine (specific process parameters: coating temperature 75℃, ICP power 380W, SiH4 and N2 flow rates 7.0 and 6.5 mL / min respectively, working gas pressure 8.5 mtorr, coating time 27 min); then spin-coat a 2.5 μm thick photoresist layer onto the silicon nitride layer at 2500 rpm, followed by pre-baking (115℃ for 70 s) and then applying a photoresist at 150 mJ / cm². 2The device is exposed to the specified exposure dose, then baked (115℃ for 70s), and then immersed in developer for 50s. After development, it is spun dry at 5800rpm for 18s to expose the pixel area. Then, a RIE etching machine is used to dry etch the silicon nitride layer of the pixel area (the dry etching process parameters are: vacuum degree of 15mTorr, etching power of 130W, etching gas is a mixture of CHF3 and O2, CHF3 gas flow rate of 50sccm, O2 gas flow rate of 10sccm, etching time of 15min) until the tungsten pillar of the pixel area is exposed. The device is then placed in a photoresist remover and immersed at 75℃ for 20min to remove the photoresist. Then, it is rinsed with an alcohol spray gun and finally purged with a nitrogen gun to obtain a chip with a reflective structure.

[0039] Comparative Example 2 It is basically the same as Example 1, except that the ytterbium layer deposition in step S4 is not performed, and the intermediate device 3 is a chip with an array-type reflective structure.

[0040] Comparative Example 3 The specific fabrication method for a chip without an array of triangular micropore structures is as follows: S1: Prepare a chip with an array of tungsten pillars; prepare a 320nm thick silicon nitride layer on the upper surface of the tungsten pillar side of the chip using an ICP-CVD coating machine (specific process parameters are: coating temperature 75℃, ICP power 380W, SiH4 and N2 flow rates 7.0 and 6.5mL / min respectively, working gas pressure 8.5mtorr, coating time 27min); then spin-coat a 2.5μm thick photoresist layer on the silicon nitride layer at 2500rpm, and after pre-baking (115℃ for 70s), apply a photoresist at 150mJ / cm². 2 Expose the device to the specified exposure dose, then bake it at 115°C for 70 seconds, then immerse it in the developer for 50 seconds, and finally spin it dry at 5800 rpm for 18 seconds to expose the tungsten pillar, thus obtaining intermediate device 1. S2: The silicon nitride layer of the pixel area of ​​intermediate device 1 is dry-etched using a RIE etching machine (the process parameters for dry etching are: vacuum degree of 15mTorr, etching power of 130W, etching gas is a mixture of CHF3 and O2, CHF3 gas flow rate of 50sccm, O2 gas flow rate of 10sccm, and etching time of 15min) until the tungsten pillar of the pixel area is exposed. Then, the device is placed in the photoresist remover and immersed at 75°C for 20min to remove the photoresist. Then, it is rinsed with an alcohol spray gun and finally purged with a nitrogen gun to obtain intermediate device 2.

[0041] S3: Inkjet printing photoresist is used to protect the metal pillars in the 2-pixel region of the intermediate device. Then, a 35nm thick ytterbium layer is deposited on the entire surface of the device by magnetron sputtering (process parameters: sputtering power 150W, device-target distance 100mm, working gas argon, working gas flow rate 50sccm, system total pressure 0.8Pa, device temperature 50℃). After deposition, the device is placed in a photoresist remover solution and immersed at 75℃ for 20min to remove the photoresist. Then, it is rinsed with an alcohol spray gun and finally purged with a nitrogen gun to obtain a chip with a reflective structure.

[0042] Example 2 S1: The process flow diagram for this step is as follows: Figure 2 As shown, the specific steps are as follows: Prepare a chip with an array of copper pillars; prepare a 350nm thick silicon nitride layer on the upper surface of one side of the copper pillars of the chip using an ICP-CVD coating machine (specific process parameters are: coating temperature 70℃, ICP power 400W, SiH4 and N2 flow rates 7.2mL / min and 6.7mL / min respectively, working gas pressure 5mtorr, coating time 30min); then spin-coat a 2μm thick photoresist layer on the silicon nitride layer at 2000rpm, and after pre-baking (110℃ for 80s), apply a photoresist at 120mJ / cm². 2 Expose with the exposure dose, bake after baking (110℃ for 80s), soak in developer for 60s, spin dry at 6000rpm for 15s after development, expose the position of the triangular micro-holes to be etched in an array, and obtain intermediate device 1. S2: The process flow diagram for this step is as follows: Figure 3 As shown, the specific steps are as follows: A RIE etching machine is used to dry etch the array of triangular micro-holes in intermediate device 1 (the dry etching process parameters are: vacuum degree 10 mTorr, etching power 140 W, etching gas is a mixture of CHF3 and O2, CHF3 gas flow rate 55 sccm, O2 gas flow rate 11 sccm, etching time 10 min, and etching depth 280 nm), forming an array of triangular micro-holes on the silicon nitride layer. After etching, the device is immersed in a photoresist remover at 80°C for 10 min to remove the photoresist. Then, it is rinsed with an alcohol spray gun and purged with a nitrogen gun to obtain intermediate device 2.

[0043] S3: The process flow diagram for this step is as follows: Figure 4 As shown, the specific steps are as follows: A 2μm thick layer of photoresist is spin-coated onto the silicon nitride layer of intermediate device 2 at 2000 rpm until the entire surface is smooth. After pre-baking (110℃ for 80s), a photoresist layer is applied at 120mJ / cm². 2The device is exposed to the specified exposure dose, then baked (110℃ for 80s), and then immersed in developer for 60s. After development, it is spun dry at 6000rpm for 15s to form a photoresist pattern that exposes the pixel area. Then, the silicon nitride layer in the pixel area is dry etched using a RIE etching machine (the process parameters for dry etching are: vacuum degree of 10mTorr, etching power of 140W, etching gas is a mixture of CHF3 and O2, CHF3 gas flow rate of 55sccm, O2 gas flow rate of 11sccm, and etching time of 18min) until the copper pillars in the pixel area are exposed. The device is then placed in a photoresist remover and immersed at 80℃ for 10min to remove the photoresist. It is then rinsed with an alcohol spray gun and finally purged with a nitrogen gun to obtain intermediate device 3.

[0044] S4: The process flow diagram for this step is as follows Figure 5 As shown, the specific steps are as follows: Inkjet printing of photoresist is performed on the copper pillars in the 3-pixel area of ​​the central device to protect the copper pillars; then, a 30nm thick ytterbium layer is deposited on the entire surface of the device by magnetron sputtering (process parameters: sputtering power 100W, device-target distance set to 80mm, working gas is argon, working gas flow rate is 60sccm, system total pressure is 1Pa, device temperature is 80℃). After deposition, the device is placed in a photoresist remover and immersed at 80℃ for 10min to remove the photoresist; then, it is rinsed with an alcohol spray gun and finally purged with a nitrogen gun to obtain a chip with an array-type reflective structure.

[0045] Example 3 S1: The process flow diagram for this step is as follows: Figure 2 As shown, the specific steps are as follows: Prepare a chip with an array of silver pillars; fabricate a 300nm thick silicon nitride layer on the upper surface of one side of the silver pillars using an ICP-CVD coating machine (specific process parameters are: coating temperature 80℃, ICP power 350W, SiH4 and N2 flow rates 6.8mL / min and 6.3mL / min respectively, working gas pressure 10mtorr, coating time 25min); then spin-coat a 3μm thick photoresist layer onto the silicon nitride layer at 3000rpm, and after pre-baking (120℃ for 60s), apply a photoresist at 180mJ / cm². 2 Expose with the exposure dose, bake after baking (120℃ for 60s), soak in developer for 45s, spin dry at 5500rpm for 20s, expose the position of the triangular micro-holes to be etched in an array, and obtain intermediate device 1. S2: The process flow diagram for this step is as follows: Figure 3As shown, the specific steps are as follows: A RIE etching machine is used to dry etch the array of triangular micro-holes in intermediate device 1 (the dry etching process parameters are: vacuum degree 20 mTorr, etching power 120 W, etching gas is a mixture of CHF3 and O2, CHF3 gas flow rate 45 sccm, O2 gas flow rate 8 sccm, etching time 15 min, and etching depth 240 nm), forming an array of triangular micro-holes on the silicon nitride layer. After etching, the device is placed in a photoresist remover solution and immersed at 70°C for 300 min to remove the photoresist. Then, it is rinsed with an alcohol spray gun and purged with a nitrogen gun to obtain intermediate device 2.

[0046] S3: The process flow diagram for this step is as follows: Figure 4 As shown, the specific steps are as follows: A 3μm thick layer of photoresist is spin-coated onto the silicon nitride layer of intermediate device 2 at 3000 rpm until the entire surface is smooth. After pre-baking (120℃ for 60s), a photoresist is applied at 180mJ / cm². 2 The device is exposed to the specified exposure dose, then baked (120℃ for 60s), and then immersed in developer for 45s. After development, it is spun dry at 5500rpm for 20s to form a photoresist pattern that exposes the pixel area. Then, the silicon nitride layer in the pixel area is dry etched using a RIE etching machine (the dry etching process parameters are: vacuum degree of 15mTorr, etching power of 120W, etching gas is a mixture of CHF3 and O2, CHF3 gas flow rate of 45sccm, O2 gas flow rate of 8sccm, and etching time of 12min) until the silver pillars in the pixel area are exposed. The device is then placed in a photoresist remover and immersed at 70℃ for 30min to remove the photoresist. Then, it is rinsed with an alcohol spray gun and finally purged with a nitrogen gun to obtain intermediate device 3.

[0047] S4: The process flow diagram for this step is as follows Figure 5 As shown, the specific steps are as follows: Inkjet printing of photoresist is performed on the copper pillars in the 3-pixel region of the central device to protect the silver pillars; then, a 40nm thick ytterbium layer is deposited on the entire surface of the device by magnetron sputtering (process parameters: sputtering power 200W, device-target distance 120mm, working gas argon, working gas flow rate 40sccm, system total pressure 0.5Pa, device temperature 25℃). After deposition, the device is immersed in a photoresist remover solution at 70℃ for 30 minutes to remove the photoresist; then, it is rinsed with an alcohol spray gun and finally purged with a nitrogen gun to obtain a chip with an array-type reflective structure.

[0048] On the chips with reflective structures in Examples 1-3 and Comparative Examples 1-3, functional layers were fabricated to obtain optoelectronic devices. The specific fabrication methods are as follows: (1) Deposition of hole transport layer: The chips prepared in Examples 1-3 and Comparative Examples 1-3 were placed in a magnetron sputtering coating machine, and the nickel oxide target was placed at the cathode position. The vacuum was evacuated to 5×10 -4 Pa was introduced into the structure and the radio frequency sputtering power supply was turned on (sputtering power of 255W). A nickel oxide layer with a thickness of about 25nm was deposited on the reflective structure to obtain a hole transport layer (in Examples 1-3 and Comparative Examples 1-3, the hole transport layer still retains the upper surface structure of the chip).

[0049] (2) Deposition of quantum dots: 310~320mg / mL of liquid-phase exchanged PbS quantum dots were spin-coated onto the hole transport layer prepared in step (1). The amount used was 45μL. The spin coater speed was 1800rpm and the spin coat time was 15s. After preparation, the layer was placed on a heating stage and annealed for 10min to obtain a quantum dot layer with a thickness of 350nm (in Examples 1~3 and Comparative Examples 1~3, the entire surface was filled until the surface was flat. The thickness of 350nm represents the thickness of the quantum dot layer in the non-pixel region. In Examples 1~3 and Comparative Example 2, the chip with an array-type reflective structure, the thickness of the quantum dots in the non-pixel region represents the thickness from the bottom of the triangular structure to the top surface of the quantum dots).

[0050] (3) Preparation of electron transport layer: On the quantum dot layer prepared in step (2), spin-coat a pre-prepared ZnO solution with a ZnO solution concentration of 50 mg / mL and a volume of 75 μL each time. The spin coater speed is 5000 rpm and the spin coat time is 20 s to obtain an electron transport layer with a thickness of 40 nm.

[0051] (4) Preparation of electrode layer: A 20 nm thick chromium layer is first vacuum-deposited on the surface of the electron transport layer prepared in step (3) at a slower rate, and then a 100 nm thick gold layer is vacuum-deposited at a faster rate to obtain a photodetector.

[0052] The responsivity and detectivity of the photodetectors fabricated with reflective structure chips in Examples 1-3 and Comparative Examples 1-3 were tested, and the test results are shown in Table 1.

[0053] Responsivity: The output voltage or current of a photodetector under unit irradiation conditions, calculated using the following formula: Where Iph and Vph are the output photocurrent and voltage, P is the incident light power density, and S is the effective area.

[0054] Detectability (D*): D* is the detector's efficiency per unit surface area (1 cm²). 2 and unit bandwidth (1 Hz) The spectral detectivity under certain conditions reflects the detector's sensitivity and signal-to-noise ratio. Normalized sensitivity can be obtained for all photodetectors through noise testing, making it easier to compare the performance of different detectors. The formula for D* is as follows: Where In is the noise current and Δf is the instrument bandwidth.

[0055] Table 1 As can be seen from the data in Table 1, the photodetector fabricated with the chip having a reflective structure in Example 1 exhibits high responsivity and detectivity. In Comparative Example 1, the photodetector fabricated with the chip having a reflective structure shows lower responsivity and detectivity compared to Example 1. The photodetector fabricated with the chip having a reflective structure in Comparative Example 2 shows a slight improvement in responsivity and detectivity compared to Comparative Example 1, but the improvement is small and significantly lower than that of Example 1. The photodetector fabricated with the chip having a reflective structure in Comparative Example 3 shows a slight improvement in responsivity and detectivity compared to Comparative Example 1, but the improvement is small and significantly lower than that of Example 1. Comparing Example 1 with Comparative Examples 1-3, the chip having a reflective structure in Example 1, due to the simultaneous presence of an arrayed triangular structure and a ytterbium layer, exhibits a synergistic effect between the two structures, significantly improving the responsivity and detectivity of the photodetector. In Examples 2-3, the process parameters of the chip having a reflective structure were adjusted, resulting in some fluctuation in the performance of the photodetectors fabricated, but all exhibited high responsivity and detectivity.

[0056] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A chip with an array-type reflective structure, characterized in that, include: Chip layer: includes independent pixel regions and non-pixel regions; Metal pillar structure: formed within the pixel region of the chip layer and arranged in a periodic array; Silicon nitride layer: formed on the upper surface of the non-pixel area of ​​the chip layer, the upper surface of the silicon nitride layer has a triangular micropore structure arranged in a periodic array; Ytterbium layer: Conformally covered on the upper surface of the silicon nitride layer.

2. The chip with an array-type reflective structure according to claim 1, characterized in that, The thickness of the silicon nitride layer is 300~350nm; And / or: the depth of the triangular microporous structure is 240~280nm; And / or: the metal column is one of tungsten column, copper column, silver column, and gold column; And / or: The thickness of the ytterbium layer is 30~40nm.

3. The method for fabricating a chip with an array-type reflective structure according to claim 1 or 2, characterized in that, Includes the following steps: S1: Prepare a chip with an arrayed metal pillar structure; A silicon nitride layer is prepared on the upper surface of one side of the metal pillar of the chip; then photoresist is spin-coated on the silicon nitride layer, and after exposure and development, the corresponding area of ​​the array of triangular micro-holes to be etched is exposed to obtain intermediate device 1. S2: Etch the area corresponding to the array of triangular micro-holes of intermediate device 1 to form an array of triangular micro-hole structures on the silicon nitride layer. Etching After completion, the photoresist is removed to obtain intermediate device 2; S3: Spin-coat photoresist onto the silicon nitride layer of intermediate device 2 until the entire surface is flat, and then expose and develop to form a photoresist pattern that exposes the pixel area; then etch the silicon nitride layer of the pixel area until the metal pillars of the pixel area are exposed, remove the photoresist, and obtain intermediate device 3; S4: Inkjet print photoresist onto the metal pillars in the 3-pixel area of ​​the intermediate device to protect the metal pillars; Then, a ytterbium layer is deposited on the entire surface of the device by magnetron sputtering. After deposition, the photoresist is removed to obtain a chip with an array-type reflective structure.

4. The method for fabricating a chip with an array-type reflective structure according to claim 3, characterized in that, In step S1, the method for preparing the silicon nitride layer is ICP-CVD deposition, and the specific process parameters are as follows: deposition temperature is 70~80℃, ICP power is 350~400W, SiH4 and N2 flow rates are 6.8~7.2mL / min and 6.3~6.7mL / min respectively, working gas pressure is 5~10mtorr; deposition time is 25~30min.

5. The method for fabricating a chip with an array-type reflective structure according to claim 3, characterized in that, In steps S1 and S3, the spin coating speed is 2000~3000 rpm, the photoresist thickness is 2~3 μm, and the exposure dose is 120~180 mJ / cm. 2 The development time is 45~60s.

6. The method for fabricating a chip with an array-type reflective structure according to claim 3, characterized in that, In step S2, the etching is performed using dry etching. The process parameters for dry etching are: vacuum degree 10~20mTorr, etching power 120~140W, etching gas is a mixture of CHF3 and O2, CHF3 gas flow rate is 45~55sccm, O2 gas flow rate is 8~11sccm, and etching time is 10~15min.

7. The method for fabricating a chip with an array-type reflective structure according to claim 3, characterized in that, In step S3, the etching is performed using dry etching. The process parameters for dry etching are: vacuum degree 10~20mTorr, etching power 120~140W, etching gas is a mixture of CHF3 and O2, CHF3 gas flow rate is 45~55sccm, O2 gas flow rate is 8~11sccm, and etching time is 12~18min.

8. The method for fabricating a chip with an array-type reflective structure according to claim 3, characterized in that, In step S4, the magnetron sputtering adopts DC magnetron sputtering; the process parameters of DC magnetron sputtering are: sputtering power of 100~200W, distance between device and target of 80~120mm, working gas of argon, working gas flow rate of 40~60sccm, total system pressure of 0.5~1Pa, and device temperature of 25~80℃.

9. A photovoltaic device, characterized in that, Includes the chip with an array-type reflective structure as described in claim 1 or 2; or the chip with an array-type reflective structure prepared by any of the preparation methods described in claims 3 to 8.

10. An optoelectronic device, characterized in that, Includes the chip with an array-type reflective structure as described in claim 1 or 2; or the chip with an array-type reflective structure prepared by any of the preparation methods described in claims 3 to 8.

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