Test structure and test method
By setting the stacked structure to be tested in the substrate sealing area, including a first metal layer, a second metal layer and interconnect vias, the problem of difficulty in detecting tiny via open defects in the prior art is solved, and efficient monitoring of the health of wafer-level interconnect vias is achieved, improving the reliability of the test structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2026-05-29
AI Technical Summary
Existing technologies are insufficient to effectively detect via open defects of one in a million, one in ten million, or even one in a hundred million, resulting in insufficient reliability of the test structure.
The stacked structure to be tested, including a first metal layer, a second metal layer and interconnecting vias, is set in the sealed area of the substrate. The contact condition is determined by obtaining the total contact resistance, thereby increasing the number of stacked structures to be tested and the effective area.
This improves the reliability of the test structure, effectively monitors the health of interconnect vias at the wafer level, and enhances testing efficiency.
Smart Images
Figure CN122121628A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a test structure and test method. Background Technology
[0002] Incomplete contact between interconnect vias and the upper and lower metal layers (via open) is one of the most challenging aspects of process inspection. Due to limited redundant circuitry, a few via open holes in a logic circuit can typically cause the entire chip to fail. Furthermore, due to physical limitations, via open holes beneath the metal layers cannot be detected using conventional defect detection methods.
[0003] For via open connections with a density of one in a million, one in ten million, or even one in a hundred million, the common approach is to design a large-area test structure and characterize the health of the interconnect via through electrical testing.
[0004] The number of interconnect vias is determined by their area; the larger the area, the higher the level of via open defect that can be characterized. However, due to limitations in the area of the test structure, the area of the test structure placed in the product is often small, making it difficult to detect via open defects of one in a million, one in ten million, or even one in a hundred million.
[0005] Currently, the reliability of the via open defect level that the test structure can characterize still needs to be improved. Summary of the Invention
[0006] The problem solved by the embodiments of the present invention is to provide a test structure and test method, which helps to improve the reliability of the test structure.
[0007] To address the aforementioned problems, embodiments of the present invention provide a test structure comprising: a substrate, the substrate including a chip region and a sealing region surrounding the chip region; a dielectric layer located above the substrate; and one or more stacked structures under test located in the dielectric layer above the sealing region of the substrate and exposing the chip region. The stacked structures under test include one or more interconnect stacks stacked vertically, the interconnect stacks under test including a first metal layer and a second metal layer located above the first metal layer, and interconnect vias located between the first metal layer and the second metal layer, wherein both the first metal layer and the second metal layer are electrically connected to the interconnect vias.
[0008] Optionally, the first metal layer includes a plurality of first sub-metal layers extending along a first direction and arranged in parallel at intervals along the first direction; the second metal layer includes a plurality of second sub-metal layers extending along a first direction and arranged in parallel at intervals along the first direction, the second sub-metal layers and the first sub-metal layers being staggered in the longitudinal direction, and the first sub-metal layers and the second sub-metal layers being sequentially connected in series through the interconnecting vias.
[0009] Optionally, the dimension of the first sub-metal layer extending in the first direction is equal to the dimension of the second sub-metal layer extending in the first direction.
[0010] Optionally, the dimension of the distance between adjacent first sub-metal layers in the first direction is equal to the dimension of the distance between adjacent second sub-metal layers in the first direction.
[0011] Optionally, the size of the spacing between adjacent first sub-metal layers in the first direction ranges from 10 nanometers to 200 nanometers.
[0012] Optionally, when there are multiple stacked structures to be tested, the stacked structures to be tested extend along a first direction and are arranged in parallel at intervals along a second direction, and the first direction and the second direction are perpendicular to each other.
[0013] Optionally, the distance between adjacent test stacks in the second direction is 40 nanometers to 800 nanometers.
[0014] Optionally, in the extension direction of the interconnect stack under test, the interconnect stack under test includes a first end and a second end opposite thereto; the test structure further includes: a first test signal loading terminal located in a dielectric layer above the substrate of the sealing region, the first test signal loading terminal being electrically connected to the first end; and a second test signal loading terminal located in a dielectric layer above the substrate of the sealing region, the second test signal loading terminal being electrically connected to the second end.
[0015] Optionally, the material of the first test signal loading end includes one or two of copper and aluminum; the material of the second test signal loading end includes one or two of copper and aluminum.
[0016] Optionally, the test structure further includes: a plurality of sealing rings located in a dielectric layer above the substrate of the sealing area, and the stacked structure under test located in a dielectric layer between adjacent sealing rings.
[0017] Optionally, the sealing ring may be made of one or both of aluminum and tantalum nitride.
[0018] Optionally, the substrate further includes a cut channel area surrounding the sealing area, and the area occupied by the cut channel area is smaller than the area occupied by the sealing area; one or more of the stacked structures under test expose the top surface of the cut channel area.
[0019] Accordingly, this embodiment of the invention also provides a testing method, including: providing the test structure provided in this embodiment of the invention; obtaining the total contact resistance between the interconnect via and the first metal layer and the second metal layer in the interconnect stack to be tested; and determining whether the interconnect via and the first metal layer and the second metal layer are in complete contact based on the obtained total contact resistance.
[0020] Optionally, in the step of providing the test structure, in the extension direction of the interconnect stack under test, the interconnect stack under test includes a first end and a second end opposite thereto; the test structure further includes: a first test signal loading terminal located in a dielectric layer above the substrate of the sealing region, the first test signal loading terminal being electrically connected to the first end; a second test signal loading terminal located in a dielectric layer above the substrate of the sealing region, the second test signal loading terminal being electrically connected to the second end; the step of obtaining the total contact resistance includes: applying a constant current to the interconnect stack under test through the first test signal loading terminal and the second test signal loading terminal; after applying the constant current, obtaining the voltage between the first test signal loading terminal and the second test signal loading terminal; based on the voltage and the constant current, obtaining the total contact resistance between the interconnect vias and the first metal layer and the second metal layer in the interconnect stack under test.
[0021] Optionally, the step of determining the reliability of the interconnect via based on the acquired total contact resistance includes: comparing the acquired total contact resistance with a preset contact resistance, wherein the preset contact resistance is used to characterize the ideal contact resistance when the interconnect via is in complete contact with the first metal layer and the second metal layer; when the total contact resistance is consistent with the preset contact resistance, the interconnect via is in complete contact with the first metal layer and the second metal layer; when the total contact resistance is inconsistent with the preset contact resistance, the interconnect via is not in complete contact with the first metal layer and the second metal layer.
[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0023] This invention provides a test structure in which one or more stacked structures under test are located in a dielectric layer above a substrate in a sealed region and exposed in a chip region. The stacked structure under test includes one or more interconnect layers stacked vertically. Each interconnect layer includes a first metal layer, a second metal layer above the first metal layer, and interconnect vias located between the first and second metal layers. Both the first and second metal layers are electrically connected to the interconnect vias. Compared to a solution where the stacked structure under test is located in a dicing area, this invention places the stacked structure under test in a sealed region, which can increase... The effective area of the stack-up structure under test is set to a large value. The effective area is positively correlated with the number of stack-up structures under test, which greatly increases the number of stack-up structures under test. During the subsequent testing of the stack-up structure under test, the total contact resistance between the interconnect vias and the first and second metal layers in the interconnect stack-up under test is obtained to determine whether the interconnect vias are in complete contact with the first and second metal layers. Since the number of stack-up structures under test is greatly increased, the health of a large number of interconnect vias at the wafer level can be monitored, the number of interconnect vias tested is increased, and thus the reliability of the test structure is improved. Attached Figure Description
[0024] Figures 1 to 4 This is a schematic diagram of an embodiment of the test structure of the present invention;
[0025] Figure 5 This is a flowchart of the steps of an embodiment of the testing method of the present invention. Detailed Implementation
[0026] As the background technology shows, the number of interconnect vias is determined by their area; the larger the area, the higher the level of via open defects it can characterize. However, due to limitations in the area of the test structure, the area of the test structure placed in the product is often small, making it difficult to capture via open defects (incomplete contact between the interconnect and the upper and lower metal layers) of one in a million, one in ten million, or even one in a hundred million. Therefore, the performance of the test structure in characterizing the level of via open defects still needs to be improved.
[0027] To address the technical problem, embodiments of the present invention provide a test structure, comprising: a substrate, the substrate including a chip region and a sealing region surrounding the chip region; a dielectric layer located above the substrate; and one or more stacked structures under test located in the dielectric layer above the sealing region of the substrate and exposing the chip region. The stacked structures under test include one or more interconnect stacks stacked vertically, the interconnect stacks under test including a first metal layer and a second metal layer located above the first metal layer, and interconnect vias located between the first metal layer and the second metal layer, wherein both the first metal layer and the second metal layer are electrically connected to the interconnect vias.
[0028] In the test structure provided by this embodiment of the invention, one or more stacked structures under test are located in a dielectric layer above the substrate of the sealed region and expose the chip region. The stacked structure under test includes one or more interconnect stacks stacked vertically. The interconnect stack includes a first metal layer, a second metal layer located above the first metal layer, and interconnect vias located between the first and second metal layers. Both the first and second metal layers are electrically connected to the interconnect vias. Compared to the scheme of setting the stacked structure under test in the dicing area, this embodiment of the invention sets the stacked structure under test in the sealed region. This method can increase the effective area of the stack-up structure under test. The effective area is positively correlated with the number of stack-up structures under test, which greatly increases the number of stack-up structures under test. During the subsequent testing of the stack-up structure under test, the total contact resistance between the interconnect vias and the first and second metal layers in the interconnect stack-up under test is obtained to determine whether the interconnect vias are in complete contact with the first and second metal layers. Since the number of stack-up structures under test is greatly increased, the health of interconnect vias at the wafer level can be monitored, improving testing efficiency and thus improving the performance of the test structure.
[0029] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0030] Figures 1 to 4 This is a schematic diagram of one embodiment of the test structure of the present invention. Figure 2 yes Figure 1 Enlarged view of the symbol A in the middle; Figure 3 yes Figure 2 An enlarged view of the symbol B in the middle; Figure 4 yes Figure 3 A cross-sectional view along the AA direction.
[0031] The test structure includes: a substrate (not shown), the substrate including a chip region 100A and a sealing region 100B surrounding the chip region 100A; a dielectric layer (not shown), located above the substrate; one or more stacked structures under test 120, located in the dielectric layer above the substrate of the sealing region 100B and exposing the chip region 100A, the stacked structure under test 120 including one or more interconnect stacks under test 130 stacked vertically, the interconnect stack 130 under test including a first metal layer 123 and a second metal layer 127 located above the first metal layer 123, and an interconnect via 124 located between the first metal layer 123 and the second metal layer 127, and both the first metal layer 123 and the second metal layer 127 are electrically connected to the interconnect via 124.
[0032] Specifically, compared to the scheme of setting the stack-up structure under test 120 in the dicing area 100C, this embodiment of the invention sets the stack-up structure under test 120 in the sealing area 100B, which can increase the effective area of the stack-up structure under test 120. The effective area is positively correlated with the number of stack-up structures under test 120, which can greatly increase the number of stack-up structures under test 120. In the subsequent testing of the stack-up structure under test 120, the total contact resistance between the interconnect via 124 and the first metal layer 123 and the second metal layer 127 in the interconnect stack-up 130 under test is obtained to determine whether the interconnect via 124 is in complete contact with the first metal layer 123 and the second metal layer 127. Since the number of stack-up structures under test 120 is greatly increased, the health of a wafer-level number of interconnect vias 124 is monitored, the number of interconnect vias tested is increased, and the reliability of the test structure is improved.
[0033] The substrate provides a process platform for setting up the test structure.
[0034] As an example, the substrate is a wafer-level substrate, that is, the test structure is a wafer-level test structure.
[0035] Specifically, it should be noted that the chip region 100A of the substrate can be equipped with various semiconductor components, such as various suitable transistors, memory, passive devices or field-effect transistors, etc.
[0036] It should be noted that the sealing region 100B provides space for setting the stack-up structure 120 under test. At the same time, the sealing region 100B surrounds the chip region 100A and protects the various semiconductor components in the chip region 100A. During the process of cutting the substrate along the dicing area 100C, it can reduce the probability of electrical failure of the semiconductor components in the chip region 100A caused by the stress generated by the cutting.
[0037] In this embodiment, the substrate also includes a cutting channel area 100C surrounding the sealing area 100B, and the area occupied by the cutting channel area 100C is smaller than the area occupied by the sealing area 100B.
[0038] It should be noted that the 100C dicing channel provides a dicing channel for dicing wafer-level substrates.
[0039] It should also be noted that the area occupied by the dicing region 100C is smaller than that occupied by the sealing region 100B, which increases the area occupied by the chip region 100A. This allows for the placement of more semiconductor components within the same substrate area. Simultaneously, the smaller area occupied by the dicing region 100C also increases the effective area of the test stack structure 120 within the sealing region 100B. The effective area is positively correlated with the number of test stack structures 120, significantly increasing the number of test stack structures 120. This enables the monitoring of the health of a wafer-level number of interconnect vias 124, increasing the number of test interconnect vias and thus improving the reliability of the test structure.
[0040] Specifically, the dielectric layer provides electrical isolation for the first metal layer 123, the second metal layer 127, and the interconnect via 124 in the stacked structure under test 120.
[0041] In this embodiment, the dielectric layer material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) and ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6).
[0042] It should be noted that, compared to the scheme of setting the stack-up structure under test 120 in the dicing area 100C, this embodiment sets the stack-up structure under test 120 in the sealing area 100B, which can increase the effective area of the stack-up structure under test 120. The effective area is positively correlated with the number of stack-up structures under test 120, which can greatly increase the number of stack-up structures under test 120. In the subsequent testing of the stack-up structure under test 120, the total contact resistance between the interconnect vias 124 and the first metal layer 123 and the second metal layer 127 in the interconnect stack-up 130 under test is obtained to determine whether the interconnect vias 124 and the first metal layer 123 and the second metal layer 127 are in complete contact. Since the number of stack-up structures under test 120 is greatly increased, the health of a wafer-level number of interconnect vias 124 is monitored, the testing efficiency is improved, and the performance of the test structure is improved.
[0043] It should also be noted that by setting the stacked structure under test 120 in the sealed area 100B, the remaining effective area of the wafer-level substrate is effectively utilized without increasing the area occupied by the test structure.
[0044] As an example, one or more of the stacked structures under test 120 expose the top surface of the cut channel region 100C.
[0045] Specifically, one or more of the stacked structures under test 120 expose the top surface of the dicing zone 100C, which is beneficial to retain the stacked structures under test 120 in each chip formed after the wafer-level substrate is diced, so that the stacked structures under test 120 in each chip can be tested separately according to actual needs.
[0046] It should be noted that when there are multiple stacked structures 120 to be tested, the stacked structures 120 to be tested extend along the first direction and are arranged in parallel at intervals along the second direction, and the first direction and the second direction are perpendicular to each other.
[0047] The number of stacked structures 120 to be tested is multiple, which can further greatly increase the number of stacked structures 120 to be tested, thereby realizing the monitoring of the health of interconnect vias 124 at the wafer level.
[0048] As an example, Figure 3 Multiple stacked structures 120 to be tested are shown in the figure.
[0049] It should be noted that the adjacent stacked structures under test 120 are spaced apart in the second direction, which reduces the probability of the adjacent stacked structures under test 120 short-circuiting. In the subsequent test method, the total contact resistance between the interconnecting via 124 and the first metal layer 123 and the second metal layer 127 in each stacked structure under test 120 can be obtained individually.
[0050] Specifically, the distance between adjacent test stack structures 120 in the second direction should not be too large or too small. If the distance between adjacent test stack structures 120 in the second direction is too small, the probability of short circuit between adjacent test stack structures 120 increases, leading to test structure failure. If the distance between adjacent test stack structures 120 in the second direction is too large, the effective area of the sealing region 100B is wasted, reducing the number of test stack structures 120 in the sealing region 100B, thus degrading the performance of the test structure. Therefore, in this embodiment, the distance between adjacent test stack structures 120 in the second direction is 40 nanometers to 800 nanometers.
[0051] In this embodiment, in the extending direction of the interconnect stack 130 under test, the interconnect stack 130 under test includes a first end and a second end opposite thereto.
[0052] It should be noted that the first end and the second end are used as the two ends of the interconnect stack 130 under test, and are used to make electrical connections with the test signal loading end, so that the current and voltage at both ends of the interconnect stack 130 under test can be obtained through the test signal loading end, and then the total contact resistance between the interconnect via 124 and the first metal layer 123 and the second metal layer 127 in the interconnect stack 130 under test can be obtained.
[0053] Specifically, the first metal layer 123 and the second metal layer 127 are electrically connected through interconnecting vias 124.
[0054] In this embodiment, the first metal layer 123 includes a plurality of first sub-metal layers 121 that extend along a first direction and are arranged in parallel at intervals along the first direction.
[0055] Specifically, by setting the first metal layer 123 as multiple first sub-metal layers 121, the multiple first sub-metal layers 121 can form a series connection with the second metal layer 127 through interconnect vias 124. This means that each interconnect stack 130 under test is provided with a large number of interconnect vias 124. Since multiple stack structures 120 under test are provided above the substrate of the sealing region 100B, the number of interconnect vias 124 provided in the sealing region 100B can be greatly increased, so that the sealing region 100B of the substrate is provided with a wafer-level number of interconnect vias 124, which is beneficial for subsequent monitoring of the health of the wafer-level number of interconnect vias 124.
[0056] In this embodiment, the second metal layer 127 includes a plurality of second sub-metal layers 125 extending along a first direction and arranged in parallel at intervals along the first direction. The second sub-metal layers 125 and the first sub-metal layer 121 are staggered in the longitudinal direction, and the first sub-metal layer 121 and the second sub-metal layer 125 are sequentially connected in series through the interconnecting vias 124.
[0057] It should be noted that the second sub-metal layer 125 and the first sub-metal layer 121 are staggered in the longitudinal direction, so that the second sub-metal layer 125 can be connected in series with the beginning and end of the adjacent first sub-metal layer 121 through the interconnecting via 124.
[0058] In this embodiment, the dimension of the first sub-metal layer 121 extending in the first direction is equal to the dimension of the second sub-metal layer 125 extending in the first direction.
[0059] It should be noted that the dimension of the first sub-metal layer 121 extending in the first direction is equal to the dimension of the second sub-metal layer 125 extending in the first direction. With a fixed substrate size, the number of the first sub-metal layer 121 and the second sub-metal layer 125 can be maximized. Since the first sub-metal layer 121 and the second sub-metal layer 125 are connected in series through interconnecting vias 124, it means that the number of interconnecting vias 124 can be maximized, thereby maximizing the number of interconnecting vias 124 within the effective area of the sealing region 100B, and thus improving the performance of the test structure.
[0060] As an example, the dimension of the distance between adjacent first sub-metal layers 121 in the first direction is equal to the dimension of the distance between adjacent second sub-metal layers 125 in the first direction.
[0061] Specifically, the spacing between adjacent first sub-metal layers 121 in the first direction is equal to the spacing between adjacent second sub-metal layers 125 in the first direction, which enables the second sub-metal layers 125 and the first sub-metal layers 121 to be uniformly staggered in the longitudinal direction. With a fixed substrate size, the number of first sub-metal layers 121 and second sub-metal layers 125 can be maximized.
[0062] It should be noted that the spacing between adjacent first sub-metal layers 121 in the first direction should not be too large or too small. If the spacing between adjacent first sub-metal layers 121 in the first direction is too large, the effective area of the sealing region 100B is wasted, reducing the number of first sub-metal layers 121 and second sub-metal layers 125 disposed in the sealing region 100B, thereby reducing the number of interconnect vias 124 and causing a decrease in the performance of the test structure. If the spacing between adjacent first sub-metal layers 121 in the first direction is too small, the process window for forming the first sub-metal layers 121 and second sub-metal layers 125 becomes too small, increasing the difficulty of forming the first sub-metal layers 121 and second sub-metal layers 125, increasing the probability of short circuits between adjacent first sub-metal layers 121 and adjacent second sub-metal layers 125, thus affecting the accuracy of the test results in the subsequent test method. Therefore, in this embodiment, the spacing between adjacent first sub-metal layers 121 in the first direction is in the range of 10 nanometers to 200 nanometers.
[0063] In this embodiment, the test structure further includes: a first test signal loading terminal 140, located in the dielectric layer above the substrate of the sealing region 100B, and the first test signal loading terminal 140 is electrically connected to the first end.
[0064] It should be noted that the first test signal loading terminal 140 is used as a signal loading terminal to obtain the voltage and current of the interconnect stack 130 under test in the test method.
[0065] As an example, the first test signal loading terminal 140 is located in the dielectric layer above the substrate on the side of the interconnect stack 130 under test, and the first test signal loading terminal 140 and the interconnect stack 130 under test are in the same layer.
[0066] In this embodiment, the material of the first test signal loading terminal 140 includes one or both of copper and aluminum.
[0067] Specifically, copper and aluminum have low resistivity, which can reduce the contact resistance between the first test signal loading terminal 140 and the interconnect stack 130 under test, thereby reducing the impact on the accuracy of the test results.
[0068] In this embodiment, the test structure further includes a second test signal loading terminal 141, located in the dielectric layer above the substrate of the sealing region 100B, and the second test signal loading terminal 141 is electrically connected to the second end.
[0069] It should be noted that the second test signal loading terminal 141 is used as a signal loading terminal to obtain the voltage and current of the interconnect stack 130 under test in the test method.
[0070] As an example, the second test signal loading terminal 141 is located in the dielectric layer above the substrate on the side of the interconnect stack 130 under test, and the second test signal loading terminal 141 and the interconnect stack 130 under test are in the same layer.
[0071] In this embodiment, the material of the second test signal loading terminal 141 includes one or both of copper and aluminum.
[0072] Specifically, copper and aluminum have low resistivity, which can reduce the contact resistance between the second test signal loading terminal 141 and the interconnect stack 130 under test, thereby reducing the impact on the accuracy of the test results.
[0073] In this embodiment, the test structure further includes: a plurality of sealing rings 110 located in a dielectric layer above the substrate of the sealing region 100B, and the stacked structure under test 120 located in a dielectric layer between adjacent sealing rings 110.
[0074] It should be noted that during the process of cutting the substrate along the cutting channel area 100C, the cutting cracks generated in the cutting channel area 100C will advance towards the chip area 100A of the substrate. In order to reduce the probability of damage to the chip area 100A of the substrate, a sealing ring 110 is provided in the sealing area 100B. The sealing ring 110 can prevent the cutting cracks from advancing towards the chip area 100A of the substrate, so that the sealing ring 110 can protect the chip area 100A of the substrate.
[0075] It should also be noted that the stacked structure under test 120 is located in the dielectric layer between adjacent sealing rings 110, so that the stacked structure under test 120 can effectively utilize the remaining area of the sealing area 100B, thereby the test structure does not increase the area occupied by the substrate, which is beneficial to further control the substrate size.
[0076] In this embodiment, the sealing ring 110 is made of one or both of aluminum and tantalum nitride.
[0077] Specifically, the high density of aluminum and tantalum nitride materials is beneficial to improving the protective performance of the sealing ring 110 on the chip area 100A. At the same time, the process of forming the sealing ring 110 using aluminum and tantalum nitride materials is mature and the process stability of forming the sealing ring 110 is high.
[0078] Accordingly, embodiments of the present invention also provide a testing method. Wherein, Figure 5 This is a flowchart of the steps corresponding to one embodiment of the testing method of the present invention. The following is in conjunction with the appendix. Figures 1 to 4 The testing methods of this implementation will be described in detail.
[0079] Reference Figures 1 to 4 Step S1: Provide the test structure provided by the present invention.
[0080] It should be noted that for a detailed description of the test structure, please refer to the corresponding description in the foregoing embodiments, which will not be repeated here.
[0081] In this embodiment, during the step of providing the test structure, in the extension direction of the interconnect stack 130 under test, the interconnect stack 130 under test includes a first end and a second end opposite thereto.
[0082] It should be noted that the first end and the second end are used as the two ends of the interconnect stack 130 under test, and are used to make electrical connections with the test signal loading end, so that the current and voltage at both ends of the interconnect stack 130 under test can be obtained through the test signal loading end, and then the total contact resistance between the interconnect via 124 and the first metal layer 123 and the second metal layer 127 in the interconnect stack 130 under test can be obtained.
[0083] In this embodiment, the test structure further includes: a first test signal loading terminal 140, located in the dielectric layer above the substrate of the sealing region 100B, and the first test signal loading terminal 140 is electrically connected to the first end.
[0084] It should be noted that the first test signal loading terminal 140 is used as a signal loading terminal to obtain the voltage and current of the interconnect stack 130 under test in the test method.
[0085] As an example, the first test signal loading terminal 140 is located in the dielectric layer above the substrate on the side of the interconnect stack 130 under test, and the first test signal loading terminal 140 and the interconnect stack 130 under test are in the same layer.
[0086] In this embodiment, the material of the first test signal loading terminal 140 includes one or both of copper and aluminum.
[0087] Specifically, copper and aluminum have low resistivity, which can reduce the contact resistance between the first test signal loading terminal 140 and the interconnect stack 130 under test, thereby reducing the impact on the accuracy of the test results.
[0088] In this embodiment, the test structure further includes: a second test signal loading terminal 141, located in the dielectric layer above the substrate of the sealing region 100B, and the second test signal loading terminal 141 is electrically connected to the second end.
[0089] It should be noted that the second test signal loading terminal 141 is used as a signal loading terminal to obtain the voltage and current of the interconnect stack 130 under test in the test method.
[0090] As an example, the second test signal loading terminal 141 is located in the dielectric layer above the substrate on the side of the interconnect stack 130 under test, and the second test signal loading terminal 141 and the interconnect stack 130 under test are in the same layer.
[0091] In this embodiment, the material of the second test signal loading terminal 141 includes one or both of copper and aluminum.
[0092] Specifically, copper and aluminum have low resistivity, which can reduce the contact resistance between the second test signal loading terminal 141 and the interconnect stack 130 under test, thereby reducing the impact on the accuracy of the test results.
[0093] Reference Figures 1 to 4 Step S2: Obtain the total contact resistance between the interconnect via 124 and the first metal layer 123 and the second metal layer 127 in the interconnect stack 130 to be tested.
[0094] It should be noted that by obtaining the total contact resistance between the interconnect via 124 and the first metal layer 123 and the second metal layer 127 in the interconnect stack 130 under test, it is beneficial to determine whether the interconnect via 124 and the first metal layer 123 and the second metal layer 127 are in complete contact based on the total contact resistance.
[0095] In this embodiment, the step of obtaining the total contact resistance includes: applying a constant current to the interconnect stack 130 under test through the first test signal loading terminal 140 and the second test signal loading terminal 141; after applying the constant current, obtaining the voltage between the first test signal loading terminal 140 and the second test signal loading terminal 141; and based on the voltage and the constant current, obtaining the total contact resistance between the interconnect via 124 and the first metal layer 123 and the second metal layer 127 in the interconnect stack 130 under test.
[0096] Specifically, the total contact resistance between the interconnect via 124 and the first metal layer 123 and the second metal layer 127 in the interconnect stack 130 under test is obtained as the ratio of voltage to constant current.
[0097] Reference Figures 1 to 4 Step S3: Based on the obtained total contact resistance, determine whether the interconnect via 124 is in complete contact with the first metal layer 123 and the second metal layer 127.
[0098] Specifically, the health status of the interconnect via 124 can be determined by judging whether the interconnect via 124 is in complete contact with the first metal layer 123 and the second metal layer 127.
[0099] In this embodiment, the step of determining the reliability of the interconnect via 124 based on the acquired total contact resistance includes: comparing the acquired total contact resistance with a preset contact resistance, wherein the preset contact resistance is used to characterize the ideal contact resistance when the interconnect via 124 is in complete contact with the first metal layer 123 and the second metal layer 127; when the total contact resistance is consistent with the preset contact resistance, the interconnect via 124 is in complete contact with the first metal layer 123 and the second metal layer 127; when the total contact resistance is inconsistent with the preset contact resistance, the interconnect via 124 is not in complete contact with the first metal layer 123 and the second metal layer 127.
[0100] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A test structure, characterized in that, include: A substrate, the substrate including a chip region and a sealing region surrounding the chip region; A dielectric layer is located above the substrate; One or more stacked structures under test are located in a dielectric layer above the substrate of the sealed region and expose the chip region. The stacked structure under test includes one or more interconnect stacks under test stacked vertically. The interconnect stack under test includes a first metal layer and a second metal layer located above the first metal layer, and an interconnect via located between the first metal layer and the second metal layer. Both the first metal layer and the second metal layer are electrically connected to the interconnect via.
2. The test structure as described in claim 1, characterized in that, The first metal layer includes a plurality of first sub-metal layers that extend along a first direction and are spaced apart and arranged in parallel along the first direction; The second metal layer includes a plurality of second sub-metal layers extending along a first direction and arranged in parallel at intervals along the first direction. The second sub-metal layers and the first sub-metal layers are staggered in the longitudinal direction, and the first sub-metal layers and the second sub-metal layers are sequentially connected in series through the interconnecting vias.
3. The test structure as described in claim 2, characterized in that, The dimension of the first sub-metal layer extending in the first direction is equal to the dimension of the second sub-metal layer extending in the first direction.
4. The test structure as described in claim 2, characterized in that, The dimension of the distance between adjacent first sub-metal layers in the first direction is equal to the dimension of the distance between adjacent second sub-metal layers in the first direction.
5. The test structure as described in claim 2, characterized in that, The size of the spacing between adjacent first sub-metal layers in the first direction ranges from 10 nanometers to 200 nanometers.
6. The test structure as described in claim 1, characterized in that, When there are multiple stacked structures to be tested, the stacked structures to be tested extend along a first direction and are arranged in parallel at intervals along a second direction, and the first direction and the second direction are perpendicular to each other.
7. The test structure as described in claim 6, characterized in that, The distance between adjacent test stacks in the second direction is 40 nanometers to 800 nanometers.
8. The test structure as described in claim 1, characterized in that, In the extension direction of the interconnect stack under test, the interconnect stack under test includes a first end and a second end opposite thereto; The test structure further includes: a first test signal loading terminal, located in the dielectric layer above the substrate of the sealed area, wherein the first test signal loading terminal is electrically connected to the first end; The second test signal loading terminal is located in the dielectric layer above the substrate of the sealed area, and the second test signal loading terminal is electrically connected to the second end.
9. The test structure as described in claim 8, characterized in that, The material of the first test signal loading end includes one or both of copper and aluminum; The material of the second test signal loading end includes one or both of copper and aluminum.
10. The test structure as described in claim 1, characterized in that, The test structure further includes: multiple sealing rings located in a dielectric layer above the substrate of the sealing area, and the stacked structure under test is located in a dielectric layer between adjacent sealing rings.
11. The test structure as described in claim 10, characterized in that, The sealing ring is made of one or both of aluminum and tantalum nitride.
12. The test structure as described in claim 1, characterized in that, The substrate also includes a cutting channel area surrounding the sealing area, and the area occupied by the cutting channel area is smaller than the area occupied by the sealing area; One or more of the stacked structures under test expose the top surface of the cut channel area.
13. A testing method, characterized in that, include: Provide a test structure as described in any one of claims 1 to 12; Obtain the total contact resistance between the interconnect vias and the first and second metal layers in the interconnect stack under test; Based on the obtained total contact resistance, it is determined whether the interconnect via is in complete contact with the first metal layer and the second metal layer.
14. The test structure as described in claim 13, characterized in that, In the step of providing the test structure, in the extension direction of the interconnect stack under test, the interconnect stack under test includes a first end and a second end opposite thereto; The test structure further includes: a first test signal loading terminal, located in the dielectric layer above the substrate of the sealed area, wherein the first test signal loading terminal is electrically connected to the first end; The second test signal loading terminal is located in the dielectric layer above the substrate of the sealing area, and the second test signal loading terminal is electrically connected to the second end. The steps for obtaining the total contact resistance include: applying a constant current to the interconnect stack under test through the first test signal loading terminal and the second test signal loading terminal; after applying the constant current, obtaining the voltage between the first test signal loading terminal and the second test signal loading terminal; and based on the voltage and the constant current, obtaining the total contact resistance between the interconnect vias and the first metal layer and the second metal layer in the interconnect stack under test.
15. The test structure as described in claim 13, characterized in that, The step of determining the reliability of the interconnect via based on the obtained total contact resistance includes: comparing the obtained total contact resistance with a preset contact resistance, wherein the preset contact resistance is used to characterize the ideal contact resistance when the interconnect via is in complete contact with the first metal layer and the second metal layer; When the total contact resistance is consistent with the preset contact resistance, the interconnect via is in complete contact with the first metal layer and the second metal layer; When the total contact resistance is inconsistent with the preset contact resistance, the interconnect via is not in complete contact with the first metal layer and the second metal layer.