Chip package structure and method of manufacturing the same

Abstract

The application provides a chip packaging structure and a preparation method thereof. The chip packaging structure comprises a substrate, a first redistribution layer arranged on one side of the substrate, a second redistribution layer arranged on a side of the substrate away from the first redistribution layer, and a third redistribution layer arranged on a side of the first redistribution layer away from the substrate and electrically connected with the first redistribution layer. The wiring density of the third redistribution layer is greater than the wiring density of the first redistribution layer and the second redistribution layer, and the wiring density of the first redistribution layer is greater than or equal to the wiring density of the second redistribution layer, so that an asymmetric laminated structure is realized on both sides of the substrate, and the demand for high computing power chips is met while the production cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a chip packaging structure and its fabrication method. Background Technology

[0002] In chip packaging structures, metal traces are typically mounted on the substrate. However, with the development of high-performance chips, chip integration is becoming increasingly higher and interconnect density is becoming increasingly dense. Traditional chip packaging structures can no longer meet the requirements in terms of fine circuitry and signal transmission rates. Summary of the Invention

[0003] The purpose of this invention is to provide a chip packaging structure and its fabrication method to solve the problem that the performance of chip packaging structures in related semiconductor technologies cannot meet practical needs.

[0004] To achieve the above objectives, the present invention provides a chip packaging structure, comprising a substrate, a first multiple wiring layer disposed on one side of the substrate, a second multiple wiring layer disposed on the side of the substrate opposite to the first multiple wiring layer, and a third multiple wiring layer disposed on the side of the first multiple wiring layer opposite to the substrate and electrically connected to the first multiple wiring layer. The wiring density of the third multiple wiring layer is greater than the wiring densities of the first and second multiple wiring layers, and the wiring density of the first multiple wiring layer is greater than or equal to the wiring density of the second multiple wiring layer.

[0005] Furthermore, the chip packaging structure further includes a receiving groove and a bridging structure. The receiving groove is disposed on the side of the substrate near the first redistribution layer and / or on the side of the third redistribution layer away from the substrate. The bridging structure is disposed in the receiving groove, and the first redistribution layer is electrically connected to the bridging structure. Preferably, the material of the bridging structure includes at least one of glass and silicon-based materials. Preferably, the chip packaging structure further includes a filler layer disposed in the receiving groove.

[0006] Furthermore, the substrate has multiple conductive vias, each containing a conductive post, and the first redistribution layer and the second redistribution layer are electrically connected through corresponding conductive posts. The substrate is made of an inorganic material. Preferably, the substrate is made of glass.

[0007] Furthermore, the chip packaging structure also includes a fourth wiring layer, which is disposed on the side of the second wiring layer away from the substrate, and the wiring density of the fourth wiring layer is less than that of the third wiring layer.

[0008] Furthermore, the chip packaging structure also includes multiple connecting posts and a chip. The connecting posts are disposed on the side of the third and fourth wiring layers facing away from the substrate. The chip is disposed on the side of the third wiring layer facing away from the substrate and is electrically connected to the third wiring layer through corresponding connecting posts.

[0009] The present invention also provides a method for fabricating a chip packaging structure, the method comprising: fabricating a first multiplexing layer on one side of a substrate, and fabricating a second multiplexing layer on the side of the substrate opposite to the first multiplexing layer, wherein the wiring density of the first multiplexing layer is greater than or equal to the wiring density of the second multiplexing layer; and fabricating a third multiplexing layer on the side of the first multiplexing layer opposite to the substrate, wherein the wiring density of the third multiplexing layer is greater than the wiring densities of the first multiplexing layer and the second multiplexing layer.

[0010] Furthermore, before the step of fabricating the first redistribution layer on one side of the substrate, the method further includes: forming a receiving groove on one side of the substrate; and forming a bridging structure in the receiving groove. Preferably, before the step of fabricating the first redistribution layer on one side of the substrate, the method further includes: forming a plurality of conductive holes in the substrate, with the receiving groove and the conductive holes formed simultaneously; and forming conductive pillars in the conductive holes.

[0011] Furthermore, after the step of preparing a third overlay layer on the side of the first overlay layer away from the substrate, the method further includes: forming a receiving groove on the side of the third overlay layer away from the substrate; and forming a bridging structure in the receiving groove.

[0012] Further, the step of forming a bridging structure in the receiving groove includes: preparing the bridging structure; and placing the bridging structure in the receiving groove. Preferably, after placing the bridging structure in the receiving groove, the step further includes: forming a filling layer in the receiving groove, the filling layer filling the gaps in the receiving groove. Preferably, the step of preparing the bridging structure includes: forming a via in the core layer; forming conductive structures on both sides of the core layer, and the conductive structures located on both sides of the core layer are electrically connected through the via.

[0013] Furthermore, after the step of preparing the second wiring layer on the side of the substrate opposite to the first wiring layer, the method further includes: preparing a fourth wiring layer on the side of the second wiring layer opposite to the substrate, wherein the wiring density of the fourth wiring layer is less than the wiring density of the third wiring layer.

[0014] The advantages of this invention are: The chip packaging structure and its fabrication method of this invention, by designing an asymmetrical stacked structure on both sides of the substrate, can individually increase the wiring density of the redistribution layer connected to the chip, thus adapting to high-performance chips. Meanwhile, the redistribution layer on the side connected to the circuit board can use a relatively lower wiring density, thereby reducing the fabrication difficulty and production cost of the chip packaging structure. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the layered structure of a chip packaging structure according to one embodiment of the present invention;

[0017] Figure 2 This is a schematic flowchart of a chip packaging structure fabrication method according to one embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of the layered structure of the chip packaging structure after step S11 in one embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the layered structure of the chip packaging structure after step S12 in one embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of the layered structure of the chip packaging structure after step S13 in one embodiment of the present invention;

[0021] Figures 6a-6d This is a schematic diagram of the layered structure of the chip packaging structure in step S14 of one embodiment of the present invention;

[0022] Figures 7a-7b This is a schematic diagram of the layered structure of the bridging structure during the fabrication process in one embodiment of the present invention;

[0023] Figures 8a-8c This is a schematic diagram of the layered structure of the chip packaging structure in step S15 of one embodiment of the present invention;

[0024] Figures 9a-9b This is a schematic diagram of the layered structure of the chip packaging structure in step S16 of an embodiment of the present invention;

[0025] Figure 10 This is a schematic diagram of the layered structure of a chip packaging structure according to one embodiment of the present invention;

[0026] Figure 11 This is a schematic diagram of the layered structure of the chip packaging structure in another embodiment of the present invention;

[0027] Figure 12 This is a schematic flowchart of a chip packaging structure fabrication method according to another embodiment of the present invention;

[0028] Figures 13a-13d This is a schematic diagram of the layered structure of the chip packaging structure after step S21 in another embodiment of the present invention;

[0029] Figure 14 This is a schematic diagram of the layered structure of the chip packaging structure after step S22 in another embodiment of the present invention;

[0030] Figure 15 This is a schematic diagram of the layered structure of the chip packaging structure after step S23 in another embodiment of the present invention;

[0031] Figures 16a-16d This is a schematic diagram of the layered structure of the chip packaging structure in step S24 of another embodiment of the present invention;

[0032] Figure 17 This is a schematic diagram of the layered structure of the chip packaging structure in another embodiment of the present invention;

[0033] The components in the diagram are shown below:

[0034] Chip packaging structure 100; substrate 110; first surface 111; second surface 112; conductive via 113; conductive post 114; first redistribution layer 121; second redistribution layer 122; third redistribution layer 123; fourth redistribution layer 124; wiring portion 101; dielectric portion 102; receiving groove 130; filling layer 131; lead pad 132; bonding adhesive film 133; bridging structure 140; conductive structure 141; core layer 142; via 143; connecting post 150; chip 160; support layer 170; protective layer 180; circuit board 200. Detailed Implementation

[0035] The following description, with reference to the accompanying drawings, illustrates preferred embodiments of the present invention, demonstrating its implementability. These embodiments provide a complete overview of the invention for those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0036] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. The dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component. To make the illustrations clearer, the thickness of components is appropriately exaggerated in some places in the drawings.

[0037] Furthermore, the following descriptions of the embodiments of the invention are made with reference to the accompanying illustrations, illustrating specific embodiments in which the invention can be implemented. Directional terms used in this invention, such as "upper," "lower," "front," "rear," "left," "right," "inner," "outer," and "side," are merely directional references to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of the invention, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0038] When a component is described as being "on" another component, the component may be placed directly on the other component; alternatively, there may be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "installed to" or "connected to" another component, both can be understood as being directly "installed" or "connected" to, or as being indirectly "installed to" or "connected to" another component via an intermediate component.

[0039] In related semiconductor chip technologies, due to the development of high-computing technologies such as AI (Artificial Intelligence) and HPC (High-Performance Computing), the production requirements for chip packaging structures are becoming increasingly stringent. However, the current chip packaging process is approaching its physical limits, and its performance, such as circuit integration and signal transmission rate, is increasingly unable to meet the needs of high-computing technology development.

[0040] In view of the problems raised in the aforementioned related semiconductor chip technologies, one embodiment of the present invention provides a chip packaging structure 100, such as... Figure 1As shown, the chip package structure 100 includes a substrate 110, a first wiring layer 121 disposed on one side of the substrate 110, a second wiring layer 122 disposed on the side of the substrate 110 opposite to the first wiring layer 121, a third wiring layer 123 disposed on the side of the first wiring layer 121 opposite to the substrate 110, and a chip 160 disposed on one side of the third wiring layer 123. The wiring density of the third wiring layer 123 is greater than that of the second wiring layer 122, meaning the wiring structure on both sides of the substrate 110 adopts an asymmetrical design. This allows for a higher wiring density on the side of the chip package structure 100 connected to the chip 160 to accommodate high-performance computing technologies, while the side of the chip package structure 100 connected to devices such as the circuit board 200 can be designed with a lower wiring density to reduce production costs.

[0041] The substrate 110 has a first surface 111 and a second surface 112 that are opposite to each other and parallel to each other. A first redistribution layer 121 is disposed on the first surface 111 of the substrate 110, and a second redistribution layer 122 is disposed on the second surface 112 of the substrate 110. Specifically, the substrate 110 has a plurality of conductive holes 113 that penetrate the substrate 110 and extend perpendicularly to the first surface 111 and the second surface 112. Each conductive hole 113 has a conductive post 114, and the two ends of the conductive post 114 in a direction perpendicular to the first surface 111 and the second surface 112 (i.e., perpendicular to the plane of the substrate 110) are electrically connected to the first redistribution layer 121 and the second redistribution layer 122, respectively, thereby enabling electrical connection between the first redistribution layer 121 and the second redistribution layer 122 located on both sides of the substrate 110.

[0042] A first wiring layer 121 is disposed on a first surface 111 of the substrate 110 and electrically connected to one end of the conductive post 114 near the first surface 111. A second wiring layer 122 is disposed on a second surface 112 of the substrate 110 and electrically connected to one end of the conductive post 114 near the second surface 112. A third wiring layer 123 is disposed on the surface of the first wiring layer 121 facing away from the substrate 110 and electrically connected to the first wiring layer 121. Each of the first, second, and third wiring layers 121 includes a trace portion 101 and a dielectric portion 102. The dielectric portion 102 surrounds the corresponding trace portion 101 to insulate and protect the corresponding trace portion 101. The trace portion 101 includes multiple conductive film layers, and each conductive film layer has multiple traces. The dielectric section 102 includes multiple dielectric film layers. In the trace section 101, at least one dielectric film layer is disposed between two adjacent conductive film layers. The dielectric film layer fills the gap between adjacent traces in the trace section 101, thereby preventing short circuits between adjacent traces in the trace section 101.

[0043] Specifically, at least a portion of the traces 101 in the first wiring layer 121 are electrically connected to the corresponding conductive post 114 by contacting the end face of the conductive post 114. Similarly, at least a portion of the traces 101 in the second wiring layer 122 are electrically connected to the corresponding conductive post 114 by contacting the end face of the conductive post 114 on the side away from the first wiring layer 121. This facilitates the connection between the first wiring layer 121 and the second wiring layer 122. Electrical connection is achieved between the two layers via conductive pillars 114. At least a portion of the traces 101 in the third wiring layer 123 are electrically connected to the corresponding traces 101 in the first wiring layer 121, thereby achieving electrical connection between the third wiring layer 123 and the first wiring layer 121. The chip 160 disposed on the side of the third wiring layer 123 away from the substrate 110 can transmit data and signals to the electronic components electrically connected to the second wiring layer 122 by being electrically connected to the third wiring layer 123.

[0044] In one embodiment of the present invention, the wiring density of the wiring portion 101 in the third wiring layer 123 is greater than the wiring density of the wiring portion 101 in the second wiring layer 122. That is, the wiring density in the third wiring layer 123 is greater than the wiring density in the second wiring layer 122. This causes the redistribution layer structure located on both sides of the substrate 110 to be an asymmetrical stacked structure. The chip package structure 100 with this asymmetrical structure can electrically connect the side with the higher wiring density to the chip 160 to meet the high computing power requirements of the chip 160, while the side with the lower wiring density of the chip package structure 100 can be electrically connected to electronic devices such as the circuit board 200 to reduce the manufacturing difficulty and production cost of the chip package structure 100.

[0045] The fact that the wiring density of the routing section 101 in the third routing layer 123 is greater than that of the routing section 101 in the second routing layer 122 can be reflected in aspects such as the number of traces in the routing section 101, the trace width, and the spacing between adjacent traces. For example, the difference between the third routing layer 123 and the second routing layer 122 can be achieved if at least one of the following conditions is met: the number of traces in the routing section 101 of the third routing layer 123 is greater than the number of traces in the routing section 101 of the second routing layer 122; the trace width in the routing section 101 of the third routing layer 123 is less than the trace width in the routing section 101 of the second routing layer 122; and the spacing between adjacent traces in the third routing layer 123 is less than the spacing between adjacent traces in the second routing layer 122.

[0046] Furthermore, the wiring density of the wiring portion 101 in the first wiring layer 121 is greater than or equal to the wiring density of the wiring portion 101 in the second wiring layer 122. Preferably, the wiring density of the wiring portion 101 in the first wiring layer 121 is equal to the wiring density of the wiring portion 101 in the second wiring layer 122, and the wiring density of the wiring portion 101 in the third wiring layer 123 is greater than the wiring density of the wiring portion 101 in the first wiring layer 121. This allows the first wiring layer 121 and the second wiring layer 122 to be fabricated simultaneously in the same process, thereby reducing the fabrication steps of the chip package structure 100 and improving production efficiency.

[0047] In some embodiments of the present invention, the substrate 110 is made of inorganic materials. Inorganic materials have better chemical stability than organic materials, enabling the substrate 110 to effectively resist environmental corrosion such as moisture and acids / alkalis. The inorganic substrate 110 also has better high-temperature resistance than the organic substrate 110, better adapting to the high-temperature environment in subsequent processes. Furthermore, the coefficient of thermal expansion of the inorganic substrate 110 is similar to that of the material in the chip 160, thereby reducing stress warping problems caused by thermal adaptation and facilitating the fabrication of multilayer wiring layers. In addition, the surface of the inorganic substrate 110 has superior flatness and lower roughness compared to the organic substrate 110, enabling denser wiring.

[0048] Among inorganic materials, glass has a much lower dielectric constant and dielectric loss compared to silicon-based materials (such as silicon nitride), which can improve signal transmission speed and signal integrity, making it more suitable for developing high-performance chips 160. Furthermore, the cost of glass is far lower than that of silicon-based materials. Therefore, glass is the preferred material for the substrate 110. Simultaneously, the glass substrate 110 can significantly improve its rigidity, allowing for asymmetrical fabrication on both sides of the substrate 110. This enables different redistribution layer structures (e.g., different number of layers, different wiring densities) on each side of the substrate 110, and also avoids problems such as warping.

[0049] In some embodiments of the present invention, the material of the wiring portion 101 includes a metallic material, and the material of the dielectric portion 102 includes an insulating material. Optionally, the material of the wiring portion 101 includes at least one of the metallic materials such as copper (Cu), aluminum (Al), gold (Au), and nickel (Ni), and the material of the dielectric portion 102 includes one of the insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), polyimide (PI), and ABF (Ajinomoto Build-up Film).

[0050] Furthermore, the chip package structure 100 also includes a fourth wiring layer 124, which is disposed on the side of the second wiring layer 122 away from the substrate 110 and is electrically connected to the second wiring layer 122. The fourth wiring layer 124 also includes a trace portion 101 and a dielectric portion 102. The trace portion 101 in the fourth wiring layer 124 is electrically connected to the trace portion 101 in the second wiring layer 122, and the wiring density of the trace portion 101 in the fourth wiring layer 124 is less than the wiring density of the trace portion 101 in the third wiring layer 123.

[0051] The chip package structure 100 also includes a bridging structure 140, which can further increase the wiring density on the side of the substrate 110 away from the second wiring layer 122, greatly reduce parasitic effects, ensure the integrity of transmitted signals, and thus improve the overall efficiency of the chip package structure 100. Specifically, at least one receiving groove 130 is provided on the side of the third wiring layer 123 away from the substrate 110, and the bridging structure 140 is disposed in the receiving groove 130 and electrically connected to the first wiring layer 121. The receiving groove 130 is formed by the dielectric portion 102 in the third wiring layer 123, that is, the sidewall of the receiving groove 130 is the surface of the third wiring layer 123 facing the receiving groove 130. To facilitate electrical connection between the bridging structure 140 in the receiving groove 130 and the first super-wiring layer 121, a portion of the surface of the first super-wiring layer 121 facing away from the substrate 110 is exposed in the receiving groove 130. The bridging structure 140 is mounted on the exposed surface of the first super-wiring layer 121 in the receiving groove 130, and the high-precision conductive structure 141 in the bridging structure 140 is electrically connected to the exposed trace portion 101 of the first super-wiring layer 121 in the receiving groove 130. At least two chips 160 can be electrically connected through the bridging structure 140, thereby integrating chips 160 with different process technologies and functions into the same chip package structure 100. This also increases the interconnection density of chips 160 in the chip package structure 100, avoiding the problem of huge costs caused by large-scale use of semiconductor chip 160 processes.

[0052] Optionally, the bridging structure 140 may be made of at least one of glass and silicon-based materials, meaning the bridging structure 140 can be either a glass bridge or a silicon bridge. Preferably, the bridging structure 140 employs a glass bridge structure, which offers higher flatness, enables higher density local interconnects, reduces transmission losses, provides high-frequency transmission services, and avoids thermal mismatch issues.

[0053] Optionally, in a direction perpendicular to the plane of the substrate 110, the depth of the receiving groove 130 is greater than or equal to the thickness of the third redistribution layer 123, so that a portion of the surface of the first redistribution layer 121 can be exposed in the receiving groove 130. Simultaneously, in a direction perpendicular to the plane of the substrate 110, the depth of the receiving groove 130 is also greater than or equal to the thickness of the bridging structure 140, thereby preventing the side of the bridging structure 140 facing away from the substrate 110 from protruding from the surface of the third redistribution layer 123 facing away from the substrate 110.

[0054] Furthermore, the chip package structure 100 also includes a filling layer 131, which is disposed in the receiving groove 130, covers the outer surface of the bridging structure 140 and fills the gap between the bridging structure 140 and the side wall and bottom surface of the receiving groove 130, thereby buffering and protecting the bridging structure 140 and fixing the position of the bridging structure 140 in the receiving groove 130, preventing the bridging structure 140 from being disconnected from the first rewiring layer 121 due to the influence of external impact.

[0055] In some embodiments of the present invention, the chip package structure 100 further includes a plurality of connecting posts 150. The third redistribution layer 123, the bridging structure 140 and the fourth redistribution layer 124 are each provided with a plurality of connecting posts 150 on the side away from the substrate 110. Electronic components such as the chip 160 and the circuit board 200 can be electrically connected to the corresponding redistribution layer by bonding with the corresponding connecting posts 150.

[0056] Furthermore, the chip package structure 100 also includes a support layer 170 and a protective layer 180. The support layer 170 is disposed between the chip 160 and the third wiring layer 123, and covers the sidewalls of the connecting pillars 150 to fill the gap between the chip 160 and the third wiring layer 123, thereby improving the structural strength of the chip package structure 100 and the connection stability between the chip 160 and the connecting pillars 150. The protective layer 180 is disposed around the chip 160 and fills the gap between adjacent chips 160, thereby protecting the chip 160 and improving the surface flatness of the chip package structure 100. Optionally, the protective layer 180 does not extend to cover the surface of the chip 160 facing away from the substrate 110, thereby improving the heat dissipation efficiency of the chip 160 and preventing thermal damage to the chip 160.

[0057] In this embodiment of the invention, a method for fabricating a chip package structure 100 is also provided to prepare the chip package structure 100 as described above. The fabrication process of the chip package structure 100 is as follows: Figure 2 As shown, it includes steps S11-S16.

[0058] Step S11) Fabrication of substrate 110:

[0059] Prepare a substrate 110, which can be made of inorganic material; preferably, the substrate 110 is made of glass.

[0060] Multiple conductive holes 113 are formed in the substrate 110 using the TGV (Through Glass Via) process. Optionally, at least one of the following hole-forming techniques can be used when forming the conductive holes 113: laser-induced wet etching, laser melting, focused discharge, plasma etching, and electrochemical discharge machining.

[0061] A seed layer is sputtered onto the hole wall of the conductive hole 113 using a physical vapor deposition (PVD) process, and then metal is filled into the conductive hole 113 using an electroplating process to form a layer such as... Figure 3 The conductive post 114 is located in the conductive hole 113 shown in the figure.

[0062] Step S12) A first redistribution layer 121 is formed on one side of the substrate 110, and a second redistribution layer 122 is formed on the side of the substrate 110 opposite to the first redistribution layer 121:

[0063] A seed layer is sputtered onto the first surface 111 and the second surface 112 of the substrate 110 using a physical vapor deposition process. A photolithography layer with a wiring pattern is formed on the seed layer using processes such as resist coating, photolithography, and development. Metal wiring is formed on the seed layer exposed in the photolithography pattern using an electroplating process. The photolithography layer and the seed layer covered by the photolithography layer are removed using resist removal and etching processes, thereby forming wiring portions 101 on both sides of the substrate 110. A multilayer dielectric film is prepared on the first surface 111 and the second surface 112 of the substrate 110 using processes such as coating and lamination, thereby forming dielectric portions 102 on both sides of the substrate 110.

[0064] In this step, such as Figure 4 As shown, the wiring portion 101 and the dielectric portion 102 located on the first surface 111 of the substrate 110 combine to form a first redistribution layer 121, and the wiring portion 101 and the dielectric portion 102 located on the second surface 112 of the substrate 110 combine to form a second redistribution layer 122. The first redistribution layer 121 and the second redistribution layer 122 can be fabricated simultaneously in the same process, ensuring that the wiring density of the first redistribution layer 121 is the same as that of the second redistribution layer 122. In some embodiments of the present invention, the number of metal wiring layers and the number of dielectric film layers fabricated in the first redistribution layer 121 and the second redistribution layer 122 can be selected according to different requirements.

[0065] Step S13) Fabricate a third redistribution layer 123 on the side of the first redistribution layer 121 facing away from the substrate 110:

[0066] A seed layer is sputtered onto the surface of the first redistribution layer 121 away from the substrate 110 using a physical vapor deposition process. A photolithography layer with a wiring pattern is formed on the seed layer using processes such as resist coating, photolithography, and development. Metal wiring is formed on the seed layer exposed in the photolithography pattern using an electroplating process. The photolithography layer and the seed layer covered by the photolithography layer are removed using resist removal and etching processes, thereby forming a wiring portion 101 on the side of the first redistribution layer 121 away from the substrate 110. A multilayer dielectric film is prepared on the surface of the first redistribution layer 121 away from the substrate 110 using processes such as coating and lamination, thereby forming a dielectric portion 102 on the side of the first redistribution layer 121 away from the substrate 110.

[0067] In this step, such as Figure 5 As shown, the trace portion 101 and dielectric portion 102 located on the side of the first wiring layer 121 opposite to the substrate 110 combine to form a third wiring layer 123. This third wiring layer 123 can be fabricated using a more precise and complex high-level process than the first and second wiring layers 121, resulting in a higher wiring density than the first and second wiring layers 121. Simultaneously, since the substrate 110 in this embodiment uses highly rigid glass, the support effect of the substrate 110 is greatly improved, enabling asymmetric stacking on both sides of the substrate 110 and avoiding warping problems in the final product. In some embodiments of the present invention, the number of metal trace layers and dielectric film layers fabricated in the third wiring layer 123 can be selected according to different needs.

[0068] Step S14) A receiving groove 130 is formed on the side of the third wiring layer 123 facing away from the substrate 110, and a bridging structure 140 is formed in the receiving groove 130:

[0069] On the side of the third wiring layer 123 facing away from the substrate 110, a patterning process is used to create a pattern such as... Figure 6a The receiving groove 130 shown has a depth in the direction perpendicular to the plane of the substrate 110 that is greater than or equal to the thickness of the third rewiring layer 123, thereby causing a portion of the surface of the first rewiring layer 121 to be exposed in the receiving groove 130.

[0070] On the bottom surface of the receiving tank 130 (i.e., the first redistribution layer 121 exposed on the surface of the receiving tank 130), a deposition process and a patterning process are used to form a pattern resembling... Figure 6b The pin pad 132 shown is electrically connected to the trace portion 101 in the first redistribution layer 121.

[0071] A bridging structure 140 is placed in a receiving groove 130, and the high-precision conductive structure 141 in the bridging structure 140 is connected to the lead pad 132 in the receiving groove 130 through a bonding process, so that the bridging structure 140 is electrically connected to the trace portion 101 in the first redistribution layer 121 through the lead pad 132, thereby forming a... Figure 6c The chip package structure 100 shown is optionally bonded to the bridging structure 140 and the lead pad 132 by means of a permanent bonding film 133 such as a die attach film (DAF).

[0072] In this step, the depth of the receiving groove 130 in the direction perpendicular to the plane of the substrate 110 is greater than or equal to the total thickness of the bridging structure 140, the lead pad 132, and the bonding film 133, thereby preventing the bridging structure 140 from protruding from the surface of the third wiring layer 123 on the side away from the substrate 110. Preferably, the depth of the receiving groove 130 in the direction perpendicular to the plane of the substrate 110 is greater than the total thickness of the bridging structure 140, the lead pad 132, and the bonding film 133, to facilitate the subsequent fabrication of the connecting posts.

[0073] Furthermore, after placing the bridging structure 140 in the receiving groove 130, the process also includes filling the receiving groove 130 with inorganic or organic materials through a potting process to form a structure such as Figure 6d The filler layer 131 shown fills the gap in the receiving groove 130 to protect the connection structure of the bridging structure 140 in the receiving groove 130. After the filler layer 131 is formed, the surface of the third wiring layer 123 facing away from the substrate 110 can be polished to make the surface of the filler layer 131 facing away from the substrate and the surface of the third wiring layer 123 facing away from the substrate 110 lie in the same plane, thereby improving the surface flatness of the third wiring layer 123.

[0074] In some embodiments of the present invention, the bridging structure 140 may be pre-prepared so that it can be directly used for implantation after the receiving groove 130 is opened. Specifically, the preparation steps of the bridging structure 140 include steps S101-S102.

[0075] Step S101) Forming vias 143 in the core layer 142:

[0076] Prepare a core layer 142, and form vias 143 in the core layer 142 to form a core layer 142 as shown in the figure. Figure 7a The structure shown is illustrated. Optionally, the core layer 142 may be made of at least one of glass or silicon-based materials. Preferably, the core layer 142 is made of glass.

[0077] Step S102) Forming conductive structures 141 on both sides of the core layer 142:

[0078] like Figure 7b As shown, conductive structures 141 are formed on both sides of the core layer 142 and in the via 143 through processes such as deposition and electroplating. The conductive structures 141 on both sides of the core layer 142 are electrically connected through the conductive structures 141 in the via 143 in step S101.

[0079] When the core layer 142 is made of glass, the vias 143 in the core layer 142 can be formed using the same fabrication process (i.e., TGV process) as the conductive holes 113 in the substrate 110, and the conductive structure 141 can also be formed using the same fabrication process as the conductive pillars 114 in the substrate 110.

[0080] Step S15) Deploy chip 160 on one side of the third wiring layer 123:

[0081] like Figure 8a As shown, a plurality of connecting posts 150 are prepared on the side of the third wiring layer 123 and the bridge away from the substrate 110. Some of the connecting posts 150 are electrically connected to the wiring portion 101 in the third wiring layer 123, and some of the connecting posts 150 are electrically connected to the conductive structure 141 in the bridge structure 140.

[0082] The chip 160 is bonded to the end of the connector 150 facing away from the substrate 110 using a bonding process, and adhesive is filled between the chip 160 and the third wiring layer 123 to form a structure as shown in the figure. Figure 8b The support layer 170 shown.

[0083] like Figure 8c As shown, a protective layer 180 is formed on the surface of the third wiring layer 123 away from the substrate 110 by a potting process. This protective layer covers the exposed surface of the chip 160 and fills the gaps between adjacent chips 160.

[0084] Step S16) A fourth redistribution layer 124 is fabricated on the side of the second redistribution layer 122 facing away from the substrate 110:

[0085] A seed layer is sputtered onto the surface of the second redistribution layer 122 away from the substrate 110 using a physical vapor deposition process. A photolithography layer with a wiring pattern is formed on the seed layer using processes such as resist coating, photolithography, and development. Metal wiring is formed on the seed layer exposed in the photolithography pattern using an electroplating process. The photolithography layer and the seed layer covered by the photolithography layer are removed using resist removal and etching processes, thereby forming a wiring portion 101 on the side of the second redistribution layer 122 away from the substrate 110. A multilayer dielectric film layer is prepared on the surface of the second redistribution layer 122 away from the substrate 110 using processes such as coating and lamination, thereby forming a dielectric portion 102 on the side of the second redistribution layer 122 away from the substrate 110.

[0086] In this step, such as Figure 9a As shown, the trace portion 101 and dielectric portion 102 located on the side of the second wiring layer 122 opposite to the substrate 110 combine to form a fourth wiring layer 124, and the wiring density of the fourth wiring layer 124 is less than the wiring density of the third wiring layer 123. In some embodiments of the present invention, the number of metal trace layers and the number of dielectric film layers prepared in the fourth wiring layer 124 can be selected according to different needs.

[0087] Furthermore, after fabricating the fourth redistribution layer 124, multiple such redistribution layers can be fabricated on the side of the fourth redistribution layer facing away from the substrate 110. Figure 9b The connecting post 150 shown is electrically connected to the wiring portion 101 in the fourth wiring layer 124, and the number of connecting posts 150 provided on the fourth wiring layer 124 side is less than the number of connecting posts 150 provided on the third wiring layer 123, or the size of the connecting posts 150 provided on the fourth wiring layer 124 side is larger than the size of the connecting posts 150 provided on the third wiring layer 123.

[0088] In some embodiments of the present invention, the protective layer 180 on the side of the chip 160 facing away from the substrate 110 can also be removed by a polishing process, thereby exposing the surface of the chip 160 facing away from the substrate 110 to form a surface as shown in the image. Figure 10 The chip packaging structure 100 shown prevents the protective layer 180 from affecting the heat dissipation of the chip 160.

[0089] In the chip packaging structure provided by the embodiments of the present invention, by using an inorganic substrate, an asymmetrical stacked structure is achieved on both sides of the substrate without causing warping problems. This allows for a separate increase in the wiring density of the redistribution layer connected to the chip, accommodating high-performance chips. Meanwhile, the redistribution layer on the side connected to the circuit board can employ a relatively lower wiring density, reducing the fabrication difficulty and production cost of the chip packaging structure.

[0090] Based on the problems raised in the aforementioned related semiconductor chip technologies, another embodiment of the present invention also provides a chip packaging structure 100, such as... Figure 11As shown, the chip package structure 100 includes a substrate 110, a first wiring layer 121 disposed on one side of the substrate 110, a second wiring layer 122 disposed on the side of the substrate 110 opposite to the first wiring layer 121, a third wiring layer 123 disposed on the side of the first wiring layer 121 opposite to the substrate 110, and a chip 160 disposed on one side of the third wiring layer 123. The wiring density of the third wiring layer 123 is greater than that of the second wiring layer 122, meaning the wiring structure on both sides of the substrate 110 adopts an asymmetrical design. This allows for a higher wiring density on the side of the chip package structure 100 connected to the chip 160 to accommodate high-performance computing technologies, while the side of the chip package structure 100 connected to devices such as the circuit board 200 can be designed with a lower wiring density to reduce production costs.

[0091] The substrate 110 has a first surface 111 and a second surface 112 that are opposite to each other and parallel to each other. A first redistribution layer 121 is disposed on the first surface 111 of the substrate 110, and a second redistribution layer 122 is disposed on the second surface 112 of the substrate 110. Specifically, the substrate 110 has a plurality of conductive holes 113 that penetrate the substrate 110 and extend perpendicularly to the first surface 111 and the second surface 112. Each conductive hole 113 has a conductive post 114, and the two ends of the conductive post 114 in a direction perpendicular to the first surface 111 and the second surface 112 (i.e., perpendicular to the plane of the substrate 110) are electrically connected to the first redistribution layer 121 and the second redistribution layer 122, respectively, thereby enabling electrical connection between the first redistribution layer 121 and the second redistribution layer 122 located on both sides of the substrate 110.

[0092] The chip package structure 100 also includes a bridging structure 140, which can further increase the routing density on the side of the substrate 110 away from the second redistribution layer 122, greatly reduce parasitic effects, ensure the integrity of transmitted signals, and thus improve the overall efficiency of the chip package structure 100. Specifically, at least one receiving groove 130 is formed on the first surface 111 of the substrate 110, and the bridging structure 140 is disposed in the receiving groove 130 and electrically connected to the conductive post 114 in the substrate 110. The orthographic projection of some conductive holes 113 in substrate 110 onto substrate 110 lies within the orthographic projection range of receiving groove 130 onto substrate 110, causing some conductive holes 113 in substrate 110 to communicate with receiving groove 130. This causes the end face of the conductive post 114 located in the corresponding conductive hole 113 to be exposed in receiving groove 130. Bridging structure 140 is directly mounted in receiving groove 130, and the high-precision conductive structure 141 in bridging structure 140 is directly bonded to the end face of the corresponding conductive post 114 exposed in receiving groove 130. At least two chips 160 can be indirectly electrically connected through bridging structure 140, thereby integrating chips 160 with different process technologies and functions into the same chip package structure 100. It can also increase the interconnection density of chips 160 in chip package structure 100, avoiding the problem of huge costs caused by large-scale use of semiconductor chip 160 processes.

[0093] Optionally, the bridging structure 140 may be made of at least one of glass and silicon-based materials, meaning the bridging structure 140 can be either a glass bridge or a silicon bridge. Preferably, the bridging structure 140 employs a glass bridge structure, which offers higher flatness, enables higher density local interconnects, reduces transmission losses, provides high-frequency transmission services, and avoids thermal mismatch issues.

[0094] Optionally, in a direction perpendicular to the plane of the substrate 110, the depth of the receiving groove 130 is less than the thickness of the substrate 110, and the depth of the receiving groove 130 is greater than or equal to the thickness of the bridging structure 140, thereby preventing the side of the bridging structure 140 away from the substrate 110 from protruding from the first surface 111 of the substrate 110, so as to facilitate the subsequent fabrication of the first redistribution layer 121.

[0095] Furthermore, the chip packaging structure 100 also includes a filling layer 131, which is disposed in the receiving groove 130 and fills the gap between the bridging structure 140 and the side wall and bottom surface of the receiving groove 130, thereby buffering and protecting the bridging structure 140 and fixing the position of the bridging structure 140 in the receiving groove 130, preventing the bridging structure 140 from breaking off from the corresponding conductive post 114 due to the influence of external impact.

[0096] A first wiring layer 121 is disposed on the first surface 111 of the substrate 110 and covers the bridging structure 140, enabling the first wiring layer 121 to be electrically connected to the conductive post 114 and the bridging structure 140. A second wiring layer 122 is disposed on the second surface 112 of the substrate 110 and is electrically connected to the end of the conductive post 114 near the second surface 112. A third wiring layer 123 is disposed on the surface of the first wiring layer 121 facing away from the substrate 110 and is electrically connected to the first wiring layer 121. A chip 160 disposed on the side of the third wiring layer 123 facing away from the substrate 110 can transmit data and signals to electronic components electrically connected to the second wiring layer 122 through electrical connection with the third wiring layer 123.

[0097] Specifically, the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 each include a trace portion 101 and a dielectric portion 102. The dielectric portion 102 surrounds the corresponding trace portion 101 to insulate and protect it. The trace portion 101 includes multiple conductive film layers, and each conductive film layer contains multiple traces. The dielectric portion 102 includes multiple dielectric film layers. At least one dielectric film layer is disposed between two adjacent conductive film layers in the trace portion 101. This dielectric film layer fills the gaps between adjacent traces in the trace portion 101, thereby preventing short circuits between adjacent traces in the trace portion 101. Part of the trace portion 101 in the first wiring layer 121 is electrically connected to the conductive pillars 114 in the substrate 110, while part of the trace portion 101 is electrically connected to the high-density conductive structure 141 in the bridging structure 140.

[0098] In some embodiments of the present invention, the wiring density of the wiring portion 101 in the third wiring layer 123 is greater than the wiring density of the wiring portion 101 in the second wiring layer 122. That is, the wiring density in the third wiring layer 123 is greater than the wiring density in the second wiring layer 122. This causes the redistribution layer structure located on both sides of the substrate 110 to be an asymmetrical stacked structure. The chip package structure 100 with this asymmetrical stacked structure can electrically connect the side with the higher wiring density to the chip 160 to meet the high computing power requirements of the chip 160, while the side with the lower wiring density of the chip package structure 100 can be electrically connected to electronic devices such as the circuit board 200 to reduce the manufacturing difficulty and production cost of the chip package structure 100.

[0099] Furthermore, the wiring density of the wiring portion 101 in the first wiring layer 121 is greater than or equal to the wiring density of the wiring portion 101 in the second wiring layer 122. Preferably, the wiring density of the wiring portion 101 in the first wiring layer 121 is equal to the wiring density of the wiring portion 101 in the second wiring layer 122, and the wiring density of the wiring portion 101 in the third wiring layer 123 is greater than the wiring density of the wiring portion 101 in the first wiring layer 121. This allows the first wiring layer 121 and the second wiring layer 122 to be fabricated simultaneously in the same process, thereby reducing the fabrication steps of the chip package structure 100 and improving production efficiency.

[0100] In some embodiments of the present invention, the substrate 110 is made of inorganic materials. Inorganic materials have better chemical stability than organic materials, enabling the substrate 110 to effectively resist environmental corrosion such as moisture and acids / alkalis. The inorganic substrate 110 also has better high-temperature resistance than the organic substrate 110, better adapting to the high-temperature environment in subsequent processes. Furthermore, the coefficient of thermal expansion of the inorganic substrate 110 is similar to that of the material in the chip 160, thereby reducing stress warping problems caused by thermal adaptation and facilitating the fabrication of multilayer wiring layers. In addition, the surface of the inorganic substrate 110 has superior flatness and lower roughness compared to the organic substrate 110, enabling denser wiring.

[0101] Among inorganic materials, glass has a much lower dielectric constant and dielectric loss compared to silicon-based materials (such as silicon nitride), which can improve signal transmission speed and signal integrity, making it more suitable for developing high-performance chips 160. Furthermore, the cost of glass is far lower than that of silicon-based materials. Therefore, glass is the preferred material for the substrate 110. Simultaneously, the glass substrate 110 can significantly improve its rigidity, allowing for asymmetrical fabrication on both sides of the substrate 110. This enables different structures (e.g., different number of layers, different wiring densities) for the redistribution layers located on opposite sides of the substrate 110, and also avoids problems such as warping.

[0102] In some embodiments of the present invention, the chip package structure 100 further includes a plurality of connecting posts 150. The second redistribution layer 122 and the third redistribution layer 123 are each provided with a plurality of connecting posts 150 on the side away from the substrate 110. Electronic components such as the chip 160 and the circuit board 200 can be electrically connected to the corresponding redistribution layer by bonding with the corresponding connecting posts 150.

[0103] Furthermore, the chip package structure 100 also includes a support layer 170 and a protective layer 180. The support layer 170 is disposed between the chip 160 and the third wiring layer 123, and covers the sidewalls of the connecting pillars 150 to fill the gap between the chip 160 and the third wiring layer 123, thereby improving the structural strength of the chip package structure 100 and the connection stability between the chip 160 and the connecting pillars 150. The protective layer 180 is disposed around the chip 160 and fills the gap between adjacent chips 160, thereby protecting the chip 160 and improving the surface flatness of the chip package structure 100. Optionally, the protective layer 180 does not extend to cover the surface of the chip 160 facing away from the substrate 110, thereby improving the heat dissipation efficiency of the chip 160 and preventing thermal damage to the chip 160.

[0104] In another embodiment of the present invention, a method for fabricating a chip package structure 100 is provided to prepare the chip package structure 100 as described above. The fabrication process of the chip package structure 100 is as follows: Figure 12 As shown, it includes steps S21-S24.

[0105] Step S21) Fabricate substrate 110, form receiving groove 130 on one side of substrate 110, and form bridging structure 140 in receiving groove 130:

[0106] A substrate 110 is prepared, which can be an inorganic material; preferably, the substrate 110 is made of glass. Multiple conductive vias 113 are formed in the substrate 110 using a TGV (Through Glass Via) process. Simultaneously, a receiving groove 130 is formed on the first surface 111 of the substrate 110. That is, the receiving groove 130 is formed simultaneously with the conductive vias 113, and some of the conductive vias 113 are connected to the receiving groove 130, to form a... Figure 13a The substrate 110 shown is shown.

[0107] A seed layer is sputtered onto the hole wall of the conductive hole 113 using a physical vapor deposition (PVD) process, and then metal is filled into the conductive hole 113 using an electroplating process to form a layer such as... Figure 13b The conductive post 114 is located in the conductive hole 113 shown in the figure.

[0108] A bridging structure 140 is pre-fabricated, and during the fabrication of the conductive post 114, the pre-fabricated bridging structure 140 is directly placed in the corresponding receiving groove 130. The high-precision conductive structure 141 in the bridging structure 140 is connected to the exposed end face of the conductive post 114 in the receiving groove 130 via a bonding process, enabling the bridging structure 140 to be electrically connected to the second redistribution layer 122 through the conductive post 114, thereby forming a... Figure 13cThe chip package structure 100 shown is optionally bonded to the bridging structure 140 and the lead pad 132 by means of a permanent bonding film 133 such as a die attach film (DAF).

[0109] In this step, in the direction perpendicular to the plane of the substrate 110, the depth of the receiving groove 130 is greater than or equal to the sum of the thicknesses of the bridging structure 140 and the bonding film 133, thereby preventing the bridging structure 140 from protruding from the first surface 111 of the substrate 110. Preferably, in the direction perpendicular to the plane of the substrate 110, the depth of the receiving groove 130 is equal to the sum of the thicknesses of the bridging structure 140 and the bonding film 133, thereby causing the surface of the bridging structure 140 away from the corresponding conductive post 114 to be in the same plane as the first surface 111 of the substrate 110, thereby improving the surface flatness of the substrate 110.

[0110] Furthermore, after placing the bridging structure 140 in the receiving groove 130, the process also includes filling the receiving groove 130 with inorganic or organic materials through a potting process to form a structure such as Figure 13d The filler layer 131 shown fills the gap in the receiving groove 130 to protect the connection structure of the bridging structure 140 in the receiving groove 130. After the filler layer 131 is formed, the first surface 111 of the substrate 110 can be polished to further improve the surface flatness of the substrate 110.

[0111] Step S22) A first redistribution layer 121 is formed on one side of the substrate 110, and a second redistribution layer 122 is formed on the side of the substrate 110 opposite to the first redistribution layer 121:

[0112] A seed layer is sputtered onto the first surface 111 and the second surface 112 of the substrate 110 using a physical vapor deposition process. A photolithography layer with a wiring pattern is formed on the seed layer using processes such as resist coating, photolithography, and development. Metal wiring is formed on the seed layer exposed in the photolithography pattern using an electroplating process. The photolithography layer and the seed layer covered by the photolithography layer are removed using resist removal and etching processes, thereby forming wiring portions 101 on both sides of the substrate 110. A multilayer dielectric film is prepared on the first surface 111 and the second surface 112 of the substrate 110 using processes such as coating and lamination, thereby forming dielectric portions 102 on both sides of the substrate 110.

[0113] In this step, such as Figure 14As shown, the wiring portion 101 and the dielectric portion 102 located on the first surface 111 of the substrate 110 combine to form a first redistribution layer 121, and the wiring portion 101 and the dielectric portion 102 located on the second surface 112 of the substrate 110 combine to form a second redistribution layer 122. The first redistribution layer 121 and the second redistribution layer 122 can be fabricated simultaneously in the same process, ensuring that the wiring density of the first redistribution layer 121 is the same as that of the second redistribution layer 122. In some embodiments of the present invention, the number of metal wiring layers and the number of dielectric film layers fabricated in the first redistribution layer 121 and the second redistribution layer 122 can be selected according to different requirements.

[0114] Step S23) Fabricate a third redistribution layer 123 on the side of the first redistribution layer 121 facing away from the substrate 110:

[0115] A seed layer is sputtered onto the surface of the first redistribution layer 121 away from the substrate 110 using a physical vapor deposition process. A photolithography layer with a wiring pattern is formed on the seed layer using processes such as resist coating, photolithography, and development. Metal wiring is formed on the seed layer exposed in the photolithography pattern using an electroplating process. The photolithography layer and the seed layer covered by the photolithography layer are removed using resist removal and etching processes, thereby forming a wiring portion 101 on the side of the first redistribution layer 121 away from the substrate 110. A multilayer dielectric film is prepared on the surface of the first redistribution layer 121 away from the substrate 110 using processes such as coating and lamination, thereby forming a dielectric portion 102 on the side of the first redistribution layer 121 away from the substrate 110.

[0116] In this step, such as Figure 15 As shown, the trace portion 101 and dielectric portion 102 located on the side of the first wiring layer 121 opposite to the substrate 110 combine to form a third wiring layer 123. This third wiring layer 123 can be fabricated using a more precise and complex high-level process than the first and second wiring layers 121, resulting in a higher wiring density than the first and second wiring layers 121. Simultaneously, since the substrate 110 in this embodiment uses highly rigid glass, the support effect of the substrate 110 is greatly improved, enabling asymmetric stacking on both sides of the substrate 110 and avoiding warping problems in the final product. In some embodiments of the present invention, the number of metal trace layers and dielectric film layers fabricated in the third wiring layer 123 can be selected according to different needs.

[0117] Step S24) Deploy chip 160 on one side of the third wiring layer 123:

[0118] like Figure 16aAs shown, a plurality of connecting posts 150 are prepared on the side of the third wiring layer 123 away from the substrate 110, and the connecting posts 150 are electrically connected to the wiring portion 101 in the third wiring layer 123.

[0119] The chip 160 is bonded to the end of the connector 150 facing away from the substrate 110 using a bonding process, and adhesive is filled between the chip 160 and the third wiring layer 123 to form a structure as shown in the figure. Figure 16b The support layer 170 shown.

[0120] like Figure 16c As shown, a protective layer 180 is formed on the surface of the third wiring layer 123 away from the substrate 110 by a potting process. This protective layer covers the exposed surface of the chip 160 and fills the gaps between adjacent chips 160.

[0121] After the chip 160 is installed, multiple [elemental components] can be fabricated on the side of the second redistribution layer 122 facing away from the substrate 110. Figure 16d The connecting post 150 shown is electrically connected to the wiring portion 101 in the second wiring layer 122, and the number of connecting posts 150 provided on the second wiring layer 122 side is less than the number of connecting posts 150 provided on the third wiring layer 123, or the size of the connecting posts 150 provided on the second wiring layer 122 side is larger than the size of the connecting posts 150 provided on the third wiring layer 123.

[0122] Furthermore, in other embodiments of the present invention, before the step of preparing the connecting post 150 on the side of the second redistribution layer 122 away from the substrate 110, other redistribution layers may be prepared on the surface of the second redistribution layer 122 away from the substrate 110 according to actual needs.

[0123] In some embodiments of the present invention, the protective layer 180 on the side of the chip 160 facing away from the substrate 110 can also be removed by a polishing process, thereby exposing the surface of the chip 160 facing away from the substrate 110 to form a surface as shown in the image. Figure 17 The chip packaging structure 100 shown prevents the protective layer 180 from affecting the heat dissipation of the chip 160.

[0124] In the chip packaging structure provided by the embodiments of the present invention, by using an inorganic substrate, an asymmetrical stacked structure is achieved on both sides of the substrate without warping issues. This allows for a separate increase in the wiring density of the redistribution layer connected to the chip, accommodating high-performance chips. The redistribution layer on the side connected to the circuit board can use a relatively lower wiring density, reducing the fabrication difficulty and production cost of the chip packaging structure. Furthermore, in the embodiments of the present invention, by fabricating the bridging structure in the substrate, the receiving groove accommodating the bridging structure can be fabricated simultaneously with the conductive vias in the substrate, thereby reducing the fabrication steps of the chip packaging structure and improving production efficiency.

[0125] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A chip packaging structure, characterized in that, include: substrate; A first wiring layer is disposed on one side of the substrate; A second wiring layer is disposed on the side of the substrate opposite to the first wiring layer; The third wiring layer is disposed on the side of the first wiring layer away from the substrate and is electrically connected to the first wiring layer. The wiring density of the third wiring layer is greater than that of the first wiring layer and the second wiring layer, and the wiring density of the first wiring layer is greater than or equal to that of the second wiring layer.

2. The chip packaging structure as described in claim 1, characterized in that, Also includes: A receiving groove is disposed on the side of the substrate near the first redistribution layer and / or on the side of the third redistribution layer away from the substrate; A bridging structure is disposed in the receiving slot, and the first rewiring layer is electrically connected to the bridging structure; Preferably, the material of the bridging structure includes at least one of glass and silicon-based materials; Preferably, the chip packaging structure further includes a filler layer disposed in the receiving groove.

3. The chip packaging structure as described in claim 1, characterized in that, The substrate has a plurality of conductive holes, and conductive pillars are disposed in the conductive holes. The first redistribution layer and the second redistribution layer are electrically connected through the corresponding conductive pillars. The substrate is made of inorganic materials; Preferably, the substrate is made of glass.

4. The chip packaging structure as described in claim 1, characterized in that, Also includes: A fourth wiring layer is disposed on the side of the second wiring layer away from the substrate, and the wiring density of the fourth wiring layer is less than that of the third wiring layer.

5. The chip packaging structure as described in claim 4, characterized in that, Also includes: Multiple connecting posts are disposed on the side of the third and fourth wiring layers away from the substrate. The chip is disposed on the side of the third wiring layer away from the substrate and is electrically connected to the third wiring layer through the corresponding connecting post.

6. A method for fabricating a chip packaging structure, characterized in that, include: A first redistribution layer is formed on one side of the substrate, and a second redistribution layer is formed on the side of the substrate opposite to the first redistribution layer, wherein the wiring density of the first redistribution layer is greater than or equal to the wiring density of the second redistribution layer. A third wiring layer is prepared on the side of the first wiring layer away from the substrate, and the wiring density of the third wiring layer is greater than the wiring density of the first wiring layer and the second wiring layer.

7. The method for fabricating the chip packaging structure as described in claim 6, characterized in that, The step of fabricating the first redistribution layer on one side of the substrate further includes: A receiving groove is formed on one side of the substrate; A bridging structure is formed in the receiving groove; Preferably, the step of fabricating the first redistribution layer on one side of the substrate further includes: Multiple conductive holes are formed in the substrate, and the receiving groove is formed simultaneously with the conductive holes; A conductive post is formed in the conductive hole.

8. The method for fabricating the chip packaging structure as described in claim 6, characterized in that, The step of fabricating a third redistribution layer on the side of the first redistribution layer facing away from the substrate further includes: A receiving groove is formed on the side of the third wiring layer opposite to the substrate; A bridging structure is formed in the receiving groove.

9. The method for fabricating the chip packaging structure as described in claim 7 or 8, characterized in that, The step of forming a bridging structure in the receiving groove includes: Prepare the bridging structure; The bridging structure is placed in the receiving groove; Preferably, the step of placing the bridging structure in the receiving groove further includes: A filling layer is formed in the receiving groove, and the filling layer fills the gap in the receiving groove; Preferably, the step of preparing the bridging structure includes: Forming vias in the core layer; Conductive structures are formed on both sides of the core layer, and the conductive structures on both sides of the core layer are electrically connected through the vias.

10. The method for fabricating the chip packaging structure as described in claim 6, characterized in that, The step of fabricating the second redistribution layer on the side of the substrate opposite to the first redistribution layer further includes: A fourth wiring layer is prepared on the side of the second wiring layer away from the substrate, and the wiring density of the fourth wiring layer is less than that of the third wiring layer.

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