Bandgap reference source curvature compensation system and control method

Abstract

This invention relates to a bandgap reference source curvature compensation system and control method, which discloses a temperature-adaptive scaling architecture: generating a voltage V complementary to the absolute temperature through a bandgap core circuit. CTAT and voltage V that is proportional to absolute temperature PTAT Two reference voltages; a dynamic scaling factor α(T) that varies linearly with temperature is constructed using a duty cycle resistor unit, such that α(T)·V PTAT This forms a secondary compensation term with no zero-point offset; the duty cycle is determined by the ramp voltage (from the reference voltage V). BG (Drive charging generation) and V PTAT A reference voltage is generated to ensure that the duty cycle D is proportional to the temperature T; and this is achieved through an independently adjustable resistor R. S and R R The primary and secondary temperature coefficients of the compensation term are adjusted separately, and the two have a chip-level linear correlation, supporting single-temperature point calibration. This solution achieves low-power, high-precision, and easily mass-producible curvature compensation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit design, and more specifically to a bandgap reference source curvature compensation system and control method. Background Technology

[0002] In high-precision analog and mixed-signal integrated circuits, the bandgap voltage reference (BGR) serves as a core voltage reference module, widely used in high-resolution analog-to-digital converters (ADCs), digital-to-analog converters (DACs), low-dropout regulators (LDOs), and sensor interface circuits. Current mainstream BGR architectures are generally based on Brokaw or Widlar structures, and their output voltage expression is: V BG =V CTAT +𝛼⋅V PTAT V BG =V CTAT +α⋅V PTAT V CTAT For voltages with a negative temperature coefficient, V PTAT Here, α is the positive temperature coefficient voltage, and α is a fixed proportionality coefficient. To suppress first-order temperature drift, the industry has maturely adopted techniques such as chopper modulation, dynamic component matching, and common-mode feedback to optimize operational amplifier offset and current mirror mismatch. Building upon this, further improving temperature drift performance (target below 5ppm / °C) requires the introduction of a higher-order curvature compensation mechanism. Existing technologies mainly form three typical schemes: one is segmented compensation, such as... Figure 1 As shown, local linear fitting is achieved by configuring trimming codes in multiple temperature ranges; secondly, compensation is achieved by utilizing the intrinsic nonlinearity of the device, such as... Figure 2 As shown, this includes bipolar junction transistor (BJT) based... Or Δ𝑉 𝐵𝐸 The construction of the ⋅ln𝑁 term, and the mobility temperature characteristics based on the MOSFET subthreshold or strong inversion region. Current generation; thirdly, on-chip self-heating closed-loop temperature control scheme, such as... Figure 3 As shown, the chip junction temperature is kept constant by integrating a heating resistor to eliminate the influence of ambient temperature.

[0003] However, the aforementioned existing technologies all suffer from fundamental limitations in balancing process compatibility, calibration efficiency, and zero-point accuracy: segmented compensation relies on a large number of trimming units, making it difficult to completely eliminate errors in each interval under the influence of process deviations and device mismatches, and the overall temperature drift remains significantly high without trimming; intrinsic nonlinearity compensation schemes are limited by the carrier mobility curvature characteristics of specific process nodes, resulting in a sharp deterioration in compensation effects in advanced CMOS processes at 28 nm and below, and the introduction of non-zero physical quantities such as the base-emitter junction zero-point voltage of BJTs or the threshold voltage of MOSFETs causes an inherent offset in the compensation term at absolute zero, which must be offset by additional trimming, making single-temperature calibration impossible; self-heating schemes can achieve ultra-low temperature drift, but continuous heating consumes a lot of power, making them unsuitable for battery-powered or low-power IoT chip scenarios. Therefore, there is an urgent need for a new curvature compensation mechanism that does not rely on intrinsic nonlinearity of devices, has no zero-point offset, is robust to process, and supports efficient single-temperature calibration. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a bandgap reference source curvature compensation system and control method that can support a new curvature compensation mechanism for efficient single-temperature calibration.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A bandgap reference source curvature compensation system includes a bandgap reference core circuit configured to generate a voltage V complementary to absolute temperature. CTAT and voltage V that is proportional to absolute temperature PTAT It outputs a reference voltage V, which is a linear combination of the two. BG =V CTAT +α·V PTAT ,

[0007] The system also includes a temperature adaptive scaling module, which is coupled to the V PTAT A branch is used to generate a dynamic scaling factor α(T) that varies linearly with temperature, such that α(T)·V PTAT This forms a temperature-dependent, quadratic nonlinear compensation voltage component that is zero at 0 K to counteract V. CTAT The residual nonlinear curvature in; the temperature adaptive scaling module includes:

[0008] (a) Duty cycle resistor unit, wherein the duty cycle resistor R X The equivalent resistance value R X,eq Controlled by clock signal CLK DCR The duty cycle D is determined, and R satisfies X,eq Proportional to D;

[0009] (b) A duty cycle resistor clock generation unit configured to generate CLK. DCR And make D linearly positively correlated with absolute temperature T; wherein, the duty cycle resistor clock generation unit includes:

[0010] The ramp generation subunit responds to the reference voltage V. BG With the second adjustable resistor R R To form a constant temperature coefficient current charging path for the energy storage capacitor C R Perform linear charging to generate a ramp voltage V RAMP (t); and

[0011] Comparison subunit, which will V RAMP (t) and the reference voltage V, which is proportional to the absolute temperature. PTAT,CMP Compare and output CLK at the comparison reversal time. DCR The edge, thus making D = (C R R R V PTAT,CMP ) / (V BG T P ), where T p For clock cycles;

[0012] (c) Adjustment interface unit, which includes a first adjustable element R S Second adjustable element R R , where R S Set in V PTAT In the transmission path, the primary temperature coefficient of the compensated voltage component is adjusted, R R It is positioned in the charging path of the ramp generation subunit to adjust the secondary temperature coefficient of the compensation voltage component, and R S With R R The chip-level linear correlation allows for adjustment of only R. R R can then be determined collaboratively. S The calibration value.

[0013] A control method applied to the bandgap reference source curvature compensation system as described in claim 1, characterized by comprising the following steps:

[0014] S1: Complementary absolute temperature voltage V is generated by the bandgap reference core circuit. CTAT and proportional to absolute temperature voltage V PTAT ;

[0015] S2: The duty cycle resistor unit of the temperature adaptive scaling module controls V. PTAT Dynamic scaling is performed to generate a scaling factor α(T) that varies linearly with absolute temperature T, such that α(T)·V PTATThis constitutes a compensation voltage component that is zero at 0 K and has a second-order temperature dependence.

[0016] S3: Generate CLK through the duty cycle resistor clock generation unit DCR And make the duty cycle D linearly positively correlated with the temperature T; the duty cycle resistive clock generation unit performs the following sub-steps:

[0017] S31: Responding to reference voltage V BG With adjustable resistor R R This forms a constant temperature coefficient current charging path for the energy storage capacitor C. R Linear charging is performed to generate a ramp voltage V. RAMP(t) =(V BG / R R )·t;

[0018] S32: The V RAMP(t) The reference voltage V, which is proportional to the absolute temperature PTAT,CMP Compare and generate CLK at the comparison reversal time. DCR The edge of the boundary such that D = (C R R R V PTAT,CMP ) / (V BG T P );

[0019] S4: Combine the compensation voltage component with V CTAT Linear addition, output reference voltage V BG =V CTAT +α(T)·V PTAT ;

[0020] S5: via the first adjustable element R S The primary temperature coefficient of the compensation voltage component is adjusted via the second adjustable element R. R Adjust the secondary temperature coefficient of the compensation voltage component.

[0021] Through the above bandgap reference source curvature compensation system and its control method, a new curvature compensation mechanism that is independent of device intrinsic nonlinearity, has no zero-point offset, is highly robust to the process, and supports efficient single-temperature calibration has been realized. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the segmented compensation of the present invention;

[0023] Figure 2 This is a schematic diagram of curvature compensation of the present invention;

[0024] Figure 3 This is a schematic diagram of the self-heating compensation of the present invention;

[0025] Figure 4 This is a schematic diagram of the adaptive scaling curvature compensation of the present invention;

[0026] Figure 5 This is a block diagram of the adaptive scaling curvature compensation circuit structure of the present invention;

[0027] Figure 6 This is the core circuit of the BGR in this invention;

[0028] Figure 7 This is the duty cycle resistor unit of the present invention;

[0029] Figure 8 This is the duty cycle resistor clock generation unit of the present invention;

[0030] Figure 9 This is the timing diagram for the duty cycle resistor clock generation of the present invention;

[0031] Figure 10 This invention provides the output results of individually adjusting the linear and nonlinear components.

[0032] Figure 11 This invention compares the output when the duty cycle resistor is enabled and disabled.

[0033] Figure 12 This invention provides the corresponding parameters of each chip and their fitting curves when the temperature drift calibration is optimized.

[0034] Figure 13 This invention relates to the calibration results of two temperature points and a single temperature point. Detailed Implementation

[0035] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0036] This application proposes a process-independent curvature-compensated bandgap reference source. The core technology involves dynamically scaling the PTAT voltage using a temperature-adaptive duty cycle resistor (DCR) to achieve a reference for V. CTAT Nonlinear and precise compensation is achieved while avoiding offset errors. As shown in Figure 4, this design transforms the originally constant α into a voltage amplification factor α(T) that adapts to temperature, thereby achieving precise dynamic compensation for the CTAT voltage.

[0037] Existing bandgap reference sources generally use a fixed coefficient α to achieve first-order temperature compensation, and its output expression is 𝑉 BG =𝑉 CTAT +𝛼⋅𝑉 PTAT , where is a constant. This structure cannot cancel out . CTAT The second-order and higher-order residual nonlinear terms after Taylor expansion (such as V) CTAT = V CTAT0 - AT 2 - BT), which makes it difficult for temperature drift to be lower than 10 ppm / °C; and traditional curvature compensation schemes rely on the intrinsic nonlinearity of BJT or MOSFET devices, which easily introduces 0K non-zero offset voltage and strong process dependence, resulting in calibration difficulties and poor cross-node reusability.

[0038] This application discloses a bandgap reference source curvature compensation system, including a bandgap reference core circuit, the core circuit being configured to generate a complementary absolute temperature voltage (ATV) 𝑉. CTAT and proportional to absolute temperature voltage 𝑉 PTAT It outputs a reference voltage φ, which is a linear combination of the two. BG =𝑉 CTAT +𝛼⋅𝑉 PTAT ;

[0039] The system also includes a temperature adaptive scaling module, which is coupled to the 𝑉 PTAT A branch is used to generate a dynamic scaling factor α(T) that varies linearly with temperature, such that α(T) ⋅ 𝑉 PTAT This forms a compensation voltage component that is zero at 0 K and has a second-order temperature dependence, to counteract 𝑉 CTAT The residual nonlinear curvature in the circuit. To achieve the temperature-adaptive amplification factor α(T), the overall circuit shown in Figure 5 was designed. The BGR Core is the core circuit, generating the CTAT voltage, PTAT voltage, and amplification factor α(T), and performing a linear combination: V CTAT +α(T)·V PTAT The amplification factor depends on the ratio of the two resistors, specifically achieved by the voltage drop across resistor R0 being V. PTAT , generating current V PTAT / R0, and let the current flow through resistor R X At this time, the resistance R X The pressure drop on is R X ·V PTAT / R0 enables V PTAT (R) X The method proposed in this patent is to amplify R ( / R0). X The resistance value is dynamically adjusted with temperature, thereby achieving an adaptive voltage amplification factor α(T).

[0040] The temperature adaptive scaling module includes:

[0041] (a) Duty cycle resistor unit, wherein the duty cycle resistor R X The equivalent resistance value R X,eq Controlled by clock signal CLK DCR The duty cycle D is determined, and R satisfies X,eq Proportional to D;

[0042] (b) Duty cycle resistor clock generation unit, see Figure 8 It is configured to generate CLK DCR And make D linearly positively correlated with absolute temperature T; wherein, the duty cycle resistor clock generation unit includes:

[0043] The ramp generation subunit responds to the reference voltage V. BG With the second adjustable resistor R R To form a constant temperature coefficient current charging path for the energy storage capacitor C R Linear charging is performed, and periodic discharging is initiated at the beginning of the cycle via a switch controlled by the service signal RSTN to generate a ramp voltage V. RAMP (t); and

[0044] Comparison subunit, which will V RAMP (t) and the reference voltage V, which is proportional to the absolute temperature. PTAT,CMP The comparison process ensures that the comparator switching time is positively correlated with temperature, generating a duty cycle resistor clock, which outputs CLK at the comparison inversion point. DCR The edge, thus making D = (C R R R V PTAT,CMP ) / (V BG T P ), where T p For clock cycles;

[0045] Specifically, see Figure 9A clock with a period of Tp generates a reset signal RSTN and its inverse signal RST, used to discharge CR to zero potential; when the reset signal RSTN is low, the charging phase begins (charging current is V). BG / R R ), V RAMP As (t) continuously increases, the voltage-time relationship is: V RAMP (t) = V BG ·t / R R When V RAMP (t) equals V PTAT,CMP (kV PTAT The time for (i.e., when the comparator inverts) is: C R R R kV PTAT / V BG The duty cycle is: (C R R R V PTAT,CMP ) / (V BG T P ).

[0046] Substitute it into α(T)⋅V PTAT The expression can be obtained as follows:

[0047] α(T)⋅V PTAT = ((R S + 2R X ) / R0)·V T lnN = ((R S + R1(2+D) / 2) / R0)·V T lnN = ((R S + R1(2 + (C R R R V PTAT,CMP ) / (V BG T P )) / 2) / R0)·V T lnN = ((R S / R0) + (R1 / R0))·V T lnN + ((R1 / 2R0) + (kC R R R / T P V BG ))·(V T lnN) 2 .

[0048] By changing R S Adjusting the first linear term changes R R Adjust the second square term to the desired AT. 2In the + BT format, compensation is completed.

[0049] Therefore, the first-order (linear) and second-order (non-linear) terms can be independently and flexibly adjusted to achieve any combination of slope and curvature. The resistance RS is the linear adjustment term, and RR is the non-linear adjustment term; there is a clear relationship between the two coefficients, and one can be used to calculate the value of the other, thus optimizing two parameters into a single parameter; the non-linear PTAT voltage is maintained at 0K with no voltage, ensuring that there is no absolute voltage deviation in the output voltage, enabling voltage calibration at a single temperature point. (c) Adjustment interface unit, which includes a first adjustable element R S Second adjustable element R R , where R S Set in V PTAT In the transmission path, the primary temperature coefficient of the compensated voltage component is adjusted, R R It is positioned in the charging path of the ramp generation subunit to adjust the secondary temperature coefficient of the compensation voltage component, and R S With R R The chip-level linear correlation allows for adjustment of only R. R R can then be determined collaboratively. S The calibration value.

[0050] In the specific implementation, see Figure 6 The core circuit of the BGR includes: a bias generation circuit (used to provide bias current to the error amplifier, startup circuit, and comparator); an error amplifier (used to generate feedback [clamping the voltage between the emitter of transistor Q1 and the upper end of resistor R0, so that the voltage difference across R1 is exactly the difference between the emitter-base voltages of the two transistors, which is the PTAT voltage], and using chopping technology to reduce noise and mismatch); and the BGR core, which includes a duty cycle resistor R. X (As shown in Figure 7), the equivalent resistance is: R X,eq = R1 / (2 - D) ≈ R1(2 + D) / 4, where D is the duty cycle of the switch control clock; the first adjustable element R S， Used for chip calibration (corresponding to the above expression V) PTAT =AT 2 + BT term B, i.e., the coefficient of the linear term).

[0051] The duty cycle resistor unit includes two parallel branches. The first branch is a resistor with a fixed resistance of R1, and the second branch is a MOS switch connected in series with another resistor of R1. When the MOS switch is on, the second branch is on, and its equivalent resistance is R1. When the MOS switch is off, the second branch is open. The CLK... DCRControlling the on and off states of the MOS switch causes the equivalent resistance R of the duty cycle resistor unit to... X,eq It can be represented as R1 / (2−D), where D is CLK. DCR Duty cycle.

[0052] The MOS switch is a transmission gate structure, consisting of complementary NMOS and PMOS transistors connected in parallel, with the gate of the NMOS transistor receiving CLK. DCR Signal, PMOS transistor gate receives CLK DCR The inverted signal is used to reduce the on-resistance nonlinearity and the effect of channel charge injection on the equivalent resistance R. X,eq The effect of temperature linearity.

[0053] The V PTAT,CMP It is generated by a pair of bipolar transistors with the same process corner and layout matching structure as bipolar transistors Q1 and Q2 in the core circuit of the bandgap reference, and its voltage expression is k·V. PTAT , where k is the adjusted gain coefficient; the adjustment of k is achieved by a digital fuse array integrated inside the chip, and the fusing state of the digital fuse array is determined by laser adjustment or electrical programming.

[0054] The resistors R1 and R2 are polycrystalline silicon resistors made of the same material and manufactured using the same process. They have the same strip width, strip length, and adjacent spacing, and are arranged in the same temperature gradient region of the chip so that the temperature coefficient matching error between them is less than ±50 ppm / °C.

[0055] The ramp generation subunit includes a chopper-stabilized operational amplifier, a PMOS current mirror, and the adjustable resistor R. R The non-inverting input of the operational amplifier is connected to a reference voltage V. BG The inverting input is connected to R. R The upper node of the PMOS current mirror is used to drive its gate; the input branch of the PMOS current mirror flows through R. R The output branch is connected to the energy storage capacitor C. R Charging, thus in C R A linearly rising ramp voltage V is generated at both ends. RAMP(t) =(V BG / R R )·t.

[0056] The adjustment interface unit also includes a calibration controller configured to perform a single-parameter calibration operation, comprising the following steps: measuring the output reference voltage V at a single calibration temperature point T0. BG The actual value; based on the chip-level linear fitting relationship R stored in the lookup table memory. S =a·R R+b, where a and b are both fitting parameters, and the measured V BG Substitute into the compensation model to calculate the required R R Target value; only for the second adjustable element R R Perform physical adjustments, the first adjustable element R S The adjustment value is automatically determined by the fitted relation and written into the corresponding adjustment register.

[0057] The calibration controller is also configured to enter a calibration startup mode when the chip is first powered on, including the following steps: acquiring V under T0. BG Initial output value; look up the reference fitting parameters a0 and b0 corresponding to the current process angle in the lookup table memory; substitute into R S =a0·R R +b0 calculates R S Initial value; set R as the initial value. S Initial value written to R S Adjust the register, and at the same time set R R Initialize to the nominal value; after completing the above operations, exit the startup calibration mode and enter the normal working mode.

[0058] The temperature adaptive scaling module is also applicable to reference current sources, ring oscillators, or voltage-controlled oscillators.

[0059] A control method applied to the bandgap reference source curvature compensation system as described in claim 1, characterized by comprising the following steps:

[0060] S1: Complementary absolute temperature voltage V is generated by the bandgap reference core circuit. CTAT and proportional to absolute temperature voltage V PTAT ;

[0061] S2: The duty cycle resistor unit of the temperature adaptive scaling module controls V. PTAT Dynamic scaling is performed to generate a scaling factor α(T) that varies linearly with absolute temperature T, such that α(T)·V PTAT This constitutes a compensation voltage component that is zero at 0 K and has a second-order temperature dependence.

[0062] S3: Generate CLK through the duty cycle resistor clock generation unit DCR And make the duty cycle D linearly positively correlated with the temperature T; the duty cycle resistive clock generation unit performs the following sub-steps:

[0063] S31: Responding to reference voltage V BG With adjustable resistor R R This forms a constant temperature coefficient current charging path for the energy storage capacitor C. R Linear charging is performed to generate a ramp voltage V. RAMP(t)=(V BG / R R )·t;

[0064] S32: The V RAMP(t) The reference voltage V, which is proportional to the absolute temperature PTAT,CMP Compare and generate CLK at the comparison reversal time. DCR The edge of the boundary such that D = (C R R R V PTAT,CMP ) / (V BG T P );

[0065] S4: Combine the compensation voltage component with V CTAT Linear addition, output reference voltage V BG =V CTAT +α(T)·V PTAT ;

[0066] S5: via the first adjustable element R S The primary temperature coefficient of the compensation voltage component is adjusted via the second adjustable element R. R Adjust the secondary temperature coefficient of the compensation voltage component. This method is applicable to temperature compensation of reference current sources, ring oscillators, or voltage-controlled oscillators.

[0067] Step S2 further includes: controlling the MOS switch at CLK DCR On when high level, during CLK DCR It is turned off when the level is low.

[0068] When controlling the MOS switch, a transmission gate structure is used, that is, CLK is synchronously applied to the gate of the NMOS transistor. DCR Signal, applying CLK to the gate of the PMOS transistor DCR The inverted signal is used to reduce the on-resistance nonlinearity and the impact of channel charge injection on R. X,eq The effect of temperature linearity.

[0069] In step S32, the V PTAT,CMP It is generated by a pair of bipolar transistors with the same process corner and layout matching structure as bipolar transistors Q1 and Q2 in the bandgap reference core circuit, and its expression is k·V. PTAT， k is the gain coefficient.

[0070] The resistor R1 in the first branch and the resistor R1 in the second branch are polysilicon resistors of the same material type and manufacturing process. They have the same strip width, strip length and adjacent spacing, and are arranged in the same temperature gradient region of the chip so that the temperature coefficient matching error between them is less than ±50 ppm / °C.

[0071] In step S31, the constant temperature coefficient current charging path consists of a chopper-stabilized operational amplifier, a PMOS current mirror, and an R... R Composition; Step S31 further includes: V BG Connect R to the non-inverting input of the operational amplifier. R The upper node is connected to the inverting input terminal, and the operational amplifier output drives the gate of the PMOS current mirror, so that the output branch of the PMOS current mirror provides CR with a precise V value. BG / R R The charging current.

[0072] Step S5 further includes: measuring V at a single calibration temperature point T0. BG The actual output value; based on the chip-level linear fitting relationship R pre-stored in the lookup table memory. S =a·R R +b, where a and b are both fitted parameters, substituted into the measured V BG Calculate the required R R Target value; only for R R Perform physical adjustments, R S The adjustment value is automatically calculated by the fitted relation and written to the corresponding adjustment register.

[0073] It also includes a calibration initiation step, performed when the chip is first powered on: acquiring V at temperature T0. BG Initial output value; look up the reference fitting parameters a0 and b0 corresponding to the current process angle in the lookup table memory; substitute into R S =a0·R R +b0 calculates R S Initial value; set R as the initial value. S Initial value written to R S Adjust the register, and at the same time set R R Initialize to the nominal value; after completing the above operations, enter normal working mode.

[0074] As shown in Figure 10, the linear and nonlinear components can be adjusted separately. As shown in Figure 11, the temperature drift performance is improved by more than 10 times after using a duty cycle resistor (DCR) to compensate for nonlinearity.

[0075] like Figure 12 As shown, when the temperature drift is adjusted to the minimum, there is a correlation between the two parameters of the chip. This relationship can be linearly fitted, and one of the parameters can be optimized using this relationship to achieve single parameter calibration.

[0076] like Figure 13 As shown, under the premise of a single parameter, since compensation does not introduce additional voltage offset, two temperature points (output voltage is calibrated to be the same at -10℃ and 95℃) or even a single temperature point (chip output is calibrated to a fixed value at 20℃) can be used for calibration.

[0077] This technical solution generates a temperature-adaptive voltage amplification factor α(T), which is used to achieve curvature calibration of the bandgap reference source. In addition to the V used in this technical solution... CTAT + α(T)·V PTAT In addition to the compensation formula, α(T)·V can also be used. CTAT + V PTAT Or α1(T)·V CTAT + α2(T)·V PTAT All three supplementary schemes compensate for residual nonlinear curvature by dynamically scaling the positive and negative temperature coefficient voltages, differing only in the combination of coefficients.

[0078] This technical solution uses a duty cycle resistor (DCR) to generate a temperature-adaptive voltage amplification factor α(T). Based on the same core objective, the following alternative methods can also be used: First, it can be generated by a proportional combination of resistors with different temperature coefficients (such as adjusting the ratio of positive temperature coefficient resistors to negative temperature coefficient resistors), utilizing the difference in the temperature characteristics of the resistors to achieve dynamic changes in α(T); Second, it can be generated by digitally controlling the proportional coefficient (such as adjusting the ratio by configuring a digital potentiometer through a register and adjusting the ratio through a digital logic module). Both alternative methods can ensure that α(T) is adaptively adjusted with temperature, meeting the curvature compensation requirements, without changing the core logic of the overall circuit.

[0079] In this technical solution, the duty cycle resistor controls the clock ramp voltage (V). RAMP The signal is generated by charging the capacitor with a constant temperature coefficient current and comparing it with the PTAT voltage. Based on the same control logic, the following alternative methods can be used: one is to generate a ramp voltage V by charging the capacitor with a temperature coefficient or no temperature coefficient current. RAMP The first approach involves comparing the voltage with or without a temperature coefficient. As long as the temperature coefficient of the charging current differs from that of the comparator reference voltage, a duty cycle signal with the required temperature coefficient can be generated. The second approach is to digitally control the duty cycle using a temperature sensor. This involves acquiring temperature data via an on-chip temperature sensor, processing it through a digital logic module, and directly outputting the duty cycle control signal. Both alternative solutions ensure that the duty cycle of CLK_DCR changes linearly with temperature, achieving temperature-adaptive adjustment of the equivalent resistance of the duty cycle resistor (DCR) and meeting core control requirements.

[0080] The core method of this technical solution, "temperature-adaptive amplification factor for curvature calibration," essentially achieves high-precision temperature compensation by adaptively adjusting the proportional coefficient based on temperature and utilizing the mutual cancellation of positive and negative temperature coefficients. Based on this core principle, this method can be directly adapted to all other high-precision circuit systems that require temperature compensation through the cancellation of positive and negative temperature coefficients, such as reference current circuits and oscillator circuits (reference frequency circuits).

[0081] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A bandgap reference source curvature compensation system, comprising a bandgap reference core circuit, said core circuit being configured to generate a voltage V complementary to absolute temperature. CTAT and voltage V that is proportional to absolute temperature PTAT It outputs a reference voltage V, which is a linear combination of the two. BG =V CTAT +α·V PTAT Its characteristics are: The system also includes a temperature adaptive scaling module, which is coupled to the V PTAT A branch is used to generate a dynamic scaling factor α(T) that varies linearly with temperature, such that α(T)·V PTAT This forms a temperature-dependent, quadratic nonlinear compensation voltage component that is zero at 0 K to counteract V. CTAT Residual nonlinear curvature in; The temperature adaptive scaling module includes: (a) Duty cycle resistor unit, wherein the duty cycle resistor R X The equivalent resistance value R X,eq Controlled by clock signal CLK DCR The duty cycle D is determined, and R satisfies X,eq Proportional to D; (b) A duty cycle resistor clock generation unit configured to generate CLK. DCR And make D linearly positively correlated with absolute temperature T; wherein, the duty cycle resistor clock generation unit includes: The ramp generation subunit responds to the reference voltage V. BG With the second adjustable resistor R R To form a constant temperature coefficient current charging path for the energy storage capacitor C R Perform linear charging to generate a ramp voltage V RAMP (t); and Comparison subunit, which will V RAMP (t) and the reference voltage V, which is proportional to the absolute temperature. PTAT,CMP Compare and output CLK at the comparison reversal time. DCR The edge, thus making D = (C R R R V PTAT,CMP ) / (V BG T P ), where T p For clock cycles; (c) Adjustment interface unit, which includes a first adjustable element R S Second adjustable element R R , where R S Set in V PTAT In the transmission path, the primary temperature coefficient of the compensated voltage component is adjusted, R R It is positioned in the charging path of the ramp generation subunit to adjust the secondary temperature coefficient of the compensation voltage component, and R S With R R The chip-level linear correlation allows for adjustment of only R. R R can then be determined collaboratively. S The calibration value.

2. The bandgap reference source curvature compensation system according to claim 1, characterized in that, The duty cycle resistor unit includes two parallel branches. The first branch is a fixed-value resistor R1, and the second branch is a MOS switch connected in series with another resistor of resistance R1. When the MOS switch is on, the second branch is on, and its equivalent resistance is R1. When the MOS switch is off, the second branch is open. The CLK... DCR Controlling the on and off states of the MOS switch causes the equivalent resistance R of the duty cycle resistor unit to... X,eq It can be represented as R1 / (2−D), where D is CLK. DCR Duty cycle.

3. The bandgap reference source curvature compensation system according to claim 2, characterized in that, The MOS switch is a transmission gate structure, consisting of complementary NMOS and PMOS transistors connected in parallel, with the gate of the NMOS transistor receiving CLK. DCR Signal, PMOS transistor gate receives CLK DCR The inverted signal is used to reduce the on-resistance nonlinearity and the effect of channel charge injection on the equivalent resistance R. X,eq The effect of temperature linearity.

4. The bandgap reference source curvature compensation system according to claim 1, characterized in that, The V PTAT,CMP It is generated by a pair of bipolar transistors with the same process corner and layout matching structure as bipolar transistors Q1 and Q2 in the core circuit of the bandgap reference, and its voltage expression is k·V. PTAT , where k is the adjusted gain coefficient; the adjustment of k is achieved by a digital fuse array integrated inside the chip, and the fusing state of the digital fuse array is determined by laser adjustment or electrical programming.

5. The bandgap reference source curvature compensation system according to claim 2, characterized in that, The resistor R1 in the first branch and the resistor R1 in the second branch are polysilicon resistors of the same material type and manufacturing process. They have the same strip width, strip length and adjacent spacing, and are arranged in the same temperature gradient region of the chip so that the temperature coefficient matching error between them is less than ±50 ppm / °C.

6. The bandgap reference source curvature compensation system according to claim 1, characterized in that, The ramp generation subunit includes a chopper-stabilized operational amplifier, a PMOS current mirror, and the adjustable resistor R. R The non-inverting input of the operational amplifier is connected to a reference voltage V. BG The inverting input is connected to R. R The upper node of the PMOS current mirror is used to drive its gate; the input branch of the PMOS current mirror flows through R. R The output branch is connected to the energy storage capacitor C. R Charging, thus in C R A linearly rising ramp voltage V is generated at both ends. RAMP(t) =(V BG / R R )·t.

7. The bandgap reference source curvature compensation system according to claim 1, characterized in that, The adjustment interface unit also includes a calibration controller configured to perform a single-parameter calibration operation, comprising the following steps: measuring the output reference voltage V at a single calibration temperature point T0. BG The actual value; based on the chip-level linear fitting relationship R stored in the lookup table memory. S =a·R R +b, where a and b are both fitting parameters, and the measured V BG Substitute into the compensation model to calculate the required R R Target value; only for the second adjustable element R R Perform physical adjustments, the first adjustable element R S The adjustment value is automatically determined by the fitted relation and written into the corresponding adjustment register.

8. The bandgap reference source curvature compensation system according to claim 7, characterized in that, The calibration controller is also configured to enter a calibration startup mode when the chip is first powered on, including the following steps: acquiring V under T0. BG Initial output value; Look up the reference fitting parameters a0 and b0 corresponding to the current process angle in the lookup table memory; substitute them into R. S =a0·R R +b0 calculates R S Initial value; set R as the initial value. S Initial value written to R S Adjust the register, and at the same time set R R Initialize to the nominal value; after completing the above operations, exit the startup calibration mode and enter the normal working mode. Preferably, the temperature adaptive scaling module is also applicable to a reference current source, a ring oscillator, or a voltage-controlled oscillator.

9. A control method applied to the bandgap reference source curvature compensation system as described in claim 1, characterized in that, Includes the following steps: S1: Complementary absolute temperature voltage V is generated by the bandgap reference core circuit. CTAT and proportional to absolute temperature voltage V PTAT ; S2: The duty cycle resistor unit of the temperature adaptive scaling module controls V. PTAT Dynamic scaling is performed to generate a scaling factor α(T) that varies linearly with absolute temperature T, such that α(T)·V PTAT This constitutes a compensation voltage component that is zero at 0 K and has a second-order temperature dependence. S3: Generate CLK through the duty cycle resistor clock generation unit DCR And make the duty cycle D linearly positively correlated with the temperature T; the duty cycle resistive clock generation unit performs the following sub-steps: S31: Responding to reference voltage V BG With adjustable resistor R R This forms a constant temperature coefficient current charging path for the energy storage capacitor C. R Linear charging is performed to generate a ramp voltage V. RAMP(t) =(V BG / R R )·t; S32: The V RAMP(t) The reference voltage V, which is proportional to the absolute temperature PTAT,CMP Compare and generate CLK at the comparison reversal time. DCR The edge such that D = (C R R R V PTAT,CMP ) / (V BG T P ); S4: Combine the compensation voltage component with V CTAT Linear addition, output reference voltage V BG =V CTAT +α(T)·V PTAT ; S5: via the first adjustable element R S The primary temperature coefficient of the compensation voltage component is adjusted via the second adjustable element R. R Adjust the secondary temperature coefficient of the compensation voltage component.

10. The method according to claim 10, characterized in that, Step S2 further includes: controlling the MOS switch at CLK DCR On when high level, during CLK DCR Off when low level; Preferably, when controlling the MOS switch, a transmission gate structure is used, that is, CLK is synchronously applied to the gate of the NMOS transistor. DCR Signal, applying CLK to the gate of the PMOS transistor DCR The inverted signal is used to reduce the on-resistance nonlinearity and the impact of channel charge injection on R. X,eq The effect of temperature linearity; Preferably, in step S32, the V PTAT,CMP It is generated by a pair of bipolar transistors with the same process corner and layout matching structure as bipolar transistors Q1 and Q2 in the bandgap reference core circuit, and its expression is k·V. PTAT， k is the gain coefficient; Preferably, the resistor with resistance value R1 in the first branch and the resistor with resistance value R1 in the second branch are polysilicon resistors of the same material type and manufacturing process, and they have the same strip width, strip length and adjacent spacing, and are arranged in the same temperature gradient region of the chip, so that the temperature coefficient matching error between the two is less than ±50 ppm / °C. Preferably, in step S31, the constant temperature coefficient current charging path consists of a chopper-stabilized operational amplifier, a PMOS current mirror, and an R... R Composition; Step S31 further includes: V BG Connect R to the non-inverting input of the operational amplifier. R The upper node is connected to the inverting input terminal, and the operational amplifier output drives the gate of the PMOS current mirror, making the output branch of the PMOS current mirror aligned with C. R Provides accurate V BG / R R The charging current; Preferably, step S5 further includes: measuring V at a single calibration temperature point T0. BG The actual output value; based on the chip-level linear fitting relationship R S =a·R R +b, substitute into the measured V BG Calculate the required R R Target value; only for R R Perform physical adjustments, R S The adjustment value is automatically calculated by the fitted relation and written into the corresponding adjustment register; Preferably, it also includes a calibration initiation step, performed when the chip is first powered on: collecting V at temperature T0. BG Initial output value; look up the reference fitting parameters a0 and b0 corresponding to the current process angle in the lookup table memory; substitute into R S =a0·R R +b0 calculates R S Initial value; set R as the initial value. S Initial value written to R S Adjust the register, and at the same time set R R Initialize to the nominal value; after completing the above operations, enter normal working mode. Preferably, the method is applicable to temperature compensation of a reference current source, a ring oscillator, or a voltage-controlled oscillator.

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