Asynchronous reset circuit, asynchronous reset method and system on chip

Abstract

This application relates to the field of integrated circuit technology, providing an asynchronous reset circuit, an asynchronous reset method, and a system-on-a-chip. The circuit includes a first functional unit, a second functional unit, and a first signal synchronization module. The first signal synchronization module includes a first selection unit and a first synchronization unit. The first selection unit selects one of a first original signal output by the first functional unit and a preset first default value signal of the first functional unit as a first intermediate signal output, based on the state of the first reset signal of the first functional unit. The first synchronization unit is driven by a second reset signal of the second functional unit and performs multi-level register synchronization on the first intermediate signal, outputting the synchronized first target signal to the second functional unit. This application solves the timing problem caused by signal jumps between adjacent functional units during asynchronous reset, ensuring that the receiving functional unit can operate normally, thereby improving the performance and reliability of the entire chip system.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to asynchronous reset circuits, asynchronous reset methods, and on-chip systems. Background Technology

[0002] In the field of modern digital integrated circuits, a System on a Chip (SoC) is a highly integrated chip. A digital SoC chip typically consists of several or even dozens of functionally independent units, such as intellectual property (IP) cores, which work together to achieve various complex functions of the chip.

[0003] In the actual operation of a SoC, in addition to performing a full reset of the entire chip, it is often necessary to reset only a specific IP or a few IPs to meet specific functional requirements or handle local faults. Among the many reset methods, asynchronous reset has the advantage of fast response speed because it can reset the circuit at any clock cycle without waiting for a specific edge of the clock signal. Therefore, it is widely used in many digital circuit designs with high requirements for reset timeliness.

[0004] However, when an IP is reset asynchronously, the signals output by that IP to other IPs may abruptly change at the moment of reset. Since different IPs within the same SoC may use different asynchronous reset signals, even if they are in the same clock domain, these asynchronous reset signals make signal transmission and synchronization between IPs extremely complex. IPs receiving this signal may face timing issues due to sudden changes in the input signal, such as setup time and hold time not meeting requirements, which severely impacts the performance and reliability of the entire SoC chip. Summary of the Invention

[0005] This application provides an asynchronous reset circuit, an asynchronous reset method, and an on-chip system, aiming to solve the problems existing in the prior art. Within the same clock domain, when an asynchronous reset is performed on a single functional unit, the output signal is prone to jumps, leading to timing errors in the chip system during the reset process. The technical solution provided in this application can effectively address the above problems, ensuring the reliability and stability of the chip system during reset operations.

[0006] This application provides an asynchronous reset circuit, including a first functional unit, a second functional unit, and a first signal synchronization module disposed between the first functional unit and the second functional unit. The first signal synchronization module includes a first selection unit and a first synchronization unit; wherein the first functional unit and the second functional unit are in the same clock domain; the first selection unit is used to select one of the first original signal output by the first functional unit and the first default value signal preset by the first functional unit as a first intermediate signal output according to the state of the first reset signal of the first functional unit; the first synchronization unit is driven by the second reset signal of the second functional unit, and the first synchronization unit is used to perform multi-level register synchronization on the first intermediate signal and output the synchronized first target signal to the second functional unit; wherein the first reset signal and the second reset signal are both asynchronous reset signals.

[0007] According to the asynchronous reset circuit provided in this application, the first input terminal of the first selection unit is used to receive the first original signal output by the first functional unit, the second input terminal of the first selection unit is used to receive the first default value signal preset by the first functional unit, and the control terminal of the first selection unit is used to receive the first reset signal of the first functional unit; the input terminal of the first synchronization unit is connected to the output terminal of the first selection unit, the output terminal of the first synchronization unit is connected to the second functional unit, and the reset terminal of the first synchronization unit is used to receive the second reset signal of the second functional unit.

[0008] According to an asynchronous reset circuit provided in this application, the first selection unit is used to: select a first default value signal as a first intermediate signal output when it is determined that the first functional unit is in a reset state according to the first reset signal; and select a first original signal as a first intermediate signal output when it is determined that the first functional unit is in a de-reset state according to the first reset signal.

[0009] According to an asynchronous reset circuit provided in this application, the first synchronization unit includes a plurality of D flip-flops; wherein each D flip-flop includes a reset terminal and a clock terminal; the clock terminal of each D flip-flop is used to receive a clock signal output by a second functional unit; and the reset terminal of each D flip-flop is used to receive a second reset signal output by the second functional unit.

[0010] According to an asynchronous reset circuit provided in this application, a plurality of D flip-flops include a first D flip-flop, a second D flip-flop, and a third D flip-flop connected in series; wherein, the input terminal of the first D flip-flop is connected to the output terminal of a first selection unit, the input terminal of the second D flip-flop is connected to the output terminal of the first D flip-flop, the input terminal of the third D flip-flop is connected to the output terminal of the second D flip-flop, and the output terminal of the third D flip-flop is connected to a second functional unit.

[0011] According to an asynchronous reset circuit provided in this application, the asynchronous reset circuit further includes a second signal synchronization module disposed between a first functional unit and a second functional unit. The second signal synchronization module includes a second selection unit and a second synchronization unit. The second selection unit is used to select one of the second original signal output by the second functional unit and the second default value signal preset by the second functional unit as a second intermediate signal output according to the state of the second reset signal of the second functional unit. The second synchronization unit is driven by the first reset signal of the first functional unit and is used to perform multi-level register synchronization on the second intermediate signal and output the synchronized second target signal to the first functional unit.

[0012] According to the asynchronous reset circuit provided in this application, the first input terminal of the second selection unit is used to receive the second original signal output by the second functional unit, the second input terminal of the second selection unit is used to receive the second default value signal preset by the second functional unit, and the control terminal of the second selection unit is used to receive the second reset signal of the second functional unit; the input terminal of the second synchronization unit is connected to the output terminal of the second selection unit, the output terminal of the second synchronization unit is connected to the first functional unit, and the reset terminal of the second synchronization unit is used to receive the first reset signal of the first functional unit.

[0013] This application also provides an asynchronous reset method using the above-described asynchronous reset circuit. The asynchronous reset method includes: receiving a first reset signal output by a first functional unit; selecting one of a first original signal output by the first functional unit and a first default value signal preset by the first functional unit as a first intermediate signal according to the state of the first reset signal; performing multi-level register synchronization on the first intermediate signal under the drive of a second reset signal from a second functional unit; and outputting the synchronized first target signal to the second functional unit.

[0014] According to an asynchronous reset method provided in this application, a first intermediate signal is selected from a first original signal output by a first functional unit and a first default value signal preset by the first functional unit, based on the state of a first reset signal. The method includes: when the first functional unit is determined to be in a reset state based on the first reset signal, the first default value signal is selected as the first intermediate signal for output; when the first functional unit is determined to be in a de-reset state based on the first reset signal, the first original signal is selected as the first intermediate signal for output.

[0015] This application also provides a system-on-a-chip including the asynchronous reset circuit described above.

[0016] This application provides an asynchronous reset circuit, an asynchronous reset method, and an on-chip system. The asynchronous reset circuit includes a first functional unit, a second functional unit, and a first signal synchronization module disposed between the first and second functional units. The first signal synchronization module includes a first selection unit and a first synchronization unit. The first and second functional units are in the same clock domain. The first selection unit selects one of a first original signal output by the first functional unit and a preset first default value signal of the first functional unit as a first intermediate signal output, based on the state of the first reset signal of the first functional unit. The first synchronization unit is driven by the second reset signal of the second functional unit and performs multi-level register synchronization on the first intermediate signal, outputting the synchronized first target signal to the second functional unit. Both the first and second reset signals are asynchronous reset signals. Through this method, this application can solve the timing problem caused by signal jumps between adjacent functional units during asynchronous reset, ensuring that the receiving functional unit can operate normally, thereby improving the performance and reliability of the entire chip system. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the structural schematic diagrams of the asynchronous reset circuit provided in the embodiments of this application.

[0019] Figure 2 This is a schematic diagram of the structure of the first synchronization unit in the asynchronous reset circuit provided in the embodiments of this application.

[0020] Figure 3 This is the second schematic diagram of the asynchronous reset circuit provided in the embodiments of this application.

[0021] Figure 4 This is the third schematic diagram of the asynchronous reset circuit provided in the embodiments of this application.

[0022] Figure 5 This is a flowchart illustrating the asynchronous reset method provided in the embodiments of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In the description of the embodiments of this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly, for example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application based on the specific circumstances.

[0025] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0026] This application provides an asynchronous reset circuit; please refer to [link / reference]. Figure 1 , Figure 1 This is one of the structural schematic diagrams of the asynchronous reset circuit provided in the embodiments of this application. In this embodiment, the asynchronous reset circuit may include a first functional unit 110, a second functional unit 120, and a first signal synchronization module 130 disposed between the first functional unit 110 and the second functional unit 120. The first signal synchronization module 130 includes a first selection unit 131 and a first synchronization unit 132; wherein, the first functional unit 110 and the second functional unit 120 are in the same clock domain.

[0027] The first selection unit 131 is used to select one of the first original signal output by the first functional unit 110 and the first default value signal preset by the first functional unit 110 as the first intermediate signal output, according to the state of the first reset signal of the first functional unit 110.

[0028] The first synchronization unit 132 is driven by the second reset signal of the second functional unit 120. The first synchronization unit 132 is used to perform multi-level register synchronization on the first intermediate signal and output the synchronized first target signal to the second functional unit 120. The first reset signal and the second reset signal are both asynchronous reset signals.

[0029] In a System-on-a-Chip (SoC), a functional unit is a circuit module or logic unit with a specific, independent function. A functional unit is a collection of circuits capable of performing a specific task or function. It can implement different functions such as data processing, signal conversion, storage, and control, tailored to different application scenarios and requirements.

[0030] The first selection unit 131 is used to select a signal based on the state of the first reset signal of the first functional unit 110. The first functional unit 110 can output a first original signal and also has a preset first default value signal. When the first reset signal is in different states, the first selection unit 131 will select one of these two signals as the first intermediate signal for output. For example, in the reset state, the first default value signal will be selected; while in the normal operating state, the first original signal will be selected.

[0031] The first synchronization unit 132 is driven by the second reset signal of the second functional unit 120. Its core function is to perform multi-level register synchronization on the first intermediate signal. In this embodiment, the signal is registered sequentially through multiple registers, making the signal more stable and synchronized in time. After multi-level register synchronization, the first synchronization unit 132 outputs the synchronized first target signal and sends it to the second functional unit 120.

[0032] It should be noted that in the case of asynchronous reset, due to the asynchronous nature of the reset signal, signal transitions may occur between adjacent functional units. Such transitions may cause timing issues, preventing the receiving functional unit from processing the signal correctly, thereby affecting the performance and reliability of the entire chip system.

[0033] This embodiment solves this problem through a first signal synchronization module. Specifically, the first selection unit 131 can select a suitable signal as an intermediate signal based on the state of the first reset signal to ensure a stable signal during the reset process. The first synchronization unit 132 is driven by the second reset signal and performs multi-level register synchronization on the intermediate signal, making the signal more stable and synchronized before entering the second functional unit 120, thereby avoiding timing problems caused by signal jumps.

[0034] In summary, the embodiments of this application effectively solve the timing problem caused by signal jumps between adjacent functional units during asynchronous reset through the processing of the first signal synchronization module. Multi-level register synchronization makes the signal more stable in time, ensuring that the functional unit receiving the signal can process the signal correctly. Since the timing problem is solved, the functional unit receiving the signal can work normally, avoiding erroneous operations caused by signal instability. The normal operation of the functional unit helps to improve the performance of the entire chip system, reduce faults caused by signal problems, and thus enhance the reliability of the chip system.

[0035] In some embodiments, the first selection unit 131 may specifically be used for: When the first functional unit 110 is determined to be in a reset state based on the first reset signal, the first default value signal is selected as the first intermediate signal output; when the first functional unit 110 is determined to be in a de-reset state based on the first reset signal, the first original signal is selected as the first intermediate signal output.

[0036] Specifically, when the first reset signal of the first functional unit 110 indicates that it is in a reset state, the first selection unit 131 selects the first default value signal. When the first reset signal indicates that the first functional unit 110 is de-reset and enters a normal working state, the first selection unit 131 switches to selecting the first original signal. The first original signal may include actual business data or control instructions, etc.

[0037] The asynchronous reset signal is characterized by its changes not depending on the clock signal, which may cause the signal to jump and become unstable when switching between reset and normal operating states.

[0038] In this embodiment, the first selection unit 131 selects a signal based on the state of the first reset signal, providing a stable default signal during reset and promptly switching to the original first signal after the reset is lifted, ensuring the transmission of normal service data. The first synchronization unit 132 further synchronizes the selected signal, eliminating potential timing differences during transmission and processing, ensuring that the signal received by the second functional unit 120 is stable and meets timing requirements. Therefore, this embodiment can guarantee stable signal transmission and correct processing even in complex asynchronous reset environments.

[0039] In some embodiments, the first input terminal of the first selection unit 131 is used to receive the first original signal output by the first functional unit 110, the second input terminal of the first selection unit 131 is used to receive the first default value signal preset by the first functional unit 110, and the control terminal of the first selection unit 131 is used to receive the first reset signal of the first functional unit 110; the input terminal of the first synchronization unit 132 is connected to the output terminal of the first selection unit 131, the output terminal of the first synchronization unit 132 is connected to the second functional unit 120, and the reset terminal of the first synchronization unit 132 is used to receive the second reset signal of the second functional unit 120.

[0040] In this embodiment, the first selection unit 121 can be a multiplexer (MUX).

[0041] The first input terminal of the first selection unit 121 is connected to the first functional unit 110 and receives the first raw signal output by the first functional unit 110. The second input terminal of the first selection unit 121 receives a first default value signal preset by the first functional unit 110. This default value signal is preset.

[0042] The control terminal of the first selection unit 131 receives the first reset signal from the first functional unit 110. The first reset signal is a crucial control signal, and its state determines the selection of the first intermediate signal: when the first reset signal is in the reset state, the first selection unit 131 outputs the first default value signal; when the first reset signal is in the normal operating state, the first selection unit 131 outputs the first original signal.

[0043] It should be noted that the first synchronization unit 132 is driven by the second reset signal and performs multi-level register synchronization on the first intermediate signal. Multi-level register synchronization utilizes multiple registers to sequentially register the signal, making the signal more stable and synchronized in time. When the second functional unit 120 is reset, the first synchronization unit 132 will also be reset, ensuring that the signal can be accurately synchronized after the reset, thereby avoiding timing problems caused by signal jumps.

[0044] In some embodiments, the first synchronization unit 132 includes a plurality of D flip-flops; wherein each D flip-flop includes a reset terminal and a clock terminal; the clock terminal of each D flip-flop is used to receive a clock signal output by the second functional unit 120; and the reset terminal of each D flip-flop is used to receive a second reset signal output by the second functional unit 120.

[0045] The first synchronization unit 132 consists of multiple D flip-flops. A D flip-flop is a sequential logic circuit element that has the function of storing and transmitting signals. In this asynchronous reset circuit, multiple D flip-flops are cascaded to form a multi-level register synchronization structure for processing the first intermediate signal.

[0046] The clock input (CLK) of each D flip-flop is connected to the clock signal output by the second functional unit 120. The clock signal is the basis for the operation of the sequential circuit, and it determines the state update time of the D flip-flop. At the rising edge (or falling edge) of the clock signal, the D flip-flop transmits the signal at its input (D) to its output (Q), thereby realizing signal registration and transmission.

[0047] The reset terminal of each D flip-flop is connected to the second reset signal output by the second functional unit 120. The second reset signal is an asynchronous signal. When this signal is valid, for example, when it is low, the D flip-flop will be forced to reset to a preset initial state regardless of the state of the clock signal.

[0048] When the first intermediate signal is input to the first synchronization unit 132, it passes through multiple D flip-flops sequentially. In each clock cycle, the D flip-flops process the input signal according to the current clock signal and reset signal state. If the second reset signal is valid, the D flip-flops are reset; if the second reset signal is invalid, the D flip-flops transmit the input signal to the output at the valid edge of the clock signal. After processing by multiple D flip-flops, the output signal is the synchronized first target signal, which is then sent to the second functional unit 120.

[0049] In this embodiment, the characteristics of D flip-flops are used to solve the signal synchronization problem during asynchronous reset. Multiple cascaded D flip-flops are used to perform multi-stage registration synchronization of the input signal. Each stage of the D flip-flop samples and registers the input signal once. After multi-stage processing, the probability of metastability of the signal is greatly reduced. Simultaneously, since all D flip-flops are driven by the clock signal of the second functional unit 120, their state updates are synchronized, thus ensuring that the output first target signal is synchronized with the clock signal of the second functional unit 120, avoiding timing problems.

[0050] In some embodiments, the plurality of D flip-flops include a first D flip-flop, a second D flip-flop, and a third D flip-flop connected in series; wherein the input of the first D flip-flop is connected to the output of the first selection unit 131, the input of the second D flip-flop is connected to the output of the first D flip-flop, the input of the third D flip-flop is connected to the output of the second D flip-flop, and the output of the third D flip-flop is connected to the second functional unit 120.

[0051] This embodiment further illustrates that the first synchronization unit 132 can be composed of three D flip-flops connected in series. This series connection method forms a three-stage signal synchronization chain.

[0052] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of the first synchronization unit in the asynchronous reset circuit provided in the embodiments of this application.

[0053] The input of the first D flip-flop DFF1 receives a first intermediate signal output from the first selection unit 131. The first selection unit 131 selects from the first original signal and the first default value signal according to the first reset signal and outputs the first intermediate signal. The first D flip-flop DFF1 samples this first intermediate signal at the effective edge of each clock cycle.

[0054] The input of the second D flip-flop DFF2 is connected to the output of the first D flip-flop DFF1, and it resamples the signal output by the first D flip-flop DFF1. The input of the third D flip-flop DFF3 is connected to the output of the second D flip-flop DFF2, and it performs a third sampling on the signal output by the second D flip-flop DFF2. Finally, its output sends the synchronized first target signal to the second functional unit 120.

[0055] The input signal is sampled three times by connecting three D flip-flops in series. Each stage of the D flip-flop can be seen as a further stabilization and synchronization of the output signal of the previous stage, ensuring that the second functional unit 120 can receive and process signals in the correct timing.

[0056] In some embodiments, the asynchronous reset circuit further includes a second signal synchronization module 140 disposed between the first functional unit 110 and the second functional unit 120. The second signal synchronization module 140 includes a second selection unit 141 and a second synchronization unit 142.

[0057] Please see Figure 3 , Figure 3 This is the second schematic diagram of the asynchronous reset circuit provided in the embodiments of this application.

[0058] The second selection unit 141 is used to select one of the second original signal output by the second functional unit 120 and the second default value signal preset by the second functional unit 120 as the second intermediate signal output according to the state of the second reset signal of the second functional unit 120; the second synchronization unit 142 is driven by the first reset signal of the first functional unit 110, and the second synchronization unit 142 is used to perform multi-level register synchronization on the second intermediate signal and output the synchronized second target signal to the first functional unit 110.

[0059] In this embodiment, in addition to the previously mentioned first signal synchronization module 130, a second signal synchronization module 140 is added between the first functional unit 110 and the second functional unit 120. Similar to the function of the first signal synchronization module 130, the function of the second signal synchronization module 140 is to process the signals fed back from the second functional unit 120 to the first functional unit 110, ensuring that the signals can be stably and correctly transmitted bidirectionally between the two functional units in the case of asynchronous reset.

[0060] Optionally, the first input terminal of the second selection unit 141 is used to receive the second original signal output by the second functional unit 120, the second input terminal of the second selection unit 141 is used to receive the second default value signal preset by the second functional unit 120, and the control terminal of the second selection unit 141 is used to receive the second reset signal of the second functional unit 120.

[0061] The input terminal of the second synchronization unit 142 is connected to the output terminal of the second selection unit 141, the output terminal of the second synchronization unit 142 is connected to the first functional unit 110, and the reset terminal of the second synchronization unit 142 is used to receive the first reset signal of the first functional unit 110.

[0062] The working principle and design of the second signal synchronization module 140 can be referred to in the previous description of the first signal synchronization module 130, and will not be repeated here.

[0063] Please see Figure 4 , Figure 4 This is the third schematic diagram of the asynchronous reset circuit provided in the embodiments of this application.

[0064] This embodiment is applicable to situations where interactive functional units are in the same clock domain but different reset domains.

[0065] Suppose there are two functional units within a System-on-a-Chip (SoC): IPa and IPb. These two functional units operate in the same clock domain and have bidirectional signal interaction; that is, IPa outputs signals to IPb, and IPb outputs signals to IPa.

[0066] During system operation, if IPA experiences an asynchronous reset, while other IP units (including IPb) remain in normal operation without resetting, it's important to note that the timing of IPA's asynchronous reset is random and follows no fixed pattern. When IPA performs an asynchronous reset, the signal it outputs to IPb may change, and the timing of this change is also random. Since the D flip-flop inside IPb samples this signal, this random signal change may cause timing issues related to setup time and hold time.

[0067] The above describes the cause of the problem when a specific IP within the SoC is reset independently. When IPA performs an asynchronous reset, the signal it sends to IPb may change at any time, leading to timing issues.

[0068] The solution in this embodiment is to add a logic circuit (i.e., the first signal synchronization module mentioned above) to IPb. This logic circuit first processes the signal transmitted from IPa, and then IPb uses the processed signal. The details are explained below: IPa and IPb use the same clock, therefore they are synchronized and in a synchronized state. Figure 4 In the circuit shown, all logic units use the clock signal.

[0069] The reset signal of IPa is the first reset signal IPa_reset, and IPa internally performs asynchronous reset; the first original signal output by IPa to IPb is Signal_a_to_b, which, after being processed by the logic circuit designed in this embodiment, becomes the first target signal Signal_a_to_b_sync when it reaches IPb; Signal_a_to_b_default is the first default value signal preset by IPa.

[0070] The reset signal for IPb is the second reset signal IPb_reset, and IPb internally performs an asynchronous reset; the second original signal output by IPb to IPa is Signal_b_to_a, which, after being processed by the logic circuit designed in this embodiment, becomes the second target signal Signal_b_to_a_sync when it reaches IPa; Signal_b_to_a_defaul is the second default value signal preset by IPb.

[0071] ①IPa Individual Reset The Signal_a_to_b signal transmitted from IPa to IPB first passes through a multiplexer, the Mux. This Mux uses IPa_reset as its selection control signal; assuming IPa_reset is 0 representing a reset state and 1 representing a de-reset state, when IPa_reset is 0, the Mux will output the Signal_a_to_b_default signal; when IPa_reset is 1, the Mux will output the Signal_a_to_b signal.

[0072] The signal output by the Mux is processed through D flip-flops for multiple cycles, and the specific number of cycles can be flexibly selected according to actual needs. In most cases, three cycles are usually sufficient. If the chip uses a more advanced process, the number of D flip-flops can be increased appropriately. It should be emphasized that the D flip-flops used for the pausing operation in this embodiment must use the IPb reset signal IPb_reset, that is, the RST terminal of the D flip-flop is connected to the IPb reset signal IPb_reset.

[0073] When IPa is reset during operation, while IPb is still in the de-reset state, the value of the Mux output signal will switch from Signal_a_to_b to Signal_a_to_b_default. During this process, the signal may jump near the rising edge of the clock of the first-stage D flip-flop (DFF), causing timing issues related to setup and hold times in the first-stage DFF. However, after three stages of such DFF processing, the final output signal Signal_a_to_b_sync is a stable value that can be correctly used by the internal circuitry of IPb.

[0074] It should be noted that this embodiment only describes the case where there is only one signal from IPa to IPb. When there are multiple signals output from IPa to IPb, the same processing method described above can be applied to each signal.

[0075] ②IPb separate reset The signal Signal_b_to_a transmitted from IPb to IPa first passes through a multiplexer (Mux). This Mux uses IPb_reset as its selection control signal; assuming IPb_reset is 0 representing a reset state and 1 representing a de-reset state, when IPb_reset is 0, the Mux will output the Signal_b_to_a_default signal; when IPb_reset is 1, the Mux will output the Signal_b_to_a signal.

[0076] Similar to the IPa individual reset method described above, the Mux output signal is also processed through a D flip-flop for multiple steps. The specific number of steps can be flexibly selected according to actual needs. It is particularly important to note that when IPb is reset individually, the D flip-flop used for synchronous stepping must be reset using the IPa reset signal IPa_reset, that is, the RST terminal of the D flip-flop is connected to the IPa reset signal IPa_reset.

[0077] When IPb is reset during operation, while IPa remains in the de-reset state, the value of the Mux output signal will switch from Signal_b_to_a to Signal_b_to_a_default. During this process, the signal may jump near the rising edge of the clock of the first-stage D flip-flop (DFF), causing timing issues related to setup and hold times in the first-stage DFF. However, after three stages of such DFF processing, the final output signal Signal_b_to_a_sync is a stable value that can be correctly used by the internal circuitry of IPa.

[0078] It should be noted that this embodiment only describes the case where there is only one signal from IPb to IPa. When there are multiple signals output from IPb to IPa, the same processing method described above can be applied to each signal.

[0079] To further improve signal processing performance, this embodiment also requires that the physical distance between each D flip-flop (DFF) stage be minimized during actual physical layout. This helps reduce signal transmission delay and interference, thereby enhancing signal stability and reliability.

[0080] The above embodiment only illustrates the scenario of signal interaction between two IPs. However, the solution proposed in this embodiment is also applicable when there is signal interaction between multiple IPs.

[0081] This embodiment is simple to implement, requiring only the addition of basic logic units such as multiplexers and D flip-flops to the existing circuit design, along with proper configuration of the reset and selection signals. This simple design ensures that when an IP performs an asynchronous reset operation in the SoC, random signal transitions will not cause timing issues for adjacent IPs, thus significantly improving the stability and reliability of the entire system.

[0082] This application also provides an asynchronous reset method using the asynchronous reset circuit described above. Please refer to... Figure 5 , Figure 5 This is a flowchart illustrating the asynchronous reset method provided in an embodiment of this application. In this embodiment, the asynchronous reset method may include steps S510 to S540, each step of which is as follows: S510: Receives the first reset signal output by the first functional unit.

[0083] S520: Based on the state of the first reset signal, select one of the first original signal output by the first functional unit and the first default value signal preset by the first functional unit as the first intermediate signal.

[0084] S530: Driven by the second reset signal of the second functional unit, the first intermediate signal is synchronized through multi-level registers.

[0085] S540: Outputs the synchronized first target signal to the second functional unit.

[0086] The asynchronous reset method of this application is used to solve timing problems that may occur due to asynchronous reset when signals interact between a first functional unit and a second functional unit. Specifically, the solution involves processing the signals output from the first functional unit to the second functional unit so that the signals can be used stably and reliably in the second functional unit.

[0087] In a System-on-a-Chip (SoC), when the first functional unit undergoes an asynchronous reset, its output signal may change at any time, which could cause timing issues for the second functional unit. This embodiment uses multi-level register synchronization to stabilize the signal output to the second functional unit, ensuring that the signal can be correctly received and processed by the second functional unit.

[0088] Optionally, the number of registers in a multi-level register can be adjusted according to actual needs, and it has good adaptability to different chip processes and application scenarios.

[0089] In some embodiments, the step of selecting one of the first original signal output by the first functional unit and the first default value signal preset by the first functional unit as the first intermediate signal according to the state of the first reset signal may specifically include: When the first functional unit is determined to be in a reset state based on the first reset signal, the first default value signal is selected as the first intermediate signal output; when the first functional unit is determined to be in a de-reset state based on the first reset signal, the first original signal is selected as the first intermediate signal output.

[0090] This embodiment is a refinement of step S520 above, detailing how to select the first intermediate signal based on the state of the first reset signal: When the first functional unit is determined to be in a reset state by the first reset signal, the first default value signal is selected as the first intermediate signal for output; when the first functional unit is determined to be in a de-reset state, i.e., a normal working state, by the first reset signal, the first original signal is selected as the first intermediate signal for output.

[0091] This embodiment selects appropriate signals in both reset and normal operation states, further improving the stability of signals transmitted to the second functional unit. Especially in the reset state, it avoids potential malfunctions of the second functional unit caused by abnormal signals, making the entire system more reliable during the reset process. Furthermore, in conjunction with the multi-level register synchronization operation in subsequent steps, it can better achieve stable signal transmission. Because the input signal is ensured to be appropriate and stable before entering the synchronization operation, the effectiveness of the synchronization operation is further improved, reducing the probability of timing problems.

[0092] This application also provides a system-on-a-chip including the asynchronous reset circuit described above.

[0093] A system-on-a-chip (SoC) is a complex system that integrates multiple functional modules onto a single chip, enabling it to perform complete system functions. The SoC in this embodiment includes the asynchronous reset circuit described above, which provides crucial assurance for the stable operation of the entire system.

[0094] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0095] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An asynchronous reset circuit, characterized in that, It includes a first functional unit, a second functional unit, and a first signal synchronization module disposed between the first functional unit and the second functional unit. The first signal synchronization module includes a first selection unit and a first synchronization unit. The first functional unit and the second functional unit are in the same clock domain. The first selection unit is used to select one of the first original signal output by the first functional unit and the first default value signal preset by the first functional unit as the first intermediate signal output, based on the state of the first reset signal of the first functional unit. The first synchronization unit is driven by the second reset signal of the second functional unit. The first synchronization unit is used to perform multi-level register synchronization on the first intermediate signal and output the synchronized first target signal to the second functional unit. The first reset signal and the second reset signal are both asynchronous reset signals.

2. The asynchronous reset circuit according to claim 1, characterized in that, The first input terminal of the first selection unit is used to receive the first original signal output by the first functional unit, the second input terminal of the first selection unit is used to receive the first default value signal preset by the first functional unit, and the control terminal of the first selection unit is used to receive the first reset signal of the first functional unit. The input terminal of the first synchronization unit is connected to the output terminal of the first selection unit, the output terminal of the first synchronization unit is connected to the second functional unit, and the reset terminal of the first synchronization unit is used to receive the second reset signal of the second functional unit.

3. The asynchronous reset circuit according to claim 1, characterized in that, The first selection unit is used for: When it is determined that the first functional unit is in a reset state based on the first reset signal, the first default value signal is selected as the first intermediate signal output. If the first functional unit is determined to be in a de-reset state based on the first reset signal, the first original signal is selected as the first intermediate signal output.

4. The asynchronous reset circuit according to claim 1, characterized in that, The first synchronization unit includes multiple D flip-flops; Each D flip-flop includes a reset terminal and a clock terminal; the clock terminal of each D flip-flop is used to receive the clock signal output by the second functional unit; the reset terminal of each D flip-flop is used to receive the second reset signal output by the second functional unit.

5. The asynchronous reset circuit according to claim 4, characterized in that, The plurality of D flip-flops includes a first D flip-flop, a second D flip-flop, and a third D flip-flop connected in series; The input of the first D flip-flop is connected to the output of the first selection unit, the input of the second D flip-flop is connected to the output of the first D flip-flop, the input of the third D flip-flop is connected to the output of the second D flip-flop, and the output of the third D flip-flop is connected to the second functional unit.

6. The asynchronous reset circuit according to claim 1, characterized in that, The asynchronous reset circuit further includes a second signal synchronization module disposed between the first functional unit and the second functional unit. The second signal synchronization module includes a second selection unit and a second synchronization unit. The second selection unit is used to select one of the second original signal output by the second functional unit and the second default value signal preset by the second functional unit as the second intermediate signal output, based on the state of the second reset signal of the second functional unit. The second synchronization unit is driven by the first reset signal of the first functional unit. The second synchronization unit is used to perform multi-level register synchronization on the second intermediate signal and output the synchronized second target signal to the first functional unit.

7. The asynchronous reset circuit according to claim 6, characterized in that, The first input terminal of the second selection unit is used to receive the second original signal output by the second functional unit, the second input terminal of the second selection unit is used to receive the second default value signal preset by the second functional unit, and the control terminal of the second selection unit is used to receive the second reset signal of the second functional unit. The input terminal of the second synchronization unit is connected to the output terminal of the second selection unit, the output terminal of the second synchronization unit is connected to the first functional unit, and the reset terminal of the second synchronization unit is used to receive the first reset signal of the first functional unit.

8. An asynchronous reset method, characterized in that, Using the asynchronous reset circuit as described in any one of claims 1 to 7, the asynchronous reset method includes: Receive the first reset signal output by the first functional unit; Based on the state of the first reset signal, one of the first original signal output by the first functional unit and the first default value signal preset by the first functional unit is selected as the first intermediate signal; Driven by the second reset signal of the second functional unit, the first intermediate signal is synchronized through multi-level registers. The synchronized first target signal is output to the second functional unit.

9. The asynchronous reset method according to claim 8, characterized in that, The step of selecting one of the first original signal output by the first functional unit and the first default value signal preset by the first functional unit as the first intermediate signal according to the state of the first reset signal includes: When the first functional unit is determined to be in a reset state based on the first reset signal, the first default value signal is selected as the first intermediate signal output. When the first functional unit is determined to be in a de-reset state based on the first reset signal, the first original signal is selected as the first intermediate signal output.

10. A system-on-a-chip, characterized in that, Includes the asynchronous reset circuit as described in any one of claims 1 to 7.

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