A one-bit full adder circuit with storage and calculation function

Abstract

This invention discloses a one-bit full adder circuit with in-memory computation functionality, comprising a summation module and a carry calculation module with independent structures. Each module includes a storage pair and a logic network. The storage pair consists of two ferroelectric transistors with complementary resistance states, used to non-volatilely store an addend and its logical inverse. The logic network receives the first addend, the carry input, and its logical inverse, and its two pull-down nodes are connected to ground via ferroelectric transistors. By directly connecting the storage cells in series in the pull-down path of the logic network, this circuit allows the stored resistance states to directly participate in and control the logic operations, achieving physical in-memory computation integration. This circuit completely abandons the complex complementary logic gate structure composed of a large number of PMOS and NMOS transistors in traditional full adders. The core calculation uses only NMOS transistors and ferroelectric transistors, resulting in a smaller total number of transistors, simplified interconnection, and reduced overall circuit area and complexity.

Description

Technical Field

[0001] This invention relates to a circuit design technique for basic arithmetic units in digital logic circuits, and more particularly to a one-bit full adder circuit with stored-value arithmetic function. Background Technology

[0002] With the development of computationally intensive applications such as artificial intelligence, the demand for computing power has surged. In the traditional von Neumann architecture, the processor and memory are separated, leading to frequent data movement during computation. This causes the "memory wall" and "power wall" problems, severely restricting the improvement of computing power. In-memory computing technology, by performing computation directly within memory, effectively avoids data movement and has become a key direction for overcoming the above bottlenecks.

[0003] A single-bit full adder is a fundamental arithmetic unit, and realizing its in-memory computing functionality is of great significance. Ferroelectric transistors combine non-volatile storage with high-speed switching characteristics and are compatible with traditional CMOS processes, providing ideal device support for in-memory computing circuits.

[0004] However, existing full adder circuits, whether traditional CMOS implementations or proposed in-memory computing solutions, generally suffer from complex circuit structures. For example, a typical traditional static CMOS full adder requires multiple XOR gates, XNOR gates, and transmission gates cascaded together to achieve summation and carry functions. It contains a large number of transistors, especially a considerable number of large-area PMOS transistors to form complementary logic networks, resulting in a large overall circuit area, complex interconnections, and difficulties in integration and performance optimization.

[0005] Although in-memory computing full adders based on ferroelectric transistors have been proposed, their circuit structures are still not simple enough. Some schemes have too many transistors, while others introduce additional timing control logic, failing to fundamentally simplify the circuit structure.

[0006] Therefore, it is essential to provide a one-bit full adder circuit that has a simple circuit structure, a small number of transistors, low interconnection complexity, and can efficiently realize in-memory computing functionality. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a one-bit full adder circuit with in-memory computing function, which has a simple circuit structure, a small number of transistors, and low interconnection complexity.

[0008] The technical solution adopted by the present invention to solve the above-mentioned technical problems is: a one-bit full adder circuit with storage and calculation function, including a summation calculation module and a carry calculation module with independent structures; The summation calculation module includes: The first storage pair consists of a first ferroelectric transistor and a second ferroelectric transistor, which have opposite resistance states and respectively store the second addend and its logical inverse in a non-volatile manner. The first logic network is composed of multiple interconnected NMOS transistors; its input terminal receives a first addend and its logical inverse, a carry input and its logical inverse; it has two pull-down nodes, which are respectively connected to the ground terminal through the first ferroelectric transistor and the second ferroelectric transistor. The first logical network works in conjunction with the first storage pair to implement the summation logic function and generate a summation signal; The carry calculation module includes: The second storage pair consists of a third ferroelectric transistor and a fourth ferroelectric transistor, which have opposite resistance states and non-volatilely store the second addend and its logical inverse value, respectively. The second logic network is composed of multiple interconnected NMOS transistors; its input terminal receives the first addend and its logical inverse value, and the carry input; it has two pull-down nodes, which are connected to the ground terminal through the third ferroelectric transistor and the fourth ferroelectric transistor, respectively. The second logic network works in conjunction with the second storage pair to implement carry logic functions and generate carry signals.

[0009] The summation calculation module further includes a first inverter, the input of which is connected to the output node of the first logic network, and the output of which outputs the summation signal. The carry calculation module also includes a second inverter, the input of which is connected to the output node of the second logic network, and the output of which outputs the carry signal.

[0010] The summation calculation module further includes a first pull-up element, which is connected between the power input terminal and the output node of the first logic network; The carry calculation module also includes a second pull-up element, which is connected between the power input terminal and the output node of the second logic network.

[0011] The first pull-up element is a first PMOS transistor, whose source is connected to the power input terminal, its gate is connected to the ground terminal, and its drain is connected to the output node of the first logic network. The second pull-up element is a second PMOS transistor, whose source is connected to the power input terminal, its gate is connected to the ground terminal, and its drain is connected to the output node of the second logic network.

[0012] The gates of the first ferroelectric transistor and the third ferroelectric transistor are both connected to the first control terminal, and the gates of the second ferroelectric transistor and the fourth ferroelectric transistor are both connected to the second control terminal. The signal received by the second control terminal is the inverse of the signal received by the first control terminal.

[0013] The first control terminal and the second control terminal are used for: During the writing phase, a write voltage with opposite polarity and an absolute value greater than the polarization reversal threshold voltage of the ferroelectric transistor is received, thereby writing the first ferroelectric transistor and the third ferroelectric transistor into a first resistance state, and writing the second ferroelectric transistor and the fourth ferroelectric transistor into a second resistance state opposite to the first resistance state. During the reading phase, a reading voltage with an absolute value less than the polarization reversal threshold voltage is received, enabling the first logic network to perform summation logic based on the first resistance state of the first ferroelectric transistor and the second resistance state of the second ferroelectric transistor; similarly, enabling the second logic network to perform carry logic based on the first resistance state of the third ferroelectric transistor and the second resistance state of the fourth ferroelectric transistor.

[0014] The first logic network interconnects six NMOS transistors, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the second logic network interconnects four NMOS transistors, including a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor.

[0015] The interconnection relationship of the six NMOS transistors in the first logic network is as follows: The gate of the first NMOS transistor receives the first addend, and its source is connected to the drain of the third NMOS transistor and the fourth NMOS transistor. The gate of the second NMOS transistor receives the logical inverse of the first addend, and its source is connected to the drain of the fifth NMOS transistor and the sixth NMOS transistor. The drain of the first NMOS transistor is connected to the drain of the second NMOS transistor, serving as the output node of the first logic network; The gates of the third NMOS transistor and the sixth NMOS transistor both receive the carry input, and the gates of the fourth NMOS transistor and the fifth NMOS transistor both receive the logic inverse of the carry input; The source of the third NMOS transistor is connected to the source of the fifth NMOS transistor, serving as a pull-down node of the first logic network, and is also connected to the drain of the first ferroelectric transistor. The source of the fourth NMOS transistor is connected to the source of the sixth NMOS transistor, serving as another pull-down node of the first logic network, and is also connected to the drain of the second ferroelectric transistor.

[0016] The interconnection relationship of the four NMOS transistors in the second logic network is as follows: The gate of the seventh NMOS transistor receives the carry input, and its source is connected to the drain of the ninth NMOS transistor and the tenth NMOS transistor. The gate of the eighth NMOS transistor receives the first addend; The drain of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, serving as the output node of the second logic network; The gate of the ninth NMOS transistor receives the logical inverse of the first addend, and the gate of the tenth NMOS transistor receives the first addend; The source of the eighth NMOS transistor is connected to the source of the ninth NMOS transistor, serving as a pull-down node of the second logic network, and is also connected to the drain of the third ferroelectric transistor. The source of the tenth NMOS transistor serves as another pull-down node of the second logic network and is connected to the drain of the fourth ferroelectric transistor.

[0017] Compared with the prior art, the advantages of the present invention are as follows: 1) This application proposes a novel architecture consisting of structurally independent summation and carry calculation modules. The core of each module is a logic network entirely composed of interconnected NMOS transistors and a storage pair consisting of only two ferroelectric transistors with complementary resistance states. This logic network has two pull-down nodes, each directly connected to ground via a ferroelectric transistor. This architecture eliminates the need for large PMOS and NMOS transistors to construct complex complementary logic gates (such as XOR and XNOR gates) in traditional CMOS full adders, fundamentally eliminating the requirement for large-area PMOS transistors in the core calculation path. Simultaneously, by directly connecting the ferroelectric transistors in series at the end of the pull-down path, the stored data (represented by resistance states) becomes the direct physical condition determining the circuit's logic output, achieving physical integration of storage and computation. This architecture has a small total number of transistors, clear and simple interconnections, significantly reducing circuit area and facilitating layout design and performance optimization.

[0018] 2) To achieve full functionality, this application adds necessary peripheral circuitry and streamlines it to the extreme. First, a PMOS transistor, always on and with its gate grounded, provides a pull-up resistor for the circuit, serving only as a fixed pull-up resistor and not participating in any logic operations. Compared to the large number of PMOS transistors used to construct logic gates in traditional schemes, this application reduces the number of PMOS transistors to a minimum (only 2), further maximizing the area advantage. Second, an inverter inverts and buffers the logic result, outputting a standard logic level signal, ensuring compatibility with subsequent circuits. The entire peripheral circuit design is simple and free of redundancy.

[0019] 3) This application uses a pair of complementary control terminals to uniformly control the gates of all ferroelectric transistors. During the write phase, applying a complementary voltage pulse exceeding the switching threshold of the ferroelectric transistors sets both pairs of ferroelectric transistors to complementary resistance states representing data "0" and "1" in one go. During the read phase, applying the same read voltage below the threshold causes the circuit to perform calculations based on the stored resistance states and the input signal. This control method eliminates the need for complex independent addressing, timing generation, or clock signals, enabling simple and reliable writing and retrieval of non-volatile stored data.

[0020] In summary, this application achieves comprehensive optimization in terms of circuit structure, transistor count, chip area, and control complexity by combining storage pairs with a pure NMOS logic network, while simultaneously realizing non-volatile in-memory computing functionality. This provides an excellent basic computing unit for building high-efficiency in-memory computing systems. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of the summation calculation module in the one-bit full adder circuit of the present invention; Figure 2 This is a circuit diagram of the carry calculation module in the one-bit full adder circuit of the present invention; Figure 3 This is a schematic diagram of the simulation results of the one-bit full adder circuit of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the examples of the present invention.

[0023] Let A and B be the two addends of a one-bit full adder, C i S0 is the carry input of a one-bit full adder, S1 is the summation output, and C is the carry input. out For carry-out output, then S0 and C out The logical expressions are as follows: , From the logical expression of S0, we know that when A, B, C... i S0 is 1 if one or all three inputs are 1; otherwise, S0 is 0. From C... out From the logical expression, we can see that when A, B, C i If there are two or more inputs with a value of 1, then C out If it is 1, otherwise C out It is 0.

[0024] This invention proposes a one-bit full adder circuit with stored computation function, which includes a summation calculation module 1 and a carry calculation module 2 with independent structures.

[0025] like Figure 1 As shown, the summation calculation module 1 includes: a first storage pair 11, composed of a first ferroelectric transistor F1 and a second ferroelectric transistor F2, with opposite resistance states, and non-volatilely storing the second addend B and its logical inverse B~; and a first logic network 12, composed of multiple interconnected NMOS transistors, whose input terminal receives the first addend A and its logical inverse A~, and the carry input C. i and its logical inverse C i ~, which has two pull-down nodes, connected to the ground terminal GND through the first ferroelectric transistor F1 and the second ferroelectric transistor F2 respectively; the first logic network 12 works in conjunction with the first storage pair 11 to realize the summation logic function and generate the summation signal S0.

[0026] like Figure 2 As shown, the carry calculation module 2 includes: a second storage pair 21, composed of a third ferroelectric transistor F3 and a fourth ferroelectric transistor F4, with opposite resistance states, and non-volatilely storing the second addend B and its logical inverse B~; and a second logic network 22, composed of multiple interconnected NMOS transistors, whose input terminal receives the first addend A and its logical inverse A~, and the carry input C. i It has two pull-down nodes, which are connected to the ground terminal GND through the third ferroelectric transistor F3 and the fourth ferroelectric transistor F4, respectively; the second logic network 22 works in conjunction with the second memory pair 21 to realize the carry logic function and generate the carry signal C. out .

[0027] In all embodiments, such as Figure 1 As shown, the summation calculation module 1 also includes a first inverter INV1. The input of the first inverter INV1 is connected to the output node of the first logic network 12, and the output of the first inverter INV1 is a summation signal S0. Figure 2 As shown, the carry calculation module 2 also includes a second inverter INV2. The input of the second inverter INV2 is connected to the output node of the second logic network 22, and the output of the second inverter INV2 is the carry signal C. out .

[0028] In all embodiments, such as Figure 1 As shown, the summation calculation module 1 also includes a first pull-up element, which is connected between the power input terminal Vdd and the output node of the first logic network 12; as Figure 2 As shown, the carry calculation module 2 also includes a second pull-up element, which is connected between the power input terminal Vdd and the output node of the second logic network 22.

[0029] In all embodiments, such as Figure 1 As shown, the first pull-up element is the first PMOS transistor P1, whose source is connected to the power input terminal Vdd, its gate is connected to the ground terminal GND, and its drain is connected to the output node of the first logic network 12; as Figure 2 As shown, the second pull-up element is the second PMOS transistor P2, whose source is connected to the power input terminal Vdd, its gate is connected to the ground terminal GND, and its drain is connected to the output node of the second logic network 22.

[0030] In all embodiments, such as Figure 1 and Figure 2 As shown, the gates of the first ferroelectric transistor F1 and the third ferroelectric transistor F3 are both connected to the first control terminal W, and the gates of the second ferroelectric transistor F2 and the fourth ferroelectric transistor F4 are both connected to the second control terminal W~. The signal received by the second control terminal W~ is the inverse of the signal received by the first control terminal W. The sources of the first ferroelectric transistor F1, the second ferroelectric transistor F2, the third ferroelectric transistor F3, and the fourth ferroelectric transistor F4 are all connected to the ground terminal GND. The drains of the first ferroelectric transistor F1 and the second ferroelectric transistor F2 are respectively connected to the two pull-down nodes of the first logic network 12, and the drains of the third ferroelectric transistor F3 and the fourth ferroelectric transistor F4 are respectively connected to the two pull-down nodes of the second logic network 22.

[0031] In all embodiments, the first control terminal W and the second control terminal W' are used to: during the write phase, receive a write voltage with opposite polarity and an absolute value greater than the polarization reversal threshold voltage of the ferroelectric transistor, thereby writing the first ferroelectric transistor F1 and the third ferroelectric transistor F3 into a first resistance state, and writing the second ferroelectric transistor F2 and the fourth ferroelectric transistor F4 into a second resistance state opposite to the first resistance state. During the read phase, receive a read voltage with an absolute value less than the polarization reversal threshold voltage, causing the first logic network 12 to implement summation logic based on the first resistance state of the first ferroelectric transistor F1 and the second resistance state of the second ferroelectric transistor F2; similarly, causing the second logic network 22 to implement carry logic based on the first resistance state of the third ferroelectric transistor F3 and the second resistance state of the fourth ferroelectric transistor F4. Here, the first resistance state is a high resistance state and the second resistance state is a low resistance state; or the first resistance state is a low resistance state and the second resistance state is a high resistance state.

[0032] In this embodiment of the invention, the first addend A and the carry input C i The input is directly from the outside, while the second addend B is represented by applying appropriate voltages to the gate and source of the ferroelectric transistor, causing the ferroelectric transistor to be in a low-resistance or high-resistance state. When the gate and source voltage bias is positive and greater than a certain value, it is written as a low-resistance state; otherwise, it is written as a high-resistance state. Since the ferroelectric transistor can store the written resistance state, the value of the second addend B is registered in the ferroelectric transistor and participates in the addition operation. Therefore, the one-bit full adder of this invention has storage and calculation capabilities.

[0033] In this embodiment of the invention, in the summation calculation module 1, when the first ferroelectric transistor F1 is written to a high-resistance state and the second ferroelectric transistor F2 is written to a low-resistance state, the second addend B is logic 0; otherwise, the second addend B is logic 1. Similarly, in the carry calculation module 2, when the third ferroelectric transistor F3 is written to a high-resistance state and the fourth ferroelectric transistor F4 is written to a low-resistance state, the second addend B is logic 0; otherwise, the second addend B is logic 1.

[0034] In all embodiments, such as Figure 1 As shown, the first logic network 12 interconnects six NMOS transistors, including a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6; as shown... Figure 2 As shown, the number of interconnected NMOS transistors in the second logic network 22 is four, including the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, and the tenth NMOS transistor N10.

[0035] In all embodiments, such as Figure 1As shown, the interconnection relationship of the six NMOS transistors in the first logic network 12 is as follows: the gate of the first NMOS transistor N1 receives the first addend A, and its source is connected to the drains of the third NMOS transistor N3 and the fourth NMOS transistor N4; the gate of the second NMOS transistor N2 receives the logical inverse A~ of the first addend A, and its source is connected to the drains of the fifth NMOS transistor N5 and the sixth NMOS transistor N6; the drains of the first NMOS transistor N1 and the second NMOS transistor N2 are connected, serving as the output node of the first logic network 12, and are connected to the input of the first inverter INV1 and the drain of the first PMOS transistor P1; the gates of the third NMOS transistor N3 and the sixth NMOS transistor N6 both receive the carry input C. i The gates of both the fourth NMOS transistor N4 and the fifth NMOS transistor N5 receive the carry input C. i The logical inverse C i ~; The source of the third NMOS transistor N3 is connected to the source of the fifth NMOS transistor N5, serving as a pull-down node of the first logic network 12, and is connected to the drain of the first ferroelectric transistor F1; The source of the fourth NMOS transistor N4 is connected to the source of the sixth NMOS transistor N6, serving as another pull-down node of the first logic network 12, and is connected to the drain of the second ferroelectric transistor F2.

[0036] In all embodiments, such as Figure 2 As shown, the interconnection relationship of the four NMOS transistors in the second logic network 22 is as follows: the gate of the seventh NMOS transistor N7 receives the carry input C. i The source of the NMOS transistor N7 is connected to the drain of the N9th NMOS transistor N9 and the N10th NMOS transistor N10; the gate of the N8th NMOS transistor N8 receives the first addend A; the drain of the N7th NMOS transistor N7 is connected to the drain of the N8th NMOS transistor N8, serving as the output node of the second logic network 22, and is connected to the input of the second inverter INV2 and the drain of the second PMOS transistor P2; the gate of the N9th NMOS transistor N9 receives the logical inverse value A~ of the first addend A, and the gate of the N10th NMOS transistor N10 receives the first addend A; the source of the N8th NMOS transistor N8 is connected to the source of the N9th NMOS transistor N9, serving as a pull-down node of the second logic network 22, and is connected to the drain of the third ferroelectric transistor F3; the source of the N10th NMOS transistor N10 serves as another pull-down node of the second logic network 22, and is connected to the drain of the fourth ferroelectric transistor F4.

[0037] In all embodiments, the substrates of all ferroelectric transistors and NMOS transistors are connected to the ground terminal GND, and the substrates of all PMOS transistors are connected to the power input terminal Vdd.

[0038] All of the above ferroelectric transistors are of the n-type type.

[0039] Figure 3 This is a schematic diagram of the simulation results of a one-bit full adder circuit according to an embodiment of the present invention. Figure 3 In the circuit, the power input terminal Vdd is connected to a high level of 2V, and the ground terminal GND is connected to a low level of 0V. The gates of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the ground terminal GND, making them in the conducting state and acting as resistors in the circuit. The write voltage of each ferroelectric transistor is ±5V, and the read voltage is 0.7V.

[0040] Figure 3 During the time interval from zero to T1, a low level of -5V is applied to the first control terminal W, and a high level of 5V is applied to the second control terminal W. Since the sources of the first ferroelectric transistor F1, the second ferroelectric transistor F2, the third ferroelectric transistor F3, and the fourth ferroelectric transistor F4 are connected to the ground terminal GND, the first ferroelectric transistor F1 and the third ferroelectric transistor F3 are written to a high-impedance state, and the second ferroelectric transistor F2 and the fourth ferroelectric transistor F4 are written to a low-impedance state. The corresponding second addend B is logic 0 and is stored in the first ferroelectric transistor F1 and the third ferroelectric transistor F3.

[0041] Between time T1 and T2, a read voltage of 0.7V is applied to the first control terminal W and the second control terminal W~; 0V is applied to the receiving terminal of the first addend A, and 2V is applied to the receiving terminal of the logic inverse of the first addend A~, corresponding to the first addend A being logic 0, and the carry input C... i Apply 0V to the receiving end, and input C at the carry input. i The logical inverse C i Apply 2V to the receiving end of ~, corresponding to the carry input C i This is a logic 0, used to test the case where all input signals of a one-bit full adder are logic 0. In this case, S0 is 0V, corresponding to logic 0, and C... out 0V corresponds to logic 0.

[0042] Between time T2 and T3, a read voltage of 0.7V is applied to W and W~; 0V is applied to the receiving terminal of A, and 2V is applied to the receiving terminal of A~, corresponding to logic 0 for A, and C... i Apply 2V to the receiving end of Ci~, and apply 0V to the receiving end of Ci~, corresponding to the carry input C. i A logic 1, used to test if only C is present in the input signal of a one-bit full adder. i In the case of logic 1, S0 is 2V, corresponding to logic 1, C out 0V corresponds to logic 0.

[0043] Between time T3 and T4, a read voltage of 0.7V is applied to W and W~; 2V is applied to the receiver of A, and 0V is applied to the receiver of A~, corresponding to logic 1 for A, and C... i Apply 0V to the receiving end, at C i Apply 2V to the receiving end of ~, corresponding to C i The value is 0, used to test the case where only A is a logic 1 in the input signal of a one-bit full adder. In this case, S0 is 2V, corresponding to logic 1, and C... out 0V corresponds to logic 0.

[0044] Between time T4 and T5, a read voltage of 0.7V is applied to W and W~; 2V is applied to the receiver of A, and 0V is applied to the receiver of A~, corresponding to logic 1 for A, and C... i Apply 2V to the receiving end, at C i Applying 0V to the receiving end of ~ corresponds to C i This is a logic 1, used to test the case where only B is a logic 0 in the input signal of a one-bit full adder. In this case, S0 is 0V, corresponding to logic 0, and C... out It is 2V, corresponding to logic 1.

[0045] Between time T5 and T6, initialization is performed by applying a high level of 5V at W and a low level of -5V at W. Since the sources of the first ferroelectric transistor F1, the second ferroelectric transistor F2, the third ferroelectric transistor F3, and the fourth ferroelectric transistor F4 are connected to the ground terminal GND, the first ferroelectric transistor F1 and the third ferroelectric transistor F3 are written to a low-impedance state, and the second ferroelectric transistor F2 and the fourth ferroelectric transistor F4 are written to a high-impedance state, corresponding to logic 1 at B, and stored in the first ferroelectric transistor F1 and the third ferroelectric transistor F3.

[0046] Between time T6 and T7, a read voltage of 0.7V is applied to W and W~; 0V is applied to the receiving terminal of A, and 2V is applied to the receiving terminal of A~, corresponding to logic 0 for A, and C... i Apply 0V to the receiving end, at C i Apply 2V to the receiving end of ~, corresponding to C i The value is 0. This is used to test the case where only B is a logic 1 in the input signals of a one-bit full adder. In this case, S0 is 2V, corresponding to logic 1, and C... out 0V corresponds to logic 0.

[0047] Between time T7 and T8, a read voltage of 0.7V is applied to W and W~; 0V is applied to the receiving terminal of A, and 2V is applied to the receiving terminal of A~, corresponding to logic 0 for A, and C... i Apply 2V to the receiving end, at C i Applying 0V to the receiving end of ~ corresponds to C iThis is a logic 1, used to test the case where only A is a logic 0 in the input signals of a one-bit full adder. In this case, S0 is 0V, corresponding to logic 0, and C... out It is 2V, corresponding to logic 1.

[0048] Between time T8 and T9, a read voltage of 0.7V is applied to W and W~; 2V is applied to the receiver of A, and 0V is applied to the receiver of A~, corresponding to logic 1 for A, and C... i Apply 0V to the receiving end, at C i Apply 2V to the receiving end of ~, corresponding to C i A logic 0 is used to test if only C is present in the input signal of a one-bit full adder. i In the case of logic 0, S0 is 0V, corresponding to logic 0, C out It is 2V, corresponding to logic 1.

[0049] Between time T9 and T10, a read voltage of 0.7V is applied to W and W~; 2V is applied to the receiving terminal of A, and 0V is applied to the receiving terminal of A~, corresponding to logic 0 for A. i Apply 2V to the receiving end, at C i The receiving end of ~ is 0V, corresponding to C i This is a logic 1 signal used to test the case where all input signals of a one-bit full adder are logic 1. In this case, S0 is 2V, corresponding to logic 1, and C... out For 2V, the corresponding logic 1.

[0050] The test results above show that the one-bit full adder proposed in this embodiment of the invention functions correctly, indicating that the one-bit full adder is feasible and effective.

Claims

1. A one-bit full adder circuit with stored computation function, characterized in that, It includes a summation calculation module and a carry calculation module that are structurally independent; The summation calculation module includes: The first storage pair consists of a first ferroelectric transistor and a second ferroelectric transistor, which have opposite resistance states and respectively store the second addend and its logical inverse in a non-volatile manner. The first logic network is composed of multiple interconnected NMOS transistors; its input terminal receives a first addend and its logical inverse, a carry input and its logical inverse; it has two pull-down nodes, which are respectively connected to the ground terminal through the first ferroelectric transistor and the second ferroelectric transistor. The first logical network works in conjunction with the first storage pair to implement the summation logic function and generate a summation signal; The carry calculation module includes: The second storage pair consists of a third ferroelectric transistor and a fourth ferroelectric transistor, which have opposite resistance states and non-volatilely store the second addend and its logical inverse value, respectively. The second logic network is composed of multiple interconnected NMOS transistors; its input terminal receives the first addend and its logical inverse value, and the carry input; it has two pull-down nodes, which are connected to the ground terminal through the third ferroelectric transistor and the fourth ferroelectric transistor, respectively. The second logic network works in conjunction with the second storage pair to implement carry logic functions and generate carry signals.

2. The one-bit full adder circuit with storage and calculation function according to claim 1, characterized in that, The summation calculation module further includes a first inverter, the input of which is connected to the output node of the first logic network, and the output of which outputs the summation signal. The carry calculation module also includes a second inverter, the input of which is connected to the output node of the second logic network, and the output of which outputs the carry signal.

3. A one-bit full adder circuit with storage and calculation function according to claim 2, characterized in that, The summation calculation module further includes a first pull-up element, which is connected between the power input terminal and the output node of the first logic network; The carry calculation module also includes a second pull-up element, which is connected between the power input terminal and the output node of the second logic network.

4. A one-bit full adder circuit with storage and calculation function according to claim 3, characterized in that, The first pull-up element is a first PMOS transistor, whose source is connected to the power input terminal, its gate is connected to the ground terminal, and its drain is connected to the output node of the first logic network. The second pull-up element is a second PMOS transistor, whose source is connected to the power input terminal, its gate is connected to the ground terminal, and its drain is connected to the output node of the second logic network.

5. A one-bit full adder circuit with storage and calculation function according to claim 1, characterized in that, The gates of the first ferroelectric transistor and the third ferroelectric transistor are both connected to the first control terminal, and the gates of the second ferroelectric transistor and the fourth ferroelectric transistor are both connected to the second control terminal. The signal received by the second control terminal is the inverse of the signal received by the first control terminal.

6. A one-bit full adder circuit with storage and calculation function according to claim 5, characterized in that, The first control terminal and the second control terminal are used for: During the writing phase, a write voltage with opposite polarity and an absolute value greater than the polarization reversal threshold voltage of the ferroelectric transistor is received, thereby writing the first ferroelectric transistor and the third ferroelectric transistor into a first resistance state, and writing the second ferroelectric transistor and the fourth ferroelectric transistor into a second resistance state opposite to the first resistance state. During the reading phase, a reading voltage with an absolute value less than the polarization reversal threshold voltage is received, enabling the first logic network to perform summation logic based on the first resistance state of the first ferroelectric transistor and the second resistance state of the second ferroelectric transistor; similarly, enabling the second logic network to perform carry logic based on the first resistance state of the third ferroelectric transistor and the second resistance state of the fourth ferroelectric transistor.

7. A one-bit full adder circuit with storage and calculation function according to claim 1, characterized in that, The first logic network interconnects six NMOS transistors, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the second logic network interconnects four NMOS transistors, including a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor.

8. A one-bit full adder circuit with storage and calculation function according to claim 7, characterized in that, The interconnection relationship of the six NMOS transistors in the first logic network is as follows: The gate of the first NMOS transistor receives the first addend, and its source is connected to the drain of the third NMOS transistor and the fourth NMOS transistor. The gate of the second NMOS transistor receives the logical inverse of the first addend, and its source is connected to the drain of the fifth NMOS transistor and the sixth NMOS transistor. The drain of the first NMOS transistor is connected to the drain of the second NMOS transistor, serving as the output node of the first logic network; The gates of the third NMOS transistor and the sixth NMOS transistor both receive the carry input, and the gates of the fourth NMOS transistor and the fifth NMOS transistor both receive the logic inverse of the carry input; The source of the third NMOS transistor is connected to the source of the fifth NMOS transistor, serving as a pull-down node of the first logic network, and is also connected to the drain of the first ferroelectric transistor. The source of the fourth NMOS transistor is connected to the source of the sixth NMOS transistor, serving as another pull-down node of the first logic network, and is also connected to the drain of the second ferroelectric transistor.

9. A one-bit full adder circuit with storage and calculation function according to claim 7, characterized in that, The interconnection relationship of the four NMOS transistors in the second logic network is as follows: The gate of the seventh NMOS transistor receives the carry input, and its source is connected to the drain of the ninth NMOS transistor and the tenth NMOS transistor. The gate of the eighth NMOS transistor receives the first addend; The drain of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, serving as the output node of the second logic network; The gate of the ninth NMOS transistor receives the logical inverse of the first addend, and the gate of the tenth NMOS transistor receives the first addend; The source of the eighth NMOS transistor is connected to the source of the ninth NMOS transistor, serving as a pull-down node of the second logic network, and is also connected to the drain of the third ferroelectric transistor. The source of the tenth NMOS transistor serves as another pull-down node of the second logic network and is connected to the drain of the fourth ferroelectric transistor.

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