Method and system for intelligent generation of RTL code based on cooperation of MCP and agent

Abstract

This invention provides an intelligent RTL code generation method and system based on MCP and Agent collaboration. The method involves: acquiring user-input circuit design requirements; initializing the Agent and large language model environment, configuring the Agent's role definition and system prompts; performing compilation and syntax checking; obtaining execution feedback results from EDA simulation tools to determine if compilation passed; generating a structured error correction report; the Agent receiving the structured error correction report and generating corrected Verilog RTL code; resubmitting the code until it passes compilation checks or reaches a preset iteration threshold. This invention significantly improves the compilability and correctness of generated code and reduces the threshold and cost of manual design by constructing an automated closed-loop process of "code generation – syntax checking – error parsing – iterative repair."

Description

Technical Field

[0001] This invention relates to an intelligent RTL code generation method and system based on MCP and Agent collaboration, belonging to the field of integrated circuit (IC) design automation technology. Background Technology

[0002] As process technology evolves and the scale of System-on-a-Chip (SoC) continues to expand, the amount of Register Transfer Level (RTL) code and interface complexity are rapidly increasing. Front-end engineers are investing a significant amount of time in highly repetitive modules such as First-In-First-Out (FIFO) queues, Finite State Machines (FSMs), and bus interfaces. Meanwhile, details such as cross-clock domains, timing constraints, and multi-module interconnections make manual coding more prone to introducing problems like bit-width mismatches, port connection errors, and imprecise timing descriptions. Once these defects reach the simulation and synthesis stages, they often lead to repeated rework and iterations, significantly slowing down project progress and increasing labor costs. In recent years, Generative Large Language Models (LLMs) have shown potential in code generation. However, Register Transfer Level (RTL) is a strongly constrained hardware description task. Correctness depends not only on the syntax but also on the satisfaction of parallel timing semantics, hierarchical structure consistency, and synthesizability constraints. Without toolchain constraints, Large Language Model (LLM) is prone to "illusionary" code writing, port mapping errors, or unsynthesizable descriptions, making it difficult for the generated results to be directly incorporated into the engineering process.

[0003] Although some work has attempted to link LLM with simulation / synthesis using multi-turn dialogues or scripts, the resulting code has low compilability and correctness due to issues such as fragmented interfaces, unstructured tool feedback, and difficulty in reusing processes. Essentially, a standardized, composable, and scalable "model-tool" collaboration mechanism is still lacking. Summary of the Invention

[0004] The purpose of this invention is to provide an intelligent RTL code generation method and system based on MCP and Agent collaboration to solve the problems of low compilability and correctness of generated code in the prior art.

[0005] The technical solution of this invention is: A method for intelligent RTL code generation based on MCP and Agent collaboration includes the following steps: Step 1: Obtain the circuit design requirements input by the user. The circuit design requirements include the circuit function described in natural language, the input and output port definitions, parameter configurations, and performance indicators. Step 2: Initialize the agent and the large language model environment, configure the role definition and system prompt of the agent, encapsulate the circuit design requirements into initial generation instructions and input them into the agent, and drive the large language model LLM to generate the initial version of Verilog RTL code; Step 3: Establish the Model Context Protocol service layer, i.e., the MCP service layer. The MCP service layer encapsulates the command-line interface of the EDA simulation tool. The agent sends a tool call request to the MCP service layer through the Model Context Protocol MCP, and passes the generated Verilog RTL code to the preset EDA simulation tool for compilation and syntax checking. Step 4: Obtain the execution feedback results from the EDA simulation tool to determine whether the compilation is successful. If the compilation is successful, output the final RTL code file; if the compilation fails, capture the raw error log in the standard error output stream. Step 5: Start the error parsing engine to perform structured cleaning and extraction on the original error log. Through preset regular expression matching logic, separate the file name, line number, error type keywords and specific error description information of the error, and generate a structured error repair report. Step 6: The agent receives the structured error repair report, combines the current context information with the Verilog RTL code from the previous round, constructs repair prompts containing error location and repair instructions, and drives the large language model again to perform targeted logical correction and syntax adjustment of the errors in the code, generating the corrected Verilog RTL code. Step 7: Resubmit the corrected Verilog RTL code to Step 3 to enter the closed-loop iterative process of generation-inspection-repair until the code passes the compilation check or reaches the preset number of iterations threshold.

[0006] Furthermore, in step 2, the System Prompt constraint constrains the output behavior of the large language model, requiring the model to play the role of a senior digital IC design engineer, and the generated code must comply with the Verilog syntax standard of IEEE 1364-2001 or higher. The code must contain complete module port declarations, parameter definitions and necessary comments, and the use of non-synthesizable simulation syntax is prohibited.

[0007] Furthermore, in step 3, the agent sends a tool call request to the MCP service layer through the Model Context Protocol (MCP). The parameters of the tool call request include the Verilog source code content or file path to be inspected. The MCP service layer converts the tool call request into a local shell command and executes it.

[0008] Furthermore, in step 5, the specific process of structured cleaning and extraction includes: Step 51: Traverse each line of the original error log text; Step 52: Apply regular expression pattern matching to lines containing the keywords "error" or "syntax error"; Step 53: Extract the colon-separated fields from the matched lines and obtain key information including file name (file_name), line number (line_number), and error message (error_message); Step 54: Remove redundant warning messages and system path prefixes from the logs; Step 55: Encapsulate the key information obtained in step 53 into a JSON object or a Markdown list and pass it as a feedback signal to the Agent.

[0009] Furthermore, in step 6, the Verilog RTL code of the previous round is specifically as follows: the first iteration uses the initial version of the Verilog RTL code generated in step 2, and subsequent iterations use the modified Verilog RTL code generated in the previous round.

[0010] Furthermore, in step 6, the specific prompts containing error location and repair instructions are as follows: Original requirements section: restate the user's core functional requirements; Current code section: Displays the code snippet generated in the previous round that contains errors; Error Reporting Section: Displays the structured error repair report generated in step 5, clearly indicating the error type and the line number where the error type is located; Repair instructions: The Large Language Model (LLM) is required to modify only the error location and related logic, while keeping the structure of the error-free code unchanged.

[0011] A system employing the RTL code intelligent generation method based on MCP and Agent collaboration as described above includes a human-computer interaction module, an agent, an MCP service layer, and an error log analysis module. Human-computer interaction module: Used to receive circuit design requirements in natural language form from the user and display the generated code results; The Agent is used to encapsulate circuit design requirements into initial generation instructions based on the System Prompt, and then drive the large language model to generate an initial version of Verilog RTL code. It sends a tool call request to the MCP service layer via the Model Context Protocol (MCP), passing the generated Verilog RTL code to a preset EDA simulation tool for compilation and syntax checking. It obtains the execution feedback from the EDA simulation tool to determine if compilation is successful. If successful, it outputs the final RTL code file; if compilation fails, it captures the raw error log in the standard error output stream. The Agent receives a structured error repair report, combines the current context information with the code generated in the previous round, constructs a secondary prompt containing error location and repair instructions, and again drives the large language model to perform targeted logical corrections and syntax adjustments to the code, generating corrected Verilog RTL code. The corrected Verilog RTL code is then resubmitted to the MCP service layer, entering a closed-loop iterative process of generation-checking-repair until the code passes the compilation check or reaches a preset iteration threshold.

[0012] MCP Service Layer: Encapsulates the command-line interface of the EDA simulation tool, receives tool call requests sent by the agent, and passes the Verilog RTL code generated by the large language model to the preset EDA simulation tool for compilation and syntax checking. Then, it sends the execution feedback result of the EDA simulation tool to the agent. Error Log Analysis Module: Starts the error parsing engine to perform structured cleaning and extraction of the raw error log. Through preset regular expression matching logic, it separates the file name, line number, error type keywords, and specific error description information of the error, and generates a structured error repair report.

[0013] Furthermore, the error log analysis module internally stores multiple sets of regular expression rule libraries for Iverilog compiler error formats, used to identify Syntax Error, Port Mismatch, Undefined Signal, and Width Truncation.

[0014] Furthermore, the agent employs a chain-of-thought prompting mechanism: before sending a repair request to the large language model, it guides the large language model to first generate intermediate analysis results for the error log, including error cause judgment, error location basis and repair points. Based on the intermediate analysis results, the agent calls the large language model to output the corrected Verilog RTL code.

[0015] The beneficial effects of this invention are: I. This method and system for intelligent RTL code generation based on MCP and Agent collaboration introduces an intelligent agent as the central hub and uses the Model Context Protocol (MCP) to seamlessly connect a general large language model with EDA simulation tools such as Iverilog, constructing an automated closed-loop process of "code generation - syntax checking - error parsing - iterative repair". This significantly improves the compilability and correctness of the generated code and reduces the threshold and cost of manual design.

[0016] II. This invention achieves intelligent debugging capabilities similar to those of a senior engineer through structured cleaning and precise feedback of error logs. Traditional automatic repair methods often directly throw lengthy compiler error messages at the model, leading to model distraction or context overflow. The error parsing engine designed in this invention uses regular expressions to reduce noise, remove duplicates, and extract structured data from the raw logs. This refined feedback signal guides the agent to precisely focus on the line of code that malfunctions, understand the root cause of the error, and thus achieve accurate localization rather than blind rewriting. This not only significantly reduces the number of iterations required for repair and lowers API call costs, but also significantly improves the success rate of repair.

[0017] Third, this intelligent RTL code generation method and system based on MCP and Agent collaboration addresses the core pain points of frequent "illusions" in large model hardware code generation and low compilability. Existing general-purpose large language models (LLMs) lack rigorous thinking about hardware circuits, often generating code with syntax errors or unsynthesizable code. Compared with existing technologies, this invention introduces open-source EDA simulation tools such as Iverilog as the decision maker. The Model Context Protocol (MCP) tightly integrates probabilistic model generation with deterministic tool checks. This invention constructs a closed-loop automated process of "generation-verification-repair". This closed-loop mechanism can automatically intercept and correct common problems such as syntax errors, port mismatches, and undefined signals, and can realize the automated generation of high-quality synthesizable code from requirements, significantly improving the efficiency and accuracy of integrated circuit front-end design. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating the intelligent RTL code generation method based on MCP and Agent collaboration in an embodiment of the present invention. Figure 2 This is a sequence diagram of the interaction between the Agent and the MCP server in this embodiment; Figure 3 This is a schematic diagram illustrating the structured cleaning and extraction of the original error log in the embodiment. Figure 4This is an illustrative diagram illustrating the generation of the modified Verilog RTL code in the embodiment. Figure 5 This is an illustrative diagram illustrating an RTL code intelligent generation system based on MCP and Agent collaboration in an embodiment. Detailed Implementation

[0019] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0020] The embodiment provides a method for intelligent RTL code generation based on MCP and Agent collaboration, such as Figure 1 This includes the following steps: Step 1: Obtain the circuit design requirements input by the user. The circuit design requirements include the circuit function, input / output port definitions, parameter configurations, and performance indicators described in natural language.

[0021] In Step 1, the user-input requirements are presented in natural language and must comprehensively cover the core elements of the circuit module. This includes a functional description of the circuit module, definitions of key interface signals (bit width and direction), parameter configurations (depth, threshold), and timing logic requirements. This information is encapsulated as initial instructions, providing explicit input for subsequent Agent code generation. For example, the user inputs natural language requirements through the interface: "Design a parallel FIR filter, module name fir_parallel. Input bit width 8, coefficient bit width 8, output bit width 20. Interface includes clk, rst_n, data_in, data_out. Code must be synthesizable." Step 2: Initialize the Agent and the large language model environment, configure the Agent's role definition and System Prompt, encapsulate the circuit design requirements into initial generation instructions and input them into the Agent, and let the Agent drive the large language model LLM to generate the initial version of Verilog RTL code.

[0022] In step 2, the initial generation instructions explicitly constrain the circuit function, interface definition, parameter configuration, and synthesis requirements, providing precise input conditions for subsequent code generation. During this process, the Agent state machine switches from the IDLE state to the GENERATING state, preparing to drive large language models such as LLM and Deepseek for code generation. The Agent is assigned the role of an "RTL design engineer," and the System Prompt constrains the output behavior of the large language model, requiring the model to act as a senior digital IC design engineer. The generated code must adhere to the Verilog syntax standard of IEEE 1364-2001 or later, and must include complete module port declarations, port definitions, strict distinctions between sequential logic non-blocking assignments and combinational logic blocking assignments, parameter definitions, and necessary comments. The use of non-synthesizable simulation syntax is prohibited. While the generated code must comply with IEEE standards, errors are often introduced in practice due to model "illusions." For example, for FIR filter requirements, the model might output the following code snippet: the module declaration contains `output signed [19:0] data_out`, but it is not explicitly defined as type `reg`; in the `always` sequential logic block, `data_out` is directly assigned a non-blocking value (`data_out<= 0`), which violates Verilog syntax rules because the default output port is of type `wire` and cannot be assigned a value in the `always` block. Such errors reflect the inadequacy of general-purpose LLMs in understanding hardware semantics. After generation, the Agent state changes to `CHECKING`, ready to enter the verification phase. The Agent maintains the dialogue context to ensure standardized code structure, laying the foundation for subsequent checks. In specific implementation, the system uses the LangChain framework to manage Agent states, including state machine transitions such as `IDLE` and `GENERATING`, ensuring an orderly process.

[0023] Step 3: Establish the Model Context Protocol service layer, i.e., the MCP service layer. The MCP service layer encapsulates the command-line interface of the EDA simulation tool. The agent sends a tool call request to the MCP service layer through the Model Context Protocol MCP, and passes the generated Verilog RTL code to the preset EDA simulation tool for compilation and syntax checking.

[0024] In step 3, the Model Context Protocol (MCP) is used to establish standardized communication between the general large language model and the local EDA simulation tool and to define the tool call function format. The EDA simulation tool is Icarus Verilog. The agent sends a tool call request named check_syntax to the MCP service layer through the MCP. The parameters of the tool call request include the Verilog source code content or file path to be checked. The MCP service layer converts the tool call request into the local shell command iverilog -t null. <filename>After execution, it returns the compilation / syntax check results and log information.

[0025] In step 3, the Agent detects that code generation is complete and immediately calls the EDA tool interface via the Model Context Protocol (MCP) to perform code syntax checks. The MCP protocol acts as a standardized bridge, submitting the generated code to the EDA simulation tool for verification. The MCP module, as an independently running service process, communicates with the Agent through standard input / output, achieving secure isolation between the large model and local tools. Figure 2 As shown, the MCP server exposes a standardized tool description to the Agent, defined in JSON format as follows: the tool name is verify_verilog, the description is "compile Verilog code using Iverilog to check for syntax errors," and the input pattern requires a string containing the code content. The Agent sends a JSON-RPC specification request, for example: {"jsonrpc": "2.0", "method": "call_tool", "params": {"name": "verify_verilog", "arguments": {"code": "module..."}}}. After receiving the request, the MCP service layer writes the code to a temporary file such as temp_design.v in the sandbox environment and executes the command line of the open-source tool Iverilog (v11.0) through the Python subprocess module. After execution, the EDAG tool returns compilation feedback to the MCP server, which then sends a JSON-RPC response (e.g., {'result': {'return_code': .., 'stderr':'...'}}) to the Agent, containing the exit code (return_code) and standard error stream (stderr), to provide the compilation result. The MCP protocol masks operating system differences, supports toolchain extensions, and can be replaced with tools such as VCS or Verilator, adapting to different toolchains through a unified function call specification.

[0026] Step 4: Obtain the execution feedback results from the EDA simulation tool and determine whether the compilation is successful. If the compilation is successful, output the final RTL code file; if the compilation fails, capture the raw error log in the standard error output stream.

[0027] In step 4, compilation feedback and log capture are performed, and the return codes and output streams of the Iverilog process are monitored in real time. If the return code is 0 and there are no error logs, the code is considered to have passed the check; otherwise, standard output stdout and standard error output stderr are extracted, and the error handling process is initiated to ensure that errors are intercepted in time and to prevent invalid code from flowing downstream. Taking the FIR filter as an example, if the compiler fails to execute, the following logs are output to the standard error stream: fir_parallel.v:10: error: data_out is not a valid l-value in this context. and fir_parallel.v:10: error: data_out is not a reg. These unstructured logs are fully captured by the MCP module and passed to the error parsing module. At this time, the Agent state changes to REPAIRING, preparing to start the repair iteration.

[0028] Step 5: Start the error parsing engine to perform structured cleaning and extraction on the original error log. Through preset regular expression matching logic, separate the file name, line number, error type keywords and specific error description information of the error, and generate a structured error repair report.

[0029] In step 5, such as Figure 3 The specific process of structured cleaning and extraction includes: Step 51: Traverse each line of the original error log text; Step 52: Apply regular expression pattern matching to lines containing the keywords "error" or "syntax error"; Step 53: Extract the colon-separated fields from the matched lines and obtain key information including file name (file_name), line number (line_number), and error message (error_message); Step 54: Remove redundant warning messages and system path prefixes from the logs; Step 55: Encapsulate the key information obtained in step 53 into a JSON object or a Markdown list and pass it as a feedback signal to the Agent.

[0030] In step 5, an error parsing engine is used to perform structured parsing of the error log using regular expressions to extract key error information. The core logic is implemented in Python using a pre-defined regular expression rule library for Iverilog error formats, such as defining the pattern `pattern = re.compile(r"^(?P`. <file> [^:]+):(?P <line>\d+):\s(?P <msg>.)$"), such as Figure 3 As shown, the system matches logs line by line, extracting filenames, line numbers, and error messages. The parsed results generate structured JSON data. Priority filtering is used, ignoring warnings and retaining only critical errors to avoid overloading Agent information. The parsed results serve as structured feedback signals, accurately pinpointing the location and type of errors. The engine has a built-in dynamically updated rule library; when encountering new error patterns, it automatically expands the regular expression templates and synchronizes them to the Agent's repair logic, improving error coverage.

[0031] Step 6: The agent receives the structured error repair report, combines the current context information with the Verilog RTL code from the previous round, constructs secondary prompts containing error location and repair instructions, and drives the large language model again to perform targeted logical correction and syntactic adjustment of the errors in the code, generating the corrected Verilog RTL code, such as... Figure 4 .

[0032] In step 6, the Verilog RTL code from the previous round is as follows: the first iteration uses the initial version of the Verilog RTL code generated in step 2, and subsequent iterations use the modified Verilog RTL code generated in the previous round.

[0033] In step 6, the specific prompts containing error location and repair instructions are as follows: Original requirements section: restate the user's core functional requirements; Current code section: Displays the code snippet generated in the previous round that contains errors; Error Reporting Section: Displays the structured error repair report generated in step 5, clearly indicating the error type and the line number where the error type is located; Repair instructions: The large language model should only be modified at the error location and related logic, while keeping the structure of the error-free code unchanged.

[0034] In step 6, based on the structured error repair report, the Agent combines the error context to construct prompt words, driving the LLM to perform targeted repairs, such as... Figure 4 As shown, the repair prompt word construction process includes: constructing a repair prompt word based on structured error information, combined with the original code and repair instruction template. Specifically, the Agent integrates structured error information (such as error location and error details), the original code, and a preset repair instruction template (containing instructions such as "change the port to output reg type") to generate a complete repair prompt word. Subsequently, the repair prompt word is input into the large language model. The large language model analyzes the root cause of the error based on the context and generates corrected code (for example, changing output signed [19:0] data_out to output reg signed [19:0] data_out), thereby completing the repair.

[0035] Step 7: Resubmit the corrected Verilog RTL code to Step 3 to enter the closed-loop iterative process of generation-inspection-repair until the code passes the compilation check or reaches the preset number of iterations threshold.

[0036] In step 7, a loop verification and final output are performed. The corrected code is resubmitted to step 3 for syntax checking. If it passes (return code 0), the system determines the process is successful, the state machine transitions to SUCCESS, and the final RTL code (e.g., fir_parallel.v) is provided to the user for download through the human-computer interaction module. If it fails, steps 3-7 are executed repeatedly, with a maximum preset number of iterations of 10. After reaching the limit, the process terminates and the final repair result is output. Through this closed-loop mechanism, the FIR filter code ultimately achieves zero-error compilation, verifying the effectiveness of the collaboration between MCP and Agent.

[0037] This intelligent RTL code generation method based on MCP and Agent collaboration introduces an intelligent agent as the central hub and uses the Model Context Protocol (MCP) to seamlessly connect general large language models with EDA simulation tools such as Iverilog, constructing an automated closed-loop process of "code generation - syntax checking - error parsing - iterative repair". This significantly improves the compilability and correctness of the generated code and reduces the threshold and cost of manual design.

[0038] This intelligent RTL code generation method based on MCP and Agent collaboration proposes a standardized connection method based on the Model Context Protocol (MCP) to connect LLM with compilers / EDA simulation tools using a unified protocol. This enables standardized calls to compilation tasks and structured feedback of compilation logs, and automatically converts error types and location information into consumable feedback signals to drive subsequent automatic repair and iteration. Simultaneously, through the collaborative work of intelligent agents in requirements analysis, architecture planning, code generation, compilation verification, and repair, a closed-loop process of "generation-verification-correction" is formed. This improves the compilability and interface consistency of RTL while maintaining the efficiency of LLM generation, and reduces the cost of manual intervention and repeated rework.

[0039] The embodiment also provides a system employing the RTL code intelligent generation method based on MCP and Agent collaboration as described above, including a human-computer interaction module, an intelligent agent, an MCP service layer, and an error log analysis module, such as Figure 5 : Human-computer interaction module: Used to receive circuit design requirements in natural language form from the user and display the generated code results; The Agent is used to encapsulate circuit design requirements into initial generation instructions based on the System Prompt, and then drive the large language model to generate an initial version of Verilog RTL code. The generated Verilog RTL code is sent to the MCP service layer via the Model Context Protocol (MCP) to request a tool call. The Agent obtains the execution feedback results from the EDA simulation tool, determines whether compilation is successful, and outputs the final RTL code file if compilation is successful; if compilation fails, it captures the raw error log in the standard error output stream. The Agent receives structured error repair reports, combines the current context information with the code generated in the previous round, constructs secondary prompts containing error location and repair instructions, and again drives the large language model to perform targeted logical corrections and syntactic adjustments to the errors in the code, generating corrected Verilog RTL code. The corrected Verilog RTL code is resubmitted to the MCP service layer, entering a closed-loop iterative process of generation-checking-repair until the code passes the compilation check or reaches a preset iteration threshold. MCP Service Layer: Encapsulates the command-line interface of the EDA simulation tool, receives tool call requests sent by the agent, and passes the Verilog RTL code generated by the large language model to the preset EDA simulation tool for compilation and syntax checking. Then, it sends the execution feedback result of the EDA simulation tool to the agent. Error Log Analysis Module: Starts the error parsing engine to perform structured cleaning and extraction of the raw error log. Through preset regular expression matching logic, it separates the file name, line number, error type keywords, and specific error description information of the error, and generates a structured error repair report.

[0040] This RTL code intelligent generation system, based on MCP and Agent collaboration, uses a human-computer interaction module for user intent input and final result display, supporting code highlighting and download. The Agent, as the system's core brain, is responsible for task decomposition, prompt word construction, tool invocation decisions, and multi-turn dialogue state management, controlling the "generate-check-repair" state transition; and maintaining a finite state machine (including IDLE, GENERATING, CHECKING, REPAIRING, and SUCCESS states) to ensure orderly process execution. The MCP service layer enhances the differentiation of EDA simulation tools, receiving tool invocation requests from the Agent and executing local tools. The error log analysis module is a core component, responsible for transforming the tool's raw feedback into structured data understandable by the model. It internally maintains a regular expression library for different EDA tool error formats. A code version manager can be used to record the code version generated in each iteration, supporting rollback and comparison to prevent "negative optimization" during the repair process.

[0041] The MCP service layer comprises the MCP tool gateway module and the tool execution unit. The MCP tool gateway module securely isolates the large language model from the local EDA simulation tool. It communicates with the agent via standard input / output (StdIO), providing a unified and standardized tool call interface (based on the JSON-RPC protocol) and encapsulating tool descriptions (such as verify_verilog / check_syntax). It supports the access and request / response of various EDA simulation tools (such as Iverilog and Verilator), including input stream mechanisms and output stream capture. The tool execution unit receives tool call requests and, based on these requests, instructs the EDA simulation tool to perform syntax checking. It calls open-source engines such as Icarus Verilogv11.0 to create temporary files in a sandbox environment and run command lines to verify code syntax. Finally, the compiler's return code and output stream are passed to the EDA simulation tool.

[0042] The error log analysis module internally stores multiple sets of regular expression rule libraries for Iverilog compiler error formats, used to identify Syntax Error, Port Mismatch, Undefined Signal, and Width Truncation.

[0043] The agent employs a chain-of-thought prompting mechanism: before sending a repair request to the large language model, it guides the large language model to generate intermediate analysis results for the error log, including error cause judgment, error location basis and repair points. Based on the intermediate analysis results, the agent calls the large language model to output the corrected Verilog RTL code.

[0044] This invention presents an intelligent RTL code generation method and system based on MCP and Agent collaboration. It acquires the user's circuit design requirements in natural language form, constructs an Agent environment, and drives a general-purpose large language model to generate initial Verilog RTL code. A Model Context Protocol (MCP) service layer is established as a communication bridge, encapsulating local EDA tool interfaces to compile and perform syntax checks on the generated code. If the checks fail, an error parsing engine performs structured cleaning and extraction of the original error logs, generating a precise error repair report. The Agent receives the report and, combined with the context, constructs repair prompts, driving the model to perform targeted iterative corrections until the code compiles successfully. This invention solves the problems of illusions, low compilability, and lack of verification loops in hardware code generation from general-purpose large models, achieving automated generation from requirements to high-quality synthesizable code, significantly improving the efficiency and accuracy of integrated circuit front-end design.

[0045] This method and system for intelligent RTL code generation based on MCP and Agent collaboration achieves a high degree of decoupling between the model and tools using the MCP protocol, endowing the system with strong compatibility and scalability. This invention uses the standardized Model Context Protocol (MCP) to encapsulate EDA tool interfaces, resulting in a highly flexible system architecture. On one hand, backend EDA tools can be seamlessly replaced or extended, for example, from Iverilog to Verilator for higher-performance simulation, or integrated with Yosys for logic synthesis and checking; on the other hand, the frontend Agent can flexibly adapt to different large-scale base models such as GPT-5, DeepSeek, and Claude. This loosely coupled architecture ensures the long-term effectiveness of the technical solution, enabling smooth evolution as models and tools are upgraded.

[0046] This intelligent RTL code generation method and system, based on MCP and Agent collaboration, can automatically complete the entire process from natural language requirements to syntax-free RTL code, automating the tedious task of syntax checking. It significantly improves the development efficiency of digital chip front-end design, reduces labor costs and technical barriers. For inexperienced junior engineers, the system acts as an "intelligent mentor," standardizing their coding style; for experienced engineers, the system serves as an "efficient assistant," handling repetitive module writing tasks (such as interface conversion and state machine templates). This allows design teams to focus their valuable energy on high-value aspects such as architecture design and algorithm optimization, significantly shortening the chip development cycle.

[0047] This intelligent RTL code generation method and system based on MCP and Agent collaboration enables standardized code output, ensuring design compliance with IEEE standards. Through the expert role setting of the System Prompt, the generated code is enforced to adhere to industry standards such as IEEE 1364. Compared to the potential for inconsistent styles and missing comments in manual coding, the code generated by this invention features unified port naming conventions, complete parameterization definitions, and a clear comment structure, significantly improving readability and maintainability, and facilitating subsequent team collaboration and design reuse.

[0048] This intelligent RTL code generation method and system based on MCP and Agent collaboration integrates the cognitive capabilities of large language models with the verification capabilities of EDA tools in a closed-loop collaboration. It can achieve automatic writing, syntax checking and automatic repair of high-quality Verilog HDL code, and can transform natural language requirements into high-quality, syntax-free RTL code. It is applicable to the fields of integrated circuit IC design automation, electronic design automation EDA and artificial intelligence-assisted development technology.

[0049] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.< / msg> < / line> < / file> < / filename>

Claims

1. A method for intelligent RTL code generation based on MCP and Agent collaboration, characterized in that, Includes the following steps: Step 1: Obtain the circuit design requirements input by the user. The circuit design requirements include the circuit function described in natural language, the input and output port definitions, parameter configurations, and performance indicators. Step 2: Initialize the agent and the large language model environment, configure the role definition and system prompt of the agent, encapsulate the circuit design requirements into initial generation instructions and input them into the agent, and drive the large language model LLM to generate the initial version of Verilog RTL code; Step 3: Establish the Model Context Protocol service layer, i.e., the MCP service layer. The MCP service layer encapsulates the command-line interface of the EDA simulation tool. The agent sends a tool call request to the MCP service layer through the Model Context Protocol MCP, and passes the generated Verilog RTL code to the preset EDA simulation tool for compilation and syntax checking. Step 4: Obtain the execution feedback results from the EDA simulation tool and determine whether the compilation is successful. If the compilation is successful, output the final RTL code file. If compilation fails, the raw error log in the standard error output stream is captured; Step 5: Start the error parsing engine to perform structured cleaning and extraction on the original error log. Through preset regular expression matching logic, separate the file name, line number, error type keywords and specific error description information of the error, and generate a structured error repair report. Step 6: The agent receives the structured error repair report, combines the current context information with the Verilog RTL code from the previous round, constructs repair prompts containing error location and repair instructions, and drives the large language model again to perform targeted logical correction and syntax adjustment of the errors in the code, generating the corrected Verilog RTL code. Step 7: Resubmit the corrected Verilog RTL code to Step 3 to enter the closed-loop iterative process of generation-inspection-repair until the code passes the compilation check or reaches the preset number of iterations threshold.

2. The intelligent RTL code generation method based on MCP and Agent collaboration as described in claim 1, characterized in that: In step 2, the System Prompt constraint constrains the output behavior of the large language model, requiring the model to play the role of a senior digital IC design engineer, and the generated code must comply with the Verilog syntax standard of IEEE 1364-2001 or higher. The code must contain complete module port declarations, parameter definitions and necessary comments, and the use of non-synthesizable simulation syntax is prohibited.

3. The intelligent RTL code generation method based on MCP and Agent collaboration as described in claim 1, characterized in that: In step 3, the agent sends a tool call request to the MCP service layer through the Model Context Protocol (MCP). The parameters of the tool call request include the Verilog source code content or file path to be inspected. The MCP service layer converts the tool call request into a local shell command and executes it.

4. The intelligent RTL code generation method based on MCP and Agent collaboration as described in any one of claims 1-3, characterized in that: Step 5, the specific process of structured cleaning and extraction includes: Step 51: Traverse each line of the original error log text; Step 52: Apply regular expression pattern matching to lines containing the keywords "error" or "syntax error"; Step 53: Extract the colon-separated fields from the matched lines and obtain key information including file name (file_name), line number (line_number), and error message (error_message); Step 54: Remove redundant warning messages and system path prefixes from the logs; Step 55: Encapsulate the key information obtained in step 53 into a JSON object or a Markdown list and pass it as a feedback signal to the Agent.

5. The intelligent RTL code generation method based on MCP and Agent collaboration as described in any one of claims 1-3, characterized in that: In step 6, the Verilog RTL code from the previous round is as follows: the first iteration uses the initial version of the Verilog RTL code generated in step 2, and subsequent iterations use the modified Verilog RTL code generated in the previous round.

6. The intelligent RTL code generation method based on MCP and Agent collaboration as described in any one of claims 1-3, characterized in that: In step 6, the specific prompts containing error location and repair instructions are as follows: Original requirements section: restate the user's core functional requirements; Current code section: Displays the code snippet generated in the previous round that contains errors; Error Reporting Section: Displays the structured error repair report generated in step 5, clearly indicating the error type and the line number where the error type is located; Repair instructions: The large language model should only be modified at the error location and related logic, while keeping the structure of the error-free code unchanged.

7. A system employing the RTL code intelligent generation method based on MCP and Agent collaboration as described in any one of claims 1-6, characterized in that: It includes a human-computer interaction module, an agent, an MCP service layer, and an error log analysis module. Human-computer interaction module: Used to receive circuit design requirements in natural language form from the user and display the generated code results; Agent: Used to encapsulate circuit design requirements into initial generation instructions based on the system prompt, and then drive the large language model to generate an initial version of Verilog RTL code; The tool call request is sent to the MCP service layer via the Model Context Protocol (MCP) to pass the generated Verilog RTL code to the preset EDA simulation tool for compilation and syntax checking; the execution feedback result of the EDA simulation tool is obtained to determine whether the compilation is successful. If the compilation is successful, the final RTL code file is output. If compilation fails, the raw error log in the standard error output stream is captured; the agent receives the structured error repair report, combines the current context information with the code generated in the previous round, constructs secondary prompt words containing error location and repair instructions, and drives the large language model to perform targeted logical correction and syntax adjustment of the errors in the code, generating the corrected Verilog RTL code. The corrected Verilog RTL code is resubmitted to the MCP service layer and enters a closed-loop iterative process of generation-inspection-repair until the code passes the compilation check or reaches the preset number of iterations threshold. MCP Service Layer: Encapsulates the command-line interface of the EDA simulation tool, receives tool call requests sent by the agent, and passes the Verilog RTL code generated by the large language model to the preset EDA simulation tool for compilation and syntax checking. Then, it sends the execution feedback result of the EDA simulation tool to the agent. Error Log Analysis Module: Starts the error parsing engine to perform structured cleaning and extraction of the raw error log. Through preset regular expression matching logic, it separates the file name, line number, error type keywords, and specific error description information of the error, and generates a structured error repair report.

8. The RTL code intelligent generation system based on MCP and Agent collaboration according to claim 7, characterized in that, The error log analysis module internally stores multiple sets of regular expression rule libraries for Iverilog compiler error formats, used to identify Syntax Error, Port Mismatch, Undefined Signal, and Width Truncation.

9. The RTL code intelligent generation system based on MCP and Agent collaboration according to claim 7, characterized in that, The agent employs a chain-of-thought prompting mechanism: before sending a repair request to the large language model, it guides the large language model to generate intermediate analysis results for the error log, including error cause judgment, error location basis and repair points. Based on the intermediate analysis results, the agent calls the large language model to output the corrected Verilog RTL code.

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