A MetroAnalyzer software can integrate CD-SEM and GDSII / OASIS layout measurement and analysis system

Abstract

This invention provides a MetroAnalyzer software system that integrates CD-SEM and GDSII / OASIS for layout measurement and analysis. Relating to the field of data processing technology, it deeply integrates quantum computing and AI technologies. Through quantum annealing optimization algorithms and multi-dimensional feature embedding methods, it achieves ultra-efficient deviation prediction and measurement optimization. Utilizing a quantum computing processor, it decomposes multi-MP measurement tasks into quantum bit states, reducing repetition rate and shortening detection time. Simultaneously, the AI ​​multi-dimensional feature embedding method, combined with temporal convolutional networks and a Transformer architecture, extracts spatial-temporal features from historical data. An adaptive knowledge distillation mechanism controls prediction errors to within 0.5nm, avoiding the limitation of traditional static models with errors exceeding 1nm, significantly improving measurement efficiency and prediction accuracy. Furthermore, through a quantum-classical hybrid architecture, it achieves seamless integration from deviation identification to optimization, breaking through the bottleneck of traditional reliance on manual intervention and repeated experiments, providing a novel solution for high-precision, high-throughput semiconductor manufacturing.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, specifically to a MetroAnalyzer software system that integrates CD-SEM and GDSII / OASIS for layout measurement and analysis. Background Technology

[0002] In the semiconductor manufacturing field, especially in chip production at 5nm and below process nodes, the analysis of CD-SEM (Critical Dimension Scanning Electron Microscopy) and GDSII / OASIS layout data is a core step in optimizing critical dimension control and improving yield. As device feature sizes shrink and process complexity increases—for example, the gate width of logic chips shrinks to below 20nm and the aperture of 3D NAND flash memory chips is controlled within 50nm—traditional analysis methods face multiple challenges. Existing technologies mainly rely on direct measurement with CD-SEM equipment and manual adjustment of process parameters, comparing SEM images with layout designs through static overlays, and combining simple statistical analysis to identify deviations and optimize the process. However, these methods have significant limitations in efficiency, accuracy, and intelligence, making it difficult to meet the high-throughput and high-precision requirements of advanced process nodes.

[0003] The aforementioned patent documents and prior art have the following technical problems when used:

[0004] Problem 1: Traditional methods rely on manually adjusting AMP parameters and repeating measurements. For example, in 5nm logic chip production, optimizing the deviation of 50 gate widths can take several hours, with a repetition rate as high as 20%-30%. Existing optimization algorithms have high computational complexity and cannot process multi-MP (multiple measurement points) tasks in parallel, resulting in low production line efficiency and a repetition rate as high as 20%-30%.

[0005] The second problem is that traditional process analysis can only identify deviations in the current wafer, such as detecting a contact point diameter deviation of 0.8nm in advanced packaging. However, it cannot predict the deviation trend of hundreds of wafers in the future, and it lacks the ability to analyze the synergistic effects of multiple processes such as photolithography and etching. Existing methods rely on static overlay diagrams and simple regression models. For example, in the production of 5nm logic chips, the prediction error is more than 1nm. Process adjustments are passive and inefficient, with yield losses as high as 5%-10%, affecting memory performance. It also lacks the ability to predict and optimize long-term trends. Summary of the Invention

[0006] Technical problems to be solved

[0007] To address the shortcomings of existing technologies, this invention provides a layout measurement and analysis system that integrates CD-SEM and GDSII / OASIS using MetroAnalyzer software, solving the following problems:

[0008] 1. Addressing the problem that traditional CD-SEM measurement is inefficient and has a high repetition rate, making it difficult to meet the needs of high-throughput production;

[0009] 2. Traditional process analysis lacks the ability to predict deviation trends and perform closed-loop optimization, resulting in a lag in yield improvement.

[0010] Technical solution

[0011] To achieve the above objectives, the present invention provides the following technical solution: a MetroAnalyzer software-integrated layout measurement and analysis system for CD-SEM and GDSII / OASIS, the system comprising the following steps:

[0012] Sp1: Loads CD-SEM measurement data files and GDSII / OASIS layout files, calculates the pixel offset between the SEM image and the layout through a multi-source data synchronization preprocessing algorithm based on feature point matching, and automatically calibrates the coordinate system deviation to within ±1nm;

[0013] Sp2: Utilizing a multi-dimensional feature embedding method that combines temporal convolutional networks and Transformer architecture, spatial-temporal features are extracted from historical CD-SEM data and process parameters. The prediction model dynamically identifies measurement deviations and marks process weaknesses where the deviations exceed a set threshold.

[0014] Sp3: Based on the quantum annealing optimization algorithm, the AMP parameters are adjusted, the multi-MP data is decomposed into quantum bit states for parallel computation, the beam intensity and scanning speed are optimized, batch measurement is realized, and the measurement time of a single measurement is reduced to 1 / 3 of the traditional method;

[0015] Sp4: Employs a cross-scale dynamic convolution method based on adaptive convolution kernels to fuse nanoscale details of SEM images, geometric structures of GDSII / OASIS layouts, and deviation distributions from lithography simulations, generating overlay analysis results from the nanoscale to the wafer level.

[0016] Sp5: Generates an adversarial network based on process trends, uses the generator and discriminator to learn adversarial learning to predict the future wafer deviation distribution trend, and adjusts the exposure dose and etching depth based on reinforcement learning algorithm to form a closed-loop optimization scheme.

[0017] Sp6: Employs a distributed data compression algorithm based on sparse coding to compress TB-level SEM image data to 10% of its original size, and generates 3D holographic visualization results with wafer-level deviations through augmented reality technology;

[0018] Sp7: Through a hybrid architecture of quantum computing modules and classical computing units, the above steps Sp1 to Sp6 are executed in a coordinated manner to form a closed-loop analysis process from data calibration and deviation prediction to process optimization.

[0019] Preferably, in step Sp2, the multi-dimensional feature embedding method extracts the time-series features of CD-SEM data through a temporal convolutional network, captures the spatial correlation of process parameters through a Transformer architecture, and introduces an adaptive knowledge distillation mechanism when dynamically identifying measurement deviations, distilling the predictive power of the large model into the small model, so that the prediction deviation error is controlled within 0.5nm.

[0020] Preferably, in step Sp3, the quantum annealing optimization algorithm optimizes the measurement path of multi-MP data through a quantum parallel measurement scheduler, dynamically balancing the relationship between beam intensity and scanning speed when adjusting AMP parameters, thereby reducing the repetitive measurement rate by 40%.

[0021] Preferably, in step Sp4, the cross-scale dynamic convolution method integrates a real-time lithography reverse modeler, uses partial differential equations and Monte Carlo methods to calculate edge roughness and mask offset during the lithography process, and generates a process deviation heatmap for overlay analysis. The cross-scale dynamic convolution method uses virtual wafer simulation technology to generate a complete wafer measurement result prediction view based on the fused overlay data, and marks areas in the view where the global process consistency deviation exceeds a set threshold with color gradients.

[0022] Preferably, in step Sp5, the process trend generative adversarial network predicts the deviation distribution of the next 1000 wafers through adversarial learning, and introduces multi-process collaborative analysis into the closed-loop optimization scheme, integrating lithography, etching and deposition process data to generate optimization parameters for mask design. The closed-loop optimization scheme dynamically adjusts process parameters through reinforcement learning and introduces a process weakness tracker to generate mask layout modification schemes and lithography condition adjustment suggestions based on the deviation distribution, thereby reducing yield loss by more than 5%.

[0023] Preferably, the distributed data compression algorithm in step Sp6 removes redundant pixels from the SEM image through sparse coding and improves compression stability by combining a quantum entanglement-inspired error correction mechanism. The data backup is updated every second through a streaming computing framework to ensure zero data loss during data processing.

[0024] Preferably, the quantum-classical hybrid architecture described in step Sp7 optimizes AMP parameter adjustment and multi-MP measurement through a quantum computing module, processes data compression and visualization through a classical computing unit, supports analysis of process nodes at 5nm and below, and generates 3D holograms that support gesture interaction through a holographic visualization engine, thereby improving overall efficiency by more than 100 times.

[0025] Preferably, the hardware components of the system include:

[0026] The data acquisition unit is equipped with a high-speed SSD memory and a multi-channel data interface, which is used to receive CD-SEM measurement data files and any one of the layout files of GDSII / OASIS in real time in step Sp1, and supports high-speed loading of TB-level data.

[0027] The quantum computing processor has a built-in quantum annealing acceleration module, which is used to execute the quantum annealing optimization algorithm in step Sp3. It achieves parallel computing of multi-MP data through quantum bit state decomposition, and the processing speed is 50 times faster than that of traditional processors.

[0028] A high-performance GPU cluster, with an integrated adaptive convolution kernel accelerator, is used to perform a cross-scale dynamic convolution method in step Sp4, reducing the computation time for fusing SEM images and map data to less than 1 second.

[0029] The holographic projection device, equipped with an augmented reality display module, is used to generate 3D holographic visualization results of wafer-level deviations in step Sp6, and supports gesture recognition sensors to achieve interactive analysis;

[0030] The aforementioned hardware components are interconnected via a high-speed PCIe bus and work in conjunction with the quantum-classical hybrid architecture in step Sp7.

[0031] Beneficial effects

[0032] This invention provides a layout measurement and analysis system that integrates CD-SEM and GDSII / OASIS using MetroAnalyzer software. It offers the following advantages:

[0033] 1. This invention deeply integrates quantum computing and AI technology, achieving ultra-efficient deviation prediction and measurement optimization through quantum annealing optimization algorithms and multi-dimensional feature embedding methods. It utilizes a quantum computing processor to decompose multi-MP measurement tasks into quantum bit states, reducing repetition rate and shortening detection time. Simultaneously, the AI ​​multi-dimensional feature embedding method combines temporal convolutional networks and a Transformer architecture to extract spatial-temporal features from historical data. An adaptive knowledge distillation mechanism controls prediction errors to within 0.5nm, avoiding the limitation of traditional static models with errors exceeding 1nm, significantly improving measurement efficiency and prediction accuracy. Furthermore, a quantum-classical hybrid architecture achieves seamless integration from deviation identification to optimization, breaking through the bottleneck of traditional reliance on manual intervention and repeated experiments, providing a novel solution for high-precision, high-throughput semiconductor manufacturing.

[0034] 2. This invention employs a system that utilizes cross-scale dynamic convolution and process trend generative adversarial networks to achieve overlay analysis from nanoscale details to wafer-level distribution. Combined with closed-loop optimization, it pioneers a new paradigm for forward-looking yield improvement. Utilizing the cross-scale dynamic convolution technology of high-performance GPU clusters, it integrates nanoscale edge details from SEM images, the geometric structure of GDSII / OASIS layouts, and the deviation distribution from lithography simulations to generate a complete wafer prediction view. A real-time lithography reverse modeler further calculates edge roughness and mask offset, providing accurate analysis of deviation sources. The process trend generative adversarial network predicts future wafer deviation trends. The closed-loop optimization process integrates lithography, etching, and deposition data through multi-process collaborative analysis. For example, in the memory chip case, adjusting the etching depth to 101nm significantly improves process consistency. This achieves a forward-looking closed loop from data analysis to process optimization, pioneering a new model for yield improvement and providing revolutionary technical support for the semiconductor industry. Attached Figure Description

[0035] Figure 1 This is a system step diagram of the present invention;

[0036] Figure 2 The graph shows the deviation prediction error between the present invention and the conventional method at 5 sample points.

[0037] Figure 3 This is a comparison chart showing the optimization effects of the present invention and the traditional method in terms of measurement time and repeatability;

[0038] Figure 4 This is a comparison chart of the yield loss trend of the present invention and the conventional method over the next 1000 wafers. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Specific Implementation Example 1:

[0041] like Figures 1 to 4As shown, MetroAnalyzer software integrates CD-SEM and GDSII / OASIS layout measurement and analysis systems. The system combines feature point matching algorithms, AI multi-dimensional feature embedding, quantum annealing optimization, cross-scale dynamic convolution, process trend prediction, data compression, and augmented reality visualization technologies. This solves the problems of long data cleaning time, insufficient prediction accuracy, and low computational efficiency in traditional SEM analysis, making it particularly suitable for semiconductor manufacturing at 5nm and below process nodes. The specific steps are as follows:

[0042] SP1: Data Loading and Coordinate Calibration: A multi-source data synchronous preprocessing algorithm based on feature point matching loads CD-SEM measurement data files and GDSII / OASIS layout files. Pixel offsets between the SEM image and the layout are calculated, and coordinate system deviations are automatically calibrated to within ±1nm. The process begins with the data acquisition unit, equipped with high-speed SSD memory and a multi-channel data interface, capable of receiving TB-level data in real-time from CD-SEM devices and layout databases. For example, a CD-SEM data file may contain microscopic images of hundreds of critical locations on the wafer, such as gate widths in logic circuits or aperture depths in memory cells, while the GDSII / OASIS file defines the geometry of the chip design, such as a straight line with a length of 50... Due to the influence of equipment scanning path or lens distortion, CD-SEM imaging has a slight offset between its image coordinate system and the layout design coordinate system. The system extracts edge features in the SEM image, such as the pixel coordinates of a gate edge, through a feature point matching algorithm and compares them with the corresponding geometric lines in the layout. The pixel offset between the two is calculated using fast Fourier transform. For example, it is found that the X-axis offset is 2nm and the Y-axis offset is 1.5nm. Then, the calibration parameters are optimized by least squares method to adjust the coordinates of the SEM image to be completely aligned with the layout. The final deviation is controlled within ±1nm. High-speed SSD caching and parallel loading technology reduce the data import time by more than 50%, for example, from 10 minutes to 5 minutes, providing a high-precision data foundation for subsequent analysis.

[0043] Sp2: Feature Extraction and Deviation Prediction: Utilizing a multi-dimensional feature embedding method combining temporal convolutional networks and the Transformer architecture, spatial-temporal features are extracted from historical CD-SEM data and process parameters. A prediction model dynamically identifies measurement deviations and marks process weaknesses where deviations exceed a set threshold. The process begins by receiving data calibrated from Sp1. Inputs include historical CD-SEM measurement records and process parameters, such as linewidth data from the past 100 wafers (fluctuating between 19.5nm and 20.5nm for each measurement) and exposure dose values ​​during lithography (ranging from 30mJ / cm² to 35mJ / cm²). The system first analyzes the temporal trends of these linewidth data using a temporal convolutional network. For example, it might find that the linewidth in a certain region has gradually deviated from the 20nm standard value in the last 10 measurements. The Transformer architecture then... The system captures the spatial correlation of process parameters, such as the average linewidth reduction of 0.2nm when the exposure dose increases by 1mJ / cm². This information is then fused to generate a multidimensional feature tensor. Next, a pre-trained neural network prediction model calculates the deviation value of each measurement point based on these features. For example, it predicts that the linewidth deviation of a certain point is 0.7nm. Combined with an adaptive knowledge distillation mechanism, the predictive power of the complex model is compressed into a lightweight model, ensuring real-time inference with the error controlled within 0.5nm. The system marks areas with excessive deviations according to a set threshold (e.g., 3Sigma value is 0.6nm). For example, if the linewidth deviation of a certain wafer area reaches 0.8nm, it is marked as a weak point, and a list is generated for subsequent optimization. This process is supported by a multi-core TPU array of AI inference accelerator, which processes 1 billion feature extraction operations per second to achieve dynamic deviation identification and avoid the cumbersome process of re-measuring using traditional methods.

[0044] Sp3: Quantum Optimization and Batch Measurement: Based on the quantum annealing optimization algorithm, AMP parameters are adjusted to decompose multi-MP data into qubit states for parallel computation. Beam intensity and scanning speed are optimized to achieve batch measurement, reducing the single measurement time to 1 / 3 of traditional methods. The process begins with the quantum computing processor receiving Sp2-tagged weak point data. For example, if the linewidth data of 100 key points (such as gates and contact holes) on a wafer needs to be measured, AMP parameters include beam intensity (e.g., 10nA to 20nA) and scanning speed (e.g., 1mm / s to 2mm / s). These parameters directly affect the measurement accuracy and efficiency of CD-SEM. The system converts these 100 measurement points into qubit states and uses the quantum annealing algorithm to... The quantum tunneling effect is used to find the optimal parameter combination. For example, determining a beam intensity of 15 nA and a scanning speed of 1.5 mm / s can simultaneously meet the requirements of accuracy and speed. The quantum parallel measurement scheduler decomposes the task and allocates resources. For example, 50 points are allocated to the first group of quantum computing units and another 50 points are allocated to the second group to achieve parallel processing. The beam intensity and scanning speed are dynamically balanced to reduce the repetitive measurement rate, for example, from 20% to 12%. The adjusted parameters are input into the CD-SEM device to perform batch measurements. The built-in quantum annealing acceleration module increases the processing speed by 50 times. For example, a task that would take 90 seconds in the traditional method is shortened to 30 seconds, and high-precision measurement results are output. This process significantly improves measurement efficiency and adapts to the needs of high-throughput production.

[0045] Sp4: Cross-Scale Overlay and Simulation: Employing a cross-scale dynamic convolution method based on adaptive convolution kernels, this method fuses nanoscale details from SEM images, the geometry of GDSII / OASIS layouts, and the deviation distribution from lithography simulations to generate overlay analysis results from the nanoscale to the wafer level. It integrates a real-time lithography reverse modeler and virtual wafer simulation technology. The process begins by receiving measurement data from Sp3 and calibration data from Sp1 from a high-performance GPU cluster. For example, if an SEM image shows a gate width of 19.8 nm, a layout design value of 20 nm, and a lithography simulation prediction deviation of 0.3 nm, the system dynamically adjusts the adaptive convolution kernel according to the feature scale. For instance, a 3x3 convolution kernel is used to extract edge details at the nanoscale, while an 11x11 convolution kernel is used to capture the overall distribution at the wafer level. These data are then fused through convolution operations. The data is used to generate an overlay view. The real-time lithography reverse modeler uses partial differential equations to describe the lithography diffusion process, such as calculating the thickness change of photoresist after exposure. It combines the Monte Carlo method to simulate the photon scattering path, such as predicting that the edge roughness of a certain area will increase to 2nm due to photon scattering, or that the mask offset will reach 1.5nm. It generates a process deviation heat map. The virtual wafer simulation technology predicts the measurement results of the complete wafer based on the overlay data, such as predicting the deviation distribution of 1000 key points on a 300mm wafer. It outputs a prediction view and marks the areas with global process consistency deviation exceeding the standard with color gradients. For example, a certain area with a deviation of more than 5nm is displayed in red. The integrated adaptive convolution kernel accelerator reduces the fusion calculation time from 3 seconds to less than 1 second. This process intuitively shows the process consistency and reveals potential defects, such as lithography offset or uneven etching.

[0046] Sp5: Trend Prediction and Closed-Loop Optimization: This method uses a Generative Adversarial Network (GAN) to predict future wafer deviation distribution trends. Reinforcement learning algorithms are used to adjust exposure dose and etching depth, forming a closed-loop optimization scheme. Multi-process collaborative analysis and a weak point tracker are introduced to generate optimization suggestions. The process begins with the deviation heatmap and historical process data from Sp4. For example, the heatmap shows a linewidth deviation of 0.8nm in a certain area. Historical data includes exposure dose and etching depth records for the past 100 wafers. The GAN generator generates the deviation distribution for the next 1000 wafers, predicting, for example, that the linewidth deviation might increase from 0.8nm to 1.2nm. The discriminator verifies its accuracy, ensuring the prediction is close to the actual trend. Reinforcement learning constructs a reward function based on the deviation distribution, for example, controlling the deviation within 0.5nm. With the goal of optimizing the exposure dose from 32mJ / cm² to 33mJ / cm² and the etching depth from 50nm to 48nm, a closed-loop optimization scheme was generated. Multi-process collaborative analysis integrated lithography data (such as exposure dose changes), etching data (such as etching rate of 0.1nm / s), and deposition data (such as film thickness of 50nm) to reveal the cross-process influence rules. For example, it was found that the increase in exposure dose led to the amplification of etching deviation. The weak point tracker located the problem area based on the deviation distribution. For example, if the linewidth deviation of a wafer edge exceeded the standard, a mask layout modification scheme was generated (such as adjusting the design linewidth from 20nm to 20.2nm) and lithography condition adjustment suggestions (such as increasing the exposure time by 10%). The yield loss was reduced from 5% to 2%. This process was executed by classical computing units to achieve forward-looking process optimization.

[0047] Sp6: Data Compression and Visualization: Employing a distributed data compression algorithm based on sparse coding, it compresses TB-level SEM image data to 10% of its original size. Augmented reality technology is used to generate 3D holographic visualization results with wafer-level deviations, and streaming computing backup is supported. The process begins with the overlay data from Sp4 and the optimized results from Sp5. For example, an SEM image containing microscopic images of 1000 key points on a wafer, with a total data volume of 1TB, uses sparse coding to identify redundant pixels in the image; for example, background areas with grayscale value changes of less than 5% are removed. A quantum entanglement-inspired error correction mechanism is used to verify the accuracy of the data through quantum state verification. To ensure data integrity after compression, such as restoring edge details lost due to compression, the data compression coprocessor reduces compression time from 10 minutes to 2 minutes through hardware acceleration. The streaming computing framework updates backups to high-speed SSDs every second, for example, automatically saving when processing the 500th image to ensure zero data loss. The holographic projection device is equipped with an augmented reality display module to project deviation data into 3D holograms, such as displaying a stereoscopic view of a certain area of ​​a wafer with a deviation of 1nm. Users can adjust the viewing angle through gesture recognition sensors, such as zooming in on edge areas to view details. This process achieves efficient storage and intuitive analysis, with a compression rate of up to 90%.

[0048] Sp7: Hybrid Architecture Collaborative Operation: Sp1 through Sp6 are executed collaboratively through a quantum-classical hybrid architecture, forming a closed-loop analysis flow from data calibration and deviation prediction to process optimization. It supports 5nm and below process nodes and generates 3D holograms with gesture interaction. The process begins with task allocation by each hardware unit. The quantum computing module handles highly complex tasks, such as optimizing AMP parameters for 100 measurement points in Sp3. Classical computing units handle data compression and visualization, such as compressing 1TB of image data and generating holograms in Sp6. A high-speed PCIe bus and a dedicated data stream bus operate in coordination, for example, real-time processing of deviation prediction results from Sp2. The quantum processor transmitted to Sp3 ensures seamless integration of steps. The system integrates the calibration data from Sp1 (deviation ±1nm), the list of weak points from Sp2 (deviation exceeding the standard), the measurement results from Sp3 (linewidth 19.8nm), the overlay view from Sp4 (wafer prediction map), the optimization suggestions from Sp5 (exposure dose 33mJ / cm²), and the compressed data from Sp6 (100GB), outputting a complete analysis report. The holographic visualization engine generates interactive 3D views, such as allowing users to rotate the wafer view with gestures. The overall efficiency is improved from 10 hours in the traditional method to 1 hour. This process adapts to the needs of advanced processes through hardware and software collaboration.

[0049] Step Sp2 further includes the following:

[0050] Temporal convolutional networks extract time-series features from CD-SEM data, and a Transformer architecture captures the spatial correlation of process parameters. An adaptive knowledge distillation mechanism is introduced to dynamically identify measurement deviations, distilling the predictive power of a large model into a smaller one, keeping the prediction error within 0.5 nm. The refinement process begins with input calibrated CD-SEM data, such as linewidth data of 100 key points on a wafer, recording the results of the past 50 measurements, fluctuating between 19.8 nm and 20.2 nm. Simultaneously, process parameters, such as lithography exposure dose varying between 30 mJ / cm² and 35 mJ / cm², are input. The temporal convolutional network analyzes the temporal patterns of these linewidth data through multi-layer convolutional operations. For example, it identifies that the linewidth of a certain point has gradually deviated from the standard value by 20 nm in the last 10 measurements, with an amplitude of 0.1 nm / measurement, and extracts feature vectors reflecting the changing trend. The ransformer architecture analyzes the spatial correlation of process parameters through an attention mechanism. For example, it calculates that when the exposure dose increases by 1 mJ / cm², the linewidth of a certain region shrinks by an average of 0.15 nm, while the linewidth of adjacent regions changes by only 0.05 nm. This generates a high-dimensional feature tensor. The optimal solution introduces an adaptive knowledge distillation mechanism, which learns complex bias patterns by pre-training a deep neural network (e.g., a large model with 20 convolutional and fully connected layers). The knowledge is then dynamically distilled into a lightweight model (e.g., a 5-layer network). The distillation process is updated based on real-time data. For example, when the bias prediction at a certain point is adjusted from 0.6 nm to 0.4 nm, the distillation weights are automatically adjusted to keep the error below 0.5 nm. This process is achieved through a multi-core TPU array of an AI inference accelerator, which can process 1 billion feature calculations per second, ensuring real-time performance and significantly outperforming the prediction accuracy of traditional static models (which typically have an error of more than 1 nm).

[0051] Step Sp3 further includes the following:

[0052] Based on the quantum annealing optimization algorithm, the measurement path of multi-MP data is optimized through a quantum parallel measurement scheduler. When adjusting AMP parameters, the relationship between beam intensity and scanning speed is dynamically balanced, reducing the repetitive measurement rate by 40%. The refinement process begins with a list of weak points received from Sp2. For example, among 200 measurement points on the wafer, 50 points have a linewidth deviation exceeding 0.5 nm. The quantum annealing optimization algorithm transforms these measurement tasks into quantum bit states, for example, using 100 qubits to represent the parameter combination of the 200 points (each bit encodes a state of beam intensity or scanning speed). The parameter space is explored through quantum tunneling to find the global optimum, for example, with the beam intensity set to 16 nA and the scanning speed to 1.6 mm / s. The quantum parallel measurement scheduler further optimizes the path, for example, dividing 200 points into 4 parallel groups of 50 points each, planning the shortest scanning path, such as scanning sequentially from the center of the wafer to the edge, avoiding time waste caused by repeated paths. The optimal scheme dynamically balances the beam intensity and scanning speed. For example, when the beam intensity increases from 15nA to 16nA, the scanning speed is adjusted from 1.5mm / s to 1.6mm / s, ensuring that the resolution does not decrease while reducing the scanning time. The repetitive measurement rate is reduced from 20% to 12%. This process is supported by the quantum computing processor, and the built-in quantum annealing acceleration module increases the computing speed by 50 times. For example, a task that would take 120 seconds in the traditional method is shortened to 40 seconds, significantly improving measurement efficiency.

[0053] Step Sp4 further includes the following:

[0054] A cross-scale dynamic convolution method integrates a real-time lithography reverse modeler, utilizing partial differential equations and Monte Carlo methods to calculate edge roughness and mask offset during the lithography process. This generates a process deviation heatmap for overlay analysis and uses virtual wafer simulation technology to generate a predicted view of the complete wafer's measurement results. Areas exceeding deviation limits are marked with color gradients. The refinement process begins with receiving measurement data from Sp3. For example, if the measured gate width is 19.7nm and the layout design value is 20nm, the cross-scale dynamic convolution method fuses data using adaptive convolution kernels. For instance, a 5x5 convolution kernel is used to extract pixel-level features for nanometer-level details at the gate edge, while a 15x15 convolution kernel is used to capture the overall deviation distribution for the wafer-level structure. By fusing SEM images, layout geometry, and lithography simulation results, an overlay view is generated for real-time lithography. The reverse modeler uses partial differential equations to calculate the diffusion behavior of photoresist after exposure, such as predicting that the photoresist thickness in a certain area will decrease from 50nm to 48nm. Combined with the Monte Carlo method to simulate the photon scattering path, for example, after 1000 photon scatterings, the edge roughness increases to 1.8nm and the mask offset reaches 1.2nm, generating a deviation heatmap. The preferred scheme uses virtual wafer simulation technology to predict the deviation distribution of 5000 points on a 300mm wafer. For example, the linewidth deviation in a certain area increases from 0.5nm to 0.9nm. The view marks areas with deviations exceeding 0.6nm in red, areas from 0.4nm to 0.6nm in yellow, and normal areas in green. The accelerator of the high-performance GPU cluster reduces the fusion calculation time from 2 seconds to 1 second. This process provides a high-precision process analysis view.

[0055] Step Sp5 further includes the following:

[0056] The Generative Adversarial Network (GAN) predicts the deviation distribution of the next 1000 wafers through adversarial learning. It introduces multi-process collaborative analysis to integrate lithography, etching, and deposition process data to generate mask design optimization parameters. Through reinforcement learning and a weak point tracker, it generates mask modification schemes and lithography adjustment suggestions, reducing yield loss by more than 5%. The refinement process starts with the deviation heatmap of the input Sp4. For example, the linewidth deviation of a certain region is 0.7nm. Historical data includes the lithography dose (32mJ / cm² to 34mJ / cm²), etching rate (0.1nm / s), and deposition thickness (50nm) of the past 200 wafers. The GAN generator predicts the deviation trend of the next 1000 wafers. For example, the linewidth deviation may increase from 0.7nm to 1nm. At 1nm, the discriminator optimizes prediction accuracy by comparing with historical data. Multi-process collaborative analysis integrates data; for example, it finds that an increase of 1mJ / cm² in the exposure dose leads to an amplification of etching deviation by 0.2nm, generating mask optimization parameters, such as adjusting the linewidth from 20nm to 20.3nm. Reinforcement learning adjusts process parameters according to the deviation distribution, such as optimizing the exposure dose from 33mJ / cm² to 34mJ / cm² and adjusting the etching depth from 49nm to 47nm. The weak point tracker locates areas with excessive deviation, such as a linewidth deviation of 1nm at the wafer edge, generating mask modification schemes (such as widening the edge by 0.2nm) and lithography suggestions (such as extending the exposure time by 5%). This process reduces yield loss from 6% to 1%, significantly improving process stability.

[0057] Step Sp6 further includes the following:

[0058] The distributed data compression algorithm removes redundant pixels from SEM images through sparse coding and enhances compression stability by incorporating a quantum entanglement-inspired error correction mechanism. A streaming computing framework updates data backups every second to ensure zero data loss and generates 3D holographic visualization results. The refinement process begins with overlay data from the input Sp4 layer, such as a 2000-point SEM image on a wafer, totaling 2TB of data. Sparse coding analyzes image pixels; for example, it identifies background regions with grayscale value changes less than 3% (e.g., from 50 to 51) and removes them, retaining only edge features. The algorithm then incorporates a quantum entanglement-inspired error correction mechanism through quantum state correction. The system recovers critical details lost during compression, such as restoring the pixel value of a linewidth edge from a missing state to the correct value of 255. The compressed data size is reduced to 200GB. The streaming computing framework backs up the compressed data to a high-speed SSD every second, for example, automatically saving it when processing the 1000th image, ensuring that the data can be recovered after an unexpected interruption. The holographic projection device generates a 3D view, such as displaying a three-dimensional structure with a deviation of 0.8nm in a certain area of ​​a wafer. Users can rotate the view to view details using a gesture sensor. This process is accelerated by the data compression coprocessor, reducing the compression time from 15 minutes to 3 minutes, resulting in a significant improvement in efficiency.

[0059] Step Sp7 further includes the following:

[0060] The quantum-classical hybrid architecture optimizes AMP parameter tuning and multi-MP measurements through a quantum computing module, while classical computing units handle data compression and visualization. It supports analysis at 5nm and below process nodes and generates 3D holograms with gesture interaction, improving efficiency by more than 100 times. The refinement process begins with coordinating Sp1 to Sp6. The quantum computing module handles Sp3 tasks, such as optimizing the beam intensity of 300 measurement points to 17nA, while classical computing units handle Sp6 compression tasks, such as compressing 3TB of data to 300GB. High-speed PCIe bus interconnect hardware is also included. The deviation prediction results of Sp2 are transmitted to the quantum processor of Sp3, reducing the time from 0.5 seconds to 0.1 seconds. The system integrates the results of all steps, such as the calibration data of Sp1 (deviation ±1nm), the overlay view of Sp4 (5000-point prediction map), and the optimization suggestions of Sp5 (exposure dose 34mJ / cm²), to generate an analysis report. The holographic visualization engine generates a 3D view. For example, users can zoom in on the central area of ​​the wafer with gestures to view the details of a deviation of 0.9nm. The overall analysis time is reduced from 12 hours to 1 hour. This process supports the complex analysis needs of the 5nm process node. Specific Implementation Example 2:

[0062] like Figures 1 to 4 As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0063] Preferably, the hardware components of the system include:

[0064] The data acquisition unit is equipped with a high-speed SSD memory and a multi-channel data interface, which is used to receive CD-SEM measurement data files and any one of the layout files of GDSII / OASIS in real time in step Sp1, and supports high-speed loading of TB-level data.

[0065] The quantum computing processor has a built-in quantum annealing acceleration module, which is used to execute the quantum annealing optimization algorithm in step Sp3. It achieves parallel computing of multi-MP data through quantum bit state decomposition, and the processing speed is 50 times faster than that of traditional processors.

[0066] A high-performance GPU cluster, with an integrated adaptive convolution kernel accelerator, is used to perform a cross-scale dynamic convolution method in step Sp4, reducing the computation time for fusing SEM images and map data to less than 1 second.

[0067] The holographic projection device, equipped with an augmented reality display module, is used to generate 3D holographic visualization results of wafer-level deviations in step Sp6, and supports gesture recognition sensors to achieve interactive analysis;

[0068] The aforementioned hardware components are interconnected via a high-speed PCIe bus and operate in conjunction with the quantum-classical hybrid architecture described in step Sp7.

[0069] The data acquisition unit is equipped with high-speed SSD storage and multi-channel data interfaces, supporting transmission rates of up to 10Gbps. It can receive 3TB CD-SEM data and GDSII files from Sp1 in real time, reducing loading time from 20 minutes to 4 minutes. The quantum computing processor has a built-in quantum annealing acceleration module, containing 512 qubits, which executes optimized tasks for Sp3, reducing the time to process 300 measurement points from 60 seconds to 20 seconds, a 50-fold speed improvement. The high-performance GPU cluster integrates an adaptive convolution kernel accelerator, containing 16 GPU cores, which processes 5000-point fused data for Sp4, reducing computation time from 3 seconds to 1 second. The holographic projection device is equipped with an augmented reality display module, with a resolution of 4K, supporting the generation of 3D views of 300mm wafers for Sp6. The gesture sensor recognizes rotational movements with a response time of less than 0.1 seconds. The hardware is interconnected via a high-speed PCIe bus, with a bandwidth of up to 32GB / s, and works in conjunction with the hybrid architecture of Sp7 to ensure seamless integration of processes. Specific Implementation Example 3:

[0071] like Figures 1 to 4 As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0072] Based on the content of the above specific embodiments one and two, the entire system is applied to actual production, including the following:

[0073] Application Case 1: Key Dimension Optimization in 5nm Logic Chip Manufacturing

[0074] In a semiconductor fab producing 5nm logic chips, the MetroAnalyzer system was used to optimize critical dimension control of gate width on wafers to improve chip performance and yield. On the production line, a CD-SEM device generated measurement data files containing 500 gate locations, totaling 2TB in size. These files recorded linewidth data from the past 50 wafers; for example, the gate width in a certain region fluctuated between 19.6nm and 20.4nm. Simultaneously, corresponding GDSII layout files were imported from the design database, with a standard linewidth defined as 20nm. The data acquisition unit loaded these files in real-time via high-speed SSD memory and a multi-channel data interface. Using a feature-point matching-based preprocessing algorithm, the pixel offset between the SEM image and the layout was calculated. For example, if a region was found to have an X-axis offset of 1.8nm and a Y-axis offset of 1.2nm, the system automatically calibrated to within ±1nm of the deviation. Next, the multi-core TPU array of the AI ​​inference accelerator initiates a multi-dimensional feature embedding method. A temporal convolutional network analyzes the temporal changes in linewidth data; for example, the linewidth at a certain point gradually deviates from 20nm to 0.3nm in the most recent 10 wafers. The Transformer architecture captures the spatial correlation of exposure doses (from 32mJ / cm² to 34mJ / cm²), for example, an increase of 1mJ / cm² in dose results in a 0.2nm reduction in linewidth. An adaptive knowledge distillation mechanism optimizes the prediction model to within 0.5nm of error, identifying 50 deviation points (e.g., 0.7nm). The quantum computing processor then intervenes, using a quantum annealing optimization algorithm to adjust AMP parameters, such as optimizing the beam intensity from 15nA to 16nA and the scanning speed from 1.5mm / s to 1.6mm / s. A quantum parallel scheduler optimizes the measurement path, processing the batch measurements of these 50 points, reducing the time from 90 seconds to 30 seconds and lowering the repeatability rate to 12%. A high-performance GPU cluster fuses SEM images, layout data, and lithography simulation results using a cross-scale dynamic convolution method. For example, given a gate diameter of 19.7nm (measured) and a design diameter of 20nm, an overlay view is generated. A real-time lithography reverse modeler calculates an edge roughness of 1.5nm and a mask offset of 1nm. Virtual wafer simulation predicts the deviation distribution of the complete wafer, highlighting areas with deviations exceeding 0.6nm in red. A process trend generative adversarial network predicts the linewidth trend of the next 1000 wafers; for example, the deviation might increase to 1nm. Reinforcement learning adjusts the exposure dose to 33.5mJ / cm², and a weak point tracker suggests widening the mask linewidth by 0.2nm, reducing yield loss from 5% to 1.5%. Finally, a distributed data compression algorithm compresses 2TB of data to 200GB, a holographic projection device generates a 3D deviation view, and engineers can zoom in on problem areas using gestures. A quantum-classical hybrid architecture integrates the results, outputs an optimization plan, and feeds it back into the production process. The entire process is reduced from 12 hours to 1 hour, and the gate width control accuracy is significantly improved.

[0075] Application Case 2: Improving Aperture Consistency in Memory Chip Manufacturing

[0076] In a factory manufacturing 3D NAND flash memory chips, the MetroAnalyzer system was deployed to improve the consistency of aperture sizes in memory cells on wafers, ensuring high-density storage performance. The factory used a CD-SEM device to generate a 1.5TB measurement data file containing 1000 apertures. For example, the aperture diameter in a certain area fluctuated between 49.5nm and 50.5nm, with a design target of 50nm. OASIS layout files were also imported. The data acquisition unit loaded the data via a 10Gbps interface and calibrated the coordinates based on a feature point matching algorithm. For instance, if a region was found to be offset by 1.5nm, the system adjusted to within ±1nm. AI-powered multidimensional feature embedding methods analyze historical data, such as the aperture diameter trends of the past 20 wafers, showing a point gradually deviating from 50nm to 0.4nm. The Transformer captures the spatial impact of etching depth (100nm to 102nm), for example, an increase of 1nm in depth results in a 0.1nm decrease in aperture diameter. Adaptive knowledge distillation optimizes the prediction model, controlling the error to within 0.5nm, and marking 30 deviation points (e.g., 0.6nm). A quantum computing processor adjusts AMP parameters through a quantum annealing optimization algorithm, such as setting the beam intensity to 17nA and the scanning speed to 1.7mm / s. The quantum scheduler optimizes the measurement path for 1000 points, reducing the time from 120 seconds to 40 seconds and the repeatability rate from 18% to 10%. A high-performance GPU cluster integrates SEM images, layout geometry, and lithography simulation data. For example, with a measured aperture of 49.6nm, the reverse modeler calculates an edge roughness of 2nm, and virtual wafer simulation generates a predictive view, marking areas with deviations of 0.4nm to 0.6nm in yellow. A process trend generative adversarial network predicts the aperture trend of the next 500 wafers, for example, the deviation may increase to 0.8nm. Multi-process collaborative analysis integrates etching and deposition data (deposition thickness 51nm), reinforcement learning adjusts the etching depth to 101nm, and the tracker suggests widening the layout aperture by 0.1nm, improving yield by 3%. A distributed data compression algorithm compresses 1.5TB of data to 150GB, a streaming computing framework backs up data every second, a holographic projection device generates a 3D view, and engineers can view the aperture distribution by rotating the image with gestures. The hybrid architecture outputs optimization reports, which are fed back to the production line. Aperture consistency is improved from ±0.5nm to ±0.3nm, and analysis time is reduced from 10 hours to 50 minutes.

[0077] Application Case 3: Contact Point Deviation Analysis in Advanced Packaging

[0078] In a company specializing in advanced packaging (such as CoWoS), the MetroAnalyzer system is used to analyze contact point deviations on wafers to optimize package reliability. The CD-SEM device generates a measurement data file containing 300 contact points, totaling 800GB in size. For example, the contact point diameter fluctuates between 29.8nm and 30.2nm, with a target value of 30nm, along with a GDSII layout file. The data acquisition unit loads the data, and a feature point matching algorithm calibrates the offset; for example, if a point's X-axis offset is 1nm, it is adjusted to ±1nm. An AI feature embedding method analyzes historical data; for example, diameter changes over the past 30 wafers show a deviation of 0.3nm at a certain point. The Transformer captures the correlation of deposition thickness (20nm to 22nm); for example, an increase of 1nm in thickness results in a 0.1nm decrease in diameter, with prediction deviation controlled within 0.5nm, and 20 out-of-target points are marked. A quantum computing processor optimizes AMP parameters, such as beam intensity of 16.5nA and scan speed of 1.8mm / s, while the scheduler optimizes the path, reducing the time from 60 seconds to 20 seconds. High-performance GPU clusters fuse data; for example, a measured thickness of 29.7nm at a certain point is used. A reverse modeler calculates a mask offset of 1.1nm, and the simulation view highlights areas with deviations exceeding 0.6nm in red. A generative adversarial network predicts the trends of the next 200 wafers; for example, if the deviation increases to 0.7nm, reinforcement learning adjusts the deposition thickness to 21nm, and a tracker suggests widening the layout diameter by 0.1nm, improving yield by 2%. Data compression algorithms compress 800GB to 80GB, holographic projection generates 3D views, engineers view details via gestures, and a hybrid architecture outputs optimized solutions. Contact point deviation is optimized from ±0.4nm to ±0.2nm, and analysis time is reduced from 6 hours to 30 minutes.

[0079] In summary, these case studies demonstrate the application of MetroAnalyzer in 5nm logic chips, 3D NAND flash memory, and advanced packaging. Through high-precision calibration (±1nm), efficient metrology (time reduced to 1 / 3), intelligent optimization (yield improvement of 2%-5%), and rapid analysis (efficiency improvement of 100 times), it significantly improves the process control capabilities of semiconductor manufacturing and verifies the practicality and advancement of the technical solutions.

[0080] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a reference structure" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0081] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A MetroAnalyzer software system that integrates CD-SEM and GDSII / OASIS for layout measurement and analysis, characterized in that: The system includes the following steps: Sp1: Loads CD-SEM measurement data files and GDSII / OASIS layout files, calculates the pixel offset between the SEM image and the layout through a multi-source data synchronization preprocessing algorithm based on feature point matching, and automatically calibrates the coordinate system deviation to within ±1nm; Sp2: Utilizing a multi-dimensional feature embedding method that combines temporal convolutional networks and Transformer architecture, spatial-temporal features are extracted from historical CD-SEM data and process parameters. The prediction model dynamically identifies measurement deviations and marks process weaknesses where the deviations exceed a set threshold. Sp3: Based on the quantum annealing optimization algorithm, the AMP parameters are adjusted, the multi-MP data is decomposed into quantum bit states for parallel computation, the beam intensity and scanning speed are optimized, batch measurement is realized, and the measurement time of a single measurement is reduced to 1 / 3 of the traditional method; Sp4: Employs a cross-scale dynamic convolution method based on adaptive convolution kernels to fuse nanoscale details of SEM images, geometric structures of GDSII / OASIS layouts, and deviation distributions from lithography simulations, generating overlay analysis results from the nanoscale to the wafer level. Sp5: Generates an adversarial network based on process trends, uses the generator and discriminator to learn adversarial learning to predict the future wafer deviation distribution trend, and adjusts the exposure dose and etching depth based on reinforcement learning algorithm to form a closed-loop optimization scheme. Sp6: Employs a distributed data compression algorithm based on sparse coding to compress TB-level SEM image data to 10% of its original size, and generates 3D holographic visualization results with wafer-level deviations through augmented reality technology; Sp7: Through a hybrid architecture of quantum computing modules and classical computing units, the above steps Sp1 to Sp6 are executed in a coordinated manner to form a closed-loop analysis process from data calibration and deviation prediction to process optimization.

2. The MetroAnalyzer software according to claim 1, which integrates CD-SEM and GDSII / OASIS for layout measurement and analysis, is characterized in that: In step Sp2, the multi-dimensional feature embedding method extracts the time-series features of CD-SEM data through a temporal convolutional network, captures the spatial correlation of process parameters through a Transformer architecture, and introduces an adaptive knowledge distillation mechanism when dynamically identifying measurement deviations, distilling the predictive power of the large model into the small model, so that the prediction deviation error is controlled within 0.5nm.

3. The MetroAnalyzer software according to claim 1, which integrates CD-SEM and GDSII / OASIS for layout measurement and analysis, is characterized in that: In step Sp3, the quantum annealing optimization algorithm optimizes the measurement path of multi-MP data through a quantum parallel measurement scheduler, and dynamically balances the relationship between beam intensity and scanning speed when adjusting AMP parameters.

4. The MetroAnalyzer software according to claim 1, which integrates CD-SEM and GDSII / OASIS layout measurement and analysis system, is characterized in that: In step Sp4, the cross-scale dynamic convolution method integrates a real-time lithography reverse modeler, uses partial differential equations and Monte Carlo methods to calculate edge roughness and mask offset during the lithography process, and generates a process deviation heatmap for overlay analysis. The cross-scale dynamic convolution method uses virtual wafer simulation technology to generate a complete wafer measurement result prediction view based on the fused overlay data, and marks areas in the view where the global process consistency deviation exceeds a set threshold with color gradients.

5. The MetroAnalyzer software according to claim 1, which integrates CD-SEM and GDSII / OASIS for layout measurement and analysis, is characterized in that: In step Sp5, the process trend generative adversarial network predicts the deviation distribution of the next 1000 wafers through adversarial learning, and introduces multi-process collaborative analysis into the closed-loop optimization scheme. It integrates data from lithography, etching, and deposition processes to generate optimization parameters for mask design. The closed-loop optimization scheme dynamically adjusts process parameters through reinforcement learning and introduces a process weakness tracker to generate mask layout modification schemes and lithography condition adjustment suggestions based on the deviation distribution.

6. The MetroAnalyzer software according to claim 1, which integrates CD-SEM and GDSII / OASIS for layout measurement and analysis, is characterized in that: The distributed data compression algorithm in step Sp6 removes redundant pixels from the SEM image through sparse coding and improves compression stability by combining a quantum entanglement-inspired error correction mechanism. The data backup is updated every second through a streaming computing framework to ensure zero data loss during data processing.

7. The MetroAnalyzer software according to claim 1, which integrates CD-SEM and GDSII / OASIS for layout measurement and analysis, is characterized in that: The quantum-classical hybrid architecture described in step Sp7 optimizes AMP parameter adjustment and multi-MP measurement through a quantum computing module, processes data compression and visualization through a classical computing unit, supports analysis of process nodes at 5nm and below, and generates 3D holograms that support gesture interaction through a holographic visualization engine.

8. A layout measurement and analysis system integrating CD-SEM and GDSII / OASIS software as described in claims 1-7, characterized in that: The hardware components of the system include: The data acquisition unit is equipped with a high-speed SSD memory and a multi-channel data interface, which is used to receive CD-SEM measurement data files and any one of the layout files of GDSII / OASIS in real time in step Sp1, and supports high-speed loading of TB-level data. The quantum computing processor has a built-in quantum annealing acceleration module, which is used to execute the quantum annealing optimization algorithm in step Sp3 and realize the parallel computing of multi-MP data through quantum bit state decomposition. A high-performance GPU cluster, with an integrated adaptive convolution kernel accelerator, is used to perform a cross-scale dynamic convolution method in step Sp4, reducing the computation time for fusing SEM images and map data to less than 1 second. The holographic projection device, equipped with an augmented reality display module, is used to generate 3D holographic visualization results of wafer-level deviations in step Sp6, and supports gesture recognition sensors to achieve interactive analysis.

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