AI adaptive hierarchical collaborative SOC chip verification method

Abstract

This invention provides an AI-adaptive hierarchical collaborative SOC chip verification method, belonging to the field of chip verification and testing technology. The method includes: configuring a verification parameter set adapted to the target SOC chip's scenario attribute information; initially hierarchically layering the target SOC chip to obtain an abstract precision model for each module; injecting faults into the target SOC chip using fault injection parameters; performing multi-mode collaborative verification based on the abstract precision model to obtain collaborative verification results; subsequently analyzing the collaborative verification results to generate verification deviation results; then generating strategy adjustment instructions through AI adaptive decision-making, including abstract hierarchical precision adjustment instructions and / or fault injection adjustment instructions; adjusting the abstract precision model and / or adjusting the fault injection parameters, followed by iterative verification until the verification target is achieved. The beneficial effects are improved solution versatility and scenario matching, enhanced verification targeting, and a balance between verification accuracy and efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip verification and testing technology, and in particular to an AI-adaptive hierarchical collaborative SOC chip verification method. Background Technology

[0002] As semiconductor processes evolve toward advanced nodes, the integration of SOC chips is increasing exponentially. They generally contain a variety of heterogeneous IP cores and are widely used in automotive-grade, 5G communication, AI computing and other fields, facing multiple verification requirements such as functional safety, low power consumption and high reliability.

[0003] Currently, mainstream technologies for SOC chip verification include hybrid simulation verification, cloud simulation verification, hierarchical abstraction verification, and AI-assisted verification. Among these, hierarchical abstraction verification often employs fixed abstraction precision (black box, full-detail abstraction) to simplify the verification process through relevant abstraction models. AI-assisted verification technologies tend to focus on single stages and fail to achieve full-process collaboration. All existing technologies operate through a "fixed strategy + multi-stage independent verification" model, relying heavily on single or simple combinations of verification methods, making them ill-suited for the verification needs of ultra-large-scale, multi-scenario SOC chips. The core issues and reasons related to this technical solution are as follows:

[0004] 1. The contradiction between accuracy and speed in layered verification is prominent: black-box abstraction verification is efficient, but it is easy to miss core defects inside the module; fully flat verification is accurate, but it consumes huge resources and has a long verification cycle; the existing abstract model lacks the ability to adapt and adjust in real time and cannot dynamically switch the abstraction accuracy according to the verification feedback. The root cause is the lack of a flexible layered abstraction mechanism, which makes it difficult to balance verification efficiency and accuracy.

[0005] 2. Fragmented AI applications and insufficient end-to-end collaboration: Existing AI-assisted verification does not achieve end-to-end collaboration in terms of layering, fault injection, result analysis, and strategy optimization. It has not built an AI-driven closed-loop verification system. Each verification link is independent of each other, data cannot be effectively reused, and it is impossible to generate targeted verification strategy adjustment instructions based on AI adaptive decision-making based on feedback data during the verification process.

[0006] 3. Poor adaptability to multiple scenarios and strong blindness in fault injection: The verification requirements of SOC chips in different scenarios such as automotive-grade and AI accelerators are different. However, the existing technology has not designed a scenario-based adaptation module, and cannot configure a set of verification parameters (including fault injection parameters) that are compatible with the scenario attribute information of the target SOC chip. At the same time, fault injection lacks specificity, does not optimize the injection strategy in combination with scenario requirements, and cannot dynamically adjust the fault injection parameters according to the verification deviation results, resulting in low verification efficiency and difficulty in improving coverage.

[0007] 4. Fixed verification strategy and lack of closed-loop iteration capability: Existing technologies adopt fixed verification strategies. After completing a round of verification and obtaining results, they cannot automatically adjust relevant parameters and iterate again based on the verification deviation results. They need to rely on manual intervention to adjust, which makes it difficult to quickly achieve the preset target of verification results and results in low verification efficiency.

[0008] Therefore, there is an urgent need for a SOC chip verification method that is adaptable to multiple scenarios, dynamically adjustable, and has full-process collaborative capabilities, in order to solve the technical pain points of existing technologies such as unadjustable abstract precision, fragmented AI applications, insufficient scenario adaptability, and lack of closed-loop iteration, and achieve a dual improvement in verification efficiency and verification quality. Summary of the Invention

[0009] To address the problems existing in the prior art, this invention provides an AI-adaptive hierarchical collaborative SOC chip verification method, comprising: Step S1, configuring a verification parameter set adapted to the target SOC chip's scenario attribute information, and performing initial hierarchical analysis on the target SOC chip to obtain an abstract precision model for each module therein, wherein the verification parameter set includes a verification target and fault injection parameters; Step S2, performing fault injection on the target SOC chip using the fault injection parameters, and performing multi-mode collaborative verification based on the abstract precision model to obtain a collaborative verification result, subsequently analyzing the collaborative verification result based on the verification target to generate a verification deviation result; Step S3, generating a strategy adjustment instruction through AI adaptive decision-making based on the verification deviation result, wherein the strategy adjustment instruction includes an abstract hierarchical precision adjustment instruction and / or a fault injection adjustment instruction; Step S4, adjusting the abstract precision model according to the abstract hierarchical precision adjustment instruction, and / or adjusting the fault injection parameters according to the fault injection adjustment instruction, and then returning to Step S2, until the collaborative verification result reaches the verification target.

[0010] Preferably, before executing step S1, a template library is pre-built, which stores verification scenario templates with different scenario attribute information. Step S1 includes: Step S11, matching the verification scenario template that matches the scenario attribute information of the target SOC chip from the template library, and extracting the corresponding verification target, high-risk module list, and abstract layering rules from the matched verification scenario template; Step S12, obtaining the design attribute information of the target SOC chip, updating the high-risk module list based on the design attribute information to obtain an updated high-risk list, and adaptively fine-tuning the abstract layering rules to obtain the abstract precision model of the target SOC chip; Step S13, configuring targeted injection parameters for each high-risk module in the updated high-risk list, configuring full-coverage injection parameters for the remaining modules, and adding the targeted injection parameters and the full-coverage injection parameters as fault injection parameters to the verification parameter set.

[0011] Preferably, the fault injection parameters include fault injection type and its corresponding injection density, and the injection density of the targeted injection parameters is higher than the injection density of the full coverage injection parameters.

[0012] Preferably, the verification modes of the multi-mode collaborative verification include prototype verification, formal verification, and simulation verification, and the corresponding collaborative verification results include multiple sub-item verification coverage rates under each verification mode; the verification target includes a single module coverage threshold and a full chip target coverage rate; in step S2, the process of generating verification deviation results includes: step S21, for each module in the target SOC chip, weighted summation of each sub-item verification coverage rate to obtain the corresponding single module comprehensive coverage rate, and then weighted summation of the single module comprehensive coverage rates of all modules to obtain the full chip coverage rate of the target SOC chip; step S22, comparing each single module comprehensive coverage rate with each single module coverage threshold, the full chip coverage rate with the full chip target coverage rate, and when any single module comprehensive coverage rate is lower than the single module coverage threshold, or the full chip coverage rate is lower than the full chip target coverage rate, the coverage deviation of the corresponding low item and the corresponding fault distribution data are taken as the verification deviation results.

[0013] Preferably, the verification target further includes a resource occupancy threshold, and the corresponding verification deviation result further includes real-time resource occupancy statistics. Step S1 further includes allocating verification computing power resources to each module of the target SOC chip according to preset rules. Step S2 further includes statistically analyzing the real-time occupancy rate of each verification resource in the entire single-round multi-mode collaborative verification process, and performing a weighted average of each real-time occupancy rate to obtain an average occupancy rate. Then, when the average occupancy rate exceeds the resource occupancy threshold, the real-time resource occupancy statistics are output. Step S3 includes the strategy adjustment instruction further including a computing power adjustment instruction. Step S4 further includes adjusting the verification computing power of each module according to the computing power adjustment instruction.

[0014] Preferably, in step S4, adjusting the abstract precision model includes: step A1, for each module in the target SOC chip, determining the upgradable precision level of the module based on the module's risk level, single-module coverage deviation, and preset precision improvement trigger conditions; step A2, determining whether the average occupancy rate exceeds the resource occupancy threshold: if yes, reducing the abstract precision of non-critical modules of the target SOC chip to release resources; if no, increasing the abstract precision of the corresponding module to the upgradable precision level.

[0015] Preferably, the fault injection parameters include fault injection type and its corresponding injection density; in step S4, adjusting the fault injection parameters includes: step B1, for each module in the target SOC chip, when the risk level of the module, the single module coverage deviation, the corresponding fault distribution data, and the average occupancy rate only meet the adjustment conditions for a single fault injection type, generating an injection type adjustment signal; when only the adjustment conditions for a single injection density are met, generating an injection density adjustment signal; and when the adjustment conditions for two parameters are met, generating a synchronous adjustment signal for the fault injection type and its corresponding injection density; step B2, executing an injection type adjustment strategy according to the injection type adjustment signal and the synchronous adjustment signal, the injection type adjustment strategy including determining the fault type with the highest proportion based on the fault distribution data as a high-priority injection type, and / or matching a preset high-priority injection type based on the function of the module, and / or matching a preset high-priority injection type based on the application scenario of the target SOC chip; step B3, executing an injection density adjustment strategy according to the injection density adjustment signal and the synchronous adjustment signal, the injection density adjustment strategy including using the product of the base injection density and the adjustment coefficient as the adjusted injection density, wherein: the adjustment coefficient = K = 1 + (1 + coverage deviation) × module risk weight.

[0016] Preferably, in step S4, the verification computing power adjustment includes: step C1, for each module in the target SOC chip, configuring computing power priority for the module according to the module's risk level, coverage deviation, current verification progress, and current verification resource occupancy reserve; step C2, on the premise that the total resource occupancy rate does not exceed the resource occupancy threshold, reclaiming the computing power of the module with lower computing power priority and adding it to the computing power of the module with higher computing power priority.

[0017] Preferably, it further includes a pre-built artificial intelligence model cluster, including a reinforcement learning decision engine, a hierarchical abstract decision sub-model, a fault injection optimization sub-model, and a resource scheduling optimization sub-model; the policy adjustment instruction also includes a resource allocation adjustment instruction; step S3 includes: step S31, based on the verification deviation result, calling the hierarchical abstract decision sub-model, the fault injection optimization sub-model, and the resource scheduling optimization sub-model respectively to generate abstract hierarchical accuracy suggestions, fault injection adjustment suggestions, and resource scheduling optimization suggestions; step S32, inputting the verification deviation result, the abstract hierarchical accuracy suggestions, the fault injection adjustment suggestions, the resource scheduling optimization suggestions, the verification parameter set, the abstract accuracy model obtained from the initial hierarchical layer, and the current verification iteration information into the reinforcement learning decision engine for fusion processing, so as to generate the abstract hierarchical accuracy adjustment instruction, and / or the fault injection adjustment instruction, and / or the resource allocation adjustment instruction.

[0018] Preferably, the artificial intelligence model cluster further includes a timing prediction and optimization sub-model; step S3 further includes statistically analyzing the power domain parameters of the target SOC chip and the timing-related data of each module, and calling the timing prediction and optimization sub-model to perform timing risk prediction and timing deviation analysis, thereby generating timing optimization suggestions; in step S32, the timing optimization suggestions are also synchronously input into the reinforcement learning decision engine for fusion processing, and the reinforcement learning decision engine also generates timing constraint optimization suggestions for the target SOC chip according to the decision, for designers to refer to.

[0019] The above technical solution has the following advantages or beneficial effects:

[0020] 1) By adapting the scenario attribute configuration to the verification parameter set and the initial abstract precision model, it can adapt to the SOC chip verification requirements of different application scenarios, get rid of the limitations of fixed verification strategies, improve the versatility and scenario matching of the solution, avoid blind fault injection from the source, and improve the verification targeting.

[0021] 2) The use of an abstract precision model to support multi-mode collaborative verification can balance verification accuracy and verification efficiency, alleviate the contradiction in traditional hierarchical verification that high precision leads to slowness and high efficiency leads to missed detections, and improve overall operational efficiency while ensuring verification completeness.

[0022] 3) By dynamically optimizing the hierarchical accuracy and fault injection strategy, a closed-loop iterative mechanism of verification, analysis, decision-making, adjustment, and re-verification is constructed, which eliminates the need for frequent manual intervention and significantly improves the level of automation and intelligence in verification.

[0023] 4) Through iterative adaptive adjustment, it can continuously approach and reach the preset verification target, effectively improve the verification completeness and fault coverage, reduce defect omissions, accelerate the verification convergence speed, and improve the overall quality and efficiency of SOC chip verification.

[0024] 5) Integrate scenario adaptation, layered abstraction, collaborative verification, fault injection, and AI adaptive adjustment into a whole to form a full-process collaborative verification system, breaking the fragmented state of independent operation of each link, and realizing effective data reuse and global strategy optimization. Attached Figure Description

[0025] Figure 1 A flowchart illustrating an AI adaptive hierarchical collaborative SOC chip verification method is shown in a preferred embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of a sub-process of step S1 in a preferred embodiment of the present invention.

[0027] Figure 3 This is a schematic diagram illustrating the process of generating verification deviation results in a preferred embodiment of the present invention.

[0028] Figure 4 This is a flowchart illustrating the process of adjusting the abstract precision model in a preferred embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram of the process for adjusting fault injection parameters in a preferred embodiment of the present invention.

[0030] Figure 6 This is a schematic diagram of the process for verifying computing power adjustment in a preferred embodiment of the present invention;

[0031] Figure 7 This is a schematic diagram of the sub-process of step S3 in a preferred embodiment of the present invention. Detailed Implementation

[0032] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment; other embodiments that conform to the spirit of the present invention may also fall within the scope of the present invention.

[0033] In a preferred embodiment of the present invention, based on the aforementioned problems existing in the prior art, an AI adaptive hierarchical collaborative SOC chip verification method is provided. Through a core architecture of AI adaptive control, dynamic hierarchical abstraction, and multi-mode collaborative verification, a closed-loop verification system is constructed, adaptable to SOC chips in various scenarios such as automotive-grade, AI accelerators, 5G communication, and IoT, balancing verification accuracy, efficiency, and resource utilization. The overall process of this SOC chip verification method is as follows: Figure 1 and Figure 2 As shown, it includes:

[0034] Preliminary preparation stage:

[0035] This includes a pre-built template library containing verification scenario templates with different scenario attribute information. These verification scenario templates are preferably based on the module complexity, historical failure rate, functional safety level, and industry standards of the same type of SOC chip. They include multiple types of templates such as automotive-grade, AI accelerator, 5G base station, and IoT, to achieve rapid scenario adaptation.

[0036] It also includes a pre-built artificial intelligence model cluster, which includes: a reinforcement learning decision engine (main engine), a hierarchical abstract decision sub-model, a fault injection optimization sub-model, a resource scheduling optimization sub-model, and a time series prediction and optimization sub-model. Each model shares data and makes collaborative decisions, forming the core of AI adaptive control. All sub-models are lightweight models and are trained on a dedicated dataset for SOC chip verification.

[0037] Verification phase of the target SOC chip:

[0038] Step S1: Scene adaptation configuration and initial layered modeling

[0039] Configure a set of verification parameters for the target SOC chip that is adapted to its scenario attribute information, and perform initial layering of the target SOC chip to obtain an abstract precision model of each module. The verification parameter set includes verification targets and fault injection parameters; such as Figure 2As shown, this step specifically includes: Step S11, matching verification scenario templates that match the scenario attribute information of the target SOC chip from the template library, and extracting the corresponding verification target, high-risk module list, and abstract layering rules from the matched verification scenario templates; Step S12, obtaining the design attribute information of the target SOC chip, updating the high-risk module list based on the design attribute information to obtain the updated high-risk list, and adaptively fine-tuning the abstract layering rules to obtain the abstract precision model of the target SOC chip; Step S13, configuring targeted injection parameters for each high-risk module in the updated high-risk list, configuring full-coverage injection parameters for the remaining modules, and adding the targeted injection parameters and full-coverage injection parameters as fault injection parameters to the verification parameter set.

[0040] The verification objectives mentioned above include at least single-module coverage thresholds, full-chip target coverage, and resource consumption thresholds. The design attribute information includes netlists, module function definitions, design specifications, and DFMEA reports.

[0041] In this embodiment, the present invention preferably also reserves a manual intervention interface to ensure flexibility. Engineers can manually modify the initial abstraction precision and layering rules of any module to cover the verification requirements of special customized SOCs. Based on this, the initial layering preferably adopts a three-level mechanism: scene template pre-configuration → AI adaptive fine-tuning → manual intervention. The priority of manual configuration is higher than that of AI adaptive fine-tuning, which not only ensures the verification efficiency of the same type of SOC, but also avoids the limitations of fixed layering, and takes into account both universality and customization requirements.

[0042] Specifically, the core of scenario template pre-configuration is the verification scenario template. The template library contains pre-set verification scenario templates for different types of SOCs, such as automotive-grade, AI accelerators, IoT, and 5G base stations. These verification scenario templates are formulated based on prior knowledge such as module complexity, historical failure rate, functional safety level, and industry verification standards for the same type of SOC. For example, in the automotive-grade SOC template, functional safety-related modules are at ASIL-D level by default, with an initial abstraction precision of no less than semi-abstract; in the AI ​​accelerator SOC template, the AI ​​computing core is initially set to full detail abstraction by default.

[0043] AI adaptive fine-tuning is used to achieve chip-level customization with initial layering. During the initialization phase, this invention uses an AI adaptive control module to read the netlist, module function definition, design specification, and DFMEA report of the target SOC chip, and adaptively fine-tunes the rules of the verification scenario template. For example, even among automotive-grade ADAS SOCs, the gate-level scale and protocol complexity of LiDAR interface modules from different manufacturers vary. AI will automatically adjust its initial abstraction level instead of completely copying the template.

[0044] The aforementioned fault injection parameters include the initial fault injection type and its corresponding injection density, and the injection density of the targeted injection parameters is higher than that of the full-coverage injection parameters.

[0045] This invention identifies high-risk modules of a target SOC chip based on a list of high-risk modules and the design attribute information of the target SOC chip, and then injects parameters in a targeted manner, as well as configuring full-coverage injection parameters for the remaining modules.

[0046] Specifically, the high-risk module list preferably includes a pre-set list adapted to the application scenario. For example, the automotive-grade template pre-sets a list of core risk modules such as ASIL-D level modules and multi-power domain switching circuits. In addition, it can also include recognized high-risk modules pre-set based on historical failure big data of similar SOCs. For example, based on publicly available industry data and historical project verification data, in similar automotive-grade ADAS SOCs, the historical failure rate of LiDAR interfaces and power domain switching circuits accounts for more than 60% of all chip failures, and they are recognized as high-risk modules, which can be pre-set in the high-risk module list. At the same time, modules with high functional safety levels, high complexity, and strong correlation with core functions identified by reading the DFMEA (Design Failure Mode and Effects Analysis) report and design specifications of the target SOC chip are also considered as high-risk modules.

[0047] Based on this, targeted injection parameters are configured for high-risk modules, and full-coverage injection parameters are configured for the remaining modules. The configuration rules are as follows: For identified high-risk modules (such as LiDAR interfaces and power domain switching circuits), high-density, multi-type, and multi-round targeted injection is performed to cover extreme scenarios and boundary conditions; for medium- and low-risk modules, baseline density and regular type full-coverage injection is performed to ensure that basic function verification is not missed; the core difference between the two is the injection density, the number of fault types, and the number of injection rounds, rather than no injection at all, to avoid verification blind spots.

[0048] In this invention, a risk scoring quantification mechanism is preferably used to determine the initial injection density. Specifically, the module is first scored on a risk level of 0-10, with scoring dimensions including: historical failure rate, functional safety level, module gate complexity, and correlation with the core functions of the chip. A baseline density is defined: an industry-standard verification benchmark, i.e., 10 faults injected per hour for every 100,000 gates, which can be adaptively adjusted according to the total SOC size. Subsequently, the initial injection density is determined in tiers.

[0049] 1) Risk score ≥ 8 (high risk level): Initial injection density = baseline density × 2.0 times;

[0050] 2) Risk score of 5-7 (medium risk): Initial injection density = baseline density × 1.0;

[0051] 3) Risk score < 5 points (risk level is low): Initial injection density = baseline density × 0.5 times.

[0052] Simultaneously, initial verification computing resources (computing power, memory, storage, and hardware acceleration resources) are allocated to each module according to preset rules. These preset rules can be based on a total computing power of 100%, with an average allocation based on the number of modules and gate size, or based on a preset allocation based on a verification scenario template; no specific limitations are imposed here.

[0053] Step S2: Fault Injection, Multi-Mode Collaborative Verification, and Deviation Generation

[0054] Fault injection parameters are used to inject faults into the target SOC chip, and multi-mode collaborative verification is performed based on an abstract precision model to obtain collaborative verification results. Subsequently, the collaborative verification results are analyzed based on the verification target to generate verification deviation results. Specifically, in this embodiment, the verification modes of multi-mode collaborative verification include prototype verification, formal verification, and simulation verification. The three modes share data and collaborate on tasks. The corresponding collaborative verification results include the coverage of multiple sub-items of verification under each verification mode.

[0055] The simulation verification unit is responsible for functional and timing verification, and the statistical verification coverage includes code coverage, functional coverage, and fault injection trigger rate. The prototype verification unit is responsible for high-fidelity verification in real environment, and the statistical verification coverage includes scenario coverage and real environment fault reproduction rate. The formal verification unit is responsible for mathematical integrity verification, and the statistical verification coverage includes assertion coverage and logic completeness coverage.

[0056] Furthermore, the multi-mode collaborative authentication process adopts a hybrid verification mode that prioritizes parallel processing and supplements serial processing:

[0057] 1) Parallel verification is the primary method: After initial configuration is completed, all modules of the SOC start basic verification tasks synchronously and execute them in parallel to minimize the verification cycle.

[0058] 2) Serial verification as a supplement: For modules with upstream and downstream dependencies, a fixed serial verification order is adopted. The core rules are: first verify the basic support modules such as power management and clock management (the basis for chip operation), and then verify other functional modules; first verify the basic functions of interface modules, and then verify the interaction logic between modules; first verify the core computing modules such as CPU and NPU, and then verify peripheral auxiliary modules.

[0059] The verification priority execution order is: basic support module (power supply, clock) → core computing module (CPU / GPU / AI core) → interaction module (interface, storage controller) → peripheral module (GPIO), taking into account both efficiency and reliability.

[0060] Understandably, high-priority modules are allocated resources and completed full-process verification first, but this does not affect the parallel basic verification of low-priority modules; verification of low-priority modules is only paused when resources are scarce to ensure the protection of high-priority modules.

[0061] Furthermore, high-density targeted injection is performed for high-risk modules, while baseline density injection is performed for medium- and low-risk modules. Fault types include manufacturing defects, timing deviations, open interconnects, and power domain fluctuations, avoiding blind injection.

[0062] For each module, the collaborative verification results include the following four categories:

[0063] 1. Functional verification data, including fault data (location, type, triggering conditions, reproduction steps), test case execution data, code coverage, functional coverage, and assertion coverage;

[0064] 2. Performance verification data, including timing deviation data, power consumption data, transmission latency data, computing power / throughput data, and protocol interaction compliance data;

[0065] 3. Resource usage data, including the CPU computing power utilization, memory utilization, storage utilization, and logic / DSP resource usage of the verification platform;

[0066] 4. Process control data, including verification progress data, verification round data, fault injection data (injection count, type, trigger rate), and scenario coverage data.

[0067] The verification targets include single-module coverage thresholds and full-chip target coverage and resource usage thresholds. The corresponding verification deviation results also include real-time statistics on resource usage. In step S2, such as... Figure 3 As shown, the process of generating verification bias results includes:

[0068] Step S21: For each module in the target SOC chip, the weighted sum of the coverage rates of each sub-item verification is used to obtain the corresponding comprehensive coverage rate of a single module. Then, the weighted sum of the comprehensive coverage rates of all modules is used to obtain the full chip coverage rate of the target SOC chip. Specifically, for the sub-item coverage rates of the same module in the three verification modes, weights are set based on the module's risk level to calculate the comprehensive fault coverage rate of the single module. For example, for high-risk modules, formal verification and simulation verification have higher weights. For the comprehensive coverage rate of all modules, weights are set based on module size and risk level to calculate the comprehensive fault coverage rate of the entire chip.

[0069] Step S22: Compare the overall coverage rate of each single module with the coverage threshold of each single module, and the coverage rate of the whole chip with the target coverage rate of the whole chip. If any single module's overall coverage rate is lower than the single module's coverage threshold, or the whole chip's coverage rate is lower than the target coverage rate of the whole chip, use the coverage deviation of the corresponding low item and the corresponding fault distribution data as the verification deviation result.

[0070] Simultaneously, it also includes the real-time utilization rate of each verification resource (computing power, memory, storage, and hardware acceleration resources) in the entire process of single-round multi-mode collaborative verification, and the weighted average utilization rate of each real-time utilization rate to obtain the average utilization rate. Then, when the average utilization rate exceeds the resource utilization threshold, the real-time statistics of resource utilization are output. The specific rules are preferred as follows: collect the real-time utilization rate of computing power, memory, storage, and hardware acceleration resources of the verification platform at a frequency of 1 time / second; calculate the weighted average utilization rate of the verification round, with the weight being the proportion of resource utilization time of each verification unit.

[0071] Step S3: AI Adaptive Global Decision Generation Strategy Adjustment Instructions

[0072] Based on the verification deviation results, strategy adjustment instructions are generated through AI adaptive decision-making. These instructions include abstract hierarchical precision adjustment instructions, and / or fault injection adjustment instructions, and / or computing power adjustment instructions, and time-constraint optimization suggestions are output. Figure 7As shown, this step specifically includes: Step S31, based on the verification deviation results, calling the hierarchical abstract decision sub-model, fault injection optimization sub-model, and resource scheduling optimization sub-model respectively to generate abstract hierarchical accuracy suggestions, fault injection adjustment suggestions, and resource scheduling optimization suggestions; Step S32, inputting the verification deviation results, abstract hierarchical accuracy suggestions, fault injection adjustment suggestions, resource scheduling optimization suggestions, verification parameter set, abstract accuracy model obtained from initial hierarchical layering, and current verification iteration information into the reinforcement learning decision engine for fusion processing, so as to generate abstract hierarchical accuracy adjustment instructions, and / or fault injection adjustment instructions, and / or resource allocation adjustment instructions; Step S3 also includes statistically analyzing the power domain parameters of the target SOC chip and the timing-related data of each module, and calling the timing prediction and optimization sub-model to perform timing risk prediction and timing deviation analysis, thereby generating timing optimization suggestions; Step S32 also includes synchronously inputting the timing optimization suggestions into the reinforcement learning decision engine for fusion processing, and the reinforcement learning decision engine also generates timing constraint optimization suggestions for the target SOC chip according to the decision, for designers to refer to.

[0073] Specifically, the inputs and outputs of each artificial intelligence model are defined as follows:

[0074] 1. The core main model is a reinforcement learning decision engine.

[0075] Core function: The overall decision-making of the global verification strategy, coordinating the output of all sub-models, outputting the final adjustment instructions, and achieving the optimal solution for global verification efficiency and coverage;

[0076] Input data:

[0077] Full chip / single module coverage, faults, resource usage, and performance data;

[0078] Output results of each specific sub-model;

[0079] Preset parameters, thresholds, and scene requirements for scene adaptation templates;

[0080] Verify progress, rounds, and historical iteration data;

[0081] Output data:

[0082] Global verification strategy adjustment command;

[0083] Abstract precision switching command;

[0084] Resource allocation adjustment instructions;

[0085] Injection density / type adjustment instructions;

[0086] General outline of chip design optimization recommendations after verification.

[0087] 2. Hierarchical Abstract Decision-Making Sub-Model (Specialized Sub-Model 1)

[0088] Core function: Specifically responsible for making decisions on switching the module abstraction precision and outputting hierarchical adjustment suggestions to the main model;

[0089] Input data:

[0090] Coverage deviation data and fault type distribution data for a single module;

[0091] The module's risk level, functional safety level, and complexity data;

[0092] The current resource availability data of the verification platform;

[0093] Historical verification data for modules of the same type;

[0094] Output data:

[0095] Suggestions for switching the abstraction precision of the target module (black box / semi-abstract / full detail);

[0096] Predicted effects after the switch (increase in coverage and increase in resource consumption).

[0097] Recommendations for reducing the abstract precision of non-critical modules (to free up resources).

[0098] 3. Fault Injection Optimization Sub-model (Specialized Sub-model 2)

[0099] Core function: Specifically responsible for optimizing fault injection density and type, and outputting fault injection adjustment suggestions to the main model;

[0100] Input data:

[0101] Fault distribution clustering data and fault trigger rate data for a single module;

[0102] Module coverage deviation data, risk level data;

[0103] Module functional attributes and scenario verification requirements;

[0104] Historical data on the validity of fault injections;

[0105] Output data:

[0106] The fault injection density adjustment factor for the target module;

[0107] Prioritization and adjustment recommendations for fault injection types;

[0108] Suggestions for adjusting the rounds and timing of fault injection;

[0109] The expected improvement in fault coverage after injection is anticipated.

[0110] 4. Resource Scheduling Optimization Sub-model (Specialized Sub-model 3)

[0111] Core function: Specifically responsible for verifying the dynamic scheduling of resources (computing power, memory, storage) and outputting resource allocation adjustment suggestions to the main model;

[0112] Input data:

[0113] Real-time resource usage data for each module;

[0114] Priority, coverage deviation, and verification progress data for each module;

[0115] Verify the platform's total resource reserves and threshold data;

[0116] Data on changes in resource requirements resulting from switching of abstract precision and adjustments to fault injection;

[0117] Output data:

[0118] The allocation and adjustment plan for computing power, memory, and storage resources of each module (quantified percentage);

[0119] Resource reclamation recommendations for low-priority modules;

[0120] Predicted occupancy rate after resource allocation;

[0121] Verify platform resource bottleneck early warning information.

[0122] 5. Time Series Prediction and Optimization Sub-model (Specialized Sub-model 4)

[0123] Core functions: Specifically responsible for timing risk prediction, timing deviation prediction in low-power scenarios, outputting timing-related verification and adjustment suggestions, and also responsible for outputting timing optimization suggestions for chip design;

[0124] Input data:

[0125] Timing deviation data and timing violation data for each module;

[0126] Power domain parameters, low-power mode switching data;

[0127] Abstract precision data and simulation verification data of the module;

[0128] Timing constraint files for chip design;

[0129] Output data:

[0130] Time-series risk prediction results and corresponding verification accuracy adjustment suggestions;

[0131] Root cause localization results for timing violations;

[0132] Timing constraint optimization suggestions for chip design;

[0133] Timing optimization suggestions for low-power mode switching.

[0134] Furthermore, all sub-models are lightweight designs, trained on a dedicated SOC validation dataset, and can be adapted to different types of SOCs, requiring only fine-tuning of parameters for use. The outputs of each sub-model are only suggestions, with the final decision being uniformly output by the main model, ensuring that there are no conflicts among the adjustment instructions and achieving global optimization. After validation, the main model coordinates the analysis results of all sub-models and outputs complete chip design optimization suggestions, covering dimensions such as timing, logic, low power consumption, and interface protocols.

[0135] Step S4: Parameter Adjustment and Iterative Verification

[0136] Adjust the abstract precision model according to the abstract layer precision adjustment instruction, and / or adjust the fault injection parameters according to the fault injection adjustment instruction, and / or verify the computing power adjustment of each module according to the computing power adjustment instruction. Then return to step S2 until the collaborative verification result reaches the verification target.

[0137] In step S4, such as Figure 4 As shown, adjusting the abstract precision model includes: Step A1, for each module in the target SOC chip, determining the module's upgradable precision level based on the module's risk level, single module coverage deviation, and preset precision improvement trigger conditions; Step A2, determining whether the average occupancy rate exceeds the resource occupancy threshold: if yes, reducing the abstract precision of non-critical modules in the target SOC chip to release resources; if no, increasing the abstract precision of the corresponding module to the upgradable precision level.

[0138] Specifically, in this embodiment, the following core thresholds are defined first:

[0139] Coverage deviation Δ = Single module coverage threshold - Current module's overall single module coverage;

[0140] Significant deviation: Δ ≥ 10%; Moderate deviation: 5% ≤ Δ < 10%; Minor deviation: Δ < 5%.

[0141] Furthermore, the accuracy enhancement trigger conditions are shown in Table 1 below:

[0142] Table 1 Precision Improvement Triggering Conditions

[0143]

[0144] Understandably, regardless of the switching method, the current resource availability of the verification platform must be checked first: if the total resource utilization rate has exceeded the 80% threshold, the abstract precision of non-critical modules should be reduced first, and after releasing resources, the precision of the target module should be increased to avoid overloading the verification platform.

[0145] In a preferred embodiment of the present invention, the fault injection parameters include the fault injection type and its corresponding injection density; in step S4, as... Figure 5 As shown, adjusting the fault injection parameters includes: Step B1, for each module in the target SOC chip, when the module's risk level, single module coverage deviation, corresponding fault distribution data, and average occupancy rate only meet the adjustment conditions for a single fault injection type, an injection type adjustment signal is generated; when only the adjustment conditions for a single injection density are met, an injection density adjustment signal is generated; and when the adjustment conditions for two parameters are met, a synchronous adjustment signal for the fault injection type and its corresponding injection density is generated; Step B2, executing the injection type adjustment strategy according to the injection type adjustment signal and the synchronous adjustment signal, the injection type adjustment strategy includes determining the fault type with the highest proportion based on the fault distribution data as the high-priority injection type, and / or matching the preset high-priority injection type based on the module's function, and / or matching the preset high-priority injection type based on the application scenario of the target SOC chip; Step B3, executing the injection density adjustment strategy according to the injection density adjustment signal and the synchronous adjustment signal, the injection density adjustment strategy includes using the product of the base injection density and the adjustment coefficient as the adjusted injection density.

[0146] Specifically, in this embodiment, the triggering scenarios for single-parameter / dual-parameter adjustment are shown in Table 2 below:

[0147] Table 2. Triggering Scenarios for Single / Dual Parameter Adjustment

[0148]

[0149] Furthermore, the fault injection density adjustment logic is as follows:

[0150] The core adjustment criteria are: module coverage deviation, module risk level, fault trigger rate, and resource utilization margin.

[0151] Basic adjustment formula: Adjustment coefficient = K = 1 + (1 + coverage deviation) × module risk weight.

[0152] (Risk weight: High-risk module 1.0, medium-risk module 0.6, low-risk module 0.3).

[0153] The tiered adjustment rules are shown in Table 3 below:

[0154] Table Three-Tier Adjustment Rules

[0155]

[0156] Based on Table 3 above, if a significant deviation exists and the adjustment coefficient K calculated using the aforementioned basic adjustment formula is greater than 2, the high-risk module will configure the adjustment coefficient to the upper limit of the mandatory constraint range of 1.5 to 2.0, while the medium- and low-risk module will configure the adjustment coefficient to the lower limit of the mandatory constraint range of 1.5 to 2.0. If the adjustment coefficient is within the aforementioned constraint range, it will be configured as the calculated adjustment coefficient. The same principle applies to the case of moderate deviations.

[0157] If a slight deviation exists, and the overall coverage of the current module is higher than the single-module coverage threshold, the coverage deviation Δ is negative, indicating that the current injection density exceeds the testing requirements. However, the higher the injection density, the greater the resource consumption. To reduce resource consumption, the injection density can be reduced by lowering the adjustment coefficient. Specifically, if the adjustment coefficient K calculated using the above basic adjustment formula is greater than 1.35, the adjustment coefficient of the corresponding module will be configured to the upper limit of the mandatory constraint range of 0.8 to 1.35. If the adjustment coefficient K is less than 0.8, the adjustment coefficient of the corresponding module will be configured to the lower limit of the mandatory constraint range of 0.8 to 1.35.

[0158] By configuring the maximum adjustment factor to not exceed 2.0, resource overload can be avoided; and the minimum adjustment factor to not be lower than 0.8, basic verification coverage can be ensured.

[0159] Furthermore, the logic for adjusting the fault injection type is as follows:

[0160] The core adjustment is based on: fault distribution clustering results, module functional attributes, and scenario verification requirements. The core principle is to focus on injecting the corresponding type of fault where there are many faults.

[0161] Adjustment rules:

[0162] 1) Priority sorting: Based on the fault clustering results, the 2-3 fault types with the highest proportion are set as high-priority injection types, and fault types with a proportion of less than 5% are set as low-priority, reducing or pausing injection;

[0163] 2) Module function matching rules:

[0164] Communication interface modules: Prioritize injecting faults related to protocol interaction, timing jitter, and open interconnection.

[0165] Power domain modules: Prioritize injection of voltage dips, power leakage, and power-on / power-down timing faults;

[0166] Computation kernel modules: Prioritize injecting faults related to computational logic errors, computing power fluctuations, and timing deviations;

[0167] Low-power modules: Prioritize injecting sleep / wake-up timing, power leakage, and low-power mode function failure faults;

[0168] 3) Scenario adaptation rules: Automotive-grade SOCs are given priority for injecting functional safety-related faults, IoT SOCs are given priority for injecting low-power-related faults, and 5G SOCs are given priority for injecting protocol interaction-related faults.

[0169] In a preferred embodiment of the present invention, in step S4, as follows: Figure 6 As shown, the verification computing power adjustment includes: Step C1, for each module in the target SOC chip, configuring computing power priority for the module according to the module's risk level, coverage deviation, current verification progress, and current verification resource usage reserve; Step C2, on the premise that the total resource usage rate does not exceed the resource usage threshold, recovering the computing power of the modules with lower computing power priority and adding it to the computing power of the modules with higher computing power priority.

[0170] Specifically, in this embodiment, the core is based on the following four-dimensional priority model (priority from high to low) to ensure the rationality and efficiency of resource allocation:

[0171] 1) Module coverage deviation: The larger the deviation, the higher the resource priority;

[0172] 2) Module risk / functional safety level: The higher the level, the higher the resource priority;

[0173] 3) Module verification progress: The greater the delay, the higher the resource priority;

[0174] 4) Current verification resource usage margin: The larger the margin, the more resources can be allocated;

[0175] Core allocation principle: Prioritize the verification needs of high-priority modules, dynamically reclaim redundant resources from low-priority modules, and ensure that total resource usage never exceeds a preset threshold of 80%.

[0176] More specifically, the core formula for adjusting computing power is as follows:

[0177] The percentage of newly added computing power in the target module = (Δ / preset coverage threshold) × priority weight × total computing power reserve;

[0178] Where Δ = coverage deviation; priority weight: high risk 1.0, medium risk 0.6, low risk 0.3; total computing power reserve = 100% - current total resource utilization rate).

[0179] Furthermore, the tiered quantitative adjustment rules are shown in Table 4 below:

[0180] Table 4: Tiered Quantitative Adjustment Rules

[0181]

[0182] After calculating the percentage of new computing power added to the target module, it is added to the percentage of redundant computing power recovered to obtain the final percentage of total new computing power.

[0183] For example: The current total resource utilization is 75%, and the total computing power reserve is 25%. The initial computing power allocation to the LiDAR module is 12%. The LiDAR module is high-risk, with Δ=7% and a priority weight of 1.0. Calculations show that the target module's newly added computing power accounts for approximately 1.84%. This, combined with the recovery of redundant computing power from the low-risk GPIO module, ultimately increases the LiDAR module's total newly added computing power to 8%, from the initial 12% to 20%. Here, the calculated result of the target module's newly added computing power plus the recovered redundant computing power (8%) falls between 5% and 10%, so the final result is 8%. If the calculated result is greater than 10%, a mandatory constraint of 10% is applied.

[0184] Boundary constraints:

[0185] The maximum computing power of a single module shall not exceed 30% of the total computing power to avoid excessive concentration of resources.

[0186] The minimum computing power of low-risk modules shall not be less than 20% of the initial allocation to ensure that basic verification is not interrupted;

[0187] The total resource utilization rate is always kept below 80%, with 20% of redundant computing power reserved to cope with sudden demands.

[0188] As a preferred implementation method, the verification objectives specifically include:

[0189] Condition 1: The overall fault coverage of the module is greater than or equal to the preset single module threshold, and the coverage of all sub-items (code, function, assertion, scenario) is greater than or equal to the minimum threshold.

[0190] Condition 2: No new critical faults (definition of critical fault: faults that affect the core functions, functional safety, and performance indicators of the chip), and all discovered critical faults have been closed-loop repaired and verified to be reproduced.

[0191] Condition 3: The resource utilization rate verified by the module meets the preset requirements, and there is no abnormal resource utilization;

[0192] Condition 4: The module's performance indicators (timing, power consumption, throughput, latency, etc.) all meet the design specifications.

[0193] Condition 5: All interaction verifications between the module and its upstream and downstream related modules have passed, with no interface protocol or data interaction failures.

[0194] Condition 6: The module has completed all scene verifications required by the scene template, with no scenes omitted;

[0195] Condition 7: After three consecutive rounds of iterative verification, no new critical faults were added, and the coverage rate remained stable and met the target without fluctuations.

[0196] If all seven conditions are met, the collaborative verification results are considered to have achieved the verification objective.

[0197] Example 1

[0198] This invention was applied to the verification of an automotive-grade ADAS SOC chip, which integrates a CPU, GPU, LiDAR interface module and multiple power domains, and must meet the ISO 26262 ASIL-D functional safety standard.

[0199] Initial configuration: Load the automotive-grade SOC verification template through scenario adaptation, set the verification coverage target to 99.5%, the resource usage threshold to 80%, and the fault injection types to be interconnect open circuit, timing jitter, and power domain voltage drop; initialize the LSTM neural network parameters and the reinforcement learning engine reward function; perform initial layering on the ADAS SOC chip, setting the LiDAR interface module to semi-abstract, the GPIO module to black-box abstraction, and the CPU / GPU to full-detail abstraction, and generate the initial abstract model.

[0200] Collaborative verification execution: Initiate UVM simulation verification, Veloce hardware-accelerated prototype verification and Conformal formal verification. Simulation verification executes functional and timing verification. Prototype verification simulates LiDAR data interaction in real driving scenarios. Formal verification verifies the integrity of core logic. Based on the initial prediction, targeted fault injection is performed on the LiDAR interface module and power domain switching circuit.

[0201] Data Acquisition and Analysis: Real-time acquisition and verification data revealed that the fault coverage of the LiDAR interface module was only 88% (below average level), and the resource utilization rate was 75% (not exceeding the threshold). A phased verification report was generated, and the distributed data, mainly interface protocol faults, was fed back to the AI ​​adaptive control module.

[0202] AI Adaptive Adjustment: The AI ​​adaptive control module analyzes feedback data through a reinforcement learning engine and determines that the low fault coverage is due to the semi-abstract mode shielding key interface logic. It then outputs instructions to switch the LiDAR interface module to a fully detailed abstract mode, increases the fault injection density of the module to 1.5 times the original, and focuses on injecting faults related to the interface protocol. At the same time, it adjusts resource allocation, allocating more computing power to the module's verification tasks.

[0203] Iterative verification: Based on the adjusted strategy, verification continued and data was collected again. The fault coverage of the LiDAR interface module increased to 99.2%, the resource utilization rate increased to 78%, and no new critical faults were added. The AI ​​adaptive control module determined that no further adjustments were needed and continued to execute the remaining verification tasks until the fault coverage of the entire chip reached 99.5%.

[0204] Verification completion: Generate a complete verification report, including fault details, coverage analysis, functional safety indicators (SPFM≥90%, LFM≥99%), resource usage statistics (average utilization rate 76%), timing and power consumption verification results; the AI ​​adaptive control module outputs optimization suggestions (such as optimizing the timing constraints of the LiDAR interface module), completing the ADAS SOC chip verification.

[0205] In this embodiment, compared with traditional verification methods, the verification cycle is shortened by 50%, resource consumption is reduced by 45%, and fault coverage is increased to 99.5%, fully meeting the requirements of ISO 26262 ASIL-D standard. Moreover, no manual intervention is required to adjust the verification strategy, and the level of intelligence is significantly improved.

[0206] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. An AI self-adaptive hierarchical cooperative SOC chip verification method, characterized in that, include: Step S1: Configure a set of verification parameters that are compatible with the target SOC chip's scenario attribute information, and perform initial layering of the target SOC chip to obtain an abstract precision model for each module. The verification parameter set includes verification targets and fault injection parameters. Step S2: Inject faults into the target SOC chip using the fault injection parameters, and perform multi-mode collaborative verification based on the abstract precision model to obtain collaborative verification results. Subsequently, analyze the collaborative verification results based on the verification targets to generate verification deviation results. Step S3: Based on the verification deviation results, generate strategy adjustment instructions through AI adaptive decision-making. The strategy adjustment instructions include abstract layering precision adjustment instructions and / or fault injection adjustment instructions. Step S4: Adjust the abstract precision model according to the abstract layering precision adjustment instructions, and / or adjust the fault injection parameters according to the fault injection adjustment instructions, and then return to step S2 until the collaborative verification results reach the verification targets.

2. The SOC chip verification method according to claim 1, characterized in that, Before executing step S1, a template library is pre-built, which stores verification scenario templates with different scenario attribute information. Step S1 includes: Step S11, matching the verification scenario template that matches the scenario attribute information of the target SOC chip from the template library, and extracting the corresponding verification target, high-risk module list, and abstract layering rules from the matched verification scenario template; Step S12, obtaining the design attribute information of the target SOC chip, updating the high-risk module list based on the design attribute information to obtain an updated high-risk list, and adaptively fine-tuning the abstract layering rules to obtain the abstract precision model of the target SOC chip; Step S13, configuring targeted injection parameters for each high-risk module in the updated high-risk list, configuring full-coverage injection parameters for the remaining modules, and adding the targeted injection parameters and the full-coverage injection parameters as fault injection parameters to the verification parameter set.

3. The SOC chip verification method according to claim 2, characterized in that, The fault injection parameters include fault injection types and their corresponding injection densities, and the injection density of the targeted injection parameters is higher than the injection density of the full-coverage injection parameters.

4. The SOC chip verification method according to claim 1, characterized in that, The verification modes of the multi-mode collaborative verification include prototype verification, formal verification, and simulation verification. The corresponding collaborative verification results include multiple sub-item verification coverage rates under each verification mode. The verification targets include single-module coverage thresholds and full-chip target coverage. In step S2, the process of generating the verification deviation result includes: step S21, for each module in the target SOC chip, the weighted summation of each of the sub-item verification coverage rates is used to obtain the corresponding single-module comprehensive coverage rate, and then the weighted summation of the single-module comprehensive coverage rates of all modules is used to obtain the full chip coverage rate of the target SOC chip; step S22, each of the single-module comprehensive coverage rates is compared with each of the single-module coverage rate thresholds, and the full chip coverage rate is compared with the full chip target coverage rate. If any single-module comprehensive coverage rate is lower than the single-module coverage rate threshold, or the full chip coverage rate is lower than the full chip target coverage rate, the coverage deviation of the corresponding low item and the corresponding fault distribution data are used as the verification deviation result.

5. The SOC chip verification method according to claim 4, characterized in that, The verification target also includes a resource occupancy threshold, and the corresponding verification deviation result also includes real-time resource occupancy statistics. Step S1 further includes allocating verification computing power resources to each module of the target SOC chip according to preset rules. Step S2 further includes calculating the real-time occupancy rate of each verification resource in the entire process of single-round multi-mode collaborative verification, and performing a weighted average of each real-time occupancy rate to obtain an average occupancy rate. Then, when the average occupancy rate exceeds the resource occupancy threshold, the real-time resource occupancy statistics are output. In step S3, the strategy adjustment instruction also includes a computing power adjustment instruction. Step S4 further includes adjusting the verification computing power of each module according to the computing power adjustment instruction.

6. The SOC chip verification method according to claim 5, characterized in that, In step S4, adjusting the abstract precision model includes: Step A1, for each module in the target SOC chip, determining the upgradable precision level of the module based on the module's risk level, single-module coverage deviation, and preset precision improvement trigger conditions; Step A2, determining whether the average occupancy rate exceeds the resource occupancy threshold: if yes, reducing the abstract precision of non-critical modules of the target SOC chip to release resources; if no, increasing the abstract precision of the corresponding module to the upgradable precision level.

7. The SOC chip verification method according to claim 5, characterized in that, The fault injection parameters include the fault injection type and its corresponding injection density. In step S4, adjusting the fault injection parameters includes: Step B1, for each module in the target SOC chip, when the module's risk level, single module coverage deviation, corresponding fault distribution data, and average occupancy rate only meet the single fault injection type adjustment condition, an injection type adjustment signal is generated; when only the single injection density adjustment condition is met, an injection density adjustment signal is generated; and when the dual parameter adjustment condition is met, a synchronous adjustment signal for the fault injection type and its corresponding injection density is generated; Step B2, an injection type adjustment strategy is executed according to the injection type adjustment signal and the synchronous adjustment signal, the injection type adjustment strategy includes determining the fault type with the highest proportion based on the fault distribution data as the high-priority injection type, and / or matching the module's function with a preset high-priority injection type, and / or matching the target SOC chip's application scenario with a preset high-priority injection type; Step B3, an injection density adjustment strategy is executed according to the injection density adjustment signal and the synchronous adjustment signal, the injection density adjustment strategy includes using the product of the base injection density and the adjustment coefficient as the adjusted injection density, wherein: the adjustment coefficient = K = 1 + (1 + coverage deviation) × module risk weight.

8. The SOC chip verification method according to claim 5, characterized in that, In step S4, the verification computing power adjustment includes: step C1, for each module in the target SOC chip, configuring computing power priority for the module according to the module's risk level, coverage deviation, current verification progress, and current verification resource usage balance; step C2, on the premise that the total resource usage rate does not exceed the resource usage threshold, reclaiming the computing power of the module with lower computing power priority and adding it to the computing power of the module with higher computing power priority.

9. The SOC chip verification method according to claim 5, characterized in that, It also includes pre-built clusters of artificial intelligence models, including a reinforcement learning decision engine, a hierarchical abstract decision sub-model, a fault injection optimization sub-model, and a resource scheduling optimization sub-model; The strategy adjustment instructions also include resource allocation adjustment instructions; Step S3 includes: Step S31, based on the verification deviation result, calling the hierarchical abstract decision sub-model, the fault injection optimization sub-model and the resource scheduling optimization sub-model respectively to generate abstract hierarchical accuracy suggestions, fault injection adjustment suggestions and resource scheduling optimization suggestions; Step S32: Input the verification deviation result, the abstract hierarchical accuracy suggestion, the fault injection adjustment suggestion, the resource scheduling optimization suggestion, the verification parameter set, the abstract accuracy model obtained from the initial hierarchical layer, and the current verification iteration information into the reinforcement learning decision engine for fusion processing, so as to generate the abstract hierarchical accuracy adjustment instruction, and / or the fault injection adjustment instruction, and / or the resource allocation adjustment instruction.

10. The SOC chip verification method according to claim 9, characterized in that, The artificial intelligence model cluster also includes a timing prediction and optimization sub-model; step S3 further includes statistically analyzing the power domain parameters of the target SOC chip and the timing-related data of each module, and calling the timing prediction and optimization sub-model to perform timing risk prediction and timing deviation analysis, thereby generating timing optimization suggestions; in step S32, the timing optimization suggestions are also synchronously input into the reinforcement learning decision engine for fusion processing, and the reinforcement learning decision engine also generates timing constraint optimization suggestions for the target SOC chip according to the decision, for designers to refer to.

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