A sensor chip on-board packaging design method and a test circuit applied thereto

Abstract

This invention discloses a sensor chip on-board packaging design method and its application test circuit, including: acquiring all input or output pad parameters corresponding to the chip, generating a basic circuit and printed circuit board pad layout model adapted to the actual die; generating a printed circuit board pad layout diagram of the chip on the board based on all input or output pad parameters corresponding to the actual die; analyzing the actual application circuit requirements of the chip, and generating a final printed circuit board layout scheme based on the current chip printed circuit board pad layout scheme. This invention directly integrates the sensor chip with the application circuit through on-board chip packaging technology, eliminating the need for extensive time and cost for rapid chip packaging, fully meeting the testing needs of both the design and application ends, effectively reducing the time cycle from project initiation to large-scale market launch, and offering flexible application capabilities. It can be extended to the design verification, laboratory testing, and application testing of other types of chips.

Description

Technical Field

[0001] This invention relates to the field of electronic equipment technology, and in particular to a sensor chip on-board packaging design method and a test circuit for its application. Background Technology

[0002] Sensor chips are the core functional units of sensors. They are dedicated integrated circuit chips that convert non-electrical signals such as external physical, chemical, and biological signals into collectable and processable electrical signals. They typically integrate core modules such as sensing elements, signal conversion circuits, and signal conditioning and processing units. They rely on the physical or chemical effects of different materials such as piezoelectric, photoelectric, thermal, magnetic, and gas-sensitive materials to accurately sense changes in various parameters in the environment, such as temperature, humidity, pressure, displacement, light intensity, gas concentration, and biological characteristics. After converting these changes into electrical signals, they perform preliminary processing such as amplification, filtering, and analog-to-digital conversion to provide raw signal support for subsequent data analysis and decision control of terminal equipment.

[0003] In the design, development, and application testing phases of sensor chips, both the design and application testing ends strive to initiate functional testing quickly after chip fabrication to efficiently verify all chip characteristics or promptly identify various issues in the design and manufacturing processes. Existing testing solutions involve rapid blind sealing after wafer fabrication or rapid packaging after wafer-level chip probe testing. After these packaging processes, full-characteristic verification testing is conducted using a specially designed application circuit board. However, this testing method has a long overall process flow, resulting in a long product cycle from project initiation to large-scale market launch, and high packaging and testing costs, making it difficult to meet the efficient and low-cost design verification requirements of the sensor chip development stage. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a sensor chip on-board packaging design method and its application test circuit.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a sensor chip on-board packaging design method, comprising: Obtain all input or output pad parameters corresponding to the chip, and generate a basic circuit and printed circuit board pad layout model that is compatible with the actual die. Based on all input or output pad parameters corresponding to the actual die, generate the pad layout of the printed circuit board for the chip on the board.

[0006] In some embodiments, all input or output pad parameters corresponding to the actual die include pad location, pad size, number of pads, and pad pin definition.

[0007] In some embodiments, all input or output pad parameters corresponding to the actual die are used to generate a standardized printed circuit board pad model using computer-aided design tools.

[0008] In some embodiments, all input or output pad parameters corresponding to the actual die are used to generate a chip-on-board printed circuit board pad layout using computer-aided design tools.

[0009] In some embodiments, when generating the printed circuit board pad layout, the printed circuit board pads are placed based on preset circuit line lengths and chip characteristic requirements.

[0010] In some embodiments, when generating the printed circuit board pad layout, the placement position of the chip die positioning frame is determined based on the actual overall die size.

[0011] In some embodiments, the die positioning frame is placed on the silkscreen layer of the printed circuit board.

[0012] In some embodiments, it also includes: Analyze the actual application circuit requirements of the preset chip, and generate the final printed circuit board layout scheme based on the current chip printed circuit board pad layout scheme.

[0013] In some embodiments, the actual application circuit requirements of the preset chip include peripheral component circuit requirements, sensor device circuit requirements, chip power supply circuit requirements, calibration system interface circuit requirements, and probe pad interface circuit requirements.

[0014] In a second aspect, the present invention also provides a sensor chip test circuit for testing a sensor chip designed using the sensor chip on-board packaging design method described in the first aspect. The test circuit includes: The onboard chip module for sensors is electrically connected to peripheral components, sensor devices, chip power supplies, calibration system interfaces, and probe pad interfaces, and is used to complete the functional testing of the onboard chip module for sensors.

[0015] The present invention has the following beneficial effects: This invention integrates sensor chips directly with application circuits through onboard chip packaging technology, eliminating the need for extensive time and costs associated with rapid chip packaging. It also enables comprehensive chip characteristic testing over a wide temperature range, fully meeting the testing needs of both design and application ends. This effectively reduces the time cycle from project initiation to large-scale market launch, offering flexibility and allowing for application in the design verification, laboratory testing, and application testing of other types of chips. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the onboard packaging design method for sensor chips proposed in this invention. Figure 2 This is a schematic diagram of the structure of the onboard packaged chip for the sensor designed in this invention. Figure 3 A printed circuit board diagram of the onboard packaged chip for the sensor designed for this invention. Figure 4 This is a block diagram of an application test circuit that includes an onboard packaged chip for a sensor. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] This application provides a sensor chip on-board packaging design method and its application test circuit, solving the problems of long overall process time and high packaging and testing costs in the prior art, which are difficult to adapt to the high-efficiency and low-cost design verification requirements of the sensor chip R&D stage. This application directly combines the sensor chip with the application circuit through on-board chip packaging technology, eliminating the need for extensive time and cost for rapid chip packaging. Furthermore, it allows for complete chip characteristic testing over a wide temperature range, fully meeting the testing needs of both the design and application ends. This effectively reduces the time cycle from project initiation to large-scale market launch, offering flexibility and applicability to the design verification, laboratory testing, and application testing of other types of chips.

[0019] It should be noted that the relevant terms in this application are explained in detail as follows: Chip on Board (COB): Unpackaged chip dies are directly mounted on a carrier such as a printed circuit board (PCB), and the electrical connection between the chip and the substrate is achieved by wire bonding. Then, the chip is encapsulated with potting compound to form a protective structure. Input or output pads (IO Pads): Interface components that enable signal and power transmission between the chip die and external circuits. They are divided into input pads and output pads, and must be precisely matched with the pads on the printed circuit board. Die anchor: A dedicated positioning structure designed on the silkscreen layer of a printed circuit board. Its size is perfectly matched to the die. It is used to provide a reference for the precise placement and fixation of the die during the packaging process, avoiding packaging misalignment and ensuring packaging quality. Printed circuit board pads (PCB pads): Metal contacts on a printed circuit board used to make electrical connections with chip input or output pads and component pins; Printed Circuit Board Layout (PCB Layout): A standardized drawing created using computer-aided design tools to guide the actual fabrication of printed circuit boards. It clearly marks the location and connection logic of all structures, including PCB pads, circuit traces, functional modules, and die positioning frames.

[0020] Please refer to the following examples for details: Reference Figure 1 An embodiment of the sensor chip on-board packaging design method provided by the present invention includes the following specific structure: S100: Obtain all input or output pad parameters corresponding to the chip, and generate a basic circuit and printed circuit board pad layout model that is compatible with the actual die. S200 generates a layout diagram of the printed circuit board pads for the chip on the board based on all input or output pad parameters corresponding to the actual bare die. S300 analyzes the actual application circuit requirements of the preset chip and generates the final printed circuit board layout scheme based on the current chip printed circuit board pad layout scheme.

[0021] For example, firstly, all input and output pad parameters corresponding to the sensor chip to be designed are accurately obtained. Based on the obtained parameters, a basic circuit schematic and a printed circuit board pad layout model that are precisely adapted to the actual bare chip are generated using a computer-aided design tool for printed circuit boards. The basic circuit schematic needs to conform to the working characteristics and pin function definitions of the bare chip to complete the logical connection design between the input and output pads and the basic circuit. The printed circuit board pad layout model needs to achieve a 1:1 precise match with the input and output pads of the actual bare chip to clarify the pad parameters. Based on the generated printed circuit board (PCB) pad layout model, a complete PCB pad layout diagram is generated using PCB computer-aided design tools, taking into account all input and output pad parameters of the actual die, preset circuit line length requirements, and the chip's own characteristics. During the layout design process, each PCB pad must be arranged strictly according to the circuit line length specifications to avoid signal attenuation and interference caused by excessively long or short lines, ensuring the stability of signal transmission during chip operation. Simultaneously, the placement position of the die positioning frame must be accurately determined based on the overall dimensions of the actual die, and designed on the PCB silkscreen layer. This provides a clear positioning reference for the precise placement and fixing of the die in subsequent packaging processes, ensuring the accuracy and efficiency of the packaging process. The design process involves analyzing the actual application circuit requirements of the sensor chip to clarify its power supply requirements, signal transmission requirements, functional module configuration, and testing requirements in real-world operating scenarios. This ensures that the designed layout can fully simulate the chip's actual application environment. Subsequently, based on the framework of the previous chip device design and packaging design, various functional modules such as peripheral components, chip power supplies, temperature sensors, calibration system interfaces, and probe pad interfaces are integrated to complete the final printed circuit board layout design. This design not only achieves a reasonable layout of all functional modules and optimized signal routing but also ensures precise connection with the previous chip pad layout and chip die positioning frame, ultimately forming a standardized layout that can be directly used for test board fabrication.

[0022] In some embodiments, the parameters of all input or output pads corresponding to the actual die include pad position, pad size, number of pads, and pad pin definition. Among them, the pad position, pad size, and number of pads determine the accuracy of the printed circuit board pad layout, ensuring physical compatibility with the chip die input and output pads. The pad pin definition is used to determine the design logic of the basic circuit schematic, clarify the signal flow of the function of each pad, avoid circuit connection errors, and ensure the compatibility of the chip devices, packages, and application test board designs on the board.

[0023] In some embodiments, all input or output pad parameters corresponding to the actual die are used to generate a standardized printed circuit board pad model using computer-aided design tools.

[0024] In some embodiments, all input or output pad parameters corresponding to the actual die are used to generate a standardized printed circuit board pad model through computer-aided design tools. Relying on the standardized design function of computer-aided design tools, the parameters of the generated printed circuit board pad model are ensured to be accurate and standardized, which can match the input and output pads of the actual die, improve design efficiency and reduce design deviation.

[0025] In some embodiments, when generating the printed circuit board pad layout, the printed circuit board pads are placed based on preset circuit line lengths and chip characteristic requirements. The preset circuit line length requirements are to adapt to the chip's signal transmission needs, avoid signal attenuation, interference, and delay caused by non-compliant line lengths, and ensure the stability of chip operation. The chip characteristic requirements are combined with the sensor chip's own operating performance, power consumption, pin functions, and other parameters to plan the pad layout, ensuring that the pad layout matches the chip's actual operating needs and avoiding problems such as pad congestion and signal conflicts.

[0026] In some embodiments, when generating the printed circuit board pad layout, the placement position of the die positioning frame is determined based on the overall size of the actual die. This provides a positioning reference for subsequent packaging processes, ensuring a perfect match with the actual die. This allows the input and output pads on the die to be precisely aligned with their corresponding pads on the printed circuit board after placement, avoiding issues such as packaging misalignment and poor pad connection. Simultaneously, the positioning frame design must reserve reasonable packaging space to provide operational margin for subsequent processes such as gold wire bonding and encapsulation, ensuring packaging quality.

[0027] In some embodiments, when gold wire (the most commonly used packaging interconnect in the industry) is used for on-board chip packaging, the metallic properties of the gold wire itself determine that it has high requirements for the soldering substrate. Therefore, the printed circuit board pads must use immersion gold material, which has advantages such as high surface flatness, strong oxidation resistance, and excellent metal bonding with the gold wire. This ensures the packaging quality of the chips on the board, effectively improves the soldering stability between the gold wire and the printed circuit board pads, reduces contact resistance, avoids problems such as cold solder joints, desoldering, and pad oxidation that affect packaging quality, and extends the service life of the chips on the board.

[0028] In some embodiments, the die positioning frame is placed on the silkscreen layer of the printed circuit board. The silkscreen layer is a dedicated layer on the surface of the printed circuit board used to mark the location, model, and border of components. Designing the die positioning frame on this layer ensures that the positioning frame is clearly visible, making it easy for packaging operators to quickly locate and place the die, thus improving the efficiency of the packaging operation. At the same time, the positioning frame on the silkscreen layer does not affect the transmission of circuit signals inside the printed circuit board, nor does it interfere with other functional layers, thus balancing the convenience of the packaging operation with the stability of chip operation.

[0029] In some embodiments, the preset chip application circuit requirements include peripheral component circuit requirements, sensor device circuit requirements, chip power supply circuit requirements, calibration system interface circuit requirements, and probe pad interface circuit requirements.

[0030] Reference Figure 2 The present invention also provides an embodiment of a sensor chip testing circuit for testing a sensor chip designed using the on-board packaging design method described in the above embodiments. The testing circuit includes: The onboard chip module for sensors is electrically connected to peripheral components, sensor devices (including first and second sensors), chip power supply, calibration system interface, and probe pad interface to perform functional testing of the onboard chip module for sensors.

[0031] For example, the above-described test circuit is specifically designed to test the sensor chip designed by the chip design method on the sensor chip board in the above embodiments. It can comprehensively verify the chip's functions, characteristics and stability, and is compatible with the entire process requirements of chip design verification, laboratory testing and application testing.

[0032] Working principle: Peripheral components are used to improve circuit functionality, achieving signal filtering, amplification, isolation, etc., simulating the peripheral circuit environment in actual chip applications; the sensor device, as the object under test, achieves precise docking with the test circuit through the chip module on the board; the chip power supply provides stable operating voltage and current for the entire test circuit and sensor chip, ensuring that the chip can start up normally and work stably; the calibration system interface is used to connect to external calibration equipment to calibrate the parameters and accuracy of the sensor chip, ensuring the accuracy of test data; the probe pad interface is used to connect external test probes and test instruments, facilitating the acquisition of test data, monitoring the chip's working status, and achieving precise detection of chip characteristics.

[0033] Through the above technical solution, this application directly combines the sensor chip with the application circuit by means of onboard chip packaging technology, realizing the integrated operation of the sensor onboard chip packaging from packaging to application test circuit. It eliminates the need to spend a lot of time and cost on rapid chip packaging, and can perform complete chip characteristic testing within a temperature range of -65℃ to +150℃, fully meeting the testing needs of the design and application ends. It effectively reduces the time to market (TTM) cycle from project initiation to large-scale market launch, and has the characteristics of flexible application. It can be extended to the design verification, laboratory testing and application testing of other types of chips.

[0034] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A sensor chip onboard packaging design method, characterized in that, include: Obtain all input or output pad parameters corresponding to the chip, and generate a basic circuit and printed circuit board pad layout model that is compatible with the actual die. Based on all input or output pad parameters corresponding to the actual die, generate the pad layout of the printed circuit board for the chip on the board.

2. The sensor chip on-board packaging design method according to claim 1, characterized in that, The input or output pad parameters corresponding to the actual bare die include pad position, pad size, number of pads, and pad pin definition.

3. The sensor chip on-board packaging design method according to claim 1, characterized in that, All input or output pad parameters corresponding to the actual bare die are used to generate a standardized printed circuit board pad model using computer-aided design tools.

4. The sensor chip on-board packaging design method according to claim 1, characterized in that, The input or output pad parameters corresponding to the actual die are used by computer-aided design tools to generate the on-board chip printed circuit board pad layout.

5. The sensor chip on-board packaging design method according to claim 1, characterized in that, When generating the printed circuit board pad layout, the printed circuit board pads are placed based on the preset circuit line length and chip characteristic requirements.

6. The sensor chip on-board packaging design method according to claim 1, characterized in that, When generating the printed circuit board pad layout, the placement position of the chip die positioning frame is determined based on the actual overall die size.

7. The sensor chip on-board packaging design method according to claim 1, characterized in that, The die positioning frame is placed on the silkscreen layer of the printed circuit board.

8. The sensor chip on-board packaging design method according to claim 1, characterized in that, Also includes: Analyze the actual application circuit requirements of the preset chip, and generate the final printed circuit board layout scheme based on the current chip printed circuit board pad layout scheme.

9. The sensor chip on-board packaging design method according to claim 8, characterized in that, The actual application circuit requirements of the preset chip include the requirements for peripheral component circuits, sensor device circuits, chip power supply circuits, calibration system interface circuits, and probe pad interface circuits.

10. A sensor chip test circuit, characterized in that, The test circuit is used to test the sensor chip designed by the sensor chip on-board packaging design method according to any one of claims 1 to 9. The test circuit includes: The onboard chip module for sensors is electrically connected to peripheral components, sensor devices, chip power supplies, calibration system interfaces, and probe pad interfaces, and is used to complete the functional testing of the onboard chip module for sensors.

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