Microdisplay package structure

Abstract

This invention provides a microdisplay packaging structure, including: a circuit board and a microdisplay chip located on the circuit board; the microdisplay chip has through-silicon vias (TSVs), and a redistributed metal layer is located in the TSVs and on a portion of the lower surface of the microdisplay chip; conductive adhesive is disposed between the solder pads on the circuit board and the microdisplay chip. This invention utilizes the redistributed metal layer in the TSVs to conduct signals from the upper surface of the microdisplay chip to the area below the microdisplay chip. The microdisplay chip is electrically connected to the solder pads on the circuit board sequentially through the redistributed metal layer and the conductive adhesive. By using conductive adhesive and the redistributed metal layer to lead electrical signals from the circuit board to the solder pads on the upper surface of the microdisplay chip, the limitations of traditional gold wire bonding are avoided. It combines structural simplification and improved heat dissipation, making it suitable for high-brightness microdisplay modules; it also combines the advantages of high-density interconnection and thermal management, breaking through traditional packaging limitations and making it suitable for miniaturization and high-power applications.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, and specifically relates to a microdisplay packaging structure. Background Technology

[0002] Traditional MicroLED packaging often uses wire bonding, where the MicroLED chip is connected to the printed circuit board (PCB) via metal wires. This method is simple but has limited heat dissipation efficiency. LCOS, on the other hand, commonly uses ceramic substrates and glass covers for packaging. The process involves chip bonding, optical component assembly, and sealing, resulting in a complex structure and higher cost.

[0003] Wire bonding presents limitations in ultra-thin chip module design due to the presence of wire arc height and forbidden zones; furthermore, the metal wires generate parasitic inductance under high-frequency driving, affecting signal integrity; additionally, the bonding points are susceptible to thermal stress fatigue fracture. Traditional designs for microdisplay packaging structures still face bottlenecks in terms of interconnect complexity and heat dissipation. Summary of the Invention

[0004] The purpose of this invention is to provide a microdisplay packaging structure that uses conductive adhesive and a redistributed metal layer to lead electrical signals from the circuit board to the solder pads on the surface of the microdisplay chip, avoiding the limitations of traditional gold wire bonding. It combines structural simplification and improved heat dissipation, making it suitable for high-brightness microdisplay modules; it also offers advantages in high-density interconnection and thermal management, breaking through the limitations of traditional packaging and making it suitable for miniaturization and high-power applications.

[0005] This invention provides a microdisplay packaging structure, comprising:

[0006] A circuit board and a microdisplay chip located on the circuit board, the microdisplay chip including a MicroLED chip or an LCOS chip;

[0007] The microdisplay chip has through-silicon vias, and a redistributed metal layer is located in the through-silicon vias and on part of the lower surface of the microdisplay chip;

[0008] A conductive adhesive is disposed between the solder pads on the circuit board and the microdisplay chip, and the microdisplay chip is electrically connected to the solder pads on the circuit board in sequence through the redistributed metal layer and the conductive adhesive.

[0009] Furthermore, thermally conductive adhesive is provided at the interface between the microdisplay chip and the circuit board.

[0010] Furthermore, the thermally conductive adhesive includes at least one of silver paste, copper paste, carbon paste, or alumina paste.

[0011] Furthermore, the redistributed metal layer fills the through-silicon via and extends downwards onto the peripheral surface and part of the lower surface of the microdisplay chip;

[0012] An insulating layer is formed on the surface of the redistributed metal layer;

[0013] An adhesive is filled between the insulating layer and the circuit board.

[0014] Furthermore, the surface of the microdisplay chip is provided with power pin pads that are prone to generating heat. The through-silicon vias are provided on both sides or one side of the power pin pads. The portion of the redistributed metal layer located in the through-silicon vias serves as a heat dissipation pad, and the heat dissipation pad serves as a grounding pin.

[0015] Furthermore, the width of the heat dissipation pad is 2 to 10 times the width of the power pin pad.

[0016] Furthermore, the heat dissipation pad and the power pin pad are arranged in parallel and have the same length and thickness.

[0017] Furthermore, the circuit board includes any one of flexible circuit boards, printed circuit boards, and ceramic substrates.

[0018] Furthermore, the circuit board is a flexible circuit board, and a graphene heat dissipation coating is formed on the upper and / or lower surfaces of the flexible circuit board.

[0019] Furthermore, the thickness of the graphene heat dissipation coating ranges from 5 μm to 25 μm.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] This invention provides a microdisplay packaging structure, comprising: a circuit board and a microdisplay chip located on the circuit board, the microdisplay chip including a MicroLED chip or an LCOS chip; a through-silicon via (TSV) is provided in the microdisplay chip, and a redistribution metal layer is located in the TSV and on a portion of the lower surface of the microdisplay chip; conductive adhesive is provided between the solder pads on the circuit board and the microdisplay chip.

[0022] This invention utilizes a redistributed metal layer within a through-silicon via (TSV) to conduct signals from the surface of a microdisplay chip to the area beneath it. The microdisplay chip is electrically connected to solder pads on a circuit board via the redistributed metal layer, conductive adhesive, and so on. In other words, the solder pads (or electrical signals) on the circuit board are led out through the conductive adhesive and the redistributed metal layer, which serves as the solder pad on the microdisplay chip. By using conductive adhesive and a redistributed metal layer to lead electrical signals from the circuit board to the solder pads on the surface of the microdisplay chip, the limitations of traditional gold wire bonding are avoided. This invention combines structural simplification and improved heat dissipation, making it suitable for high-brightness microdisplay modules; it also offers advantages in high-density interconnection and thermal management, breaking through traditional packaging limitations and making it suitable for miniaturization and high-power applications. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the microdisplay packaging structure according to an embodiment of the present invention.

[0024] Figure 2 This is a schematic diagram of the power pin pads and heat dissipation pads on the upper surface of the microdisplay packaging structure according to an embodiment of the present invention.

[0025] Figure 3 This is a list of temperature ratios corresponding to different ratios of the width of the thermal pad to the width of the power pin pad in the microdisplay packaging structure of this invention.

[0026] Figure 4 This is a bar chart showing the cooling ratio corresponding to different ratios of the width of the thermal pad to the width of the power pin pad in the microdisplay packaging structure of this invention.

[0027] Figure 5 This is a schematic diagram showing the simulated temperature corresponding to different ratios of the width of the power pin pad to the width of the heat dissipation pad in the microdisplay packaging structure of this invention.

[0028] Figure 6 This is a schematic diagram showing the simulated temperatures of the flexible circuit board surface with and without a graphene heat dissipation coating in the microdisplay packaging structure of this invention.

[0029] The reference numerals in the attached figures are as follows:

[0030] 10-Circuit board; 11-Solder pads on the circuit board; 20-Micro display chip; 30-Redistributed metal layer; 40-Conductive adhesive; 50-Thermal conductive adhesive; 60-Insulating layer; 70-Colloid. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0032] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings. It should be understood that, in addition to the orientations described in the drawings, spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used, may be replaced where appropriate.

[0033] This invention provides a microdisplay packaging structure, such as... Figure 1 As shown, it includes: a circuit board 10 and a micro display chip 20 located on the circuit board 10, the micro display chip 20 including a MicroLED chip or an LCOS chip;

[0034] The microdisplay chip 20 has through-silicon vias, and the redistributed metal layer 30 is located in the through-silicon vias and on part of the lower surface of the microdisplay chip 20.

[0035] A conductive adhesive 40 is provided between the solder pad 11 on the circuit board and the micro display chip 20. The micro display chip 20 is electrically connected to the solder pad 11 on the circuit board in sequence through the redistribution metal layer 30 and the conductive adhesive 40.

[0036] This invention utilizes a redistributed metal layer 30 within a through-silicon via (TSV) to conduct signals from the upper surface of a microdisplay chip 20 to the area beneath it. The microdisplay chip 20 is electrically connected to solder pads 11 on a circuit board via the redistributed metal layer 30 and conductive adhesive 40. In other words, the solder pads 11 (or electrical signals) on the circuit board are led out through the conductive adhesive 40 and the redistributed metal layer 30. The redistributed metal layer 30 within the TSV serves as the solder pad on the microdisplay chip 20. By using conductive adhesive 40 and the redistributed metal layer 30 to lead electrical signals from the circuit board to the solder pads on the upper surface of the microdisplay chip 20, the limitations of traditional gold wire bonding are avoided. This invention combines structural simplification with improved heat dissipation, making it suitable for high-brightness microdisplay modules.

[0037] Conductive adhesive 40 is, for example, an anisotropic conductive film, which is a thin film material that simultaneously possesses adhesive, mechanical, and electrical connection functions. In the vertical direction, when subjected to heat and pressure, the conductive particles inside the anisotropic conductive film are compressed, forming a unique current path. In the horizontal direction, the density of the conductive particles is insufficient for them to contact each other, and they are separated by an insulating resin matrix, thus preventing short circuits between adjacent lines.

[0038] For example, thermally conductive adhesive 50 is provided at the interface between the microdisplay chip 20 and the circuit board 10. For instance, thermally conductive adhesive 50 can be filled in the middle area between the conductive adhesives 40 at both ends.

[0039] This makes the heat conduction path more direct and improves heat dissipation efficiency. Simulation results show that the thermally conductive adhesive 50 can form additional heat conduction channels, significantly reducing local temperature rise. This invention combines the advantages of high-density interconnection and thermal management, breaking through the limitations of traditional packaging and making it suitable for miniaturization and high-power applications. The thermally conductive adhesive 50 includes at least one of silver paste, copper paste, carbon paste, or alumina paste. The thermally conductive adhesive 50 has high insulation strength, high conductivity, and good high-temperature adhesion.

[0040] In one example, a redistributed metal layer 30 fills the through-silicon vias and extends downwards onto the peripheral surface and part of the lower surface of the microdisplay chip 20. An insulating layer 60 is formed on the lower surface of the redistributed metal layer 30. An adhesive 70 is filled between the insulating layer 60 and the circuit board 10. The adhesive 70 has high thermal conductivity and may be, for example, any one of epoxy resin, potting compound, or adhesive, or other suitable materials.

[0041] Figure 2 This is a schematic diagram of the power pin pad 31 and heat dissipation pad 32 on the upper surface of the microdisplay packaging structure according to an embodiment of the present invention. Figure 2 As shown, the surface of the microdisplay chip 20 is provided with power pin pads 31 that easily generate heat. Through-silicon vias (TSVs) are provided on both sides or one side of the power pin pads 31. The portion of the redistribution metal layer 30 located within the TSVs serves as a thermal pad 32, which can also function as a ground pin. The width of the thermal pad 32 is 2 to 10 times the width of the power pin pads 31. For example, the thermal pads 32 and 31 are arranged parallel to each other and have the same length and thickness. Power pins are, for example, pins used for carrying high current, heat dissipation, or connecting to high-power supplies. Examples of power pins include VDD, VDDI, and VEE, etc. The power pin configuration is based on actual needs and is not limited.

[0042] The heat dissipation pad 32 in the through-silicon via, the redistributed metal layer below it, the conductive adhesive 40, and the pad 11 on the circuit board form a heat dissipation path. This heat dissipation path is provided on both sides or one side of the power pin pad 31 to guide and shunt the heat source.

[0043] Figure 3 This is a list of temperature ratios corresponding to different ratios of the width of the thermal pad to the width of the power pin pad in the microdisplay packaging structure of this invention. Figure 4 This is a bar chart showing the cooling ratio corresponding to different ratios of the width of the thermal pad to the width of the power pin pad in the microdisplay packaging structure of this invention. Figure 5This is a schematic diagram showing the simulated temperature corresponding to different ratios of the width of the power pin pad to the width of the heat dissipation pad in the microdisplay packaging structure of this invention.

[0044] like Figures 3 to 5 As shown, the formula for calculating thermal resistance is: Rth = L / (k*A); where Rth is the thermal resistance (the lower the thermal resistance, the faster the heat dissipation); L is the length of the heat conduction path; k is the thermal conductivity of the material; and A is the cross-sectional area (wire width W * thickness t). The ratio of the width W of the thermal pad 32 to the width of the power pin pad 31 is denoted as the width ratio Rw. Further investigation reveals that when the width ratio Rw is 1, heat easily creates a thermal bottleneck in the path. When the width ratio Rw is 3, the thermal resistance decreases significantly, and the heat dissipation efficiency increases by approximately 40-60%. When the width ratio Rw is 5, under the same thickness t, the cross-sectional area A increases by 5 times, which directly reduces the thermal resistance of the path by 80%. This encourages heat to flow more readily to the thermal pad 32 path rather than accumulating on the microdisplay chip 20; the heat dissipation path is extremely unobstructed, effectively handling high power densities such as 100mW. When the width ratio Rw is greater than 5 and less than 10, the improvement in heat dissipation efficiency plateaus, and too much space is sacrificed, since other signal lines need to be installed. When the width ratio Rw is greater than 10, it will result in excessive wiring space being occupied. Therefore, the width of the thermal pad 32 should be 2 to 10 times the width of the power pin pad 31.

[0045] The power pin pad 31 has heat dissipation paths on both sides or one side to guide and distribute heat. In instantaneous simulation, for the same length, the wider the heat dissipation path, the more heat energy can be removed from the power pin. The ratio of the width of the heat dissipation pad 32 to the width of the power pin pad 31 is denoted as the width ratio Rw. The ratio of the temperature of the heat dissipation pad 32 to the temperature of the power pin pad 31 is denoted as the temperature ratio Rt.

[0046] The heat dissipation structure of this invention effectively reduces the heat load in the adjacent area by adjusting the ratio of the width of the heat dissipation pad 32 to the width of the power pin pad 31. When the width ratio Rw is between 2 and 5, the temperature of the heat dissipation pad 32 can be maintained between 56% and 69% of the temperature of the power pin pad 31. Data shows that as the width ratio Rw increases, the relative temperature of the heat dissipation pad 32 decreases, especially when the width ratio is 2, achieving a cooling effect of approximately 31%; and when the width ratio is increased to 5, the cooling efficiency can be further improved to approximately 44%, indicating that the expansion of the heat dissipation pad 32 is beneficial for heat diffusion and dissipation.

[0047] Figure 6 This is a schematic diagram illustrating the simulated temperatures of the flexible circuit board surface with and without a graphene heat dissipation coating in the microdisplay packaging structure of this invention, according to an embodiment of the invention. Figure 1 and Figure 6 As shown, circuit board 10 includes any one of flexible circuit board, printed circuit board, and ceramic substrate. In one example, circuit board 10 is a flexible circuit board, and a graphene heat dissipation coating is formed on the upper and / or lower surfaces of the flexible circuit board. The thickness of the graphene heat dissipation coating ranges from 5 μm to 25 μm. The graphene heat dissipation coating is designed to accommodate the flexibility of the flexible circuit board.

[0048] The microdisplay packaging structure of this invention can be widely used in LCOS and μLED microdisplay modules, automotive displays, and high-brightness projection. Improved heat dissipation and interconnection efficiency support higher brightness and smaller designs, while enhancing reliability.

[0049] The microdisplay packaging structure of this invention has passed reliability verification, including thermal cycling tests, mechanical bending tests, and long-term stability assessments. By comprehensively considering the bonding accuracy of the conductive adhesive 40, the consistency of the silver paste wire shape, and the yield of through-silicon vias, process stability is ensured, costs are reduced, and yield is improved.

[0050] In summary, the present invention provides a microdisplay packaging structure, comprising: a circuit board and a microdisplay chip located on the circuit board, the microdisplay chip including a MicroLED chip or an LCOS chip; a through-silicon via (TSV) is provided in the microdisplay chip, and a redistributed metal layer is located in the TSV and on a portion of the lower surface of the microdisplay chip; conductive adhesive is provided between the solder pads on the circuit board and the microdisplay chip.

[0051] This invention utilizes a redistributed metal layer within a through-silicon via (TSV) to conduct signals from the surface of a microdisplay chip to the area beneath it. The microdisplay chip is electrically connected to solder pads on a circuit board via the redistributed metal layer, conductive adhesive, and so on. In other words, the solder pads (or electrical signals) on the circuit board are led out through the conductive adhesive and the redistributed metal layer, which serves as the solder pad on the microdisplay chip. By using conductive adhesive and a redistributed metal layer to lead electrical signals from the circuit board to the solder pads on the surface of the microdisplay chip, the limitations of traditional gold wire bonding are avoided. This invention combines structural simplification and improved heat dissipation, making it suitable for high-brightness microdisplay modules; it also offers advantages in high-density interconnection and thermal management, breaking through traditional packaging limitations and making it suitable for miniaturization and high-power applications.

[0052] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.

[0053] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A microdisplay packaging structure, characterized in that, include: A circuit board and a microdisplay chip located on the circuit board, the microdisplay chip including a MicroLED chip or an LCOS chip; The microdisplay chip has through-silicon vias, and a redistributed metal layer is located in the through-silicon vias and on part of the lower surface of the microdisplay chip; A conductive adhesive is disposed between the solder pads on the circuit board and the microdisplay chip, and the microdisplay chip is electrically connected to the solder pads on the circuit board in sequence through the redistributed metal layer and the conductive adhesive.

2. The microdisplay packaging structure as described in claim 1, characterized in that, Thermally conductive adhesive is provided at the interface between the microdisplay chip and the circuit board.

3. The microdisplay packaging structure as described in claim 2, characterized in that, The thermally conductive adhesive includes at least one of the following: silver adhesive, copper adhesive, carbon adhesive, or alumina adhesive.

4. The microdisplay packaging structure as described in claim 1, characterized in that, The redistributed metal layer fills the through-silicon via and extends downwards onto the peripheral surface and part of the lower surface of the microdisplay chip; An insulating layer is formed on the surface of the redistributed metal layer; The space between the insulating layer and the circuit board is filled with colloid.

5. The microdisplay packaging structure as described in claim 1, characterized in that, The surface of the microdisplay chip is provided with power pin pads that are prone to generating heat. The through-silicon vias are provided on both sides or one side of the power pin pads. The portion of the redistributed metal layer located in the through-silicon vias serves as a heat dissipation pad, and the heat dissipation pad serves as a ground pin.

6. The microdisplay packaging structure as described in claim 5, characterized in that, The width of the heat dissipation pad is 2 to 10 times the width of the power pin pad.

7. The microdisplay packaging structure as described in claim 5, characterized in that, The heat dissipation pad and the power pin pad are arranged in parallel and have the same length and thickness.

8. The microdisplay packaging structure as described in claim 1, characterized in that, The circuit board includes any one of flexible circuit boards, printed circuit boards, and ceramic substrates.

9. The microdisplay packaging structure as described in claim 8, characterized in that, The circuit board is a flexible circuit board, and a graphene heat dissipation coating is formed on the upper and / or lower surfaces of the flexible circuit board.

10. The microdisplay packaging structure as described in claim 8, characterized in that, The thickness of the graphene heat dissipation coating ranges from 5μm to 25μm.

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