Display device and display method

Abstract

The application provides a display device and a display method. In the display device, a system-level chip transmits display data to a driving circuit and controls the display panel to switch the transmission rate of the display data; the driving circuit comprises a timing controller chip, which monitors the boot state of the display panel when the system-level chip controls the display panel to switch the transmission rate of the display data, and works at a preset initial clock frequency to parse the display data at the initial clock frequency to obtain an initial transmission rate of the display data when the display panel is detected to be booted; then the initial clock frequency is adjusted to obtain a target clock frequency matched with the real-time transmitted display data. Thus, the timing controller chip works at the initial clock frequency when the display panel is booted, and then is dynamically adjusted to match the actual transmission rate of the system-level chip, so that the clock frequency can be adaptively adjusted to reduce power consumption and improve energy efficiency.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and display method. Background Technology

[0002] In existing display device architectures, the system-on-a-chip (SoC) is responsible for generating display data and transmitting it to the driver circuit. The driver circuit includes a timing controller chip and other auxiliary chips. After receiving the data, the timing controller chip parses it and drives the display panel to complete the image display. In current technology, the internal clock frequency of the timing controller chip is fixed at its maximum value to ensure it can handle the maximum data transmission rate that the SoC might output. For example, when the SoC transmits display data at a rate of 4.29 Gbit / s, the internal clock frequency of the timing controller chip is typically set to 4.5 Gbit / s. However, in scenarios where the SoC actively reduces the display data transmission rate, such as switching to 1 Gbit / s, the timing controller chip still maintains a high-frequency operation of 4.5 Gbit / s, causing the clock circuit to continuously consume additional energy. This fixed high-frequency operation mechanism causes unnecessary power waste during low-rate transmission. Especially during dynamic switching of display data transmission rates, the timing controller chip lacks the ability to adaptively adjust to the real-time transmission rate and cannot optimize the clock frequency according to the display panel's power-on status or changes in data content, further exacerbating the energy consumption problem. Summary of the Invention

[0003] This application provides a display device and display method that have the advantage of adaptively adjusting the clock frequency to match the actual transmission rate, thereby reducing power consumption and improving the energy efficiency of the display device.

[0004] In a first aspect, the display device provided in the embodiments of this application includes a system-on-a-chip, a driving circuit, and a display panel, wherein the driving circuit is connected to the system-on-a-chip and the display panel respectively; The system-on-a-chip is used to transmit display data to the driving circuit and control the display panel to switch the transmission rate of the display data. The driving circuit includes a timing controller chip, which is used for: When the system-on-a-chip controls the display panel to switch the transmission rate of the display data, it monitors the power-on status of the display panel and operates at a preset initial clock frequency when the display panel is detected to be powered on. The display data is parsed at the initial clock frequency to obtain the initial transmission rate of the display data; The initial clock frequency is adjusted according to the display data transmitted in real time by the system chip to obtain a target clock frequency that matches the real-time transmitted display data.

[0005] Secondly, the display method provided in the embodiments of this application is applied to a display device, and the method includes: The system-on-a-chip transmits display data to the driving circuit and controls the display panel to switch the transmission rate of the display data. When the system-on-a-chip controls the display panel to switch the transmission rate of the display data, the driving circuit monitors the power-on status of the display panel and operates at a preset initial clock frequency when the display panel is detected to be powered on. The display data is parsed at the initial clock frequency to obtain the initial transmission rate of the display data; the initial clock frequency is adjusted according to the display data transmitted in real time by the system-on-a-chip to obtain a target clock frequency that matches the real-time transmitted display data.

[0006] In summary, the display device and display method provided in this application operate at the initial clock frequency when the display panel is powered on by a timing controller chip, and dynamically adjust it to match the actual transmission rate of the system-on-a-chip. This solves the problem of power consumption waste caused by fixed high-frequency operation in the prior art, and has the advantages of adaptively adjusting the clock frequency to reduce power consumption and improve energy efficiency. Attached Figure Description

[0007] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for illustrating some embodiments of the present invention. Those skilled in the art can obtain other drawings based on the above drawings without any creative effort.

[0008] Figure 1 This is one of the schematic diagrams of a display device provided for an embodiment of this application.

[0009] Figure 2 This is a second schematic diagram of a display device provided for an embodiment of this application.

[0010] Figure 3 This is a schematic diagram illustrating the process of a system-on-a-chip (SoC) switching transmission rates according to user selection, as provided in an embodiment of this application.

[0011] Figure 4 This is a schematic diagram illustrating the process of a timing controller chip responding to rate switching, provided for an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0013] In this invention, the terms "first," "second," etc., are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to the aforementioned process, method, product, or apparatus.

[0014] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply that all embodiments are the same, nor are they independent or alternative embodiments mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0015] This application provides a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0016] In one embodiment, Figure 1 One of the schematic diagrams of a display device provided for an embodiment of this application; as shown Figure 1 As shown, the display device 100 includes a system on chip (SoC) 101, a driving circuit 102, and a display panel 103. The driving circuit 102 is connected to the system on chip 101 and the display panel 103 respectively. The system-on-a-chip 101 is used to transmit display data to the driving circuit 102 and control the display panel 103 to switch the transmission rate of display data. The drive circuit 102 includes a timing controller chip (Tcon), which is used for: When the system-on-chip 101 controls the display panel 103 to switch the transmission rate of display data, it monitors the power-on status of the display panel 103, and when it detects that the display panel 103 is powered on, it operates at a preset initial clock frequency. The display data is parsed using the initial clock frequency to obtain the initial transmission rate of the display data; The initial clock frequency is adjusted according to the display data transmitted in real time by the system-on-chip 101 to obtain a target clock frequency that matches the real-time transmitted display data.

[0017] Specifically, the system-on-chip 101 can integrate a display controller module to generate display data through software programming or hardware logic circuits. The system-on-chip 101 transmits display data to the driver circuit 102 via a dedicated interface. Simultaneously, the system-on-chip 101 can send control commands to the driver circuit 102 based on preset display modes, user operations, or system states to switch the data transmission rate of the display panel 103. For example, when the displayed content switches from high frame rate video to a static image, the system-on-chip 101 can instruct the display panel 103 to reduce its data transmission rate.

[0018] When the system-on-a-chip 101 controls the display panel 103 to switch the display data transmission rate, the timing controller chip monitors the power-on status of the display panel 103. This monitoring can be achieved by detecting the power supply voltage of the display panel 103, a reset signal, or a specific handshake protocol signal. Once the display panel 103 is detected to be in the power-on state, the internal clock circuit of the timing controller chip will be set to a preset initial clock frequency. This initial clock frequency setting is usually fixed and relatively high.

[0019] The timing controller chip parses the received display data using the initial clock frequency to identify the initial transmission rate of the display data. This parsing process can utilize the timing controller chip's internal phase-locked loop circuit or frequency synthesizer for data sampling and decoding. After identifying the initial transmission rate, the timing controller chip adjusts its internal clock frequency according to this initial transmission rate to obtain a target clock frequency. The target clock frequency is designed to match the real-time transmission rate of the display data transmitted by the system-on-chip 101. For example, the timing controller chip can calculate a fixed multiple slightly higher than the identified initial transmission rate as the target clock frequency using an internal algorithm or lookup table. The target clock frequency can be the internal clock frequency determined by the timing controller chip after adjustment based on the real-time transmission rate of the display data transmitted by the system-on-chip 101, ensuring that the timing controller chip's parsing frequency matches the actual data transmission rate. The initial transmission rate can be the actual transmission rate of the display data identified by the timing controller chip after parsing the display data using the initial clock frequency.

[0020] As an example, the driving circuit 102 further includes a panel driver chip connected to the timing controller chip; the timing controller chip is further configured to: synchronously adjust the data transmission rate transmitted to the panel driver chip based on the target clock frequency, so that the operating frequency of the panel driver chip matches the target clock frequency of the timing controller chip, so as to drive the display panel to display the image.

[0021] Specifically, the timing controller chip adjusts the data transmission rate of the panel driver chip in the driving circuit 102 based on the target clock frequency. The timing controller chip sends instructions to the panel driver chips (e.g., source driver chips, gate driver chips) via an internal control bus or dedicated interface, informing them of the new data transmission rate. The panel driver chips adjust their internal operating timing and drive parameters according to the received instructions to adapt to the new transmission rate and generate corresponding drive signals, ultimately driving the display panel 103 to display the image. For example, the source driver chip can adjust its data sampling frequency and output timing to ensure synchronization with the pixel refresh of the display panel 103. The panel driver chips can be auxiliary chips in the driving circuit 102 other than the timing controller chip, such as source driver chips, gate driver chips, power management chips, etc., which work together to drive the display panel 103 under the coordination of the timing controller chip. The data transmission rate can be the data transmission rate determined by the panel driver chip based on the target clock frequency adjusted by the timing controller chip, used to drive the display panel 103 to display the image.

[0022] As an example, a timing controller chip can also be called a main chip; a panel driver chip can also be called an auxiliary chip. Figure 2 A second schematic diagram of a display device provided for an embodiment of this application; as shown Figure 2 As shown, all display data originates from an external SOC. The SOC transmits display signals to the main chip Tcon of the display panel driver circuit. After parsing the data, Tcon sends the actions to be performed to the various auxiliary chips in the circuit.

[0023] The display device of this application monitors the power-on status of the display panel 103 through a timing controller chip and operates at a preset initial clock frequency upon power-on. Subsequently, the timing controller chip parses the display data to obtain an initial transmission rate, and then adjusts its internal clock frequency to a target clock frequency to match the real-time display data rate transmitted by the system-on-a-chip 101. Thus, the panel driver chip in the driving circuit 102 can adjust its operating rate based on this target clock frequency, effectively avoiding the waste of speed resources and power consumption caused by a fixed, excessively high clock frequency in traditional solutions, thereby improving the energy efficiency of the display device.

[0024] In some embodiments of this application, if the display panel 103 remains in operation during the switching of display data transmission rates, its display screen may exhibit visual artifacts such as brief flickering, tearing, or screen distortion due to the instability of the data stream or the resynchronization of timing. This may not only affect the user's viewing experience but also cause unnecessary power consumption during the switching process.

[0025] Based on this, in one embodiment, the system-on-a-chip 101 is also used to transmit display data according to the user's operation information, and to turn off the power supply to the display panel 103 when switching the transmission rate, and to turn on the power supply to the display panel 103 after the transmission rate switching is completed.

[0026] Specifically, the system-on-chip 101 transmits display data based on user operation information, responding to specific user needs. For example, when a user is watching high frame rate videos, playing games, or performing other interactions requiring a high refresh rate, the system-on-chip 101 will determine that a higher display data transmission rate is needed based on the operation information; when the user is in static browsing, reading, or low-power mode, the system-on-chip 101 may determine that a lower transmission rate is needed. This method of transmitting data based on user operation information allows the display device to adapt more intelligently and flexibly to different usage scenarios, optimizing performance and power consumption.

[0027] During data transmission rate switching, turning off the power supply to the display panel 103 can effectively prevent display abnormalities caused by signal instability or timing mismatch due to changes in transmission rate. When the display panel 103 is in a power-off state, its display circuit stops working and will not receive potentially unstable data streams, thus avoiding undesirable display effects such as screen flickering, distorted images, or black screens during rate switching. Turning off the power supply can be achieved by controlling the power management unit (PMU) of the display panel 103 or by disconnecting the power line.

[0028] After the data transmission rate switch is completed, i.e., the transmission link between the system-on-a-chip 101 and the driver circuit 102 has stabilized at the new transmission rate, and the timing controller chip has completed the corresponding clock frequency adjustment and data parsing preparation, power is restored to the display panel 103. During power restoration, a preset startup sequence is typically followed to ensure that the display panel 103 can stably receive the new, stable display data stream and display the image normally. This strategy of shutting down before re-powering ensures that the display panel 103 only starts working after receiving a stable data stream, thereby guaranteeing the quality and stability of the display image.

[0029] In this application, the system-on-a-chip 101 can intelligently adjust the transmission rate of display data according to the user's actual operating needs, thereby achieving a balance between performance and power consumption. More importantly, during the critical stage of transmission rate switching, by temporarily shutting off the power supply to the display panel 103, signal instability that may be caused by rate changes can be effectively isolated, avoiding visual artifacts such as flickering and tearing of the display screen, and significantly improving the user's visual experience when switching between different display modes. After the new transmission rate is established stably, the power supply to the display panel 103 is restored, ensuring that the display panel 103 only starts working when it receives a stable, high-quality display data stream, thereby guaranteeing the continuity and stability of the display screen, while avoiding unnecessary power consumption of the display panel 103 during rate switching.

[0030] In some embodiments of this application, at the moment the display panel 103 is powered on or re-energized, the display data signal may not yet be fully stable, or the timing controller chip may not yet be fully prepared for accurate parsing. If parsing is performed immediately at this time, it may lead to misjudgment of the initial transmission rate, thereby affecting the subsequent adjustment of the clock frequency and the stability of the display screen.

[0031] Based on this, in one embodiment, the timing controller chip is also used to maintain a preset parsing duration at the initial clock frequency when the display panel 103 is powered on or when the display panel 103 is re-powered, so as to identify the initial transmission rate.

[0032] Specifically, the timing controller chip is the core component of the driver circuit 102. It is responsible for receiving display data from the system-on-a-chip 101, performing timing control and processing, and ultimately driving the display panel 103 to display the image. When the display panel 103 is powered on or re-powered under the control of the system-on-a-chip 101, such as after the display data transmission rate switch is completed, the system-on-a-chip 101 will transmit display data according to the user's operation information and re-power the display panel 103. During the startup or recovery phase, there may be brief signal instability or setup time during the transmission of display data signals from the system-on-a-chip 101 to the timing controller chip. To ensure that the timing controller chip can accurately identify the initial transmission rate of the display data transmitted in real time by the system-on-a-chip 101, the timing controller chip is configured not to immediately identify the transmission rate when it detects that the display panel 103 is powered on or re-powered, but instead to first operate at a preset initial clock frequency and maintain a preset resolution duration. The preset parsing duration can be a fixed time period, such as milliseconds or microseconds. Its specific value can be determined through system design or factory calibration and stored in the timing controller chip's internal registers or non-volatile memory. Within this parsing duration, the timing controller chip continuously samples and analyzes the incoming display data at the initial clock frequency, allowing the signal to stabilize sufficiently. After the preset parsing duration ends, the timing controller chip accurately identifies the initial transmission rate of the display data based on the stable data collected during this period. The process of identifying the initial transmission rate may include analyzing specific synchronization signals, packet header information, or clock recovery signals in the data stream.

[0033] As an example, Figure 3 This is a schematic diagram illustrating the process of a system-on-a-chip (SoC) switching transmission rates based on user selection, as provided in an embodiment of this application. Figure 3 As shown, when the SOC switches rates, it first shuts off the power to the display panel and sets Tcon to always operate at its highest frequency upon power-on to analyze the SOC input rate. This prevents Tcon from being unable to analyze high-speed data transmissions when operating at a low frequency.

[0034] When the display panel 103 is powered on or re-energized, the timing controller chip maintains a preset parsing duration at the initial clock frequency. This effectively avoids parsing before the signal is fully stable, thus ensuring accurate identification of the initial transmission rate. This improves the stability and reliability of the display device during startup or transmission rate switching, preventing display abnormalities or system instability caused by misjudgment of the transmission rate, thereby guaranteeing normal display presentation and a smooth user experience. Especially in scenarios where the system-on-a-chip 101 frequently switches transmission rates based on user operation information, coinciding with the power switch of the display panel 103, this technical solution effectively addresses signal instability, ensuring that the timing controller chip quickly and accurately enters normal operating mode after each rate switch and panel power restoration, thereby improving the robustness of the entire display system and the user experience.

[0035] In some embodiments of this application, in scenarios where the display data transmission rate frequently switches or is transmitted at high speed, simply matching the transmission rate may not be sufficient to guarantee the integrity of the signal, which may lead to signal distortion, data errors, and thus affect the quality and stability of the display screen.

[0036] Based on this, in one embodiment, the timing controller chip is further configured to: after synchronously adjusting the data transmission rate transmitted to the panel driver chip based on the target clock frequency, determine the target eye diagram parameters that match the data transmission rate according to a preset eye diagram parameter correspondence, and transmit display data to the panel driver chip according to the target eye diagram parameters to ensure the transmission quality of the display data; the preset eye diagram parameter correspondence is a mapping data table of display data transmission rate and eye diagram parameters verified by the timing controller chip through experiments.

[0037] Specifically, when the display data transmitted in real time by the system-on-a-chip 101 causes the timing controller chip to adjust its clock frequency, and consequently adjust the data transmission rate of the panel driver chip connected to the timing controller chip, the timing controller chip uses the currently determined data transmission rate as a lookup key to search for a matching set of eye diagram parameters in a pre-stored mapping relationship. This is the target eye diagram parameter, which indicates the physical layer transmission characteristics required to ensure signal quality at the given data transmission rate. Subsequently, the timing controller chip transmits display data to the panel driver chip according to the target eye diagram parameter to ensure the transmission quality of the display data. After determining the target eye diagram parameter, the timing controller chip configures the physical layer settings of its internal transmitter or receiver, as well as the data transmission interface with the panel driver chip, based on the parameter. As an example, Figure 4 This is a schematic diagram illustrating the process of a timing controller chip responding to rate switching, provided as an embodiment of this application. Figure 4As shown, when the SOC switches data rates, it will power off the display panel. A power-on check is configured on the Tcon. Upon power-on, the Tcon is set to operate at its highest frequency. The highest frequency of the Tcon is used to analyze the data rate sent by the SOC. Based on the analyzed SOC data rate, the Tcon automatically adjusts its internal clock to precisely match the data rate transmitted by the SOC. After the Tcon's internal clock is adjusted, the data rate output by the Tcon to other panel driver ICs also needs to be adjusted accordingly. The Tcon needs to establish a table mapping data rates to eye diagram parameters internally. After adjusting the data rate sent by the Tcon to other panel driver ICs, the corresponding eye diagram is adjusted to ensure data transmission quality.

[0038] In this application, the display device can actively manage and optimize the physical transmission characteristics of signals when dynamically adjusting the display data transmission rate. The timing controller chip pre-establishes and stores the correspondence between transmission rate and eye diagram parameters, enabling the rapid determination and application of the optimal eye diagram parameters matching the current rate after a change in transmission rate. Based on the target eye diagram parameters, the timing controller chip can finely adjust the physical layer settings for data transmission, effectively offsetting signal integrity issues such as attenuation, crosstalk, and jitter that may occur during high-speed signal transmission. This ensures that even with frequent transmission rate switching or at extremely high transmission rates, display data can be transmitted to the panel driver chip with high quality and high reliability, thereby avoiding display flickering, screen distortion, or data errors caused by signal distortion, significantly improving display stability and user experience.

[0039] In some embodiments of this application, when the transmission rate of the display data changes, the signal may be distorted, such as inter-symbol interference, increased jitter, or amplitude attenuation. Relying solely on preset eye diagram parameters may not be able to effectively compensate for the distortion, thereby affecting the transmission quality and stability of the display data.

[0040] Based on this, in one embodiment, the target eye diagram parameters include eye height parameters, eye width parameters, jitter parameters, eye cross ratio parameters, and time parameters when the transmission rate changes; the timing controller chip is also used to adjust the eye height parameters, eye width parameters, jitter parameters, eye cross ratio parameters, and time parameters to compensate for signal distortion caused by changes in the transmission rate.

[0041] Specifically, the eye height parameter measures the vertical aperture size of a signal, reflecting its noise margin and amplitude distortion. Timing controller chips can optimize the eye height parameter by adjusting the drive voltage at the transmitter or the equalizer gain at the receiver to ensure sufficient amplitude margin during transmission, effectively resisting noise interference. The eye width parameter measures the horizontal aperture size of a signal, reflecting its timing margin and jitter. Timing controller chips can optimize the eye width parameter by adjusting the bandwidth of the clock recovery circuit, the data sampling points, or introducing jitter compensation mechanisms to improve the system's tolerance to jitter and ensure accurate data sampling within the correct clock cycle. The jitter parameter measures the deviation of the signal edge from its ideal position. Timing controller chips can reduce signal jitter by optimizing the performance of the phase-locked loop, using jitter attenuation circuits, or implementing feedforward / feedback control algorithms, thereby improving timing accuracy and reducing bit error rate. The eye crossover ratio parameter measures the vertical position of the eye diagram crossover point, typically representing the signal's DC bias or common-mode noise. Timing controller chips can optimize the eye cross ratio parameter by adjusting the common-mode voltage or the balance of the differential signal to ensure stable DC characteristics of the signal and reduce common-mode interference.

[0042] The timing controller chip dynamically adjusts the aforementioned eye diagram parameters by monitoring signal quality in real time or according to a preset rate switching strategy. For example, when a change in transmission rate is detected, the timing controller chip can calculate the optimal combination of eye diagram parameters based on a preset adjustment algorithm or lookup table, and control the corresponding hardware modules (such as transmit drivers, receive equalizers, clock recovery circuits, etc.) to adjust the parameters. This allows the system to proactively adapt to changes in transmission rate, thereby effectively offsetting the resulting signal distortion.

[0043] In this application, the timing controller chip can dynamically adjust the eye height parameter, eye width parameter, jitter parameter, eye cross ratio parameter, and time parameter when the transmission rate changes according to the change in transmission rate, so that the display device can effectively compensate for and offset the signal distortion caused by the change in transmission rate.

[0044] In some embodiments of this application, different transmission rate scenarios place different emphasis on the efficiency and stability of signal transmission. For example, in high-speed transmission, it is challenging to quickly complete rate switching while ensuring efficiency; while in low-speed transmission, it is more critical to effectively suppress crosstalk between signals to ensure data accuracy. If parameters are adjusted indiscriminately, it may not be possible to achieve the optimal balance between efficiency and signal quality.

[0045] Based on this, in one embodiment, the time parameters include a rise time parameter and a fall time parameter. The rise time parameter is the time it takes for the display data signal to transition from a low level to a high level, and the fall time parameter is the time it takes for the display data signal to transition from a high level to a low level. The timing controller chip is further configured to: determine whether the initial transmission rate is greater than a preset transmission rate threshold; when the initial transmission rate is greater than the transmission rate threshold, adjust the rise time parameter and the fall time parameter to be less than the preset time threshold to improve the efficiency of transmission rate switching; when the initial transmission rate is less than or equal to the transmission rate threshold, adjust the rise time parameter and the fall time parameter to be greater than or equal to the time threshold to reduce the crosstalk effect of transmission rate switching.

[0046] Specifically, when the initial transmission rate is determined to be greater than a preset transmission rate threshold, the timing controller chip adjusts the rise and fall time parameters to be less than the preset threshold. This makes the signal edges steeper, helping the signal reach a stable state faster, thus reducing signal setup time and improving data transmission efficiency. The timing controller chip can accelerate the rise and fall edges of the signal by sending control commands to its internal driver or signal processing module, such as increasing the drive current or adjusting the pre-emphasis intensity. This aims to improve the overall efficiency of transmission rate switching and reduce latency during the switching process. Conversely, when the initial transmission rate is determined to be less than or equal to the preset transmission rate threshold, the timing controller chip adjusts the rise and fall time parameters to be greater than or equal to the preset threshold. By appropriately extending the rise and fall times of the signal, the signal edges become smoother, effectively reducing high-frequency components of the signal and thus reducing electromagnetic interference to adjacent signal lines, i.e., reducing crosstalk during transmission rate switching. The timing controller chip can achieve smoother signal edges by reducing the drive current or adjusting the deemphasis intensity. This strategy aims to ensure the stability and accuracy of data transmission at lower transmission rates.

[0047] In some embodiments of this application, when the display device operates for a long time or the displayed content changes dynamically, the actual transmission rate of the system-on-a-chip 101 may fluctuate, causing a deviation between the current target clock frequency of the timing controller chip and the actual transmission rate of the system-on-a-chip 101. If this deviation persists or exceeds a certain range, it may lead to a decrease in system power efficiency or affect the stability of display data transmission.

[0048] Based on this, in one embodiment, the timing controller chip is also used to monitor the actual transmission rate of the system-on-a-chip 101, and when the deviation between the actual transmission rate and the target clock frequency is greater than a preset power efficiency threshold, the step of readjusting the initial clock frequency is triggered.

[0049] Specifically, the timing controller chip continuously or periodically acquires the current data transfer rate of the system-on-a-chip (SoC) 101. This can be achieved by the SoC 101 reporting its current output data rate to the timing controller chip via a dedicated communication channel (e.g., a sideband signal or a status register). Alternatively, the timing controller chip can infer the actual transfer rate of the SoC 101 by analyzing the incoming data stream (e.g., measuring the frequency of data pulses or counting data packets within a specific time period). Subsequently, the timing controller chip compares the monitored actual transfer rate of the SoC 101 with its current target clock frequency for processing data and calculates the difference between the two. This difference represents the deviation between the actual transfer rate and the target clock frequency.

[0050] The power efficiency threshold is a pre-defined, acceptable upper limit for deviation. When the deviation between the actual transmission rate and the target clock frequency exceeds this threshold, it indicates that the current operating state no longer offers optimal power efficiency or data transmission stability. This threshold can be stored in the timing controller chip's registers or memory and determined during the design or calibration phase to balance the overhead of readjustment with the benefits of power optimization or stability improvement. Once the deviation exceeds the preset power efficiency threshold, the timing controller chip initiates a process to re-evaluate and adjust its clock frequency. This process begins with a preset initial clock frequency, which is typically greater than the maximum data transmission rate of the system-on-chip 101 corresponding to the display device's highest refresh rate, to ensure robust data transmission during the readjustment process.

[0051] In this application, the display device can dynamically adapt to changes in the actual transmission rate of the system-on-a-chip (SoC) 101. The timing controller chip continuously monitors the actual transmission rate of the SoC 101 and compares it with its target clock frequency. Once the deviation exceeds a preset power efficiency threshold, it triggers a readjustment of the initial clock frequency. This ensures that the clock frequency of the timing controller chip is always closely matched to the actual data output rate of the SoC 101, effectively avoiding power efficiency degradation and data transmission instability caused by long-term deviations. This solution provides a robust and efficient frequency synchronization mechanism that optimizes system power consumption and maintains high-quality display data transmission even in dynamically changing operating environments.

[0052] In some embodiments of this application, the transmission rate of the system-on-a-chip 101 may experience brief fluctuations or instantaneous deviations. If frequency adjustment is triggered immediately every time a deviation is detected, the system may frequently perform unnecessary frequency switching, which not only increases system overhead and may affect the stability of the display screen, but may also lead to an unnecessary increase in power consumption. Therefore, a mechanism is needed to ensure that frequency adjustment is only performed when the deviation persists and reaches a certain level, in order to avoid misjudgment and over-response.

[0053] Based on this, in one embodiment, the timing controller chip includes a timer, and is further configured to start the timer when the deviation is greater than a power efficiency threshold; and to perform a step of adjusting the initial clock frequency when the deviation persists for a set duration of the timer.

[0054] Specifically, the timing controller chip integrates or connects a timer. This timer can be a hardware counter. The main function of the timer is to provide accurate time measurement capabilities so that after a specific event occurs, it can track and determine whether a condition has lasted for a certain duration. When the timing controller chip detects a deviation between the actual transmission rate of the system-on-chip 101 and the currently set target clock frequency, and the absolute value of this deviation exceeds a preset power efficiency threshold, the timing controller chip immediately starts its internal timer. The timer starts counting down from zero or from a preset starting value. The power efficiency threshold is a preset parameter used to define what level of deviation is considered to require attention and may need adjustment; its setting comprehensively considers factors such as power consumption, performance, and stability. After the timer starts, the timing controller chip continuously monitors the deviation between the actual transmission rate of the system-on-chip 101 and the target clock frequency. If the deviation remains greater than the power efficiency threshold for a preset duration set by the timer (e.g., a few milliseconds to tens of milliseconds), i.e., the deviation is not instantaneous but continuous, then the timing controller chip will execute the step of readjusting the initial clock frequency. The duration can be configured according to the actual application scenario and the system's stability requirements.

[0055] In this application, when the timing controller chip detects that the deviation between the actual transmission rate of the system-on-a-chip 101 and the target clock frequency exceeds the power efficiency threshold, it does not immediately trigger frequency adjustment. Instead, it first starts a timer to observe for a period of time. Only when the deviation persists within the set duration of the timer is the initial clock frequency readjusted. This effectively avoids frequent and unnecessary frequency switching caused by instantaneous fluctuations or brief deviations in the transmission rate of the system-on-a-chip 101. This improves the operational stability of the display device, reduces unnecessary system overhead and processing burden, thereby lowering overall power consumption. Simultaneously, by ensuring that frequency adjustment is only performed when truly needed, it also avoids display instability or visual artifacts that may be caused by frequent adjustments, thus improving the user experience.

[0056] In some implementations, if frequency adjustment is performed simply by matching based on the real-time transmission rate, it may result in frequent fluctuations in the clock frequency or the selected frequency may not be optimal, thereby affecting the power efficiency and stability of the system.

[0057] Based on this, in one embodiment, the timing controller chip has a preset set of standard clock frequencies optimized for power consumption. When adjusting the initial clock frequency, the timing controller chip selects a frequency greater than or equal to the actual transmission rate of the system-on-a-chip 101 from the standard clock frequencies as the target clock frequency.

[0058] Specifically, the timing controller chip or its connected memory unit pre-stores a set of discrete standard clock frequencies. These standard clock frequencies are determined by system designers during the R&D phase through comprehensive evaluation and optimization of multiple dimensions, including power consumption, performance, and signal integrity, under different operating modes and transmission rates. For example, they may include 100MHz, 200MHz, 300MHz, and 400MHz, which optimize the overall power consumption of the display device while ensuring display performance.

[0059] When the timing controller chip needs to adjust the initial clock frequency to match the real-time display data transmitted by the system-on-a-chip 101, the timing controller chip monitors the actual data transmission rate of the system-on-a-chip 101 in real time. Subsequently, the timing controller chip searches and selects from a preset set of power-optimized standard clock frequencies. Its selection logic is to select the minimum standard clock frequency that is greater than or equal to the current actual transmission rate as the target clock frequency, provided that the actual transmission rate requirement of the system-on-a-chip 101 is met.

[0060] This application employs a strategy of pre-setting a set of power-optimized standard clock frequencies and selecting a frequency greater than or equal to the actual transmission rate of the system-on-a-chip 101 from this set as the target clock frequency. This strategy allows the timing controller chip to avoid blind or frequent adjustments over a wide frequency range. It ensures that the selected target clock frequency meets the real-time display data transmission requirements of the system-on-a-chip 101 while maximizing the utilization of the pre-optimized frequency points. This effectively reduces the power consumption of the display device at different transmission rates, improving the system's energy efficiency and operational stability. Simultaneously, the discrete frequency selection mechanism simplifies the complexity of frequency adjustment, reducing signal integrity issues that may arise from frequency mismatch or frequent adjustments, thereby enhancing the stability and reliability of the displayed image.

[0061] In one embodiment, the system-on-a-chip 101 is further configured to: acquire content information of the display data; generate a frequency adjustment adaptation instruction based on the content information and send it to the timing controller chip, so that the timing controller chip determines an adaptation strategy for adjusting the initial clock frequency based on the frequency adjustment adaptation instruction, so as to balance the smoothness of the display screen and power consumption.

[0062] The system-on-a-chip 101 can acquire the type or characteristic information of the data to be displayed, i.e., the content information of the data to be displayed. The content information can be identified by analyzing the metadata of the displayed data stream (e.g., video encoding format, frame rate, content tags, etc.), or it can be acquired by real-time analysis of image or video frames (e.g., detecting inter-frame differences, motion vectors, texture complexity, etc.), or it can be provided by the operating system or application through a specific interface.

[0063] After acquiring the content information of the display data, the system-on-a-chip 101 generates corresponding frequency adjustment adaptation instructions based on the information. A frequency adjustment adaptation instruction is a set of signals or parameters that instructs the timing controller chip on how to adjust the initial clock frequency. The system-on-a-chip 101 can internally maintain a mapping table between content information and adaptation instructions; when specific content information is identified, the corresponding adaptation instruction is generated.

[0064] After receiving a frequency adjustment adaptation command, the timing controller chip determines an adaptation strategy for adjusting the initial clock frequency based on the command. The adaptation strategy is a set of rules and parameters that guide the timing controller chip in frequency adjustment. It may include, but is not limited to, response sensitivity (i.e., the speed of response to changes in the display data transmission rate), frequency adjustment step (i.e., the magnitude of each clock frequency adjustment), and response time (i.e., the time required from detecting a change to completing the frequency adjustment). The timing controller chip can preset multiple adaptation strategies and select one based on the received command, or dynamically calculate the corresponding strategy parameters based on the command. In this way, the timing controller chip can flexibly adjust the initial clock frequency according to the actual needs of the displayed content, achieving the optimal balance between display smoothness and system power consumption.

[0065] In this application, the system-on-a-chip 101 can actively acquire the content information of the display data and generate a frequency adjustment adaptation command based on this content information, which is then sent to the timing controller chip. After receiving the command, the timing controller chip no longer passively adjusts the frequency according to the real-time data transmission rate, but can adjust the initial clock frequency in a targeted manner according to a preset adaptation strategy.

[0066] In some implementations, different types of content (such as still images and dynamic videos) have significantly different requirements for smoothness and power consumption. If a single adaptation strategy is used, it may not be possible to simultaneously meet the low power consumption requirements of static content and the high smoothness requirements of dynamic content, resulting in wasted power consumption or screen stuttering in certain scenarios.

[0067] Based on this, in one embodiment, the adaptation strategy includes a first adaptation strategy and a second adaptation strategy; the first adaptation strategy includes a first response sensitivity parameter, a first frequency adjustment step parameter, and a first response time parameter; the second adaptation strategy includes a second response sensitivity parameter, a second frequency adjustment step parameter, and a second response time parameter; the system-on-a-chip 101 is further configured to: when the content information is statically displayed, adopt the first adaptation strategy to save power consumption of the display screen; wherein, the first response sensitivity parameter is less than the second response sensitivity parameter, the first frequency adjustment step parameter is greater than the second frequency adjustment step parameter, and the first response time parameter is greater than the second response time parameter; when the content information is dynamically displayed, adopt the second adaptation strategy to ensure the smoothness of the display screen; wherein, the second response sensitivity parameter is greater than the first response sensitivity parameter, the second frequency adjustment step parameter is less than the first frequency adjustment step parameter, and the second response time parameter is less than the first response time parameter.

[0068] The adaptation strategy refers to a set of rules or parameters used to guide the timing controller chip in adjusting its initial clock frequency. It defines how the display device responds to changes in the display data transmission rate and how it adjusts the frequency to achieve specific performance targets.

[0069] The first adaptation strategy is a set of adjustment parameters designed for static content information to maximize power savings in the display. The first response sensitivity parameter defines how sensitive the display device is to changes in the data transmission rate. When its value is less than the second response sensitivity parameter, the display device is less sensitive to small fluctuations in the transmission rate and tolerates larger deviations before triggering frequency adjustments, thus reducing unnecessary adjustments and lowering power consumption. The first frequency adjustment step parameter determines the magnitude of each frequency adjustment. When its value is greater than the second frequency adjustment step parameter, it means the display device will adjust with larger steps when adjustments are needed. For static content, even with larger adjustment steps, the image quality will not be significantly affected; instead, it may reach a stable state more quickly, reducing the number of adjustments. The first response time parameter represents the time delay between detecting the need for adjustment and actually executing the adjustment. When its value is greater than the second response time parameter, the display device will wait longer before performing frequency adjustments. This delay helps filter out brief, non-continuous rate fluctuations, further reducing the adjustment frequency and thus lowering power consumption.

[0070] The second adaptation strategy is a set of adjustment parameters designed for dynamically displayed content to ensure smooth display. The second response sensitivity parameter defines how sensitive the display device is to changes in the data transmission rate. When its value is greater than the first response sensitivity parameter, the display device is more sensitive to even small changes in the transmission rate, enabling it to respond quickly and trigger frequency adjustments to ensure real-time updates and smooth display of dynamic images. The second frequency adjustment step parameter determines the magnitude of each frequency adjustment. When its value is less than the first frequency adjustment step parameter, it indicates that the display device will adjust in smaller steps when adjustments are needed.

[0071] The system-on-chip 101 intelligently selects an appropriate adaptation strategy by analyzing the content information of the displayed data, such as determining whether it is a static image (e.g., a document, webpage, desktop) or a dynamic video (e.g., a movie, a game). This content type-based strategy selection mechanism enables the display device to dynamically optimize between power consumption and smoothness according to actual needs.

[0072] This application utilizes a system-on-a-chip 101 to intelligently select different frequency adjustment adaptation strategies based on the content information of the displayed data, thereby maximizing power saving while ensuring smooth display. Specifically, when the content is static, the display device employs a first adaptation strategy, which features low response sensitivity, a large frequency adjustment step, and a long response time. This allows the timing controller chip to reduce unnecessary frequency adjustments and filter out brief rate fluctuations when dealing with static images, significantly reducing power consumption and extending battery life without affecting the viewing experience. When the content is dynamic, the display device employs a second adaptation strategy, which features high response sensitivity, a small frequency adjustment step, and a short response time. This allows the timing controller chip to quickly and accurately respond to changes in the dynamic data transmission rate, ensuring high synchronization between the display frequency and the real-time data stream. This effectively avoids potential stuttering, tearing, or unsmoothness in dynamic images, providing users with a high-quality dynamic visual experience. The mechanism of dynamically switching adaptation strategies based on content type overcomes the limitation that a single strategy cannot balance power consumption and smoothness, and achieves the best performance balance of display devices in different application scenarios.

[0073] In some implementations, ensuring the efficiency, stability, and compatibility of display data transmission between the system-on-a-chip 101 and the driver circuit 102 is a technical challenge that needs to be addressed in display scenarios requiring high bandwidth, dynamic refresh rates, and strict signal integrity. Using generic or non-standardized interfaces may lead to signal attenuation, electromagnetic interference, or data transmission errors during high-speed switching, thereby affecting the quality of the display and the overall power consumption of the system.

[0074] Based on this, in one embodiment, the system-on-a-chip 101 includes an embedded display port interface; the system-on-a-chip 101 transmits display data through the embedded display port interface.

[0075] Specifically, the Embedded Display Port Interface (eDP) is a digital display interface standard designed specifically for internal display connections. It is based on the VESA DisplayPort standard but optimized for internal applications. This interface is typically integrated within the system-on-chip 101 as part of its display output module. The eDP features high bandwidth, low power consumption, and support for various advanced display functions (such as panel self-refresh and selective updates). Its physical layer typically uses differential signal transmission, effectively suppressing common-mode noise and improving the anti-interference capability and reliability of signal transmission. The link layer is responsible for data encapsulation, decapsulation, error detection, and correction to ensure the accuracy of data transmission. Auxiliary channels are used for transmitting control information such as link training, device configuration, and status monitoring. By integrating the eDP into the system-on-chip 101, a standardized, high-performance transmission channel for display data is provided.

[0076] The system-on-a-chip (SoC) 101 transmits display data via the embedded display port interface. This can be achieved by the SoC 101 encapsulating the image data to be displayed, timing control signals, and other relevant control information according to the embedded display port interface protocol, and then sending this data to the driver circuit 102 via its high-speed differential signal lines. The timing controller chip or other relevant chips in the driver circuit 102 then receive and parse the embedded display port interface data stream.

[0077] In this application, the system-on-a-chip 101 of the display device uses an embedded display port interface for display data transmission, thereby establishing a standardized, high-bandwidth, and robust internal data link. This solves the signal integrity, efficiency, and compatibility issues that may arise in display data transmission under dynamic transmission rate switching and high-resolution display scenarios. The differential signal transmission characteristics and protocol-level error detection mechanism of the embedded display port interface significantly improve the reliability of data transmission and reduce display anomalies caused by signal attenuation or interference. Simultaneously, its excellent support for multiple transmission rates allows the system-on-a-chip 101 to more flexibly control the transmission rate of the display panel 103 and seamlessly coordinate with the timing controller chip's frequency adjustment, eye diagram parameter optimization, and power management strategies. This ensures that the display maintains smoothness while effectively optimizing power consumption under different display content and user operations.

[0078] This application also proposes a display method using the aforementioned display device. The method includes: transmitting display data to a driving circuit 102 via a system-on-a-chip (SoC) 101 and controlling a display panel 103 to switch the transmission rate of the display data; while the SoC 101 controls the display panel 103 to switch the transmission rate of the display data, the driving circuit 102 monitors the power-on status of the display panel 103, and when the display panel 103 is detected to be powered on, operates at a preset initial clock frequency; the initial clock frequency is greater than the maximum data transmission rate of the SoC 101 corresponding to the highest refresh rate of the display device; parsing the display data at the initial clock frequency to obtain the initial transmission rate of the display data; and adjusting the initial clock frequency according to the display data transmitted in real-time by the SoC 101 to obtain a target clock frequency that matches the real-time transmitted display data.

[0079] The details of the display method can be found in the previous description of the display device, and will not be repeated here.

[0080] The display device and display method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. The above modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display device, characterized in that, It includes a system-on-a-chip, a driving circuit, and a display panel, wherein the driving circuit is connected to the system-on-a-chip and the display panel respectively; The system-on-a-chip is used to transmit display data to the driving circuit and control the display panel to switch the transmission rate of the display data. The driving circuit includes a timing controller chip, which is used for: When the system-on-a-chip controls the display panel to switch the transmission rate of the display data, it monitors the power-on status of the display panel and operates at a preset initial clock frequency when the display panel is detected to be powered on. The display data is parsed at the initial clock frequency to obtain the initial transmission rate of the display data; The initial clock frequency is adjusted according to the display data transmitted in real time by the system-on-a-chip to obtain a target clock frequency that matches the real-time transmitted display data.

2. The display device according to claim 1, characterized in that, The driving circuit also includes a panel driver chip connected to the timing controller chip; the timing controller chip is further configured to: synchronously adjust the data transmission rate transmitted to the panel driver chip based on the target clock frequency, so that the operating frequency of the panel driver chip matches the target clock frequency of the timing controller chip, so as to drive the display panel to display the image.

3. The display device according to claim 2, characterized in that, The timing controller chip is also used to maintain a preset parsing duration at the initial clock frequency when the display panel is powered on or when the display panel is re-powered, so as to identify the initial transmission rate.

4. The display device according to claim 2, characterized in that, The timing controller chip is also used for: After adjusting the data transmission rate to the panel driver chip based on the target clock frequency, a target eye diagram parameter matching the data transmission rate is determined according to a preset eye diagram parameter correspondence. Display data is then transmitted to the panel driver chip according to the target eye diagram parameter to ensure the transmission quality of the display data. The preset eye diagram parameter correspondence is a mapping data table of display data transmission rate and eye diagram parameter verified by the timing controller chip through experiments.

5. The display device according to claim 4, characterized in that, The target eye diagram parameters include eye height parameters, eye width parameters, jitter parameters, eye cross ratio parameters, and time parameters when the transmission rate changes. The timing controller chip is also used to adjust the eye height parameter, the eye width parameter, the jitter parameter, the eye cross ratio parameter, and the time parameter to compensate for signal distortion caused by changes in the transmission rate.

6. The display device according to claim 5, characterized in that, The time parameters include a rise time parameter and a fall time parameter. The rise time parameter is the time it takes for the display data signal to transition from a low level to a high level, and the fall time parameter is the time it takes for the display data signal to transition from a high level to a low level. The timing controller chip is also used for: Determine whether the initial transmission rate is greater than a preset transmission rate threshold; When the initial transmission rate is greater than the transmission rate threshold, the rise time parameter and the fall time parameter are adjusted to be less than the preset time threshold to improve the efficiency of the transmission rate switching. When the initial transmission rate is less than or equal to the transmission rate threshold, the rise time parameter and the fall time parameter are adjusted to be greater than or equal to the time threshold to reduce the crosstalk effect of the transmission rate switching.

7. The display device according to claim 1, characterized in that, The timing controller chip is also used to monitor the actual transmission rate of the system-on-a-chip. When the deviation between the actual transmission rate and the target clock frequency is greater than a preset power efficiency threshold, the step of readjusting the initial clock frequency is triggered.

8. The display device according to claim 7, characterized in that, The timing controller chip includes a timer and is further configured to start the timer when the deviation is greater than the power efficiency threshold; and to perform the step of adjusting the initial clock frequency when the deviation persists for a set duration of the timer.

9. The display device according to claim 1, characterized in that, The timing controller chip has a preset set of standard clock frequencies optimized for power consumption. When adjusting the initial clock frequency, the timing controller chip selects a frequency from the standard clock frequencies that is greater than or equal to the actual transmission rate of the system-on-a-chip as the target clock frequency.

10. The display device according to claim 2, characterized in that, The system-on-a-chip is also used for: Obtain the content information of the displayed data; A frequency adjustment adaptation instruction is generated based on the content information and sent to the timing controller chip, so that the timing controller chip determines an adaptation strategy to adjust the initial clock frequency based on the frequency adjustment adaptation instruction, so as to balance the smoothness of the display screen and power consumption.

11. The display device according to claim 10, characterized in that, The adaptation strategy includes a first adaptation strategy and a second adaptation strategy; the first adaptation strategy includes a first response sensitivity parameter, a first frequency adjustment step parameter, and a first response time parameter; the second adaptation strategy includes a second response sensitivity parameter, a second frequency adjustment step parameter, and a second response time parameter; the system-on-a-chip is further used for: When the content information is static display content information, the first adaptation strategy is adopted to save power consumption of the display screen; wherein, the first response sensitivity parameter is less than the second response sensitivity parameter, the first frequency adjustment step parameter is greater than the second frequency adjustment step parameter, and the first response time parameter is greater than the second response time parameter; When the content information is dynamically displayed, the second adaptation strategy is adopted to ensure the smoothness of the display screen; wherein, the second response sensitivity parameter is greater than the first response sensitivity parameter, the second frequency adjustment step parameter is less than the first frequency adjustment step parameter, and the second response time parameter is less than the first response time parameter.

12. The display device according to any one of claims 1-11, characterized in that, The system-on-a-chip includes an embedded display port interface; the system-on-a-chip transmits the display data through the embedded display port interface.

13. A display method, characterized in that, The method of using the display device according to any one of claims 1-12 includes: The system-on-a-chip transmits display data to the driving circuit and controls the display panel to switch the transmission rate of the display data. When the system-on-a-chip controls the display panel to switch the transmission rate of the display data, the driving circuit monitors the power-on status of the display panel and operates at a preset initial clock frequency when the display panel is detected to be powered on. The display data is parsed at the initial clock frequency to obtain the initial transmission rate of the display data; the initial clock frequency is adjusted according to the display data transmitted in real time by the system-on-a-chip to obtain a target clock frequency that matches the real-time transmitted display data.

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