Memory refresh method and device, electronic equipment and storage medium
By selecting the target address range to be refreshed under the write-back trigger mechanism, the problem of data loss caused by inconsistency in the contents of non-volatile memory cached by CPU cache is solved, memory refresh efficiency is improved and system resources are saved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PHYTIUM TECH CO LTD
- Filing Date
- 2026-02-27
- Publication Date
- 2026-06-02
AI Technical Summary
When the CPU cache caches non-volatile memory content, inconsistencies may occur, leading to data loss when the computer system loses power. Existing technologies that disable the CPU cache or frequently write back to non-volatile memory can negatively impact system performance.
By recording the modification operations of memory pages, the first set of memory pages is determined, and the target address range to be refreshed is selected according to the write-back trigger mechanism. This reduces the amount of content to be refreshed, avoids a full write-back when power is lost, and improves refresh efficiency.
It improves memory refresh efficiency, reduces system resource waste, and avoids system performance degradation.
Smart Images
Figure CN122135754A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and more specifically, to a memory refresh method, apparatus, electronic device, and storage medium. Background Technology
[0002] Since non-volatile memory, or persistent memory, is an order of magnitude slower than the application processor core's cache (CPU cache), in order to improve system performance and reduce latency, the contents of non-volatile memory are usually cached in the CPU cache. This allows modifications to the contents of the CPU cache to be made, and then, based on the CPU cache's write-back mechanism, the contents of the CPU cache are written back to the persistent cache at an appropriate time, such as when a cache line is replaced or flushed, in order to reduce direct access to non-volatile memory.
[0003] When the CPU cache is allowed to cache the contents of non-volatile memory, there may be situations where the contents of the CPU cache are newer than the contents of the non-volatile memory. In this case, the contents of the cache are only flushed to the non-volatile memory when a sudden power failure occurs in the computer system. However, the power may not be sufficient to support writing too much content to persistent memory, resulting in data loss. Summary of the Invention
[0004] The purpose of this application is to address the shortcomings of the prior art by providing a memory refresh method, apparatus, electronic device, and storage medium, so as to refresh content under the condition of satisfying the write-back triggering mechanism and improve refresh efficiency.
[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a memory refresh method, the method comprising: Based on the modification operation targeting a memory page of non-volatile memory, a first set of memory pages is determined, the first set of memory pages including at least one address range of memory pages; According to the write-back triggering mechanism, a second memory page set is determined from the first memory page set. The second memory page set includes: the target address range to be refreshed. The write-back triggering mechanism includes: triggering period, triggering condition, or, computer system power failure event. Based on the target address range, determine the content to be refreshed from the cache, and refresh the content to be refreshed from the cache to the physical address segment corresponding to the non-volatile memory.
[0006] Optionally, before determining the second memory page set from the first memory page set according to the write-back triggering mechanism, the method further includes: A third memory page set is generated based on the number of write protection exceptions for each memory page in the first memory page set. The third memory page set includes: a first memory page whose number of write protection exceptions meets the threshold of the first number. Each memory page in the first memory page set periodically enters the write protection state. The step of determining the second memory page set from the first memory page set according to the write-back triggering mechanism includes: In response to the write-back triggering mechanism, the second memory page set is determined based on the first memory page set and the third memory page set.
[0007] Optionally, after generating a third memory page set based on the number of write protection exceptions for each memory page in the first memory page set, the method further includes: Each time the write protection count of the first memory page increases and meets the first count threshold, the count of the first memory page is incremented by 1. Add the second memory page in the third memory page set whose statistical count meets the second threshold to the preset filter bitmap; In response to the write-back triggering mechanism, determining the second memory page set based on the first memory page set and the third memory page set includes: In response to the write-back triggering mechanism, the second memory page set is determined based on the first memory page set and the preset filter bitmap.
[0008] Optionally, after adding the second memory pages in the third memory page set whose statistical counts satisfy the second threshold to the preset filter bitmap, the method further includes: According to the preset decay algorithm, the statistical count of all first memory pages in the third memory page set is decayed; The second memory page whose attenuated count is less than the threshold of the third count is deleted from the preset filter bitmap, and the first memory page whose attenuated count is 0 is deleted from the third memory page set.
[0009] Optionally, determining the second memory page set from the first memory page set according to the write-back triggering mechanism includes: According to the triggering cycle, after each triggering cycle arrives, the second memory page set is determined from the first memory page set of each triggering cycle.
[0010] Optionally, determining the second memory page set from the first memory page set according to the write-back triggering mechanism includes: According to the triggering condition, after the first memory page set satisfies the triggering condition, the second memory page set is determined from the first memory page set. The triggering condition is: the number of address ranges in the first memory page set is greater than a first preset number, and / or, the number of memory pages corresponding to any address range in the first memory page set is greater than a second preset number, and / or, the total number of memory pages in the first memory page set is greater than a third preset number.
[0011] Optionally, determining the second memory page set from the first memory page set according to the write-back triggering mechanism includes: The second memory page set is determined from the first memory page set of each triggering cycle or the first memory page set that satisfies the triggering condition, based on the triggering cycle or the triggering condition. During the process of refreshing the target address range in the second memory page set, based on the computer system power failure event, the second memory page set is updated according to the first memory page set at the time of power failure, and the updated second memory page set is determined.
[0012] Optionally, determining the first set of memory pages based on modification operations targeting memory pages of non-volatile memory includes: Based on the modification operation on the target memory page of the non-volatile memory, if the first memory page set is empty, an address range is created according to the target address information of the target memory page; If the first memory page set is not empty, the merged address range is determined based on the target address information and the address range in the first memory page set; The first set of memory pages is generated based on at least one of the address ranges.
[0013] Optionally, determining the merged address range based on the target address information and the address range in the first memory page set includes: Based on the distance between the target address information and the address range in the first memory page set, determine in order of distance whether the number of memory pages corresponding to each address range exceeds a second preset number after expanding each address range to the target address information; The target address information is merged with the address range that has the shortest distance and whose number does not exceed the second preset number to obtain the merged address range.
[0014] Optionally, the method further includes: If the number of memory pages corresponding to all address ranges in the first memory page set exceeds the second preset number, a separate address range is created based on the target address information.
[0015] Optionally, the method further includes: If the sum of the number of address ranges in the first memory page set and the second memory page set at the time of power failure is greater than the fourth preset number, a global refresh is performed on the non-volatile memory.
[0016] Secondly, embodiments of this application also provide a memory refresh device, the device comprising: The first page set determination module is used to determine a first memory page set based on modification operations on memory pages of non-volatile memory. The first memory page set includes at least one address range of memory pages. The second page set determination module is used to determine a second memory page set from the first memory page set according to the write-back triggering mechanism. The second memory page set includes: the target address range to be refreshed. The write-back triggering mechanism includes: triggering period, triggering condition, or, computer system power failure event. The page refresh module is used to determine the content to be refreshed from the cache according to the target address range, and refresh the content to be refreshed from the cache to the physical address segment corresponding to the non-volatile memory.
[0017] Optionally, the device further includes: The third page set determination module is used to generate a third memory page set based on the number of write protection exceptions of each memory page in the first memory page set. The third memory page set includes: a first memory page whose number of write protection exceptions meets the first threshold, and each memory page in the first memory page set periodically enters the write protection state. The second page set determination module is specifically used to determine the second memory page set based on the first memory page set and the third memory page set in response to the write-back trigger mechanism.
[0018] Optionally, the device further includes: The filter bitmap generation module is used to increment the count of the first memory page by 1 each time the write protection count of the first memory page increases and meets the first count threshold; and to add the second memory page in the third memory page set whose count meets the second count threshold to the preset filter bitmap. The second page set determination module is specifically used to determine the second memory page set in response to the write-back triggering mechanism, based on the first memory page set and the preset filter bitmap.
[0019] Optionally, the device further includes: The counting decay module is used to decay the count of all first memory pages in the third memory page set according to a preset decay algorithm; delete second memory pages whose decayed count is less than the third count threshold from the preset filter bitmap; and delete first memory pages whose decayed count is 0 from the third memory page set.
[0020] Optionally, the second page set determination module is specifically used to determine the second memory page set from the first memory page set of each trigger cycle after each trigger cycle arrives, based on the trigger cycle.
[0021] Optionally, the second page set determination module is specifically used to determine the second memory page set from the first memory page set after the first memory page set satisfies the triggering condition, wherein the triggering condition is: the number of address ranges in the first memory page set is greater than a first preset number, and / or, the number of memory pages corresponding to any address range in the first memory page set is greater than a second preset number, and / or, the total number of memory pages in the first memory page set is greater than a third preset number.
[0022] Optionally, the second page set determination module is specifically used to determine the second memory page set from the first memory page set of each triggering period or the first memory page set that meets the triggering condition according to the triggering period or the triggering condition; during the process of refreshing the target address range in the second memory page set, based on the computer system power failure event, the second memory page set is updated according to the first memory page set at the time of power failure, and the updated second memory page set is determined.
[0023] Optionally, the first page set determination module is specifically used to, based on the modification operation of the target memory page of the non-volatile memory, if the first memory page set is empty, create an address range according to the target address information of the target memory page; if the first memory page set is not empty, determine the merged address range according to the target address information and the address range in the first memory page set; and generate the first memory page set according to at least one of the address ranges.
[0024] Optionally, the first page set determination module is further configured to determine, based on the distance between the target address information and the address ranges in the first memory page set, whether the number of memory pages corresponding to each address range after expanding each address range to the target address information exceeds a second preset number; and to merge the target address information with the address range with the shortest distance and the number not exceeding the second preset number to obtain the merged address range.
[0025] Optionally, the first page set determination module is further configured to create a separate address range based on the target address information if the number of memory pages corresponding to all address ranges in the first memory page set exceeds the second preset number.
[0026] Optionally, the page refresh module is further configured to perform a global refresh of the non-volatile memory if the sum of the number of address ranges in the first memory page set and the second memory page set during power failure is greater than a fourth preset number.
[0027] Thirdly, embodiments of this application also provide an electronic device, including: a processor, a storage medium, and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to perform the steps of the memory refresh method as described in any of the first aspects.
[0028] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the memory refresh method as described in any of the first aspects.
[0029] The beneficial effects of this application are: The memory refresh method, apparatus, electronic device, and storage medium provided in this application, by recording a first set of modified memory pages, refreshes the content to be refreshed corresponding to the target address range of the second set of pages that meet the conditions in the first set of memory pages to non-volatile memory under the triggering of the write-back trigger mechanism. This reduces the amount of content to be refreshed, avoids writing back only when a power failure occurs, and improves refresh efficiency. Attached Figure Description
[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 An architecture diagram of a computer system provided in an embodiment of this application; Figure 2 Flowchart of the memory refresh method provided in the embodiments of this application Figure 1 ; Figure 3 Flowchart of the memory refresh method provided in the embodiments of this application Figure 2 ; Figure 4 Flowchart of the memory refresh method provided in the embodiments of this application Figure 3 ; Figure 4 Flowchart of the memory refresh method provided in the embodiments of this application Figure 5 ; Figure 6 Flowchart of the memory refresh method provided in the embodiments of this application Figure 5 ; Figure 6 Flowchart of the memory refresh method provided in the embodiments of this application Figure 7 ; Figure 6 This is a schematic diagram of the structure of the memory refresh device provided in the embodiments of this application; Figure 8 A schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.
[0033] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0034] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0035] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.
[0036] When the CPU cache is allowed to cache the contents of non-volatile memory, there may be situations where the contents of the CPU cache are newer than the contents of non-volatile memory. If the computer system suddenly loses power, the application may think that it has written the contents to non-volatile memory, but in fact, the latest version of the contents is not stored in non-volatile memory.
[0037] Existing technologies address the aforementioned issues by disabling the CPU cache or directly flushing frequently changing non-volatile memory regions. However, disabling the CPU cache leads to a decrease in system performance, while frequently flushing content to non-volatile memory regions increases memory bandwidth and impacts system performance.
[0038] Figure 9 The architecture diagram of the computer system provided in the embodiments of this application is as follows: Figure 1 As shown, the computer system includes multiple Non-Uniform Memory Access (NUMA) nodes, each of which includes one or more application processor cores.
[0039] The cache of a computer system is divided into multi-level caches within each application processor core, such as L1 and L2 caches, and a global cache (System Level Cache). The global cache (SLC) can be shared by the application processor cores in each NUMA node. The SLC cache is located between the multi-level cache and non-volatile memory. The SLC cache can be composed of multiple cache home agents (CHAs). Data written from the SLC cache to non-volatile memory may be temporarily stored in a data buffer (Date Buffer). The data buffer (Date Buffer) can be set in the ComputeExpress Link (CXL) controller or converter.
[0040] In some embodiments, multiple NUMA nodes can share a single non-volatile memory, or each NUMA node can be configured with its own non-volatile memory, or some NUMA nodes can be configured with shared non-volatile memory while others are configured with separate non-volatile memory. This embodiment does not impose any restrictions on this approach. Figure 1 Taking non-volatile memory connected to NUMA node 0 as an example, multiple NUMA nodes share this non-volatile memory.
[0041] For example, the computer system in this embodiment can be an ARM server system, and the security engine (SE) or system control processor within each node can be responsible for controlling the modules within that node.
[0042] Based on the above computer system, the specific implementation of the memory refresh method provided in this application will be described below with reference to the embodiments.
[0043] Figure 1 Flowchart of the memory refresh method provided in the embodiments of this application Figure 2 ,like Figure 1 As shown, the method may include: S101. Based on the modification operation for the memory page of non-volatile memory, determine a first set of memory pages, the first set of memory pages including at least one address range of memory pages.
[0044] In this embodiment, during the initial system startup state, the operating system kernel or virtualization monitor sets all physical memory pages allocated to non-volatile memory to a write-protected state. These write-protected memory pages are actually in a "read-only" state, which can be achieved by clearing the "W (Write)" bit of the page table entry in the memory management unit. At this time, any write instruction to the corresponding physical memory page will trigger a write-protection exception.
[0045] When an application or driver attempts to write to the address of any physical memory page, the processor triggers a page fault exception because the memory page at that address is write-protected. This removes the write protection from the physical memory page, changing its modification permissions to "read-write," and writes the data to the physical memory page into the cache. Furthermore, the processor periodically re-sets the physical memory pages to write-protected mode.
[0046] By parsing the exception context, the physical address of the page where the exception occurred is determined. The system maintains a first set of memory pages, which is initially empty. After each page fault exception is triggered, the physical address of the page where the exception occurred is added to the first set of memory pages.
[0047] In some embodiments, during the process of placing the physical address of the page that has malfunctioned into the first memory page set, the physical addresses of the pages in the first memory page set that are less than a preset distance are merged to obtain an address range, and the number of physical memory pages contained in each address range is recorded.
[0048] The first memory page set contains: the page identifier of the modified memory page, the physical address of the modified memory page, at least one address range, and the number of physical memory pages contained in each address range.
[0049] S102. According to the write-back triggering mechanism, determine the second memory page set from the first memory page set. The second memory page set includes: the target address range to be refreshed. The write-back triggering mechanism includes: triggering period, triggering condition, or, computer system power failure event.
[0050] In some embodiments, a write-back triggering mechanism for non-volatile memory is pre-configured. The write-back triggering mechanism may be, for example, a triggering period, a triggering condition, or a computer system power failure event. When the triggering period, the triggering condition, or a computer system power failure event is detected, a target address range that meets the preset filtering conditions is determined from the first memory page set set using preset filtering conditions. The target address range that meets the preset filtering conditions is added to the second memory page set set' to obtain the target address range to be refreshed.
[0051] Furthermore, after adding the target address range from the first memory page set to the second memory page set, the target address range is removed from the first memory page set. The address range of the remaining memory pages is still retained in the first memory page set for continued monitoring until the next write-back trigger mechanism is triggered.
[0052] S103. Based on the target address range, determine the content to be refreshed from the cache, and refresh the content to be refreshed from the cache to the physical address segment corresponding to the non-volatile memory.
[0053] In this embodiment, after determining the target address range from the second memory page set', the dirty data collection and multi-core consistency coordination of all cache levels are automatically and transparently processed, and the data is directly refreshed to the corresponding physical address of non-volatile memory.
[0054] For example, after the write-back trigger mechanism is satisfied, the memory refresh process is as follows: 1. Acquire the change lock of the first set of memory pages (set) to prevent modification of the first set of memory pages during this process. If a modification operation for a new memory page is detected at this time, write the information of the new memory page into the waiting queue.
[0055] 2. Determine the second set of memory pages from the first set of memory pages set'.
[0056] 3. Release the change lock on the first memory page set and write the information of the new memory pages in the write queue to the first memory page set.
[0057] 4. Restore write protection for memory pages in the second memory page set'.
[0058] 5. Implement an address-based flush (ABF) mechanism on the target address range in the second memory page set', and delete the flushed target address range from the second memory page set'.
[0059] The memory refresh method provided in the above embodiments records the first set of memory pages that have been modified. Under the triggering of the write-back triggering mechanism, the content to be refreshed corresponding to the target address range of the second set of pages that meet the conditions in the first set of memory pages is refreshed to non-volatile memory. This reduces the amount of content to be refreshed, avoids writing back only when a power failure occurs, and improves refresh efficiency.
[0060] In one possible implementation, before determining the second memory page set from the first memory page set according to the write-back triggering mechanism in S102 above, the method may further include: A third set of memory pages is generated based on the number of write protection exceptions for each memory page in the first set of memory pages. The third set of memory pages includes the first memory pages whose write protection exception count meets the threshold of the first set. Each memory page in the first set of memory pages periodically enters the write protection state.
[0061] The process of determining the second memory page set from the first memory page set according to the write-back triggering mechanism in S102 above may include: In response to the write-back trigger mechanism, the second memory page set is determined based on the first memory page set and the third memory page set.
[0062] In this embodiment, if a memory page that is frequently modified is refreshed every time a write-back is triggered, a large number of redundant write-backs will occur, resulting in a waste of system resources. Therefore, by counting the number of times memory pages are modified, memory pages that are frequently modified are filtered out to avoid redundant write-backs.
[0063] Specifically, when a memory page is write-protected, if a modification to the memory page is detected, a write protection exception will be triggered, and the write protection status of the memory page will be lifted. For a period of time afterward, the modifications to the memory page will be written to the cache, but no more write protection exceptions will be triggered, thus avoiding frequent triggering of write protection exceptions that could cause system crashes.
[0064] After a memory page is modified for the first time, triggering a write protection exception, the memory page and its physical address are written into the first memory page set. For memory pages in the first memory page set, the first preset period is used to periodically reset them to write protection state.
[0065] When memory pages periodically re-enter write-protected state, the number of write protection exceptions triggered by modifications to memory pages is counted. The number of write protection exceptions is used to indicate the frequency of modifications to memory pages.
[0066] For the first memory page in the first memory page set set whose write protection exception count is greater than or equal to the threshold for the first exception, add it to the third memory page set set''.
[0067] After the write-back trigger mechanism is satisfied, based on the memory pages in the first memory page set set and the first memory pages in the third memory page set'', the remaining memory pages located in the first memory page set set but not in the third memory page set'' are added to the second memory page set'.
[0068] In some embodiments, a new page address range is generated by re-merging the remaining memory pages based on their physical page addresses. The second memory page set' includes the new page address range, i.e., the target address range.
[0069] It should be noted that after the remaining memory pages are added to the second memory page set', the first memory page located in the third memory page set'' remains in the first memory page set' and is under monitoring. When the write protection exception count of the first memory page decreases and it is no longer located in the third memory page set'', the first memory page will also be added to the second memory page set' for memory refresh.
[0070] The memory refresh mechanism provided in the above embodiments counts the number of write protection exceptions and removes the first memory page with too many write protection exceptions from the first memory page set to obtain a second memory page set. This ensures that the remaining memory pages in the second memory page set are memory pages that are not frequently modified. The memory pages that are not frequently modified are refreshed, while the memory pages that are frequently modified are not refreshed, thereby reducing unnecessary write-backs and saving system resources.
[0071] In one possible implementation, Figure 2 Flowchart of the memory refresh method provided in the embodiments of this application Figure 3 ,like Figure 2 As shown, after generating the third memory page set based on the write protection exception count of each memory page in the first memory page set, the method may further include: S201. Each time the write protection count of the first memory page increases and meets the first count threshold, the count of the first memory page is incremented by 1.
[0072] S202. Add the second memory page in the third memory page set whose count meets the second threshold to the preset filter bitmap.
[0073] The process of determining the second memory page set based on the first and third memory page sets in response to the write-back trigger mechanism may include: S203. In response to the write-back trigger mechanism, determine the second memory page set based on the first memory page set and the preset filter bitmap.
[0074] In this embodiment, after the write protection count of the first memory page increases by more than or equal to the first count threshold each time, it is determined whether the first memory page is in the third memory page set set''. If the first memory page is not in the third memory page set set'', it means that the write protection count of the first memory page is greater than or equal to the first count threshold for the first time (limited to before the triggering of the write-back triggering mechanism in this round). The first memory page is then placed into the third memory page set set'', and the count of the first memory page is determined to be 1.
[0075] If the first memory page is in the third memory page set set'', it means that the write protection count of the first memory page is not greater than or equal to the first count threshold. Increment the count of the first memory page by 1.
[0076] The system checks whether the number of times each first memory page in the third memory page set '' is counted within the second preset period is greater than or equal to the second threshold. If the number of times is counted is greater than or equal to the second threshold, it means that the corresponding memory page has a high modification frequency within the second preset period. The second memory page whose number of times is counted is greater than or equal to the second threshold is added to the preset filter bitmap.
[0077] After the write-back trigger mechanism is satisfied, based on the memory pages in the first memory page set set and the second memory pages in the preset filter bitmap, the remaining memory pages located in the first memory page set set but not in the preset filter bitmap are added to the second memory page set set'.
[0078] It should be noted that during the initialization phase, if there is no memory page information in the preset filter bitmap when the write-back trigger mechanism is met, then all memory pages in the first memory page set set are put into the second memory page set set'.
[0079] The memory refresh method provided in the above embodiments counts the number of times the write protection count of the first memory page is greater than or equal to the threshold of the first count, and removes the second memory page with too many counts from the first memory page set to obtain the second memory page set. This ensures that the remaining memory pages in the second memory page set are memory pages with low modification frequency. The memory pages with low modification frequency are refreshed, while the memory pages with high modification frequency are not refreshed, thereby reducing unnecessary write-backs and saving system resources.
[0080] In one possible implementation, Figure 3 Flowchart of the memory refresh method provided in the embodiments of this application Figure 4 ,like Figure 3 As shown, after adding the second memory page in the third memory page set whose statistical count meets the second threshold to the preset filter bitmap in S202, the method may further include: S301. According to the preset decay algorithm, the statistical count of all first memory pages in the third memory page set is decayed.
[0081] S302. Delete the second memory page whose attenuated statistical count is less than the threshold of the third number from the preset filter bitmap, and delete the first memory page whose attenuated statistical count is 0 from the third memory page set.
[0082] In this embodiment, to avoid memory pages that have been frequently modified for a period of time and whose modification frequency decreases afterward remaining in the preset filter bitmap, thus preventing the corresponding memory pages from being refreshed, this embodiment adds second memory pages whose statistical count is greater than or equal to the second threshold to the preset filter bitmap in each second preset period, and then attenuates the statistical count of all first memory pages in the third memory page set''. For example, attenuation can be achieved by subtraction or multiplication, such as subtracting one from the statistical count or multiplying the statistical count by a coefficient greater than 0 and less than 1.
[0083] For the second memory page in the third memory page set'' whose decayed count is less than the threshold of the third count, it is removed from the preset filter bitmap. When the write-back trigger mechanism is met, based on the memory pages in the first memory page set set and the second memory page in the updated preset filter bitmap, the remaining memory pages located in the first memory page set set but not in the preset filter bitmap are added to the second memory page set'.
[0084] In addition to updating the preset filter bitmap, when the count of the second memory page decays to 0, it is removed from the third memory page set'' to recount the count of the second memory page.
[0085] The memory refresh method provided in the above embodiments slows down the increase frequency of write protection exceptions and reduces the increase frequency of the statistical count of the first memory page when the modification frequency of the first memory page decreases. By attenuating the statistical count of the first memory page, the second memory page whose attenuated statistical count is less than the third threshold is deleted from the preset filter bitmap. This enables the page to be added back to the second memory page set for page refresh when the modification frequency of the memory page decreases, ensuring that the page refresh and modification frequency are consistent.
[0086] In one possible implementation, the process of determining the second memory page set from the first memory page set according to the write-back triggering mechanism in step S102 above may include: Based on the trigger cycle, after each trigger cycle arrives, the second memory page set is determined from the first memory page set of each trigger cycle.
[0087] In this embodiment, the system is configured to automatically trigger a write-back mechanism for the modified page at regular intervals, i.e., a periodic triggering mechanism. After each triggering cycle is reached, the second memory page set' is determined from the first memory page set set of each triggering cycle using the method described in the previous embodiment.
[0088] In another possible implementation, the process of determining the second memory page set from the first memory page set according to the write-back triggering mechanism in S102 above may include: According to the triggering conditions, after the first memory page set satisfies the triggering conditions, a second memory page set is determined from the first memory page set. The triggering conditions are: the number of address ranges in the first memory page set is greater than a first preset number, and / or, the number of memory pages corresponding to any address range in the first memory page set is greater than a second preset number, and / or, the total number of memory pages in the first memory page set is greater than a third preset number.
[0089] In this embodiment, during the process of adding the modified memory pages to the first memory page set and merging the page physical addresses, the number of page physical address ranges obtained by merging in the first memory page set, the number of memory pages corresponding to each page physical address range, and the total number of all modified memory pages in the first memory page set are counted.
[0090] The system sets the trigger conditions for the write-back trigger mechanism. The trigger condition is that the number of each of the above conditions is greater than the corresponding preset number. When the number of the corresponding conditions is greater than the corresponding preset number, it is determined that the write-back trigger mechanism is satisfied.
[0091] In another possible implementation Figure 4 Flowchart of the memory refresh method provided in the embodiments of this application Figure 5 ,like Figure 4 As shown, the process of determining the second memory page set from the first memory page set according to the write-back triggering mechanism in S102 above may include: S401. Determine the second memory page set from the first memory page set of each triggering cycle or the first memory page set that meets the triggering condition, based on the triggering cycle or triggering condition.
[0092] S402. During the process of refreshing the target address range in the second memory page set, based on the computer system power failure event, the second memory page set is updated according to the first memory page set at the time of power failure, and the updated second memory page set is determined.
[0093] In this embodiment, when the system is working normally, the second memory page set is determined from the first memory page set set based on the triggering period or triggering condition. During the memory refresh of the target address range in the second memory page set set', the first memory page set has been updated based on the new modification operation of the memory page.
[0094] If a system power failure occurs before the target address range in the second memory page set set' is completely refreshed, the address ranges in the first memory page set set and the second memory page set set' can be aggregated to obtain a new address range set that covers all address ranges defined by the two sets. This new address range set set' is then used as the updated second memory page set set', and memory refresh is performed on each address range in the new address range set set.
[0095] For example, when a system power failure occurs, the first memory page set is {(100,200), (500,560)}, and the second memory page set is {(300,400), (520, 600)}. Then, ABF is finally performed on {(100,200),(300,400), (500,600)}.
[0096] In one possible implementation, Figure 5 This is a flowchart illustrating the memory refresh method provided in an embodiment of this application, as shown below. Figure 6 As shown, the process of determining the first set of memory pages in S101 based on the modification operation on the memory pages of non-volatile memory may include: S501. Based on the modification operation of the target memory page for non-volatile memory, if the first memory page set is empty, create an address range according to the target address information of the target memory page; if the first memory page set is not empty, determine the merged address range according to the target address information and the address range in the first memory page set.
[0097] S502. Generate a first set of memory pages based on at least one of the address ranges.
[0098] In this embodiment, during the process of placing the physical address of the page that has malfunctioned into the first memory page set, the physical addresses of the pages with a distance less than a preset distance are merged according to the physical addresses of each memory page to obtain the first memory page set containing at least one address range, and the number of physical memory pages contained in each address range is recorded.
[0099] Specifically, after the target memory page is modified, it is determined whether the first memory page set has an address range. If there is no address range, that is, the first memory page set is empty, an address range is created, which only covers the physical address of the target memory page.
[0100] If the first set of memory pages already contains k address ranges, where k is less than the first preset number, find the address range among the k address ranges that is closest to the physical address of the target memory page. By expanding this address range to cover the physical address of the target memory page, the existing address range is updated.
[0101] In some embodiments, Figure 6 Flowchart of the memory refresh method provided in the embodiments of this application Figure 7 ,like Figure 6 As shown, the process of determining the merged address range based on the target address information and the address range in the first memory page set in S501 may include: S601. Based on the distance between the target address information and the address range in the first memory page set, determine in turn whether the number of memory pages corresponding to each address range exceeds the second preset number after expanding each address range to the target address information according to the distance.
[0102] S602. Merge the target address information with the address range that is the shortest distance away and whose number does not exceed the second preset number to obtain the merged address range.
[0103] In this embodiment, the address range closest to the physical address of the target memory page is found among k address ranges. This address range is expanded to cover the physical address of the target memory page. If the number of memory pages included in the expanded address range is greater than a second preset number, the address range closest to the physical address of the target memory page can be expanded. The process continues to determine whether the number of memory pages included in the expanded address range is greater than the second preset number, until an address range containing a number of memory pages less than or equal to the second preset number is found. The physical address of the target memory page is then merged with this address range to obtain a merged address range.
[0104] Furthermore, the method may also include: If the number of memory pages corresponding to all address ranges in the first memory page set exceeds the second preset number, a separate address range is created based on the target address information.
[0105] In this embodiment, if the number of memory pages contained in all address ranges of the first memory page set exceeds the second preset number after the expansion of all address ranges to cover the physical address of the target memory page, it means that the physical address of the target memory page cannot be merged with the existing physical range. Therefore, only a new address range can be created, which only covers the physical address of the target memory page.
[0106] The memory refresh method provided in the above embodiments can reduce the number of address ranges in the first memory page set by merging the address ranges in the first memory page set, thereby reducing the number of instructions required for the system to perform address refresh and improving memory refresh efficiency.
[0107] In one possible implementation, the method may further include: If the sum of the number of address ranges in the first memory page set and the second memory page set at the time of power failure is greater than the fourth preset number, a global refresh is performed on the non-volatile memory.
[0108] In this embodiment, when a power failure occurs in the system, it is determined whether the total number of address ranges contained in the first memory page set set and the second memory page set' at the time of power failure is greater than a fourth preset number. If it is greater than the fourth preset number, it means that a large number of memory pages need to be refreshed. Instead of executing a refresh instruction for each target address range separately, a global refresh instruction is used to traverse each cache line in the cache one by one and refresh the dirty data in it to non-volatile memory.
[0109] The memory refresh method provided in the above embodiments adopts a global refresh mechanism to improve memory refresh efficiency when the total address range of the first memory page set and the second memory page set is too large during power failure.
[0110] In one possible implementation, prior to S101 above, the method may further include: Register the physical address range of non-volatile memory.
[0111] In this embodiment, the physical address range of the non-volatile memory is registered with the system control processor of the NUMA node where the non-volatile memory is located in the computer system, so that the system control processor can manage the physical address range of the non-volatile memory. When the write-back trigger mechanism is met, the address-based refresh mechanism is executed sequentially on each physical address range, and the global cache SLC is notified to refresh the contents of the cache line corresponding to the physical address range to the non-volatile memory.
[0112] Based on the above method embodiments, this application also provides a memory refresh device. Figure 7 This is a schematic diagram of the structure of the memory refresh device provided in the embodiments of this application, as shown below. Figure 8 As shown, the device may include: The first page set determination module 701 is used to determine a first memory page set based on modification operations on memory pages of non-volatile memory. The first memory page set includes at least one address range of memory pages. The second page set determination module 702 is used to determine a second memory page set from the first memory page set according to the write-back triggering mechanism. The second memory page set includes: the target address range to be refreshed. The write-back triggering mechanism includes: triggering period, triggering condition, or, computer system power failure event. The page refresh module 703 is used to determine the content to be refreshed from the cache according to the target address range, and refresh the content to be refreshed from the cache to the physical address segment corresponding to the non-volatile memory.
[0113] Optionally, the device further includes: The third page set determination module is used to generate a third memory page set based on the number of write protection exceptions of each memory page in the first memory page set. The third memory page set includes: a first memory page whose number of write protection exceptions meets the first threshold, and each memory page in the first memory page set periodically enters the write protection state. The second page set determination module 702 is specifically used to determine the second memory page set based on the first memory page set and the third memory page set in response to the write-back trigger mechanism.
[0114] Optionally, the device further includes: The filter bitmap generation module is used to increment the count of the first memory page by 1 each time the write protection count of the first memory page increases and meets the first count threshold; and to add the second memory page in the third memory page set whose count meets the second count threshold to the preset filter bitmap. The second page set determination module 702 is specifically used to determine the second memory page set in response to the write-back trigger mechanism, based on the first memory page set and the preset filter bitmap.
[0115] Optionally, the device further includes: The counting decay module is used to decay the count of all first memory pages in the third memory page set according to a preset decay algorithm; delete second memory pages whose decayed count is less than the third count threshold from the preset filter bitmap; and delete first memory pages whose decayed count is 0 from the third memory page set.
[0116] Optionally, the second page set determination module 702 is specifically used to determine the second memory page set from the first memory page set of each trigger cycle after each trigger cycle is reached, according to the trigger cycle.
[0117] Optionally, the second page set determination module 702 is specifically used to determine the second memory page set from the first memory page set after the first memory page set satisfies the triggering condition, wherein the triggering condition is: the number of address ranges in the first memory page set is greater than a first preset number, and / or, the number of memory pages corresponding to any address range in the first memory page set is greater than a second preset number, and / or, the total number of memory pages in the first memory page set is greater than a third preset number.
[0118] Optionally, the second page set determination module 702 is specifically used to determine the second memory page set from the first memory page set of each triggering period or the first memory page set that meets the triggering condition according to the triggering period or the triggering condition; during the process of refreshing the target address range in the second memory page set, based on the computer system power failure event, the second memory page set is updated according to the first memory page set at the time of power failure, and the updated second memory page set is determined.
[0119] Optionally, the first page set determination module 701 is specifically used to, based on the modification operation of the target memory page of the non-volatile memory, if the first memory page set is empty, create an address range according to the target address information of the target memory page; if the first memory page set is not empty, determine the merged address range according to the target address information and the address range in the first memory page set; and generate the first memory page set according to at least one of the address ranges.
[0120] Optionally, the first page set determination module 701 is further configured to determine, based on the distance between the target address information and the address ranges in the first memory page set, whether the number of memory pages corresponding to each address range after expanding each address range to the target address information exceeds a second preset number; and to merge the target address information with the address range with the shortest distance and the number not exceeding the second preset number to obtain the merged address range.
[0121] Optionally, the first page set determination module 701 is further configured to create a separate address range based on the target address information if the number of memory pages corresponding to all address ranges in the first memory page set exceeds the second preset number.
[0122] Optionally, the page refresh module 703 is further configured to perform a global refresh on the non-volatile memory if the sum of the number of address ranges in the first memory page set and the second memory page set during power failure is greater than a fourth preset number.
[0123] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.
[0124] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more microprocessors, or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).
[0125] Figure 8 A schematic diagram of the electronic device provided in the embodiments of this application, such as... Figure 9 Figure 9 As shown, the electronic device 800 includes a processor 801, a storage medium 802, and a bus. The storage medium 802 stores program instructions executable by the processor 801. When the electronic device 800 is running, the processor 801 communicates with the storage medium 802 via the bus, and the processor 801 executes the program instructions to perform the above-described method embodiment. The specific implementation and technical effects are similar and will not be described in detail here.
[0126] Optionally, this application also provides a computer-readable storage medium storing a computer program, which is executed by a processor to perform the above-described method embodiments.
[0127] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0128] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0129] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.
[0130] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0131] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A memory refresh method, characterized in that, The method includes: Based on the modification operation targeting a memory page of non-volatile memory, a first set of memory pages is determined, the first set of memory pages including at least one address range of memory pages; According to the write-back triggering mechanism, a second memory page set is determined from the first memory page set. The second memory page set includes: the target address range to be refreshed. The write-back triggering mechanism includes: triggering period, triggering condition, or, computer system power failure event. Based on the target address range, determine the content to be refreshed from the cache, and refresh the content to be refreshed from the cache to the physical address segment corresponding to the non-volatile memory.
2. The method as described in claim 1, characterized in that, Before determining the second memory page set from the first memory page set according to the write-back triggering mechanism, the method further includes: A third memory page set is generated based on the number of write protection exceptions for each memory page in the first memory page set. The third memory page set includes: a first memory page whose number of write protection exceptions meets the threshold of the first number. Each memory page in the first memory page set periodically enters the write protection state. The step of determining the second memory page set from the first memory page set according to the write-back triggering mechanism includes: In response to the write-back triggering mechanism, the second memory page set is determined based on the first memory page set and the third memory page set.
3. The method as described in claim 2, characterized in that, After generating a third memory page set based on the number of write protection exceptions for each memory page in the first memory page set, the method further includes: Each time the write protection count of the first memory page increases and meets the first count threshold, the count of the first memory page is incremented by 1. Add the second memory page in the third memory page set whose statistical count meets the second threshold to the preset filter bitmap; In response to the write-back triggering mechanism, determining the second memory page set based on the first memory page set and the third memory page set includes: In response to the write-back triggering mechanism, the second memory page set is determined based on the first memory page set and the preset filter bitmap.
4. The method as described in claim 3, characterized in that, After adding the second memory pages in the third memory page set whose statistical counts meet the second threshold to the preset filter bitmap, the method further includes: According to the preset decay algorithm, the statistical count of all first memory pages in the third memory page set is decayed; The second memory page whose attenuated count is less than the threshold of the third count is deleted from the preset filter bitmap, and the first memory page whose attenuated count is 0 is deleted from the third memory page set.
5. The method as described in claim 1, characterized in that, The step of determining the second memory page set from the first memory page set according to the write-back triggering mechanism includes: According to the triggering cycle, after each triggering cycle arrives, the second memory page set is determined from the first memory page set of each triggering cycle.
6. The method as described in claim 1, characterized in that, The step of determining the second memory page set from the first memory page set according to the write-back triggering mechanism includes: According to the triggering condition, after the first memory page set satisfies the triggering condition, the second memory page set is determined from the first memory page set. The triggering condition is: the number of address ranges in the first memory page set is greater than a first preset number, and / or, the number of memory pages corresponding to any address range in the first memory page set is greater than a second preset number, and / or, the total number of memory pages in the first memory page set is greater than a third preset number.
7. The method as described in claim 1, characterized in that, The step of determining the second memory page set from the first memory page set according to the write-back triggering mechanism includes: The second memory page set is determined from the first memory page set of each triggering cycle or the first memory page set that satisfies the triggering condition, based on the triggering cycle or the triggering condition. During the process of refreshing the target address range in the second memory page set, based on the computer system power failure event, the second memory page set is updated according to the first memory page set at the time of power failure, and the updated second memory page set is determined.
8. The method as described in claim 1, characterized in that, The step of determining the first set of memory pages based on modification operations on non-volatile memory pages includes: Based on the modification operation on the target memory page of the non-volatile memory, if the first memory page set is empty, an address range is created according to the target address information of the target memory page; If the first memory page set is not empty, the merged address range is determined based on the target address information and the address range in the first memory page set; The first set of memory pages is generated based on at least one of the address ranges.
9. The method as described in claim 8, characterized in that, The step of determining the merged address range based on the target address information and the address range in the first memory page set includes: Based on the distance between the target address information and the address range in the first memory page set, determine in order of distance whether the number of memory pages corresponding to each address range exceeds a second preset number after expanding each address range to the target address information; The target address information is merged with the address range that has the shortest distance and whose number does not exceed the second preset number to obtain the merged address range.
10. The method as described in claim 9, characterized in that, The method further includes: If the number of memory pages corresponding to all address ranges in the first memory page set exceeds the second preset number, a separate address range is created based on the target address information.
11. The method as described in claim 7, characterized in that, The method further includes: If the sum of the number of address ranges in the first memory page set and the second memory page set at the time of power failure is greater than the fourth preset number, a global refresh is performed on the non-volatile memory.
12. A memory refresh device, characterized in that, The device includes: The first page set determination module is used to determine a first memory page set based on modification operations on memory pages of non-volatile memory. The first memory page set includes at least one address range of memory pages. The second page set determination module is used to determine a second memory page set from the first memory page set according to the write-back triggering mechanism. The second memory page set includes: the target address range to be refreshed. The write-back triggering mechanism includes: triggering period, triggering condition, or, computer system power failure event. The page refresh module is used to determine the content to be refreshed from the cache according to the target address range, and refresh the content to be refreshed from the cache to the physical address segment corresponding to the non-volatile memory.
13. An electronic device, characterized in that, include: The device includes a processor, a storage medium, and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to perform the steps of the memory refresh method as described in any one of claims 1 to 11.
14. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, performs the steps of the memory refresh method as described in any one of claims 1 to 11.