A method and system for improving the insulation resistance of ceramic capacitors

Abstract

This invention proposes a method and system for improving the insulation resistance of ceramic capacitors, relating to the field of ceramic capacitor technology. The method involves acquiring capacitor usage scenario data, performing scenario determination analysis on the usage scenario data to obtain scenario determination analysis data, conducting ceramic material analysis based on the scenario determination analysis data to obtain ceramic material analysis data, performing ceramic structure dimension analysis and adjustment based on the ceramic material analysis data to obtain various analysis and adjustment data, performing joint dimension and impurity analysis based on the various analysis and adjustment data to obtain joint dimension and impurity analysis and adjustment data, and performing production process impurity analysis and adjustment based on the joint dimension and impurity analysis and adjustment data to obtain insulation resistance improvement data. This invention achieves multi-stage synergy and scenario-driven capability for improving insulation resistance.

Description

Technical Field

[0001] This invention proposes a method and system for improving the insulation resistance of ceramic capacitors, relating to the field of ceramic capacitor technology, specifically to the field of improving the insulation resistance of ceramic capacitors. Background Technology

[0002] Ceramic capacitors, due to their small size and excellent stability, are widely used in electronic equipment, power systems, and other fields. Their insulation resistance performance directly determines the reliability of equipment operation. Current technologies for controlling the insulation resistance of ceramic capacitors often employ a single-dimensional adjustment mode, relying on experience for material selection and lacking precise adaptation to the application scenario, easily leading to performance redundancy or inadequacy. The structural dimensions are often disconnected from the material impurity content, lacking a targeted redundancy compensation mechanism, making it difficult to address insulation shortcomings caused by impurity fluctuations. Impurity control in the production process is passive, relying solely on post-production inspection to remove defective products, failing to monitor impurity changes and their impact in real time. This results in poor batch consistency, high risk of insulation failure, cost waste, and limited applicability. Summary of the Invention

[0003] This invention provides a method and system for improving the insulation resistance of ceramic capacitors to solve the above-mentioned problems: This invention proposes a method and system for improving the insulation resistance of ceramic capacitors, the method comprising: S1. Obtain capacitor usage scenario data, perform scenario determination analysis on the capacitor usage scenario data, obtain scenario determination analysis data, perform ceramic material analysis based on the scenario determination analysis data, and obtain ceramic material analysis data. S2. Based on the ceramic material analysis data, perform ceramic structure size analysis and adjustment to obtain various analysis and adjustment data. Based on the various analysis and adjustment data, perform joint size and impurity analysis to obtain joint size and impurity analysis and adjustment data. S3. Based on the combined analysis and adjustment data of size and impurities, conduct impurity analysis and adjustment of the production process to obtain data on improving insulation resistance.

[0004] Further, S1 includes: Acquire capacitor usage scenario data, and extract scenario performance features based on the capacitor usage scenario data to obtain scenario performance extraction information; The performance extraction information of the scenario is subjected to performance requirement data analysis to obtain performance requirement analysis data; Based on performance requirements, capacitor usage scenario data is matched with ceramic materials to obtain scenario-material matching data; The scene material matching data is the ceramic material analysis data.

[0005] Furthermore, the step of performing performance requirement data analysis on the extracted scenario performance information to obtain performance requirement analysis data includes: The scene performance extraction information is decomposed into performance category data to obtain multiple performance category decomposition data; Different level range information is preset for each performance category decomposition data. The different level range information of multiple performance category decomposition data is matched with the level to obtain the category level correspondence range information of multiple performance category decomposition data. The data of multiple performance categories are broken down and compared with the information of different category level ranges to obtain multiple performance category level data; Obtain preset weight data for multiple performance category breakdown data, calculate the product of performance category level data and preset weight data, and obtain category requirement analysis data; The sum of multiple performance level requirements analysis data is obtained to acquire performance requirements analysis data.

[0006] Furthermore, the step of matching capacitor usage scenario data with ceramic materials based on performance requirement information to obtain scenario material matching data includes: Obtain the material performance guarantee range data of ceramic materials, decompose the material performance guarantee range data into multiple performance guarantee range levels, and obtain multiple performance guarantee level decomposition ranges; By breaking down multiple performance assurance levels into ranges and mapping them to levels, information on the ranges corresponding to the assurance levels is obtained. By matching the performance requirements of capacitor usage scenarios with the corresponding range of protection levels, scenario material matching data is obtained.

[0007] Further, S2 includes: Based on the ceramic material analysis data, single-layer dielectric thickness analysis and adjustment, chip size analysis and adjustment, and safety spacing analysis and adjustment are performed to obtain first analysis and adjustment data, second analysis and adjustment data, and third analysis and adjustment data. Based on the first analysis adjustment data, the second analysis adjustment data, and the third analysis adjustment data, size redundancy compensation impurity analysis adjustment is performed to obtain size impurity joint analysis adjustment data.

[0008] Furthermore, the step of performing single-layer dielectric thickness analysis and adjustment, chip size analysis and adjustment, and safety spacing analysis and adjustment based on ceramic material analysis data to obtain first analysis and adjustment data, second analysis and adjustment data, and third analysis and adjustment data includes: Based on the impurity content threshold and impurity content data in the ceramic material analysis data; The ratio of impurity content data to impurity threshold is used to obtain the material impurity content coefficient. The material impurity content coefficient is compared with the preset threshold corresponding to a single-layer medium to obtain the first analytical data. The thickness of the single-layer medium is adjusted based on the first analysis data to obtain the first analysis adjustment data; The material impurity content coefficient is compared with the preset chip size threshold to obtain the second analysis data; The chip size is adjusted based on the second analysis data to obtain the second analysis adjustment data; The material impurity content coefficient is compared with the threshold corresponding to the preset safety distance to obtain the third analysis data; The safety spacing is adjusted based on the third analysis data to obtain the third analysis adjustment data.

[0009] Further, the step of performing size redundancy compensation impurity analysis and adjustment based on the first analysis and adjustment data, the second analysis and adjustment data, and the third analysis and adjustment data to obtain joint size and impurity analysis and adjustment data includes: Redundancy compensation calculations were performed on the first, second, and third analysis adjustment data to obtain the redundancy compensation calculation results: Based on the redundancy compensation calculation results, the absolute value of the difference between the impurity content and the preset control limit is obtained to obtain data close to the impurity limit. Based on the impurity upper limit data, redundant adjustments are made to the single-layer dielectric thickness, chip size, and safety spacing to obtain joint size and impurity analysis adjustment data.

[0010] Further, S3 includes: Based on the combined analysis and adjustment data of size and impurities, the entire production process is controlled to obtain full-process control information. Based on the full-process control information, monitor the changes in impurity data to obtain impurity change monitoring data; Based on the monitoring data of impurity changes, an impact analysis of impurity changes is conducted to obtain data on the impact analysis of impurity changes. Based on the data analysis of the impact of impurity changes, early warning of the impact of impurity changes is generated. Based on the early warning of the impact of impurity changes, impurity early warning adjustment information is generated to obtain data on the improvement of insulation resistance.

[0011] Furthermore, the step of performing impurity change impact analysis based on impurity change monitoring data to obtain impurity change impact analysis data includes: Based on the impurity change monitoring data, information on the magnitude of impurity changes is obtained; Determine the maximum and minimum impurity information based on the impurity variation range information; Data on the insulation resistance attenuation amplitude when the impurity information is maximized is obtained to acquire data on the maximum impact of the change. Data on insulation resistance attenuation amplitude when impurities are minimized is obtained to acquire data on the minimum impact of change. Obtain the difference between the data with the maximum and minimum impact of change to obtain the data for analyzing the impact of impurity changes.

[0012] Furthermore, the system includes: The materials analysis module is used to acquire capacitor usage scenario data, perform scenario determination analysis on the capacitor usage scenario data to obtain scenario determination analysis data, and perform ceramic material analysis based on the scenario determination analysis data to obtain ceramic material analysis data. The size adjustment module is used to perform ceramic structure size analysis and adjustment based on ceramic material analysis data, obtain various analysis and adjustment data, and perform joint size and impurity analysis based on the various analysis and adjustment data to obtain joint size and impurity analysis and adjustment data. The resistance enhancement module is used to analyze and adjust the production process impurities based on the joint analysis and adjustment data of size and impurities, in order to obtain data on improving insulation resistance.

[0013] The beneficial effects of this invention are as follows: This invention solves the technical problems of poor scenario adaptability, disconnect between material and size control, and passive detection in the production process of traditional ceramic capacitors; it achieves precise adaptation between scenario requirements and ceramic capacitor design and production, breaking the bottleneck of single-dimensional control being unable to meet the needs of multiple scenarios; it improves the stability of the insulation performance of ceramic capacitors, the flexibility of scenario adaptability, and the controllability of the production process, effectively avoiding the risk of insulation failure caused by impurities and structural size mismatch; it reduces the insulation performance non-compliance rate, material waste, and subsequent operation and maintenance costs during the production process, while improving the product's tolerance to different working conditions and expanding the product's application range. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a method to improve the insulation resistance of a ceramic capacitor. Detailed Implementation

[0015] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0016] In one embodiment of the present invention, a method and system for improving the insulation resistance of a ceramic capacitor are provided, the method comprising: S1. Obtain capacitor usage scenario data, perform scenario determination analysis on the capacitor usage scenario data, obtain scenario determination analysis data, perform ceramic material analysis based on the scenario determination analysis data, and obtain ceramic material analysis data. S2. Based on the ceramic material analysis data, perform ceramic structure size analysis and adjustment to obtain various analysis and adjustment data. Based on the various analysis and adjustment data, perform joint size and impurity analysis to obtain joint size and impurity analysis and adjustment data. S3. Based on the combined analysis and adjustment data of size and impurities, perform impurity analysis and adjustment of the production process to obtain data on improving insulation resistance, such as... Figure 1 As shown.

[0017] The working principle and technical effects of the above-mentioned technical solution are as follows: This method obtains data on capacitor usage scenarios to accurately determine the scenario type and core requirements, and then matches suitable ceramic materials. Based on the characteristics of the selected materials, it specifically adjusts the key dimensions of the ceramic structure, and performs joint synergistic analysis of dimensions and impurities in conjunction with impurity content. Dimensional redundancy design is used to compensate for potential insulation shortcomings caused by impurities. Based on the joint adjustment parameters of dimensions and impurities, the entire production process is precisely controlled, and impurity changes are monitored in real time and dynamically adjusted to ensure that the negative impact of impurities on insulation performance during production is controllable, achieving a stable improvement in insulation resistance. The entire process forms a closed loop of linkage from scenario to material to dimension, and from impurities to production, with data exchange and dynamic adaptation among each link, avoiding the limitations of single-link control.

[0018] This invention solves the technical problems of poor scenario adaptability, disconnect between material and size control, and passive inspection in the production process of traditional ceramic capacitors. It achieves precise adaptation between scenario requirements and ceramic capacitor design and production, breaking the bottleneck of single-dimensional control being unable to meet the needs of multiple scenarios. It improves the stability of the insulation performance of ceramic capacitors, the flexibility of scenario adaptability, and the controllability of the production process, effectively avoiding the risk of insulation failure caused by impurities and structural size mismatch. It reduces the insulation performance failure rate, material waste, and subsequent operation and maintenance costs during the production process, while improving the product's tolerance to different working conditions and expanding the product's application range.

[0019] In one embodiment of the present invention, S1 includes: Acquire capacitor usage scenario data, and extract scenario performance features based on the capacitor usage scenario data to obtain scenario performance extraction information; The performance extraction information of the scenario is subjected to performance requirement data analysis to obtain performance requirement analysis data; Based on performance requirements, capacitor usage scenario data is matched with ceramic materials to obtain scenario-material matching data; The scene material matching data is the ceramic material analysis data.

[0020] The working principle and technical effects of the above technical solution are as follows: Through a progressive process of data acquisition, feature extraction, demand analysis, and material matching, a precise correspondence between the application scenario and the ceramic material is achieved. This involves acquiring raw data on the actual application scenario of the capacitor, including application area, working environment, and performance requirements; extracting core performance characteristics based on this data, filtering out key information related to insulation resistance and overall performance, and eliminating redundant data; conducting in-depth analysis of the extracted performance characteristics to clarify the core performance requirements and priorities of the capacitor for the scenario; using performance requirements as a benchmark, retrieving the performance guarantee range of the ceramic material, and precisely matching the scenario requirements with material performance to determine the most suitable ceramic material and core parameters, thus forming ceramic material analysis data. For example, in high-frequency scenarios for communication equipment, performance characteristics such as high-frequency stability and low loss need to be extracted, and then ceramic materials with strong high-frequency adaptability and low impurity tolerance need to be matched.

[0021] This invention solves the technical problems of traditional ceramic material selection relying on experience and having vague application scenarios, avoiding insufficient insulation performance or material waste caused by mismatch between material selection and scenario requirements; it achieves precise transformation of scenario performance requirements into ceramic material selection, making material selection more targeted; it improves the accuracy of material selection and the compatibility of capacitors with application scenarios; it reduces product scrap rates caused by improper material selection and cost increases due to excessive performance redundancy, ensuring the feasibility of the overall insulation improvement solution.

[0022] In one embodiment of the present invention, the step of performing performance requirement data analysis on the scene performance extraction information to obtain performance requirement analysis data includes: The performance information extracted from the scene is decomposed into performance categories to obtain multiple performance category decomposition data; the performance category data includes operating frequency data, capacitance data, voltage data, and accuracy and stability, etc. Different level range information is preset for each performance category decomposition data. The different level range information of multiple performance category decomposition data is matched with the level to obtain the category level correspondence range information of multiple performance category decomposition data. The data of multiple performance categories are broken down and compared with the information of different category level ranges to obtain multiple performance category level data; Obtain preset weight data for multiple performance category breakdown data, calculate the product of performance category level data and preset weight data, and obtain category requirement analysis data; The sum of multiple performance level requirements analysis data is obtained to acquire performance requirements analysis data.

[0023] The working principle and technical effects of the above technical solution are as follows: Through quantitative decomposition and weighted calculation, qualitative scenario performance extraction information is transformed into quantifiable and comparable performance requirement analysis data, ensuring the objectivity and accuracy of the requirement analysis. Scenario performance extraction information is decomposed into core dimensions such as operating frequency, capacitance, voltage, and precision stability, with each dimension serving as independent performance category decomposition data. Multiple grade ranges are preset for each performance category (e.g., operating frequency is divided into high-frequency, mid-frequency, and low-frequency levels, each corresponding to a specific numerical range), and the grade ranges of different performance categories are standardized to form a standardized grade comparison system. The decomposed performance data is compared with the corresponding grade range to determine the grade data to which each performance category belongs. Based on actual application scenarios, preset weights are assigned to each performance category (core performance weights are higher than secondary performance weights; for example, in high-frequency precision scenarios, precision stability weights are higher than capacitance weights). The requirement analysis data for a single performance category is obtained by calculating the product of each performance grade data and its corresponding weight. The requirement analysis data for all performance categories are summed to form comprehensive performance requirement analysis data, providing a quantitative basis for material matching. For example, in general home appliance scenarios, voltage and capacity are the core performance parameters, with weights set at 0.4 and 0.3 respectively. Accuracy and stability have a weight of 0.2, and operating frequency has a weight of 0.1. By weighting these parameters, comprehensive performance requirements data are obtained, and ceramic materials that balance cost-effectiveness and capacity are matched.

[0024] This invention solves the technical problems of traditional scenario performance requirement analysis being qualitative, subjective, and vague in prioritization, avoiding material and scenario mismatch caused by inaccurate requirement analysis; it realizes the quantification and standardization of scenario performance requirements, making performance requirements of different dimensions comparable and superimposed; it improves the accuracy, objectivity, and distinguishability of requirements in different scenarios; it reduces design errors caused by misunderstandings of requirements, while improving the universality and efficiency of performance requirement analysis in different scenarios.

[0025] In one embodiment of the present invention, the step of matching capacitor usage scenario data with ceramic materials based on performance requirement information to obtain scenario material matching data includes: Obtain the material performance guarantee range data of ceramic materials, decompose the material performance guarantee range data into multiple performance guarantee range levels, and obtain multiple performance guarantee level decomposition ranges; By breaking down multiple performance assurance levels into ranges and mapping them to levels, information on the ranges corresponding to the assurance levels is obtained. By matching the performance requirements of capacitor usage scenarios with the corresponding range of protection levels, scenario material matching data is obtained.

[0026] The working principle and technical effect of the above technical solution are as follows: Through material performance grading and demand matching, a precise correspondence between the scenario and the ceramic material is achieved. Core performance parameters of various ceramic materials are collected, including insulation performance, impurity resistance, temperature stability, and dielectric constant. These performance parameters are broken down into multiple performance guarantee ranges. For each performance guarantee range, multiple guarantee levels are defined (e.g., insulation performance is divided into high, medium, and low levels, corresponding to different insulation resistance guarantee intervals), and a correspondence between each performance level is established, forming a standardized guarantee level system. The scenario performance requirement information obtained in the early stages is compared one by one with the corresponding guarantee level ranges of the ceramic materials to select ceramic materials whose performance levels can meet the scenario requirements and have the highest overall adaptability. Scenario material matching data is formed, clarifying the core performance parameters and adaptability basis of the selected materials. For example, high-voltage scenarios have high requirements for the voltage withstand performance and insulation stability of ceramic materials. The voltage withstand performance of materials is divided into three levels, and ceramic materials corresponding to the high-voltage guarantee level are selected, while also considering other performance requirements to complete the matching.

[0027] This invention solves the technical problems of lack of standardization system and vague compatibility assessment in traditional material matching, avoiding product performance defects caused by excessive or insufficient material performance; it realizes standardized and refined matching of scenario requirements and ceramic material performance, breaking the limitations of experience-based matching; it improves the accuracy, efficiency and adaptability of material matching in different scenarios, ensuring that the selected material can maximize the satisfaction of the core requirements of the scenario; it reduces performance risks and cost waste caused by improper material compatibility, and ensures the consistency of the overall solution.

[0028] In one embodiment of the present invention, S2 includes: Based on the ceramic material analysis data, single-layer dielectric thickness analysis and adjustment, chip size analysis and adjustment, and safety spacing analysis and adjustment are performed to obtain first analysis and adjustment data, second analysis and adjustment data, and third analysis and adjustment data. Based on the first analysis adjustment data, the second analysis adjustment data, and the third analysis adjustment data, size redundancy compensation impurity analysis adjustment is performed to obtain size impurity joint analysis adjustment data.

[0029] The working principle and technical effects of the above-mentioned technical solution are as follows: A complementary adjustment system for size and impurities is constructed through a logic of segmented adjustment and joint coordination, enhancing the redundancy of insulation performance. Based on the core parameters such as the impurity content threshold and dielectric properties of the selected ceramic material, three key structural dimensions are specifically adjusted: single-layer dielectric thickness, chip size, and safety spacing, obtaining analytical adjustment data for each dimension. Single-layer dielectric thickness directly affects the insulation barrier capability, chip size affects impurity aggregation and electric field distribution, and safety spacing avoids the risk of insulation breakdown under high voltage. The adjustment data of the three dimensions are integrated, and a joint analysis of size and impurities is performed in conjunction with the actual impurity content of the material. Through redundancy compensation calculation, it is determined whether the current size can compensate for the insulation shortcomings that impurities may cause. For cases where the impurity content is high or close to the control limit, the size parameters are further optimized to increase insulation redundancy, forming joint analysis and adjustment data of size and impurities. This ensures that the structural size and impurity content are compatible, maximizing the improvement of insulation performance. For example, if the material impurity content is close to the control limit, the negative impact of impurities on insulation can be compensated by increasing the single-layer dielectric thickness, reducing the chip size tolerance, and widening the safety spacing.

[0030] This invention solves the technical problems of traditional structural size design being disconnected from material impurity characteristics, lack of redundant design, and limited effect of single-size adjustment; it achieves coordinated adaptation between structural size and material impurity content, and constructs double insulation protection through dimensional redundancy design; it improves the scientific nature of ceramic capacitor structural design, the redundancy of insulation performance, and tolerance to impurities, effectively avoiding the problem that single-size adjustment is difficult to cope with impurity fluctuations; it reduces the risk of insulation breakdown caused by size and impurity mismatch, the cost of repeated structural design optimization, and at the same time improves the stability and reliability of the product structure.

[0031] In one embodiment of the present invention, the step of performing single-layer dielectric thickness analysis and adjustment, chip size analysis and adjustment, and safety spacing analysis and adjustment based on ceramic material analysis data to obtain first analysis and adjustment data, second analysis and adjustment data, and third analysis and adjustment data includes: Based on the impurity content threshold and impurity content data in the ceramic material analysis data; The ratio of impurity content data to impurity threshold is used to obtain the material impurity content coefficient. The material impurity content coefficient is compared with the preset threshold corresponding to a single-layer medium to obtain the first analytical data. The thickness of the single-layer medium is adjusted based on the first analysis data to obtain the first analysis adjustment data; The material impurity content coefficient is compared with the preset chip size threshold to obtain the second analysis data; The chip size is adjusted based on the second analysis data to obtain the second analysis adjustment data; The material impurity content coefficient is compared with the threshold corresponding to the preset safety distance to obtain the third analysis data; The safety spacing is adjusted based on the third analysis data to obtain the third analysis adjustment data.

[0032] Example: For a certain type 2 ceramic capacitor, the ceramic material analysis data clearly states that the impurity content threshold is 50 ppm, while the actual measured impurity content is 40 ppm. The calculated material impurity content coefficient is 40 ppm ÷ 50 ppm = 0.8. A preset threshold system is established: an impurity content coefficient of 0.6-0.8 represents the mid-to-high range, corresponding to a single-layer dielectric thickness of 4.5-5 μm, a chip size tolerance of ±0.04-±0.045 mm, and a safety clearance of 5.5-6 mm. After comparing the coefficient 0.8 with the preset threshold, the adjustment scheme is determined: the single-layer dielectric thickness is adjusted to the upper limit of the mid-to-high range (5 μm) (first analysis adjustment data), the chip size tolerance is adjusted to the lower limit of the mid-to-high range (±0.04 mm) (second analysis adjustment data), and the safety clearance is adjusted to the upper limit of the mid-to-high range (6 mm) (third analysis adjustment data), to accommodate the insulation effects caused by impurity content.

[0033] The working principle and technical effect of the above technical solution are as follows: Using material impurity content as the core quantitative basis, precise graded adjustment of structural dimensions is achieved. The impurity content threshold (maximum allowable impurity content) and actual impurity content data are extracted from the ceramic material analysis data. By calculating the ratio of the actual impurity content to the impurity threshold, a material impurity content coefficient is obtained. This coefficient directly reflects the degree to which the impurity content is close to the control limit (the closer the coefficient is to 1, the higher the impurity content). For single-layer dielectric thickness, multiple sets of impurity content coefficients and corresponding thresholds for dielectric thickness are preset. The calculated impurity content coefficient is compared with the preset thresholds to determine the appropriate dielectric thickness adjustment direction and magnitude, forming the first analysis and adjustment data (the higher the impurity content coefficient, the greater the dielectric thickness needs to be, strengthening the insulation barrier). Using the same logic, the impurity content coefficient is compared with the preset chip size corresponding threshold and the preset safety distance corresponding threshold, respectively. Combining the influence of size on insulation performance, the chip size accuracy (the higher the impurity content coefficient, the smaller the size tolerance needs to be, reducing impurity aggregation and electric field concentration) and safety distance (the higher the impurity content coefficient, the wider the distance needs to be, avoiding the risk of breakdown) are adjusted respectively, forming the second and third analysis and adjustment data. For example, when the impurity content coefficient is 0.8 (close to the upper limit), after comparing with the preset threshold, the thickness of the single-layer dielectric is adjusted to the upper limit of the corresponding range, the chip size tolerance is adjusted to the lower limit of the range, and the safety distance is adjusted to the upper limit of the range to ensure insulation redundancy.

[0034] This invention solves the technical problems of traditional structural dimension adjustment lacking quantitative basis, being disconnected from impurity content, and having subjective adjustment range, thus avoiding performance defects caused by excessive or insufficient dimension adjustment; it realizes quantitative linkage adjustment between impurity content and structural dimensions, making dimension adjustment more targeted; it improves the accuracy, consistency, and adaptability to material impurity characteristics of structural dimension adjustment, ensuring that each dimension parameter can specifically compensate for the insulation effects caused by impurities; and it reduces the trial-and-error cost of dimension adjustment and the fluctuation of insulation performance caused by improper dimensions.

[0035] In one embodiment of the present invention, the step of performing size redundancy compensation impurity analysis and adjustment based on first analysis and adjustment data, second analysis and adjustment data, and third analysis and adjustment data to obtain joint size and impurity analysis and adjustment data includes: Redundancy compensation calculations were performed on the first, second, and third analysis adjustment data to obtain the redundancy compensation calculation results: Based on the redundancy compensation calculation results, the absolute value of the difference between the impurity content and the preset control limit is obtained to obtain data close to the impurity limit. Based on the impurity upper limit data, redundant adjustments are made to the single-layer dielectric thickness, chip size, and safety spacing to obtain joint size and impurity analysis adjustment data.

[0036] For example, consider a type 2 ceramic capacitor with a preset impurity control threshold of 50 ppm. After adjustments to each component, the following analytical adjustment data are obtained: single-layer dielectric thickness 4.5 μm, chip size tolerance ±0.045 mm, and safety clearance 5.5 mm. The actual detected impurity content is 48 ppm, and the calculated upper limit of impurities is close to 2 ppm (50 ppm - 48 ppm), which is a small difference and close to the upper limit. After redundancy compensation calculation, redundant adjustments are made based on the individual adjustment data: the single-layer dielectric thickness is increased by an additional 0.5 μm to 5 μm, the chip size tolerance is reduced by 0.005 mm to ±0.04 mm, and the safety clearance is widened by 0.5 mm to 6 mm, ultimately forming a combined size and impurity analysis adjustment data.

[0037] The working principle and technical effect of the above technical solution are as follows: Based on the size-specific adjustment data, through redundancy compensation calculation, a deep collaborative optimization of size and impurities is achieved, further strengthening insulation protection. A comprehensive redundancy compensation calculation is performed on the first, second, and third analysis and adjustment data to assess the compensation capability of the current size adjustment parameters for impurities and determine whether there are any shortcomings in insulation performance. The absolute value of the difference between the actual impurity content and the preset control upper limit is calculated to obtain the impurity upper limit approximation data. This data quantitatively reflects the remaining space between the impurity content and the control upper limit (the smaller the difference, the higher the approximation, and the greater the insulation risk). Redundancy adjustment rules are set according to the impurity upper limit approximation data. If the impurity upper limit approximation data is small (impurity content is close to the upper limit), then based on the sub-item adjustment data, the single-layer dielectric thickness is further increased, the chip size tolerance is reduced, and the safety distance is widened to supplement insulation redundancy. If the impurity upper limit approximation data is large (impurity content is low), the size parameters can be appropriately optimized to balance product volume and cost while ensuring insulation performance, forming size and impurity joint analysis and adjustment data to ensure accurate matching between redundant design and impurity risk. For example, when the upper limit of impurities is close to 0.05 (small difference, close to the upper limit), on the basis of the sub-item adjustment, an additional 0.5μm dielectric thickness and a 0.005mm chip size tolerance are added to improve insulation redundancy.

[0038] This invention solves the technical problems of traditional size adjustment lacking redundant design, difficulty in coping with impurity fluctuations, and performance-cost imbalance; it achieves dynamic adaptation between impurity risk and size redundancy, breaking the limitation of fixed size design that cannot accommodate different impurity contents; it improves the ceramic capacitor's tolerance to impurity fluctuations, the stability of insulation performance, and the flexibility of design schemes, ensuring that insulation performance can still be guaranteed when the impurity content is close to the control limit; it reduces the risk of insulation failure caused by impurity fluctuations, and the increase in product size and cost caused by excessive redundancy, achieving an optimal balance between insulation performance, product size, and cost.

[0039] In one embodiment of the present invention, S3 includes: Based on the combined analysis and adjustment data of size and impurities, the entire production process is controlled to obtain full-process control information. Based on the full-process control information, monitor the changes in impurity data to obtain impurity change monitoring data; Based on the monitoring data of impurity changes, an impact analysis of impurity changes is conducted to obtain data on the impact analysis of impurity changes. Based on the data analysis of the impact of impurity changes, early warning of the impact of impurity changes is generated. Based on the early warning of the impact of impurity changes, impurity early warning adjustment information is generated to obtain data on the improvement of insulation resistance.

[0040] For example, in the production of a certain type of ceramic capacitor, the joint analysis and adjustment data of dimensional impurities clearly showed: a single-layer dielectric thickness of 5μm, a chip size tolerance of ±0.04mm, and a safety spacing of 6mm, corresponding to an impurity control threshold of 50ppm. Based on this, the entire process control indicators were broken down, with the sintering stage set at a temperature of 1320℃ and a high-purity oxygen atmosphere protection. Real-time monitoring during production revealed that the impurity content in the sintering stage rapidly increased from 35ppm to 46ppm, exceeding the preset warning threshold (45ppm), and the system immediately issued an impurity exceedance warning. Subsequently, based on the warning information, the sintering temperature was lowered by 10℃, the holding time was extended by 5 minutes, and the oxygen flow was increased to suppress impurity migration and aggregation. After the adjustment, the impurity content dropped back to 38ppm, the product insulation performance met the standard, and the insulation resistance was stably improved.

[0041] The working principle and technical effects of the above-mentioned technical solution are as follows: Using size and impurity joint analysis and adjustment data as the control benchmark, a closed-loop production system is constructed, encompassing full-process control, real-time monitoring, dynamic early warning, and precise adjustment. Size and impurity joint adjustment parameters are broken down into specific control indicators for each stage of production, covering the entire process from raw material preparation, molding, sintering, electrode preparation, and encapsulation. Process parameters for each stage are precisely set and controlled to ensure the production process meets design requirements and obtains full-process control information. During production, impurity data at each key node is collected in real time, monitoring the trend and magnitude of impurity content changes to form impurity change monitoring data. Based on the monitoring data, the potential impact of impurity changes on insulation performance is analyzed to determine if there are risks exceeding controllable limits. If impurity changes are detected that may lead to substandard insulation performance, an early warning is immediately issued, and production process parameters are adjusted based on the warning information to dynamically optimize control strategies, promptly curb the negative impact of impurities on insulation performance, obtain data on increased insulation resistance, and ensure that the product's insulation performance meets standards. For example, if an abnormal increase in impurity content is detected during the sintering stage, an early warning is immediately issued, and sintering temperature and atmosphere parameters are adjusted to suppress impurity migration and aggregation.

[0042] This invention solves the technical problems of passive impurity control, fixed process parameters, and difficulty in coping with process fluctuations in traditional production processes. It avoids batch insulation performance defects caused by impurity changes during production; it achieves precise control of the entire production process and dynamic response to impurity changes, breaking the traditional model of post-production inspection and batch rejection; it improves the controllability of the production process, the early warning capability of impurity changes, and the dynamic adaptability of process parameters, ensuring the consistency and stability of product insulation performance; it reduces the scrap rate of batch products, production energy consumption, and subsequent quality control costs, while improving production efficiency and batch pass rate, and strengthening the anti-interference capability of the production system.

[0043] In one embodiment of the present invention, the step of performing impurity change impact analysis based on impurity change monitoring data to obtain impurity change impact analysis data includes: Based on the impurity change monitoring data, information on the magnitude of impurity changes is obtained; Determine the maximum and minimum impurity information based on the impurity variation range information; Data on the insulation resistance attenuation amplitude when the impurity information is maximized is obtained to acquire data on the maximum impact of the change. Data on insulation resistance attenuation amplitude when impurities are minimized is obtained to acquire data on the minimum impact of change. Obtain the difference between the data with the maximum and minimum impact of change to obtain the data for analyzing the impact of impurity changes.

[0044] Example: In the production of a certain type of ceramic capacitor, the impurity content during the sintering process was monitored to fluctuate between 30ppm and 48ppm (minimum impurity information: 30ppm; maximum impurity information: 48ppm). Testing showed that when the impurity level was 30ppm, the insulation resistance decreased by 5% (minimum change impact data); when the impurity level was 48ppm, the insulation resistance decreased by 22% (maximum change impact data). The difference between the two is 17%, meaning the impact of impurity variation is 17%, indicating that the impurity fluctuation in this batch is highly sensitive to insulation performance, and impurity control during the sintering process needs to be strengthened.

[0045] The working principle and technical effect of the above technical solution are as follows: This step accurately assesses the impact of impurity changes on insulation performance by quantitatively analyzing the correlation between impurity changes and insulation resistance attenuation. Based on impurity change monitoring data, the variation range of impurity content at different production nodes and in different batches is calculated to clarify the fluctuation range and trend of impurity content, obtaining information on the magnitude of impurity changes. From the variation range information, the maximum value (most unfavorable operating condition) and minimum value (most favorable operating condition) of impurity content are extracted to determine the maximum and minimum impurity information. The attenuation of the insulation resistance of the ceramic capacitor is tested or simulated when impurities are at their maximum and minimum values, respectively, to obtain the maximum and minimum change impact data. By calculating the difference between the maximum and minimum change impact data, the influence range and sensitivity of impurity changes on insulation resistance attenuation are quantified, forming impurity change impact analysis data. For example, when the impurity content is at its maximum, the insulation resistance attenuation is more significant than the baseline value, while when the impurity content is at its minimum, the attenuation is smaller. The difference between the two reflects the degree of impact of impurity fluctuations on insulation performance. The larger the difference, the more sensitive the impurities are to insulation performance, requiring stronger control.

[0046] This invention solves the technical problems of traditional impurity impact analysis being qualitative and difficult to quantify the correlation between impurity fluctuations and insulation performance. It avoids unreasonable warning threshold settings and a lack of targeted process adjustments. It enables quantitative assessment of the impact of impurity changes on insulation performance, clarifying the scope and sensitivity of impurity fluctuations. It improves the accuracy of impurity impact analysis, the scientific nature of warning strategies, and the targeted nature of process adjustments, ensuring that appropriate control measures can be formulated based on the degree of impact of impurity changes. It reduces the risk of uncontrolled insulation performance due to inaccurate impurity impact assessment and the increase in process costs caused by over-adjustment. At the same time, it provides data support for the dynamic optimization of the production process, further ensuring the stable improvement of insulation resistance.

[0047] According to one embodiment of the present invention, the system includes: The materials analysis module is used to acquire capacitor usage scenario data, perform scenario determination analysis on the capacitor usage scenario data to obtain scenario determination analysis data, and perform ceramic material analysis based on the scenario determination analysis data to obtain ceramic material analysis data. The size adjustment module is used to perform ceramic structure size analysis and adjustment based on ceramic material analysis data, obtain various analysis and adjustment data, and perform joint size and impurity analysis based on the various analysis and adjustment data to obtain joint size and impurity analysis and adjustment data. The resistance enhancement module is used to analyze and adjust the production process impurities based on the joint analysis and adjustment data of size and impurities, in order to obtain data on improving insulation resistance.

[0048] The working principle and technical effects of the above-mentioned technical solution are as follows: This system acquires data on capacitor usage scenarios to accurately determine the scenario type and core requirements, and then matches suitable ceramic materials. Based on the characteristics of the selected materials, it specifically adjusts the key dimensions of the ceramic structure, and performs joint collaborative analysis of dimensions and impurities in conjunction with impurity content. Through dimensional redundancy design, it compensates for potential insulation shortcomings caused by impurities. Based on the joint adjustment parameters of dimensions and impurities, it precisely controls the entire production process, monitors impurity changes in real time and dynamically adjusts them to ensure that the negative impact of impurities on insulation performance during production is controllable, achieving a stable improvement in insulation resistance. The entire process forms a closed loop of linkage from scenario to material to dimension, and from impurities to production, with data exchange and dynamic adaptation among each link, avoiding the limitations of single-link control.

[0049] This invention solves the technical problems of poor scenario adaptability, disconnect between material and size control, and passive inspection in the production process of traditional ceramic capacitors. It achieves precise adaptation between scenario requirements and ceramic capacitor design and production, breaking the bottleneck of single-dimensional control being unable to meet the needs of multiple scenarios. It improves the stability of the insulation performance of ceramic capacitors, the flexibility of scenario adaptability, and the controllability of the production process, effectively avoiding the risk of insulation failure caused by impurities and structural size mismatch. It reduces the insulation performance failure rate, material waste, and subsequent operation and maintenance costs during the production process, while improving the product's tolerance to different working conditions and expanding the product's application range.

[0050] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for improving the insulation resistance of a ceramic capacitor, characterized in that, The method includes: S1. Obtain capacitor usage scenario data, perform scenario determination analysis on the capacitor usage scenario data, obtain scenario determination analysis data, perform ceramic material analysis based on the scenario determination analysis data, and obtain ceramic material analysis data. S2. Based on the ceramic material analysis data, perform ceramic structure size analysis and adjustment to obtain various analysis and adjustment data. Based on the various analysis and adjustment data, perform joint size and impurity analysis to obtain joint size and impurity analysis and adjustment data. S3. Based on the combined analysis and adjustment data of size and impurities, conduct impurity analysis and adjustment of the production process to obtain data on improving insulation resistance.

2. The method for improving the insulation resistance of a ceramic capacitor according to claim 1, characterized in that, S1 includes: Acquire capacitor usage scenario data, and extract scenario performance features based on the capacitor usage scenario data to obtain scenario performance extraction information; The performance extraction information of the scenario is subjected to performance requirement data analysis to obtain performance requirement analysis data; Based on performance requirements, capacitor usage scenario data is matched with ceramic materials to obtain scenario-material matching data; The scene material matching data is the ceramic material analysis data.

3. The method for improving the insulation resistance of a ceramic capacitor according to claim 2, characterized in that, The step of performing performance requirement data analysis on the extracted scenario performance information to obtain performance requirement analysis data includes: The scene performance extraction information is decomposed into performance category data to obtain multiple performance category decomposition data; Different level range information is preset for each performance category decomposition data. The different level range information of multiple performance category decomposition data is matched with the level to obtain the category level correspondence range information of multiple performance category decomposition data. The data of multiple performance categories are broken down and compared with the information of different category level ranges to obtain multiple performance category level data; Obtain preset weight data for multiple performance category breakdown data, calculate the product of performance category level data and preset weight data, and obtain category requirement analysis data; The sum of multiple performance level requirements analysis data is obtained to acquire performance requirements analysis data.

4. The method for improving the insulation resistance of a ceramic capacitor according to claim 2, characterized in that, The step of matching capacitor usage scenario data with ceramic materials based on performance requirement information to obtain scenario material matching data includes: Obtain the material performance guarantee range data of ceramic materials, decompose the material performance guarantee range data into multiple performance guarantee range levels, and obtain multiple performance guarantee level decomposition ranges; By breaking down multiple performance assurance levels into ranges and mapping them to levels, information on the ranges corresponding to the assurance levels is obtained. By matching the performance requirements of capacitor usage scenarios with the corresponding range of protection levels, scenario material matching data is obtained.

5. The method for improving the insulation resistance of a ceramic capacitor according to claim 1, characterized in that, S2 includes: Based on the ceramic material analysis data, single-layer dielectric thickness analysis and adjustment, chip size analysis and adjustment, and safety spacing analysis and adjustment are performed to obtain first analysis and adjustment data, second analysis and adjustment data, and third analysis and adjustment data. Based on the first analysis adjustment data, the second analysis adjustment data, and the third analysis adjustment data, size redundancy compensation impurity analysis adjustment is performed to obtain size impurity joint analysis adjustment data.

6. The method for improving the insulation resistance of a ceramic capacitor according to claim 5, characterized in that, The process of adjusting the single-layer dielectric thickness, chip size, and safety spacing based on ceramic material analysis data to obtain first, second, and third analysis adjustment data includes: Based on the impurity content threshold and impurity content data in the ceramic material analysis data; The ratio of impurity content data to impurity threshold is used to obtain the material impurity content coefficient. The material impurity content coefficient is compared with the preset threshold corresponding to a single-layer medium to obtain the first analytical data. The thickness of the single-layer medium is adjusted based on the first analysis data to obtain the first analysis adjustment data; The material impurity content coefficient is compared with the preset chip size threshold to obtain the second analysis data; The chip size is adjusted based on the second analysis data to obtain the second analysis adjustment data; The material impurity content coefficient is compared with the threshold corresponding to the preset safety distance to obtain the third analysis data; The safety spacing is adjusted based on the third analysis data to obtain the third analysis adjustment data.

7. The method for improving the insulation resistance of a ceramic capacitor according to claim 5, characterized in that, The step of performing size redundancy compensation and impurity analysis and adjustment based on the first analysis and adjustment data, the second analysis and adjustment data, and the third analysis and adjustment data to obtain joint size and impurity analysis and adjustment data includes: Redundancy compensation calculations were performed on the first, second, and third analysis adjustment data to obtain the redundancy compensation calculation results: Based on the redundancy compensation calculation results, the absolute value of the difference between the impurity content and the preset control limit is obtained to obtain data close to the impurity limit. Based on the impurity upper limit data, redundant adjustments are made to the single-layer dielectric thickness, chip size, and safety spacing to obtain joint size and impurity analysis adjustment data.

8. The method for improving the insulation resistance of a ceramic capacitor according to claim 1, characterized in that, S3 includes: Based on the combined analysis and adjustment data of size and impurities, the entire production process is controlled to obtain full-process control information. Based on the full-process control information, monitor the changes in impurity data to obtain impurity change monitoring data; Based on the monitoring data of impurity changes, an impact analysis of impurity changes is conducted to obtain data on the impact analysis of impurity changes. Based on the data analysis of the impact of impurity changes, early warning of the impact of impurity changes is generated. Based on the early warning of the impact of impurity changes, impurity early warning adjustment information is generated to obtain data on the improvement of insulation resistance.

9. The method for improving the insulation resistance of a ceramic capacitor according to claim 8, characterized in that, The step of performing impurity change impact analysis based on impurity change monitoring data to obtain impurity change impact analysis data includes: Based on the impurity change monitoring data, information on the magnitude of impurity changes is obtained; Determine the maximum and minimum impurity information based on the impurity variation range information; Data on the insulation resistance attenuation amplitude when the impurity information is maximized is obtained to acquire data on the maximum impact of the change. Data on insulation resistance attenuation amplitude when impurities are minimized is obtained to acquire data on the minimum impact of change. Obtain the difference between the data with the maximum and minimum impact of change to obtain the data for analyzing the impact of impurity changes.

10. A system for improving the insulation resistance of a ceramic capacitor, characterized in that, The system includes: The materials analysis module is used to acquire capacitor usage scenario data, perform scenario determination analysis on the capacitor usage scenario data to obtain scenario determination analysis data, and perform ceramic material analysis based on the scenario determination analysis data to obtain ceramic material analysis data. The size adjustment module is used to perform ceramic structure size analysis and adjustment based on ceramic material analysis data, obtain various analysis and adjustment data, and perform joint size and impurity analysis based on the various analysis and adjustment data to obtain joint size and impurity analysis and adjustment data. The resistance enhancement module is used to analyze and adjust the production process impurities based on the joint analysis and adjustment data of size and impurities, in order to obtain data on improving insulation resistance.

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