Display panels with improved electrode light shielding and their fabrication methods

Abstract

This disclosure provides a display panel with improved electrode light-shielding and its fabrication method, belonging to the field of optoelectronic manufacturing technology. The display panel includes: multiple light-emitting units, a passivation layer, connecting electrodes, and a transparent conductive layer; the multiple light-emitting units are arranged at intervals, the passivation layer is located within the gaps between adjacent light-emitting units, and the connecting electrodes are located on the surface of the passivation layer and within the gaps between adjacent light-emitting units; each light-emitting unit includes a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer stacked sequentially, the passivation layer at least covering the sidewalls of the first semiconductor layer and the sidewalls of the multiple quantum well layer, the connecting electrodes are connected to the sidewalls of the second semiconductor layer, and the transparent conductive layer is located on the surface of the connecting electrodes away from the passivation layer and on each light-emitting unit. The embodiments of this disclosure can improve the problem of connecting electrodes blocking light emission from the light-emitting units, thereby improving the light emission efficiency of the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a display panel with improved electrode light shielding and a method for its fabrication. Background Technology

[0002] Micro LED (Micro Light Emitting Diode) display panels are an emerging display technology. The core of this technology is to use micron-sized Micro LED chips as light-emitting units and integrate them into a high-density array on a driving substrate to achieve independent light control for each light-emitting unit.

[0003] In related technologies, a display panel includes a driving substrate and multiple light-emitting units arranged at intervals on the driving substrate. To achieve centralized electrical control of each light-emitting unit, a common connection electrode is usually provided on the side of these light-emitting units facing away from the driving substrate (i.e., the light-emitting side). By applying current to this connection electrode, driving current can be provided to all light-emitting units simultaneously. This design simplifies circuit layout and driving method.

[0004] However, the connecting electrodes are typically made of metal. While the metal layer has good electrical conductivity, it is opaque, thus directly blocking the light emitted by the light-emitting units located below it. This causes some light energy to be absorbed or blocked by the electrodes, reducing the overall light emission efficiency and brightness of the display panel. Summary of the Invention

[0005] This disclosure provides a display panel with improved electrode light-blocking and its manufacturing method, which can improve the problem of connecting electrodes blocking light emission from the light-emitting unit and improve the light emission efficiency of the display panel. The technical solution is as follows: On one hand, this disclosure provides a display panel comprising: a plurality of light-emitting units, a passivation layer, a connection electrode, and a transparent conductive layer; the plurality of light-emitting units are arranged at intervals, the passivation layer is located within the gaps between adjacent light-emitting units, the connection electrode is located on the surface of the passivation layer and within the gaps between adjacent light-emitting units; each light-emitting unit comprises a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer stacked sequentially, the passivation layer at least covers the sidewalls of the first semiconductor layer and the sidewalls of the multiple quantum well layer, the connection electrode is connected to the sidewall of the second semiconductor layer, and the transparent conductive layer is located on the surface of the connection electrode away from the passivation layer and on each light-emitting unit.

[0006] In another implementation of this disclosure, the passivation layer includes a DBR layer.

[0007] In another implementation of this disclosure, the connecting electrode includes at least one of an Au layer, a Ge layer, an AuGe layer, a Ti layer, a Ni layer, and an Al layer.

[0008] In another implementation of this disclosure, the display panel further includes a driving substrate and a light-collecting structure. A plurality of light-emitting units are arranged at intervals on the driving substrate. The light-collecting structure corresponds to at least one of the light-emitting units and is located on the surface of the transparent conductive layer away from the driving substrate. The orthographic projection of the light-emitting unit on the surface of the driving substrate is located within the orthographic projection of the corresponding light-collecting structure on the surface of the driving substrate.

[0009] In another implementation of this disclosure, the display panel further includes bonding metal blocks corresponding to the light-emitting units one by one. The bonding metal blocks are located on the surface of the driving substrate, and the light-emitting units are located on the surfaces of the corresponding bonding metal blocks that are away from the driving substrate. The orthographic projection of the light-emitting unit on the surface of the driving substrate is located within the orthographic projection of the corresponding bonding metal block on the surface of the driving substrate.

[0010] In another implementation of this disclosure, the contact area between the connecting electrode and the sidewall of the second semiconductor layer is provided with a plurality of spaced protrusions.

[0011] This disclosure provides a method for fabricating a display panel, the method comprising: forming an epitaxial layer on a substrate; bonding the epitaxial layer to a driving substrate and removing the substrate; patterning the epitaxial layer to form a plurality of spaced-apart light-emitting units, each light-emitting unit comprising a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer sequentially stacked on the driving substrate; forming a passivation layer on the driving substrate and in the gaps between adjacent light-emitting units; forming a connection electrode on the surface of the passivation layer away from the driving substrate and in the gaps between adjacent light-emitting units, the passivation layer at least covering the sidewalls of the first semiconductor layer and the sidewalls of the multiple quantum well layer, the connection electrode being connected to the sidewall of the second semiconductor layer; and forming a transparent conductive layer on the surface of the connection electrode away from the driving substrate and on each light-emitting unit.

[0012] In another implementation of this disclosure, forming a passivation layer on the driving substrate and in the gap between adjacent light-emitting units includes: forming an insulating material film covering each light-emitting unit on the driving substrate; etching the insulating material film to expose the light-emitting surface of each light-emitting unit away from the driving substrate, and retaining a portion of the insulating material film in the gap between adjacent light-emitting units to form the passivation layer.

[0013] In another implementation of this disclosure, etching the insulating material film includes: etching the insulating material film to remove the insulating material film located on the light-emitting surface of each of the light-emitting units, and etching the insulating material film to a height above the multiple quantum well layer in the gap between adjacent light-emitting units.

[0014] In another implementation of this disclosure, forming a connection electrode on the surface of the passivation layer away from the driving substrate and in the gap between adjacent light-emitting units includes: forming a metal layer covering the light-emitting units on the surface of the passivation layer away from the driving substrate; etching the metal layer to remove the metal layer on the light-emitting surface of each light-emitting unit, and retaining the metal layer in the gap between adjacent light-emitting units to form the connection electrode.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The display panel provided in this disclosure places the connecting electrodes within the gaps between adjacent light-emitting units, ensuring that the metal electrodes do not directly cover the light-emitting area. Simultaneously, a transparent conductive layer is applied above the connecting electrodes and to the light-emitting surface of the light-emitting units. This not only connects the connecting electrodes in series to retain their conductivity but also prevents the metal from absorbing and blocking light. This eliminates the light energy loss caused by electrode obstruction in related technologies, directly improving the overall light emission efficiency and brightness of the display panel.

[0016] Furthermore, the sidewalls and bottom surface of the light-emitting unit are surrounded by metal electrodes and a passivation layer, forming a total internal reflection structure that restricts light to only emanating from the light-emitting surface. The high transmittance of the transparent conductive layer further reduces interface reflection loss. This directional light emission design improves light collimation, reduces light leakage outside the viewing angle, and enhances contrast and color purity. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure; Figure 2 This is a flowchart of a method for manufacturing a display panel according to an embodiment of this disclosure; Figure 3 This is a manufacturing state diagram of a display panel provided in an embodiment of this disclosure; Figure 4 This is a manufacturing state diagram of a display panel provided in an embodiment of this disclosure.

[0019] The markings in the diagram are explained as follows: 10. Epitaxial layer; 11. First semiconductor layer; 12. Multiple quantum well layer; 13. Second semiconductor layer; 100. Light-emitting unit; 20. Driving substrate; 30. Passivation layer; 40. Connect the electrodes; 50. Transparent conductive layer; 60. Bonded metal block; 61. First metal layer; 62. Second metal layer; 70. Substrate; 80. Light-collecting structure. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0021] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0022] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure. Figure 1 As shown, the display panel includes: a driving substrate 20, multiple light-emitting units 100, a passivation layer 30, a connecting electrode 40, and a transparent conductive layer 50.

[0023] like Figure 1As shown, multiple light-emitting units 100 are arranged at intervals on the driving substrate 20. A passivation layer 30 is located on the driving substrate 20 and in the gap between adjacent light-emitting units 100. A connecting electrode 40 is located on the surface of the passivation layer 30 away from the driving substrate 20 and in the gap between adjacent light-emitting units 100. The connecting electrode 40 is electrically connected to the sidewall of the light-emitting unit 100. A transparent conductive layer 50 is located on the surface of the connecting electrode 40 away from the driving substrate 20 and on the light-emitting surface of each light-emitting unit 100 away from the driving substrate 20.

[0024] like Figure 1 As shown, the orthographic projection of the connecting electrode 40 on the surface of the driving substrate 20 is outside the orthographic projection of the light-emitting surface on the surface of the driving substrate 20.

[0025] The display panel provided in this embodiment places the connecting electrode 40 within the gap between adjacent light-emitting units 100, and its orthographic projection is completely outside the projection of the light-emitting surface of the light-emitting unit 100, ensuring that the metal electrode does not directly cover the light-emitting area. Simultaneously, a transparent conductive layer 50 is covered above the connecting electrode 40 and on the light-emitting surface of the light-emitting unit 100, which both connects the connecting electrode 40 in series to retain its conductive function and avoids the absorption and obstruction of light by the metal. This eliminates the light energy loss caused by electrode obstruction in related technologies, directly improving the overall light emission efficiency and brightness of the display panel.

[0026] Furthermore, the sidewalls and bottom surface of the light-emitting unit 100 are surrounded by metal electrodes and a passivation layer 30, forming a total internal reflection structure that restricts light to only emanating from the light-emitting surface. The high transmittance of the transparent conductive layer 50 further reduces interface reflection loss. This directional light emission design improves light collimation, reduces light leakage outside the viewing angle, and enhances contrast and color purity.

[0027] For example, the transparent conductive layer 50 may be an ITO layer or an IZO layer.

[0028] As an example, the thickness of the transparent conductive layer 50 can be greater than or equal to 2000 angstroms. This thickness range ensures good conductivity for effective transmission of electrical signals while also providing high transparency to reduce obstruction of light emitted from the light-emitting unit.

[0029] Optionally, such as Figure 1 As shown, the light-emitting unit 100 includes a first semiconductor layer 11, a multiple quantum well layer 12, and a second semiconductor layer 13, which are sequentially stacked on the driving substrate 20.

[0030] In this process, one of the first semiconductor layer 11 and the second semiconductor layer 13 is an n-type layer, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 is a p-type layer.

[0031] Optionally, the n-type layer is an n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 1 μm.

[0032] Optionally, the multiple quantum well layer 12 includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multiple quantum well layer 12 may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0033] As an example, in an embodiment of this disclosure, the multi-quantum-well layer 12 includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0034] Optionally, the thickness of the multiple quantum well layer 12 can be from 150 nm to 200 nm.

[0035] Optionally, the p-type layer is a p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 1 μm.

[0036] like Figure 1 As shown, the passivation layer 30 covers at least the sidewalls of the first semiconductor layer 11 and the sidewalls of the multiple quantum well layer 12, and the connecting electrode 40 is connected to the sidewall of the second semiconductor layer 13.

[0037] Since the multi-quantum-well layer 12 is the light-emitting core film layer, it is susceptible to non-radiative recombination caused by sidewall defects; the sidewalls of the first semiconductor layer 11 are also prone to oxidation or doping loss due to exposure. The passivation layer 30 covers the sidewalls of both layers, which can effectively isolate moisture and oxygen erosion and suppress sidewall leakage current.

[0038] Furthermore, the connecting electrode 40 is directly connected to the sidewall of the second semiconductor layer 13. Compared with the top electrode contact in related technologies, this shortens the lateral path of current from the electrode to the light-emitting region, reduces current diffusion loss, and improves carrier injection efficiency. At the same time, the sidewall contact avoids the electrode covering the surface of the light-emitting layer. Combined with the design of the connecting electrode 40 being located in the cell gap, it completely eliminates the obstruction of the light-emitting surface.

[0039] Optionally, the passivation layer 30 includes a DBR layer.

[0040] In an example, the DBR layer is an insulating film layer composed of alternating layers of high and low refractive index dielectrics. For instance, the DBR layer comprises multiple alternating layers of silicon oxide and multiple layers of titanium oxide.

[0041] The DBR layer has high reflectivity in the visible light band. Covering the sidewall of the light-emitting unit with the DBR layer can form a total internal reflection barrier. Light that would normally escape from the sidewall is efficiently reflected back to the light-emitting area or reused from the light-emitting surface, reducing stray light loss and further improving the collimation of the emitted light.

[0042] Furthermore, the DBR layer also has a passivation function. Its dense stacked structure can isolate water vapor and oxygen from the erosion of sidewall defects and suppress non-radiative recombination.

[0043] Optionally, the passivation layer 30 may also include at least one of a silicon oxide layer, a silicon nitride layer, and a titanium oxide layer.

[0044] Optionally, a plurality of spaced protrusions are provided in the contact area between the electrode 40 and the sidewall of the second semiconductor layer 13 of the light-emitting unit 100.

[0045] For example, the protrusion may be hemispherical or prismatic.

[0046] This increases the contact area between the electrode and the semiconductor sidewall, preventing the electrode from easily detaching from the semiconductor and improving the reliability of the connection between the electrode and the semiconductor layer; the raised structure can also guide the scattered light from the contact area out of the light surface, reducing light absorption loss near the electrical contact point.

[0047] Alternatively, the protrusions and connecting electrodes 40 can be made of different metallic materials.

[0048] For example, the protrusions can be made of a high-hardness metal (such as W) to enhance wear resistance.

[0049] For example, the protrusion may be a Ti layer or a Ni layer to enhance the adhesion between the connection electrode 40 and the semiconductor layer.

[0050] Optionally, the connecting electrode 40 includes at least one of Au layer, Ge layer, AuGe layer, Ti layer, Ni layer and Al layer.

[0051] For example, the connecting electrode 40 includes an Au layer. The Au layer has high chemical stability, excellent conductivity, and strong oxidation resistance, which can ensure long-term reliable contact of the electrode and reduce contact resistance drift.

[0052] For example, the connection electrode 40 includes a Ge layer. The Ge layer can form a low-resistance ohmic contact with the semiconductor layer, reducing the carrier injection barrier and improving current transport efficiency.

[0053] For example, the connecting electrode 40 includes an AuGe layer. The AuGe layer combines the stability of Au with the contact characteristics of Ge, forming a low-resistivity interface after sintering, thus optimizing current injection performance.

[0054] For example, the connecting electrode 40 includes a Ti layer. The Ti layer has strong adhesion and can act as a diffusion barrier layer to prevent metal interpenetration, thereby enhancing the reliability of the bonding between the electrode and the semiconductor layer.

[0055] For example, the connecting electrode 40 includes a Ni layer. The Ni layer has good conductivity and is moderately cost-effective, serving as a transition layer to improve the adhesion between the electrode and the substrate and enhance process compatibility.

[0056] For example, the connecting electrode 40 includes an Al layer. The Al layer has excellent conductivity and low cost, making it suitable for high current transmission and balancing performance and economy in a gap layout.

[0057] Optionally, such as Figure 1 As shown, the display panel also includes a light-collecting structure 80, which corresponds to at least one light-emitting unit 100 and is located on the surface of the transparent conductive layer 50 away from the driving substrate 20.

[0058] like Figure 1 As shown, the orthographic projection of the light-emitting unit 100 on the surface of the driving substrate 20 is located within the orthographic projection of the corresponding light-collecting structure 80 on the surface of the driving substrate 20.

[0059] For example, the top surface of the light-collecting structure 80 is an arc surface.

[0060] By setting up a light-collecting structure 80, the curved surface of the light-collecting structure 80 can converge the light and increase the amount of transmitted light. Since the light-emitting unit 100 may have lateral divergence, the light-collecting structure 80 (such as the top surface being convex) can converge the light in the normal direction, thereby improving the forward light intensity; combined with the reflection of sidewall light by the DBR layer, the light collimation is further improved, and the brightness uniformity is improved.

[0061] Alternatively, the light-collecting structure 80 can be made of PDMS, PMMA, or silicon dioxide.

[0062] Polydimethylsiloxane (PDMS) is a flexible and bendable material; its light transmittance exceeds 90%, which reduces total reflection and makes it suitable for flexible Micro LED panels.

[0063] Among them, polymethyl methacrylate (PMMA) has a light transmittance of over 92%, good optical uniformity, moderate mechanical strength, good weather resistance, and is easy to mold, making it suitable for preparing light-collecting structures for large-area planar displays.

[0064] Among them, silicon dioxide has a light transmittance of over 95% and excellent thermal stability, and can be precisely processed into microstructures through etching, making it suitable for high-temperature processes and high-precision display requirements.

[0065] Optionally, such as Figure 1 As shown, the display panel also includes bonding metal blocks 60 corresponding to the light-emitting units 100. The bonding metal blocks 60 are located on the surface of the driving substrate 20, and the light-emitting units 100 are located on the surface of the corresponding bonding metal blocks 60 away from the driving substrate 20.

[0066] like Figure 1As shown, the orthographic projection of the light-emitting unit 100 on the surface of the driving substrate 20 lies within the orthographic projection of the corresponding bonding metal block 60 on the surface of the driving substrate 20.

[0067] For example, the driving substrate 20 may be a complementary metal-oxide-semiconductor (CMOS) integrated circuit board.

[0068] like Figure 1 As shown, an electrode block corresponding to each light-emitting unit 100 is provided on the driving substrate 20. Each light-emitting unit 100 has a bonding metal block 60 on the side near the driving substrate 20. The bonding metal block 60 of each light-emitting diode is electrically connected to the corresponding electrode block, so as to realize the purpose of the driving substrate 20 controlling the operation of each light-emitting unit 100.

[0069] For example, the bonding metal block 60 may include at least one of AuBe layer, Au layer, Ti layer, Ni layer and Pt layer.

[0070] Figure 2 This is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of this disclosure. Figure 2 As shown, the preparation method includes: S11: An epitaxial layer 10 is formed on the substrate 70.

[0071] For example, the substrate is a sapphire substrate. Sapphire substrates have high light transmittance, meaning they are transparent. Furthermore, sapphire material is relatively hard and chemically stable, giving the light-emitting diode (LED) good luminous efficacy and stability.

[0072] S12: The epitaxial layer 10 is patterned to form multiple spaced light-emitting units 100.

[0073] The light-emitting unit 100 has an opposite light-emitting surface and a backlight surface, and the surface of the light-emitting unit 100 that is away from the driving substrate 20 is the light-emitting surface.

[0074] S13: A passivation layer 30 is formed on the driving substrate 20 and in the gap between adjacent light-emitting units 100.

[0075] S14: A connecting electrode 40 is formed on the surface of the passivation layer 30 away from the driving substrate 20 and in the gap between adjacent light-emitting units 100.

[0076] The orthographic projection of the connecting electrode 40 on the surface of the driving substrate 20 is located outside the orthographic projection of the light-emitting surface on the surface of the driving substrate 20.

[0077] S15: A transparent conductive layer 50 is formed on the surface of the connecting electrode 40 away from the driving substrate 20 and on the light-emitting surface of each light-emitting unit 100.

[0078] The display panel prepared by the method disclosed herein places the connecting electrode 40 within the gap between adjacent light-emitting units 100, and its orthographic projection is completely outside the projection of the light-emitting surface of the light-emitting unit 100, ensuring that the metal electrode does not directly cover the light-emitting area. Simultaneously, a transparent conductive layer 50 is covered above the connecting electrode 40 and on the light-emitting surface of the light-emitting unit 100, which both connects the connecting electrode 40 in series to retain its conductive function and avoids the absorption and obstruction of light by the metal. This eliminates the light energy loss caused by electrode obstruction in related technologies, directly improving the overall light emission efficiency and brightness of the display panel.

[0079] Furthermore, the sidewalls and bottom surface of the light-emitting unit 100 are surrounded by metal electrodes and a passivation layer 30, forming a total internal reflection structure that restricts light to only emanating from the light-emitting surface. The high transmittance of the transparent conductive layer 50 further reduces interface reflection loss. This directional light emission design improves light collimation, reduces light leakage outside the viewing angle, and enhances contrast and color purity.

[0080] In step S11, the epitaxial layer 10 may include a first semiconductor layer 11, a multiple quantum well layer 12, and a second semiconductor layer 13 sequentially stacked on the substrate 70.

[0081] The first semiconductor layer 11 has a first conductivity type, the second semiconductor layer 13 has a second conductivity type different from the first conductivity type, and the multi-quantum well layer 12 is used to generate light through electron-hole recombination.

[0082] Among them, one of the first semiconductor layer 11 and the second semiconductor layer 13 is a p-type layer, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 is an n-type layer.

[0083] As an example, the first semiconductor layer 11 is an n-type layer and the second semiconductor layer 13 is a p-type layer.

[0084] Optionally, the first semiconductor layer 11 is an n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 1 μm.

[0085] Optionally, the multiple quantum well layer 12 includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multiple quantum well layer 12 may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0086] As an example, in an embodiment of this disclosure, the multi-quantum-well layer 12 includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0087] Optionally, the thickness of the multiple quantum well layer 12 can be from 150 nm to 200 nm.

[0088] Optionally, the second semiconductor layer 13 is a p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 1 μm.

[0089] Following step S11, the following steps may be included: First step, such as Figure 3 As shown, on the surface-treated driving substrate 20, a metal thin film of uniform thickness is deposited on the surface of the pre-arranged contact electrodes by processes such as magnetron sputtering or electron beam evaporation to form a first metal layer 61 for subsequent bonding.

[0090] For example, the first metal layer 61 may include at least one of an AuBe layer, an Au layer, a Ti layer, a Ni layer, and a Pt layer.

[0091] The second step, as Figure 3 As shown, a uniform metal thin film is deposited on the surface of the epitaxial layer 10 by magnetron sputtering or electron beam evaporation to form a second metal layer 62 for subsequent bonding, ensuring that it completely covers and is tightly attached to the underlying structure.

[0092] For example, the second metal layer 62 may include at least one of an AuBe layer, an Au layer, a Ti layer, a Ni layer, and a Pt layer.

[0093] The third step, as Figure 3 As shown, a hot-press bonding process is used to align and bond the first metal layer 61 on the surface of the driving substrate 20 with the second metal layer 62 on one side of the epitaxial layer 10. The bonding is maintained for 10 to 30 seconds at a temperature of 200°C to 300°C and a pressure of 1 MPa to 5 MPa to promote the interdiffusion of atoms in the two metal layers to form a strong metallurgical bond. After bonding is completed, the substrate 70 is selectively removed by laser lift-off or chemical etching process to expose the epitaxial layer 10.

[0094] Step S12 may include the following steps: First step, such as Figure 3 As shown, the epitaxial layer 10 is etched in an array to remove non-patterned areas, forming multiple trapezoidal block structures.

[0095] The second step, as Figure 3 As shown, the bonding metal is etched in the gap between adjacent light-emitting units 100 to form a bonding metal block 60.

[0096] Step S13 may include the following steps: The first step is to form an insulating material film covering each light-emitting unit 100 on the driving substrate 20.

[0097] Specifically, this may include: uniformly depositing an insulating material film on the surface of the driving substrate 20 and the light-emitting unit 100 using plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). The film thickness is controlled between 1 μm and 3 μm to ensure complete coverage of the light-emitting unit 100 and the gaps between adjacent light-emitting units 100.

[0098] For example, the insulating material film may be a DBR layer.

[0099] The second step, as Figure 4 As shown, an insulating material film is etched to expose the light-emitting surface of each light-emitting unit 100, and a portion of the insulating material film is retained in the gap between adjacent light-emitting units 100 to form a passivation layer 30.

[0100] During the etching process of the insulating material film, the insulating material film located on the light-emitting surface of each light-emitting unit 100 is removed, and the insulating material film is etched to a height above the multi-quantum well layer 12 in the gap between adjacent light-emitting units 100.

[0101] Specifically, this may include: coating a photoresist mask on the light-emitting surface area of ​​the light-emitting unit 100 using a photolithography process to expose the area to be etched; selectively removing the insulating material film not covered by the mask using reactive ion etching (RIE), while simultaneously etching the insulating material film in the gap between adjacent units to a height slightly higher than the multi-quantum well layer 12, ultimately forming a passivation layer 30 that only covers the sidewalls and gaps.

[0102] Step S14 may include the following steps: The first step is to form a metal layer covering the light-emitting unit 100 on the surface of the passivation layer 30 away from the driving substrate 20.

[0103] Specifically, this may include: uniformly depositing a metal layer on the surface of the passivation layer 30 away from the driving substrate 20 using magnetron sputtering or electron beam evaporation processes, ensuring that the metal layer completely covers the surface of the passivation layer 30 and the light-emitting surface of the light-emitting unit 100 during deposition.

[0104] For example, the metal layer may be a Ti / Au / Ti stack or an AuGe / Ni composite layer.

[0105] The second step, as Figure 4 As shown, the metal layer is etched to remove the metal layer on the light-emitting surface of each light-emitting unit 100, and the metal layer is retained in the gap between adjacent light-emitting units 100 to form the connecting electrode 40.

[0106] Specifically, this may include: coating a photoresist mask on the light-emitting surface area of ​​the light-emitting unit 100 using a photolithography process, selectively removing the metal layer not covered by the mask using reactive ion etching (RIE), retaining the metal layer only in the gap between adjacent light-emitting units 100, forming a connection electrode 40 whose orthogonal projection is located outside the light-emitting surface, thus avoiding the metal from blocking the light emission.

[0107] like Figure 4 As shown, step S15 may include forming a transparent conductive layer 50 on the surface of the connecting electrode 40 away from the driving substrate 20 and on the light-emitting surface of each light-emitting unit 100.

[0108] For example, the transparent conductive layer 50 includes an ITO layer or an IZO layer.

[0109] Specifically, this may include: using magnetron sputtering to deposit a transparent conductive layer 50 on the surface of the connecting electrode 40 and the light-emitting surface of the light-emitting unit 100. By adjusting the oxygen partial pressure, high transmittance and low sheet resistance are ensured, uniformly covering the electrode and the light-emitting surface, which both conducts current and minimizes light absorption, providing a flat substrate for the subsequent light-harvesting structure 80.

[0110] like Figure 1 As shown, after step S15, the process may further include: fabricating a light-collecting structure 80 on the transparent conductive layer 50. A polymer (such as PMMA) is imprinted using photoresist as a template to form a curved surface, or periodic grooves are etched using RIE, so that the orthogonal projection of the structure covers the light-emitting unit 100, thereby achieving light refraction and convergence, reducing interface reflection loss, and improving light collimation and brightness.

[0111] For example, the light-collecting structure 80 can be made of PDMS, PMMA, or silicon oxide.

[0112] Polydimethylsiloxane (PDMS) is a flexible and bendable material; its light transmittance exceeds 90%, which reduces total reflection and makes it suitable for flexible Micro LED panels.

[0113] Among them, polymethyl methacrylate (PMMA) has a light transmittance of over 92%, good optical uniformity, moderate mechanical strength, good weather resistance, and is easy to mold, making it suitable for preparing light-collecting structures for large-area planar displays.

[0114] Among them, silicon dioxide has a light transmittance of over 95% and excellent thermal stability, and can be precisely processed into microstructures through etching, making it suitable for high-temperature processes and high-precision display requirements.

[0115] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. The data therein represents only illustrative examples. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A display panel, characterized in that, The display panel includes: multiple light-emitting units (100), a passivation layer (30), a connecting electrode (40), and a transparent conductive layer (50). Multiple light-emitting units (100) are arranged at intervals, the passivation layer (30) is located in the gap between adjacent light-emitting units (100), and the connecting electrode (40) is located on the surface of the passivation layer (30) and in the gap between adjacent light-emitting units (100). The light-emitting unit (100) includes a first semiconductor layer (11), a multi-quantum well layer (12), and a second semiconductor layer (13) stacked sequentially. The passivation layer (30) covers at least the sidewalls of the first semiconductor layer (11) and the sidewalls of the multi-quantum well layer (12). The connecting electrode (40) is connected to the sidewall of the second semiconductor layer (13). The transparent conductive layer (50) is located on the surface of the connecting electrode (40) away from the passivation layer (30) and on each of the light-emitting units (100).

2. The display panel according to claim 1, characterized in that, The passivation layer (30) includes a DBR layer.

3. The display panel according to claim 1, characterized in that, The connecting electrode (40) includes at least one of Au layer, Ge layer, AuGe layer, Ti layer, Ni layer and Al layer.

4. The display panel according to any one of claims 1 to 3, characterized in that, The display panel further includes a driving substrate (20) and a light-collecting structure (80). A plurality of light-emitting units (100) are arranged at intervals on the driving substrate (20). The light-collecting structure (80) corresponds to at least one of the light-emitting units (100). The light-collecting structure (80) is located on the surface of the transparent conductive layer (50) away from the driving substrate (20). The orthographic projection of the light-emitting unit (100) on the surface of the driving substrate (20) is located within the orthographic projection of the corresponding light-collecting structure (80) on the surface of the driving substrate (20).

5. The display panel according to claim 4, characterized in that, The display panel also includes bonding metal blocks (60) corresponding to each of the light-emitting units (100). The bonding metal blocks (60) are located on the surface of the driving substrate (20), and the light-emitting units (100) are located on the surface of the corresponding bonding metal blocks (60) away from the driving substrate (20). The orthographic projection of the light-emitting unit (100) on the surface of the driving substrate (20) lies within the orthographic projection of the corresponding bonding metal block (60) on the surface of the driving substrate (20).

6. The display panel according to any one of claims 1 to 3, characterized in that, The contact area between the connecting electrode (40) and the sidewall of the second semiconductor layer (13) is provided with a plurality of protrusions arranged at intervals.

7. A method for manufacturing a display panel, characterized in that, The preparation method includes: An epitaxial layer (10) is formed on a substrate (70); The epitaxial layer (10) is bonded to the driving substrate (20), and the substrate (70) is removed. The epitaxial layer (10) is patterned to form a plurality of spaced light-emitting units (100), wherein the light-emitting unit (100) includes a first semiconductor layer (11), a multi-quantum well layer (12) and a second semiconductor layer (13) sequentially stacked on the driving substrate (20). A passivation layer (30) is formed on the driving substrate (20) and in the gap between adjacent light-emitting units (100). A connection electrode (40) is formed on the surface of the passivation layer (30) away from the driving substrate (20) and in the gap between adjacent light-emitting units (100). The passivation layer (30) covers at least the sidewall of the first semiconductor layer (11) and the sidewall of the multiple quantum well layer (12). The connection electrode (40) is connected to the sidewall of the second semiconductor layer (13). A transparent conductive layer (50) is formed on the surface of the connecting electrode (40) away from the driving substrate (20) and on each of the light-emitting units (100).

8. The preparation method according to claim 7, characterized in that, Forming a passivation layer (30) on the driving substrate (20) and within the gap between adjacent light-emitting units (100) includes: An insulating material film covering each of the light-emitting units (100) is formed on the driving substrate (20); The insulating material film is etched to expose the light-emitting surface of each of the light-emitting units (100) away from the driving substrate (20), and a portion of the insulating material film is retained in the gap between adjacent light-emitting units (100) to form the passivation layer (30).

9. The preparation method according to claim 8, characterized in that, Etching the insulating material film includes: The insulating material film is etched to remove the insulating material film located on the light-emitting surface of each of the light-emitting units (100), and the insulating material film is etched to a height above the multiple quantum well layer (12) in the gap between adjacent light-emitting units (100).

10. The preparation method according to any one of claims 7 to 9, characterized in that, Forming a connection electrode (40) on the surface of the passivation layer (30) away from the driving substrate (20) and within the gap between adjacent light-emitting units (100) includes: A metal layer covering the light-emitting unit (100) is formed on the surface of the passivation layer (30) away from the driving substrate (20); The metal layer is etched to remove the metal layer on the light-emitting surface of each of the light-emitting units (100), and the metal layer is retained in the gap between adjacent light-emitting units (100) to form the connecting electrode (40).

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