Substrate structure and preparation method thereof, substrate mother board, chip package module and electronic device

Abstract

This application provides a substrate structure and its fabrication method, a substrate motherboard, a chip packaging module, and an electronic device. The substrate structure includes: a first substrate layer, including a first surface and a second surface perpendicular to the thickness direction, the first surface and the second surface being opposite to each other; the first substrate layer is embedded with a first target pad layer, at least one first circuit layer, and a first connection circuit layer that are electrically connected layer by layer, the first target pad layer being located on the first surface of the first substrate layer, and the first connection circuit layer being located on the second surface of the first substrate layer; a second substrate layer, adjacent to the second surface of the first substrate layer, and embedded with a second connection circuit layer, at least one second circuit layer, and a second target pad layer that are electrically connected layer by layer, the second connection circuit layer being electrically connected to the first connection circuit layer; the minimum linewidth of the circuit in the second circuit layer, the minimum linewidth of the circuit in the second connection circuit layer, and the minimum linewidth of the circuit in the first connection circuit layer are all greater than the minimum linewidth of the circuit in the first circuit layer.

Description

[0001] This application claims priority to PCT patent application filed on November 27, 2024, with application number "PCT / CN2024 / 134961" and patent title "Chip Packaging Method, Chip Packaging Module and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and in particular to a substrate structure and its preparation method, a substrate motherboard, a chip packaging module, and an electronic device. Background Technology

[0003] The development of chips is rapidly moving towards faster speeds, more functions, and smaller sizes. Increasing integration has become a crucial way to overcome performance bottlenecks. A key direction in current chip technology advancements is integration in packaging, one approach being to improve the integration density of the substrate structure. In 2.5D or 3D packaging technologies, one method for integrating chips from different process technologies is to use a substrate structure including a silicon interposer and a packaging substrate. The substrate structure uses a silicon interposer (TI) to enhance integration, serving as a connection layer between the chip and the packaging substrate. For example, in the CoWoS (Chip on Wafer on Substrate) technology, when using a substrate structure including a silicon interposer for chip packaging, the chip is typically soldered onto a circuit layer formed on one side of the silicon interposer. Through-silicon vias (TSVs) are then used to electrically connect the circuit layer on the silicon interposer to the circuit layer on the packaging substrate on the other side of the silicon interposer. However, due to the use of TSVs, these technologies have higher manufacturing costs and more complex manufacturing processes. Summary of the Invention

[0004] This application provides a substrate structure and its preparation method, a substrate motherboard, a chip packaging module, and an electronic device.

[0005] According to a first aspect of the embodiments of this application, a substrate structure is provided, comprising:

[0006] The first substrate layer includes a first surface and a second surface perpendicular to the thickness direction, with the first surface and the second surface of the first substrate layer facing each other; the first substrate layer is embedded with a first target pad layer, at least one first circuit layer and a first connection circuit layer that are electrically connected layer by layer, the first target pad layer being located on the first surface of the first substrate layer and the first connection circuit layer being located on the second surface of the first substrate layer.

[0007] The second substrate layer is adjacent to the second side of the first substrate layer and is embedded with a second connection line layer, at least one second line layer and a second target pad layer that are electrically connected layer by layer. The second connection line layer is electrically connected to the first connection line layer.

[0008] The substrate structure also satisfies at least one of the following conditions:

[0009] The minimum linewidth of the lines in the second line layer, the minimum linewidth of the lines in the second connecting line layer, and the minimum linewidth of the lines in the first connecting line layer are all greater than the minimum linewidth of the lines in the first line layer.

[0010] The minimum line spacing of the lines in the second line layer, the minimum line spacing of the lines in the second connecting line layer, and the minimum line spacing of the lines in the first connecting line layer are all greater than the minimum line spacing of the lines in the first line layer.

[0011] According to a second aspect of the embodiments of this application, a substrate motherboard is provided, comprising: a plurality of substrate structures as described in any one of the first aspects, wherein the plurality of substrate structures are arranged at intervals along a predetermined direction, or the plurality of substrate structures are arranged in a panel-level matrix.

[0012] According to a third aspect of the embodiments of this application, a chip packaging module is provided, comprising: a substrate structure as described in any one of the first aspects; and a chip electrically connected to a first target pad layer or a second target pad layer of the substrate structure.

[0013] According to a fourth aspect of the embodiments of this application, an electronic device is provided, including: a chip packaging module as described in the third aspect.

[0014] According to a fifth aspect of the embodiments of this application, a method for preparing a substrate structure is provided, comprising:

[0015] A wafer having a first substrate layer is obtained. The first substrate layer is embedded with a first target pad layer, at least one first circuit layer, and a first connection circuit layer that are electrically connected layer by layer. The first substrate layer includes a first surface and a second surface perpendicular to the thickness direction. The first surface and the second surface of the first substrate layer are opposite to each other. The first surface of the first substrate layer is in contact with the wafer. The first target pad layer is located on the first surface of the first substrate layer. The first connection circuit layer is located on the second surface of the first substrate layer and is exposed from the second surface of the first substrate layer.

[0016] On the second side of the first substrate layer, a second substrate layer is formed with a second connection line layer, at least one second line layer and a second target pad layer embedded in it, and the second connection line layer is electrically connected to the first connection line layer exposed from the second side of the first substrate layer, and the second target pad layer is exposed outward from the second substrate layer.

[0017] At least partially remove the wafer that is in contact with the first side of the first substrate layer, so that the first target pad layer is exposed outward from the first side of the first substrate layer to obtain a substrate structure;

[0018] The prepared substrate structure also satisfies at least one of the following conditions:

[0019] The minimum linewidth of the lines in the second line layer, the minimum linewidth of the lines in the second connecting line layer, and the minimum linewidth of the lines in the first connecting line layer are all greater than the minimum linewidth of the lines in the first line layer.

[0020] The minimum line spacing of the lines in the second line layer, the minimum line spacing of the lines in the second connecting line layer, and the minimum line spacing of the lines in the first connecting line layer are all greater than the minimum line spacing of the lines in the first line layer.

[0021] According to a sixth aspect of the embodiments of this application, a method for preparing a substrate structure is provided, comprising:

[0022] A second substrate layer is formed, which is embedded with a second connection line layer, at least one second line layer and a second target pad layer, wherein the second connection line layer and the second target pad layer are exposed outward from two surfaces of the second substrate layer perpendicular to the thickness direction;

[0023] On the side of the second substrate layer where the second interconnection layer is exposed, a first substrate layer is formed with a first interconnection layer, at least one first line layer and a first target pad layer embedded therein, so as to obtain a substrate structure, wherein the first interconnection layer is electrically connected to the second interconnection layer, and the first target pad layer is exposed outward from the first substrate layer.

[0024] The prepared substrate structure also satisfies at least one of the following conditions:

[0025] The minimum linewidth of the lines in the second line layer, the minimum linewidth of the lines in the second connecting line layer, and the minimum linewidth of the lines in the first connecting line layer are all greater than the minimum linewidth of the lines in the first line layer.

[0026] The minimum line spacing of the lines in the second line layer, the minimum line spacing of the lines in the second connecting line layer, and the minimum line spacing of the lines in the first connecting line layer are all greater than the minimum line spacing of the lines in the first line layer.

[0027] The substrate structure provided in this application embodiment has, on the one hand, a first substrate layer embedded with a first target pad layer, at least one first circuit layer, and a first connection circuit layer electrically connected layer by layer; and a second substrate layer embedded with a second connection circuit layer, at least one second circuit layer, and a second target pad layer electrically connected layer by layer. The second connection circuit layer is electrically connected to the first connection circuit layer. Furthermore, this substrate structure satisfies the following conditions: "the minimum linewidth of the circuit in the second circuit layer, the minimum linewidth of the circuit in the second connection circuit layer, and the minimum linewidth of the circuit in the first connection circuit layer are all greater than the minimum linewidth of the circuit in the first circuit layer," and "the minimum line spacing of the circuit in the second circuit layer and the minimum line width of the circuit in the second connection circuit layer are all greater than the minimum linewidth of the circuit in the first circuit layer." The minimum line spacing of the lines in the first interconnection layer is greater than at least one of the following: the line width and / or line spacing of the lines in the first interconnection layer is smaller, which facilitates the realization of high-density lines and interconnections and is beneficial to improving the integration of the substrate structure. On the other hand, since the substrate structure in this application does not rely on the through silicon via (TSV) process, the preparation cost is lower, the manufacturing process complexity is lower, and the yield is better. Furthermore, since the above-mentioned substrate structure has good integration and yield, when using the substrate structure to manufacture chip packaging modules with chips, the chip packaging modules can also have good integration and yield. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0029] Figure 1 A schematic diagram of the structure of a chip packaging module obtained by a chip packaging scheme in the related technology is shown.

[0030] Figure 2A Schematic diagrams of substrate structures for some examples of those in this application are shown.

[0031] Figure 2B Schematic diagrams of substrate structures for some other examples in this application are shown.

[0032] Figure 2C Some exemplary stacked structures in the form of a first line layer in the form of a metal stacked line are shown.

[0033] Figure 3A Schematic diagrams of some examples of chip packaging modules in this application are shown.

[0034] Figure 3B Schematic diagrams of chip packaging modules for some other examples in this application are shown.

[0035] Figure 4A A schematic diagram of a substrate motherboard for some examples of those in this application is shown.

[0036] Figure 4B Schematic diagrams of substrate motherboards for some other examples in this application are shown.

[0037] Figure 4C A schematic diagram of a substrate motherboard, representing some further examples of those in this application, is shown.

[0038] Figure 5 A schematic block diagram of the electronic device in this application is shown.

[0039] Figure 6 A flowchart of a method for fabricating a substrate structure according to this application is shown.

[0040] Figure 7 The following is a flowchart illustrating some of the alternative fabrication methods for the first substrate layer in this application.

[0041] Figure 8 The following is a flowchart illustrating some of the alternative fabrication methods for the second substrate layer in this application.

[0042] Figure 9 A flowchart of another method for fabricating a substrate structure according to this application is shown.

[0043] Figure 10 Flowcharts illustrating alternative fabrication methods for some other second substrate layers in this application are shown.

[0044] Figure 11 Flowcharts illustrating alternative fabrication methods for some of the first substrate layers in this application are shown.

[0045] Figures 12A to 12N Schematic diagrams illustrating the fabrication process of some example substrate structures are shown.

[0046] Figures 13A to 13N Schematic diagrams of the fabrication process for other examples of substrate structures are shown.

[0047] Explanation of reference numerals in the attached figures: 110, substrate structure; 1, first substrate layer; 10, wafer; 11, first target pad layer; 111, first target pad; 12, first circuit layer; 13, first connection circuit layer; 2, second substrate layer; 21, second connection circuit layer; 22, second circuit layer; 23, second target pad layer; 231, second target pad; 201, first substrate dielectric layer; 202, second substrate dielectric layer; 3, chip; 31, first seed metal layer; 32, second seed metal layer; 41, first enclosure layer; 411, first enclosure opening; 42, second enclosure layer; 421, second enclosure opening; 51, first carrier board; 52, second carrier board; 100, chip packaging module; 120, substrate motherboard; 200, electronic device. Detailed Implementation

[0048] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0049] Chip development is rapidly advancing towards faster speeds, more functions, and smaller sizes. With the advancement of microelectronics technology, increasing integration has become a crucial way to overcome chip performance bottlenecks. A significant direction for current chip technology advancement is integration in packaging, one approach being to increase the integration density of the substrate structure. However, there is still room for further improvement in the integration density of current substrate structures. Furthermore, some related technologies, while aiming to increase integration density, result in higher manufacturing costs and greater process complexity.

[0050] For example, to facilitate understanding of the technical problems in the background art, Figure 1 This diagram illustrates a substrate structure and a schematic diagram of a chip packaging module in a related technology chip packaging scheme. Figure 1 An example can be a stacked structure obtained using the CoWoS technology. For example... Figure 1As shown, chips a and b are connected to a circuit layer formed on the upper surface of a silicon interposer in a substrate structure via solder. This circuit layer includes interconnect metal lines of various sizes fabricated using wafer-level manufacturing processes. The final interconnection is then electrically connected to the lower surface of the silicon interposer via through-silicon vias (TSVs) within the silicon interposer, and finally interconnected with the circuitry of the substrate structure's packaging substrate via solder. However, due to the characteristics of TSV technology in such a silicon interposer in the substrate structure, and because the aspect ratio of TSVs generally exceeds 10:1, their manufacturing technology is extremely difficult, resulting in high manufacturing costs and high process complexity.

[0051] However, including but not limited to Figure 1 The CoWoS technology uses a silicon interposer as its substrate structure. Due to the characteristics of through-silicon vias (TSVs), the manufacturing cost is high and the process complexity is high. Furthermore, while CoWoS technology can utilize the silicon interposer to achieve high-density metal interconnects, and this process is compatible with the wafer manufacturing process, the chip is integrated with the silicon interposer of the substrate structure in CoWoS, and then shipped as a module to downstream packaging plants for soldering to the packaging substrate. If damage occurs in this module due to process deviations in the silicon interposer (such as defects in the TSVs) or open / short circuits in the interconnects, the chip will be scrapped, further increasing the overall process cost. Moreover, due to this process architecture, it is difficult to ensure the yield of the substrate structure and the chip packaging module, thus significantly increasing the cost of packaging integration.

[0052] In view of this, this application provides a substrate structure and its fabrication method to at least partially improve the above-mentioned problems. This technical solution can effectively improve the integration density of the substrate structure, reduce the fabrication cost and process complexity of the substrate structure, and effectively improve the integration density and yield of the substrate structure and the chip packaging module using the substrate structure.

[0053] The specific implementation of the technical solutions of the embodiments of this application is described below with reference to the accompanying drawings. It should be noted that, for ease of illustration, the structures in the various drawings are not necessarily drawn to scale. The various drawings are not intended to limit the embodiments of this application.

[0054] According to the first aspect of the embodiments of this application, referring to Figure 2A , Figure 2BAs shown, a substrate structure 110 is provided, including a first substrate layer 1 and a second substrate layer 2. The first substrate layer 1 includes a first surface and a second surface perpendicular to its thickness direction, with the first surface and the second surface facing each other. The first substrate layer 1 is embedded with a first target pad layer 11, at least one first circuit layer 12, and a first connection circuit layer 13, which are electrically connected layer by layer. The first target pad layer 11 is located on the first surface of the first substrate layer 1, and the first connection circuit layer 13 is located on the second surface of the first substrate layer 1. The second substrate layer 2 is adjacent to the second surface of the first substrate layer 1 and is embedded with a second connection circuit layer 21, at least one second circuit layer 22, and a second target pad layer 23, which are electrically connected layer by layer. The second connection circuit layer 21 is electrically connected to the first connection layer 13.

[0055] The substrate structure 110 also satisfies at least one of the following conditions: the minimum linewidth of the lines in the second line layer 22, the minimum linewidth of the lines in the second connection line layer 21, and the minimum linewidth of the lines in the first connection line layer 13 are all greater than the minimum linewidth of the lines in the first line layer 12; the minimum line spacing of the lines in the second line layer 22, the minimum line spacing of the lines in the second connection line layer 21, and the minimum line spacing of the lines in the first connection line layer 13 are all greater than the minimum line spacing of the lines in the first line layer 12.

[0056] Based on this, the substrate structure 110 provided in this solution has, on the one hand, a first substrate layer 1 embedded with a first target pad layer 11, at least one first circuit layer 12 and a first connection circuit layer 13 electrically connected layer by layer, and a second substrate layer 2 embedded with a second connection circuit layer 21, at least one second circuit layer 22 and a second target pad layer 23 electrically connected layer by layer. The second connection circuit layer 21 is electrically connected to the first connection circuit layer 13, and the substrate structure 110 satisfies the following conditions: "the minimum linewidth of the lines in the second circuit layer 22, the minimum linewidth of the lines in the second connection circuit layer 21, and the minimum linewidth of the lines in the first connection circuit layer 13 are all greater than the minimum linewidth of the lines in the first circuit layer 12", and "the minimum line spacing of the lines in the second circuit layer 22 and the minimum line spacing of the lines in the second connection circuit layer 21 are all greater than the minimum linewidth of the lines in the first circuit layer 12", and "the minimum line spacing of the lines in the second circuit layer 22 and the minimum line spacing of the lines in the second connection circuit layer 21 are all greater than the minimum linewidth of the lines in the first circuit layer 12", and "the minimum line spacing of the lines in the second circuit layer 21 and the minimum line spacing of the lines in the second connection circuit layer 13 ... spacing of the lines in the first circuit layer 12", and "the minimum line spacing of the lines in the second circuit layer 21 and the minimum line spacing of the lines in the second connection circuit layer 12 are all greater than the minimum line spacing of the lines in the first circuit layer 13". The minimum line spacing of the lines in layer 11 and the minimum line spacing of the lines in the first interconnection layer 13 are both greater than at least one of the minimum line spacing of the lines in the first line layer 12. This results in a smaller line width and / or line spacing of the lines in the first line layer 12, which facilitates the realization of high-density lines and interconnections and is beneficial to improving the integration of the substrate structure 110. On the other hand, since the substrate structure 110 in this application does not rely on the through-silicon via (TSV) process, the manufacturing cost is lower, the manufacturing process complexity is lower, and the yield can be better. Furthermore, since the substrate structure 110 has good integration and yield, when using the substrate structure 110 to fabricate a chip packaging module with a chip, the chip packaging module can also have good integration and yield.

[0057] Furthermore, traditional solutions are costly, have complex packaging structures and high stress, and have high technical barriers to entry, which are not conducive to promotion. In contrast, the technical solutions of this application are low-cost, simple in structure, highly flexible in application, easy to promote and use, and have a lower barrier to entry.

[0058] Optionally, the first target pad layer 11 can be used to connect chips (such as...). Figure 3A , Figure 3B The chip 3 in the chip packaging module 100 shown is adapted to meet the electrical connection requirements between the chip and the substrate structure 110, so as to facilitate the fabrication of the chip packaging module 100. Optionally, the first target pad layer 11 can be electrically connected to the chip by means including but not limited to solder, conductive adhesive, bonding wires, etc.

[0059] It should be understood that the type of chip 3 is not limited in this application, and it can be any chip. For example, it can include, but is not limited to, processor chips (such as, but not limited to, GPU (Graphics Processing Unit), CPU (Central Processing Unit), MCU (Micro Control Unit), DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array), etc.), memory chips (such as, but not limited to, HBM (High Bandwidth Memory) chips, ROM (Read-Only Memory) chips, RAM (Random Access Memory) chips, FLASH memory chips, EEPROM (Electrically Erasable Programmable Read-Only Memory) chips, EPROM (Erasable Programmable Read-Only Memory) chips), system-on-a-chip (also known as system on chip, or SoC), etc.), or it can be other analog circuit chips or digital circuit chips. This application does not limit the number of chips 3; one or more chips 3 may be electrically connected to the first target pad layer 11. For example... Figure 3A , Figure 3B The example shown has a chip 3 electrically connected to the first target pad layer 11.

[0060] Optionally, the second target pad layer 23 can be used to connect external circuit structures, which can be circuit boards (including but not limited to flexible printed circuits (FPCs), printed circuit boards (PCBs)), other chips, modules, electronic devices, or even electrical interconnects, etc., to meet the needs of wiring between the substrate structure 110 and other external circuit structures, so that the chip packaging module made using the substrate structure 110 can be used. Optionally, the second target pad layer 23 can be electrically connected to the external circuit structure through methods including but not limited to solder, conductive adhesive, bonding wires, etc.

[0061] Optionally, such as Figure 2A , Figure 2BAs shown, the first target pad layer 11 may include a plurality of first target pads 111. The plurality of first target pads 111 can be used to achieve electrical connections with different pads of the chip 3. It should be noted that the number of first target pads 111 can be designed as needed, and the shape and size of each pair of the plurality of first target pads 111 can be the same or different, without limitation. Optionally, the plurality of first target pads 111 can be used to achieve electrical connections with different pads of the chip 3. Optionally, as... Figure 2A , Figure 2B As shown, the second target pad layer 23 may include a plurality of second target pads 231. Optionally, the plurality of second target pads 231 may be used to achieve electrical connection with different pads of other external circuit structures. It should be noted that the number of second target pads 231 can be designed as needed, and the shape and size of each pair of the plurality of second target pads 231 may be the same or different, which is not limited here.

[0062] In other feasible solutions, the second target pad layer 23 can be used to connect the chip, and the first target pad layer 11 can be used to connect the circuit board and other external circuit structures, depending on the requirements. There is no single limitation here.

[0063] Optionally, such as Figure 2A , Figure 2B As shown, the first target pad layer 11 and the second target pad layer 23 in this application are located on two opposite sides of the substrate structure 110 in the thickness direction, so as to meet the requirement of double-sided wiring of the substrate structure 110 (that is, the circuits packaged by the first substrate layer 1 and the second substrate layer 2 can be electrically connected to the chip 3 and other circuit structures respectively), so as to facilitate the use of the substrate structure 110 and the chip packaging module 100 made therefrom.

[0064] It should be understood that, in combination Figure 2A , Figure 2B Substrate structure 110 and Figure 3A , Figure 3B In the chip packaging module 100, it is understood that, optionally, in the first substrate layer 1 and the second substrate layer 2 obtained in this application, the first substrate layer 1 can be regarded as a silicon interposer, and does not need to rely on through-silicon via (TSV) technology; the second substrate layer 2 can be regarded as a packaging substrate. Clearly, this solution does not involve TSVs, and... Figure 1 The CoWoS technology solution shown has significant differences in chip packaging process and product structure.

[0065] The first substrate layer 1 can be formed using any suitable material. Optionally, the first substrate layer 1 can be formed using a material suitable for subsequent fabrication of circuits using wafer-level, panel-level, or strip-level manufacturing processes. In some optional embodiments, the material of the first substrate layer 1 can be SiO2, i.e., silicon dioxide. That is, in some optional embodiments, the first substrate layer 1 is a SiO2 layer. For example, SiO2 can be grown on the wafer 10 using at least one of the following processes, including but not limited to PECVD (Plasma-Enhanced Chemical Vapor Deposition), HDPCVD (High-Density Plasma Chemical Vapor Deposition), and LPCVD (Low-Pressure Chemical Vapor Deposition), to form the first substrate layer 1 in the form of a SiO2 layer.

[0066] It should be understood that the first substrate layer 1, which adopts the form of a SiO2 layer, can, on the one hand, serve as an insulating layer to effectively meet some insulation requirements between the subsequently formed layer structures (i.e., the first target pad layer 11, at least one first line layer 12, and the first connection line layer 13); on the other hand, by adopting the first substrate layer 1 in the form of a SiO2 layer, it is easier to make the line width and / or line spacing of the lines in the first line layer 12 smaller when forming it, thereby improving the integration of the substrate structure 110 and further improving the integration of the chip packaging module 100 made using the substrate structure 110.

[0067] The second substrate layer 2 can be formed using any suitable material. Optionally, the second substrate layer 2 can be an organic insulating layer to meet insulation requirements. For example, the second substrate layer 2 can be fabricated using organic insulating materials using processes including but not limited to coating, printing, bonding, and molding.

[0068] The second substrate layer 2 can be made of any organic insulating material. For example, the organic insulating layer is made of at least one of polyimide (PI) materials, epoxy resin materials, and silane materials. Using at least one of the above organic insulating materials can effectively improve the insulation performance of the second substrate layer 2. In some embodiments, the epoxy resin material can be selected as epoxy molding compound (EMC). EMC materials have advantages such as low cost, convenient molding operation, high production efficiency, good high temperature resistance, good electrical insulation, and good heat dissipation performance, which can effectively meet the molding performance requirements. Furthermore, EMC materials can also meet the requirements for fabricating circuits.

[0069] It is understood that the electrical connection between the first target pad layer 11 and the first circuit layer 12 can mean that at least a portion of the first target pads 111 in the first target pad layer 11 are electrically connected to at least a portion of the circuits in the first circuit layer 12. The electrical connection between the first circuit layers 12 and 13 can mean that at least a portion of the circuits in the first circuit layer 12 are electrically connected to each other. The electrical connection between the first circuit layer 12 and the first connection layer 13 can mean that at least a portion of the circuits in the first circuit layer 12 are electrically connected to at least a portion of the circuits in the first connection layer 13. The electrical connection between the first connection layer 13 and the second connection layer 21 can mean that at least a portion of the circuits in the first connection layer 13 are electrically connected to at least a portion of the circuits in the second connection layer 21. The electrical connection between the second connection layer 21 and the second circuit layer 22 can mean that at least a portion of the circuits in the second connection layer 21 are electrically connected to at least a portion of the circuits in the second circuit layer 22. The second circuit layer 22 is electrically connected to the second circuit layer 22, which can mean that at least a portion of the circuits in the second circuit layer 22 are electrically connected to each other. The second circuit layer 22 is electrically connected to the second target pad layer 23, which can mean that at least a portion of the circuits in the second circuit layer 22 are electrically connected to at least a portion of the second target pads 231 in the second target pad layer 23.

[0070] One or more first circuit layers 12 can be embedded in the first substrate layer 1. Optionally, the first substrate layer 1 can be embedded with 1 to 10 first circuit layers 12 to better meet the requirements of circuit connection and signal transmission of the substrate structure 110. Of course, more first circuit layers 12 can also be provided as needed. For example Figure 2A , Figure 2B In the example, the first substrate layer 1 is embedded with two first circuit layers 12.

[0071] It should be understood that when there are multiple first line layers 12, the line structures between each first line layer 12 can be the same or roughly the same, or they can all be completely different. This application does not restrict the line structure in each first line layer 12, and it can be designed according to actual needs.

[0072] One or more second circuit layers 22 can be embedded in the second substrate layer 2. Optionally, the second substrate layer 2 can have 1 to 10 second circuit layers 22 embedded to better meet the requirements of circuit connection and signal transmission of the substrate structure 110. Of course, more layers of second circuit layers 22 can also be provided as needed. For example Figure 2A , Figure 2B In the example, the second substrate layer 2 is embedded with three second circuit layers 22.

[0073] It should be understood that when there are multiple second line layers 22, the line structures between each second line layer 22 can be the same or roughly the same, or they can all be completely different. This application does not restrict the line structure in each second line layer 22, and it can be designed according to actual needs.

[0074] This application does not specifically limit the line width of the lines in each line layer; some examples are given below for illustration.

[0075] In some alternative embodiments, the linewidth of the lines in the first circuit layer 12 is less than or equal to 2 μm. Such a linewidth range is beneficial for achieving a higher line density in the first circuit layer 12, facilitating the implementation of high-density lines and interconnections, and improving the integration density of the substrate structure 110.

[0076] Preferably, the linewidth of the lines in the first circuit layer 12 is 0.2µm to 2µm. This preferred linewidth range is beneficial for achieving a higher line density in the first circuit layer 12, facilitating the implementation of high-density circuits and interconnections, improving the integration of the substrate structure 110, and making fabrication relatively easier. Within this preferred range, the linewidth of the lines in the first circuit layer 12 can be selected as needed. For example, 0.2µm, 0.3µm, 0.4µm, 0.5µm, 0.6µm, 0.7µm, 0.8µm, 0.9µm, 1.0µm, 1.1µm, 1.2µm, 1.3µm, 1.4µm, 1.5µm, 1.6µm, 1.7µm, 1.8µm, 1.9µm, 2.0µm, etc., can be selected.

[0077] In some optional embodiments, the linewidth of the lines in the first interconnect layer 13 is 2µm to 8µm. A linewidth within this range is neither too wide nor too narrow, facilitating the connection and signal transmission requirements of the substrate structure 110, and also making the fabrication of the lines relatively convenient. This first interconnect layer 13 also facilitates connection with the second interconnect layer 21 embedded in the second substrate layer 2. Within this optional range, the linewidth of the lines in the first interconnect layer 13 can be selected as needed; for example, 2.0µm, 2.5µm, 3.0µm, 3.5µm, 4.0µm, 4.5µm, 5.0µm, 5.5µm, 6.0µm, 6.5µm, 7.0µm, 7.5µm, 8.0µm, etc., can be selected.

[0078] In some optional embodiments, the linewidth of the lines in the second circuit layer 22 is 2µm to 8µm. A linewidth within this range is neither too wide nor too narrow, facilitating the connection and signal transmission requirements of the substrate structure 110, and also making the fabrication of the lines relatively convenient. Within this optional range, the linewidth of the lines in the second circuit layer 22 can be selected as needed; for example, 2.0µm, 2.5µm, 3.0µm, 3.5µm, 4.0µm, 4.5µm, 5.0µm, 5.5µm, 6.0µm, 6.5µm, 7.0µm, 7.5µm, 8.0µm, etc., can be selected.

[0079] In some optional embodiments, the linewidth of the lines in the second connection layer 21 is 2µm to 8µm. A linewidth within this range is neither too wide nor too narrow, facilitating the connection and signal transmission requirements of the substrate structure 110, and also making the fabrication of the lines relatively convenient. This second connection layer 21 also facilitates connection with the first connection layer 13 embedded in the first substrate layer 1. Within this optional range, the linewidth of the lines in the second connection layer 21 can be selected as needed; for example, 2.0µm, 2.5µm, 3.0µm, 3.5µm, 4.0µm, 4.5µm, 5.0µm, 5.5µm, 6.0µm, 6.5µm, 7.0µm, 7.5µm, 8.0µm, etc., can be selected.

[0080] This application does not specifically limit the line spacing in each line layer; some examples are given below for illustration.

[0081] In some alternative embodiments, the line spacing in the first circuit layer 12 is less than or equal to 2 μm. Such a line spacing range is beneficial for achieving a higher circuit density in the first circuit layer 12, facilitating the implementation of high-density circuits and interconnections, and improving the integration density of the substrate structure 110.

[0082] Preferably, the line spacing of the lines in the first circuit layer 12 is 0.2µm to 2µm. This preferred line spacing range is beneficial for achieving a higher circuit density in the first circuit layer 12, facilitating the realization of high-density circuits and interconnections, improving the integration of the substrate structure 110, and making fabrication relatively easier. Within this preferred range, the line spacing of the lines in the first circuit layer 12 can be selected as needed. For example, 0.2µm, 0.3µm, 0.4µm, 0.5µm, 0.6µm, 0.7µm, 0.8µm, 0.9µm, 1.0µm, 1.1µm, 1.2µm, 1.3µm, 1.4µm, 1.5µm, 1.6µm, 1.7µm, 1.8µm, 1.9µm, 2.0µm, etc., can be selected.

[0083] In some optional embodiments, the line spacing of the lines in the first connection layer 13 is 2µm to 8µm. This line spacing range is neither too wide nor too narrow, facilitating the connection and signal transmission requirements of the substrate structure 110, and also making the lines relatively easy to fabricate. Within this optional range, the line spacing of the lines in the second connection layer 21 can be arbitrarily selected as needed. For example, 2.0µm, 2.5µm, 3.0µm, 3.5µm, 4.0µm, 4.5µm, 5.0µm, 5.5µm, 6.0µm, 6.5µm, 7.0µm, 7.5µm, 8.0µm, etc., can be selected.

[0084] In some optional embodiments, the line spacing of the lines in the second circuit layer 22 is 2µm to 8µm. A line spacing within this range is neither too wide nor too narrow, facilitating the connection and signal transmission requirements of the substrate structure 110, and also making the lines relatively easy to fabricate. Within this optional range, the line spacing of the lines in the second circuit layer 22 can be selected as needed; for example, 2.0µm, 2.5µm, 3.0µm, 3.5µm, 4.0µm, 4.5µm, 5.0µm, 5.5µm, 6.0µm, 6.5µm, 7.0µm, 7.5µm, 8.0µm, etc., can be selected.

[0085] In some optional embodiments, the line spacing of the lines in the second connection layer 21 is 2µm to 8µm. A line spacing within this range is neither too wide nor too narrow, facilitating the connection and signal transmission requirements of the substrate structure 110, and also making the lines relatively easy to fabricate. Within this optional range, the line spacing of the lines in the second connection layer 21 can be selected as needed; for example, 2.0µm, 2.5µm, 3.0µm, 3.5µm, 4.0µm, 4.5µm, 5.0µm, 5.5µm, 6.0µm, 6.5µm, 7.0µm, 7.5µm, 8.0µm, etc., can be selected.

[0086] Optionally, the first circuit layer 12 can be fabricated using a wafer-level process to facilitate the fabrication of a smaller linewidth and / or line spacing (e.g., a linewidth of 0.2µm to 2µm, and / or a line spacing of 0.2µm to 2µm), thereby achieving a higher circuit density in the first circuit layer 12, realizing high-density circuitry and interconnections, and improving the integration of the substrate structure 110. Alternatively, the first circuit layer 12 can also be fabricated using panel-level or strip-level processes, whichever meets the requirements.

[0087] In this embodiment of the application, at least one of the first line layer 12, the first connecting line layer 13, the second connecting line layer 21, and the second line layer 22 can be implemented with any structure. For example, it can be implemented as a single-layer metal line or a multi-layer metal stacked line, etc.

[0088] In some optional embodiments, the lines in at least one of the first line layer 12, the first connection line layer 13, the second connection line layer 21, and the second line layer 22 include electroplated metal lines. It should be understood that electroplated metal lines are easy to manufacture and have good conductivity and signal integrity. The surface flatness of electroplated metal lines is high, which can effectively reduce impedance mismatch problems in signal transmission.

[0089] In some optional embodiments, at least one of the first line layer 12, the first connecting line layer 13, the second connecting line layer 21, and the second line layer 22 includes a metal multilayer circuit, and at least one metal layer of the metal multilayer circuit is an electroplated metal layer. It should be understood that such a circuit structure is easy to manufacture and has good conductivity and signal integrity. The surface flatness of the electroplated metal circuit is high, which can effectively reduce impedance mismatch problems in signal transmission.

[0090] Optionally, when using a metal multilayer circuit including electroplated metal layers, at least one of the metal layers can be a seed metal layer for electroplating. During the circuit fabrication stage, the seed metal layer can be used as the cathode (electroplated substrate) for electroplating. Based on the principle of electrolysis, electroplating metal is applied to the seed metal layer to form the electroplated metal layer, thereby facilitating the fabrication of the metal multilayer circuit. For example, refer to... Figure 2C As shown, Figure 2C The diagram illustrates some exemplary stacked structures of a first circuit layer 12 in the form of a metal stacked circuit, which may be divided into an electroplated metal layer and a seed metal layer. Other circuit layers can also be understood with reference to the first circuit layer 12.

[0091] Metal stacked circuits can be stacked circuits of the same type of metal or stacked circuits of different types of metals; no limitation is made here.

[0092] Optionally, the metal material of any layer in the metal multilayer circuit may include, but is not limited to, at least one of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, or an alloy of at least two of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead. Alternatively, other feasible metal materials may be used, as long as they meet the requirements.

[0093] Optionally, the material of the electroplated metal layer may include at least one of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, or an alloy of at least two of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead. Alternatively, other feasible metal materials may be used, as long as they meet the requirements.

[0094] In some alternative embodiments, the metal stacked circuit includes a first metal layer and a second metal layer, the first and second metal layers being made of different materials; and at least a portion of the second metal layer is an electroplated metal layer, the thickness of which is greater than the thickness of the first metal layer. It should be understood that such a circuit structure is easy to manufacture and has good conductivity and signal integrity. The high surface flatness of the electroplated metal circuit effectively reduces impedance mismatch problems in signal transmission. Furthermore, the fact that the thickness of the first metal layer is less than the thickness of the electroplated metal layer of the second metal layer also helps to reduce circuit costs.

[0095] The thickness of the first metal layer and the thickness of the second metal layer can be set as needed, without any specific limitations here.

[0096] Optionally, the second metal layer is a copper layer and the first metal layer is a titanium layer. It should be understood that this optional metal stack-up circuit has better performance, better conductivity and signal integrity, and the thickness of the titanium layer is less than that of the copper layer, which helps to reduce circuit cost and avoid peeling.

[0097] For example, in some cases, such metal stacked circuits can be obtained by using a titanium layer as the seed metal layer for electroplating and electroplating copper on the titanium layer as the electroplating metal; in other cases, a titanium-copper metal stack can be obtained by using a titanium-copper metal stack as the seed metal layer for electroplating and electroplating copper on the copper layer in the seed metal layer as the electroplating metal material.

[0098] For example, you can refer to Figure 2C As shown, Figure 2C The diagram illustrates some exemplary stacked structures of a first circuit layer 12 in the form of a metal stacked circuit. This first circuit layer 12 can be divided into an electroplated metal layer and a seed metal layer. In some examples, the seed metal layer can be a titanium-copper stack, the electroplated metal layer can be a copper layer, the titanium layer in the seed metal layer can be the first metal layer, and the copper layer and the electroplated metal layer in the seed metal layer can be the second metal layers. Other circuit layers can also be understood with reference to the first circuit layer 12.

[0099] For example, you can refer to Figure 2C As shown, Figure 2CThe diagram illustrates some exemplary stacked structures of a first circuit layer 12 in the form of a metal stacked circuit. This first circuit layer 12 can be divided into an electroplated metal layer and a seed metal layer. In some examples, the seed metal layer can be a copper layer, the electroplated metal layer can be a copper layer, the seed metal layer (copper layer) can be the first metal layer, and the electroplated metal layer (copper layer) can be the second metal layer. Other circuit layers can also be understood with reference to the first circuit layer 12.

[0100] In some optional embodiments, at least one of the first line layer 12, the first connecting line layer 13, the second connecting line layer 21, and the second line layer 22 is a single-layer metal line, and at least a portion of the single-layer metal line is electroplated metal. It should be understood that such a line structure is easy to manufacture and has good conductivity and signal integrity. The high surface flatness of the electroplated metal line can effectively reduce impedance mismatch problems in signal transmission.

[0101] Optionally, one implementation where at least a portion of the aforementioned single-layer metal circuit is electroplated metal is that the seed metal layer and the electroplating metal material are the same metal. In this case, since the seed metal layer and the electroplating metal layer are the same metal, they are difficult to distinguish in some situations, and therefore the resulting circuit can also be considered a single-layer metal circuit. For example, in some cases, a copper layer can be used as the seed metal layer for electroplating, and copper can be used as the electroplating metal material on the copper layer that serves as the seed metal layer to obtain the circuit.

[0102] In some optional embodiments, at least one of the first target pad layer 11 and the second target pad layer 23 may also include an electroplated metal layer, such as a metal stack (e.g., a titanium-copper metal stack) or a single metal layer, and may adopt optional structures as described above for other circuits, which will not be repeated here.

[0103] It should be understood that the preparation of the substrate structure 110 of the first aspect of this application can be understood with reference to the preparation methods in the various optional embodiments below.

[0104] According to a second aspect of the embodiments of this application, referring to... Figure 4A , Figure 4B , Figure 4C As shown, a substrate motherboard 120 is provided, comprising: a plurality of substrate structures 110 as described in any one of the first aspects, wherein the plurality of substrate structures 110 are arranged in a strip-like spaced manner along a predetermined direction (see reference). Figure 4A (Understanding), or, multiple substrate structures 110 are arranged in a panel-level matrix (refer to...). Figure 4B (Understanding), or, multiple substrate structures 110 are distributed within a predetermined circumference (refer to...). Figure 4C understand).

[0105] Therefore, this application provides a substrate motherboard 120, which may include a plurality of substrate structures 110 of the first aspect, so as to obtain a plurality of substrate structures 110 in the future, and the plurality of substrate structures 110 and the substrate motherboard 120 can meet the requirements of different packaging processes.

[0106] For example, some of the substrate motherboards 120 provided in this application can be referred to Figure 4A It is understood that the substrate motherboard 120 can be elongated, and multiple substrate structures 110 are arranged in a strip-like interval along a predetermined direction, so that the multiple substrate structures 110 and the substrate motherboard 120 can meet the requirements of strip-level packaging technology. Therefore, such a substrate motherboard 120 can be fabricated using strip-level packaging technology to prepare the multiple substrate structures 110 therein.

[0107] For example, in some other substrate motherboards 120 provided in this application, reference can be made to Figure 4B It is understood that the substrate motherboard 120 can be panel-shaped (e.g., rectangular), and the multiple substrate structures 110 are arranged in a panel-level matrix, so that the multiple substrate structures 110 and the substrate motherboard 120 can meet the requirements of panel-level packaging technology. Therefore, such a substrate motherboard 120 can be fabricated using panel-level packaging technology to prepare the multiple substrate structures 110.

[0108] For example, in some of the substrate motherboards 120 provided in this application, reference can be made to Figure 4C It is understood that the substrate motherboard 120 can be circular, with multiple substrate structures 110 distributed around a predetermined circumference. Optionally, the predetermined circumference can be the circumference of a wafer of the substrate motherboard 120, so that the multiple substrate structures 110 and the substrate motherboard 120 can meet the requirements of wafer-level packaging technology. Therefore, such a substrate motherboard 120 can be fabricated using wafer-level packaging technology to prepare the multiple substrate structures 110 therein.

[0109] It should be understood that the specific layout and principles of strip-level, panel-level, and wafer-level packaging processes can be understood by referring to relevant technologies, and will not be elaborated here.

[0110] According to a third aspect of the embodiments of this application, referring to Figure 3A , Figure 3B As shown, a chip packaging module 100 is provided, including: a substrate structure 110 as provided in the first aspect, and a chip 3, wherein the chip 3 is electrically connected to a first target pad layer 11 or a second target pad layer 23 of the substrate structure 110.

[0111] Optionally, the chip 3 can be electrically connected to the first target pad layer 11 or the second target pad layer 23 by means including but not limited to solder, conductive adhesive, bonding wires, etc.

[0112] Optionally, as Figure 3A , Figure 3B For example, chip 3 can be electrically connected to the first target pad layer 11 of substrate structure 110 via solder. Chip 3 may include multiple chip pads, and the first target pad layer 11 may include multiple first target pads 111. The multiple chip pads can be electrically connected to the multiple first target pads 111. When the first target pads 111 are connected to chip 3, the second target pad layer 23 can be used to connect other external circuit structures. These external circuit structures can be circuit boards (including but not limited to FPC circuit boards, PCB circuit boards), other chips, modules, electronic devices, and even electrical connection lines, etc., so that the chip packaging module 100 can be used.

[0113] It should be understood that since the chip packaging module 100 in this application uses the substrate structure 110 provided in the first aspect, which has high integration, low manufacturing cost, low process complexity, and good yield, the chip packaging module 100 can also have good integration, low manufacturing cost, low process complexity, and good yield.

[0114] In some alternative embodiments, refer to Figure 3A , Figure 3B As shown, the chip packaging module 100 also includes a protective layer 5 covering at least a portion of the chip 3.

[0115] Based on this, the protective layer 5 can physically protect at least part of the chip 3 and the substrate structure 110 to achieve electrical and environmental isolation. While providing electrical insulation, it also isolates the chip 3 from the influence of external water, oxygen and other adverse environmental factors, which is conducive to the normal operation of the chip 3, effectively ensures its lifespan, effectively improves the reliability of the packaged chip module 100, and improves the performance of the chip 3 and the packaged chip module 100.

[0116] Optionally, refer to Figure 3A , Figure 3B As shown, the protective layer 5 can completely cover the chip 3. Obviously, this provides more comprehensive protection for the chip 3 and better improves the performance of the chip 3 and the chip packaging module 100.

[0117] The protective layer 5 can be made of any material, such as an epoxy resin molding compound, an inorganic oxide system, or an organic polyimide (PI) material. Alternatively, other materials can be used if necessary.

[0118] According to the fourth aspect of the embodiments of this application, referring to Figure 5 As shown, an electronic device 200 is provided, including: the chip packaging module 100 provided in the third aspect above.

[0119] Optionally, the electronic device 200 can be any electronic device, including but not limited to mobile phones, computers, etc. It should be understood that the above are merely illustrative applications and do not constitute any limitation on the embodiments of this application.

[0120] According to a fifth aspect of the embodiments of this application, a method for fabricating a substrate structure is provided. This fabrication method can fabricate the substrate structure 110 described in the first aspect above. For example... Figure 6 The flowchart shown illustrates that the preparation method includes the following steps S102, S104, and S106, specifically:

[0121] S102: A first substrate layer is formed on a wafer. The first substrate layer is embedded with a first target pad layer, at least one first circuit layer, and a first connection circuit layer that are electrically connected layer by layer. The first substrate layer includes a first surface and a second surface perpendicular to the thickness direction. The first surface and the second surface of the first substrate layer are opposite to each other. The first surface of the first substrate layer is in contact with the wafer. The first target pad layer is located on the first surface of the first substrate layer. The first connection circuit layer is located on the second surface of the first substrate layer and is exposed from the second surface of the first substrate layer.

[0122] S104: On the second side of the first substrate layer, a second substrate layer is formed with a second connection line layer, at least one second line layer and a second target pad layer embedded therein, and the second connection line layer is electrically connected to the first connection line layer exposed from the second side of the first substrate layer, and the second target pad layer is exposed outward from the second substrate layer.

[0123] S106: At least partially remove the wafer that is in contact with the first surface of the first substrate layer, so that the first target pad layer is exposed outward from the first surface of the first substrate layer to obtain a substrate structure.

[0124] The prepared substrate structure 110 also satisfies at least one of the following conditions: the minimum linewidth of the lines in the second line layer 22, the minimum linewidth of the lines in the second connection line layer 21, and the minimum linewidth of the lines in the first connection line layer 13 are all greater than the minimum linewidth of the lines in the first line layer 12; the minimum line spacing of the lines in the second line layer 22, the minimum line spacing of the lines in the second connection line layer 21, and the minimum line spacing of the lines in the first connection line layer 13 are all greater than the minimum line spacing of the lines in the first line layer 12.

[0125] It should be understood that, through the preparation method of steps S102 to S106 described above in this application, a substrate structure 110 including a first substrate layer 1 and a second substrate layer 2 can be effectively prepared. The first substrate layer 1 is embedded with a first target pad layer 11, at least one first circuit layer 12, and a first connection line layer 13, which are electrically connected layer by layer. The second substrate layer 2 is embedded with a second connection line layer 21, at least one second circuit layer 22, and a second target pad layer 23, which are electrically connected layer by layer. The second connection line layer 21 is electrically connected to the first connection line layer 13. Furthermore, the substrate structure 110 satisfies the following conditions: "the minimum linewidth of the lines in the second circuit layer 22, the minimum linewidth of the lines in the second connection line layer 21, and the minimum linewidth of the lines in the first connection line layer 13 are all greater than the minimum linewidth of the lines in the first circuit layer 12," and "the minimum line spacing of the lines in the second circuit layer 22, the minimum line spacing of the lines in the second connection layer 22, and the minimum linewidth of the lines in the second connection layer 13 are all greater than the minimum linewidth of the lines in the first circuit layer 12," and "the minimum line spacing of the lines in the second circuit layer 22, the minimum line spacing of the lines in the second connection layer 22, and the minimum line spacing ...13, and the minimum line spacing of the lines in the second The minimum line spacing of the lines in the circuit layer 21 and the minimum line spacing of the lines in the first interconnecting circuit layer 13 are both greater than at least one of the minimum line spacing of the lines in the first circuit layer 12. This results in a smaller line width and / or line spacing of the lines in the first circuit layer 12, which facilitates the realization of high-density circuits and interconnections, and is beneficial to improving the integration of the prepared substrate structure 110. On the other hand, since the preparation of the substrate structure 110 in the above preparation method does not rely on the through silicon via (TSV) process, the preparation cost is lower, the manufacturing process complexity is lower, and the substrate structure 110 can have a better yield. Furthermore, since the substrate structure 110 prepared by the above preparation method has a better integration and yield, when the substrate structure 110 is used with the chip 3 to make the chip packaging module 100, the chip packaging module 100 can also have a better integration and yield.

[0126] To facilitate understanding of the fabrication method of the substrate structure 110 in the fifth aspect, it can be combined with Figures 12A to 12N The example fabrication process of the substrate structure shown is for understanding purposes; alternatively, this example fabrication process can be used to fabricate, for example... Figure 2A The substrate structure 110 shown is shown.

[0127] The method for fabricating the substrate structure 110 provided in the fifth aspect of this application can first form a first substrate layer 1 on a wafer 10. Optionally, the wafer 10 here can refer to a silicon wafer. The wafer can be of any size as needed, for example, including but not limited to 6-inch wafers, 8-inch wafers, 12-inch wafers, etc.

[0128] The first substrate layer 1 can be formed using any suitable material. Optionally, in step S102 of this application, forming the first substrate layer 1 on the wafer can be forming a first substrate layer 1 in the form of a SiO2 layer on the wafer 10. The specific process and beneficial effects can be referred to the foregoing embodiments, and will not be repeated here.

[0129] Optionally, the first substrate layer 1 may be embedded with 1 to 10 first circuit layers 12.

[0130] In some alternative embodiments, the linewidth of the lines in the first line layer 12 is less than or equal to 2 μm.

[0131] In some optional embodiments, the linewidth of the lines in the first line layer 12 is 0.2µm to 2µm.

[0132] In some optional embodiments, the line width of the lines in the first connection line layer 13 is 2µm to 8µm.

[0133] In some alternative embodiments, the line spacing in the first line layer 12 is less than or equal to 2 μm.

[0134] In some optional embodiments, the line spacing in the first line layer 12 is 0.2µm to 2µm.

[0135] In some optional embodiments, the line spacing in the first connection line layer 13 is 2µm to 8µm.

[0136] In some alternative embodiments, the first target pad layer 11 is used to connect the chip.

[0137] It should be understood that the contents and beneficial effects of the first circuit layer 12, the first connection circuit layer 13, and the first target pad layer 11 can also be referred to the description in the previous embodiment of the substrate structure 110, and will not be repeated here.

[0138] This application does not limit the specific fabrication method of the first substrate layer 1. In some optional embodiments, refer to... Figure 7 The flowchart shown illustrates that the first substrate layer 1 can be implemented through the following steps S1022 to S1026, specifically:

[0139] S1022: Form the first target pad layer on the wafer.

[0140] For example, such as Figures 12A to 12N The fabrication process of some examples of substrate structure 110 is shown. For example, in... Figure 12A As shown, a first target pad layer 11 can be formed on wafer 10.

[0141] Optionally, the first target pad layer 11 may include multiple first target pads 111. The first target pad layer 11 can be fabricated in any manner. For example, in one implementation, the first target pad layer 11 can be formed on the wafer 10 by depositing a metal layer on the wafer (such as by sputtering, metal foil pressing, metal deposition, etc.) and then etching the metal layer.

[0142] In some alternative embodiments, the first target pad layer 11 can be formed on the wafer 10 by electroplating. For example, in one example, a seed metal layer covering the entire surface can be formed on the wafer 10 by a cryogenic sputtering process or a metal foil process, and then a barrier layer can be formed on the seed metal layer, such that the barrier layer defines at least one barrier opening. Then, the seed metal layer can be energized and electroplated with an electroplating metal material to form an electroplated metal layer on the seed metal layer within at least one barrier opening. Then, the barrier layer and the portion of the seed metal layer covered by the barrier layer are removed. The portion of the seed metal layer remaining on the wafer 10 and the electroplated metal layer can be effectively formed on the wafer 10, thus forming the first target pad layer 11.

[0143] In the cryogenic sputtering process, any metal material can be used to form the seed metal layer. For example, at least one of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, or an alloy of at least two of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, can be used. In one optional example, cryogenic sputtering can use titanium and copper metals. First, a full-layer titanium metal layer is cryogenically sputtered on the wafer, and then a full-layer copper metal layer is cryogenically sputtered on the titanium metal layer. The titanium metal layer and the copper metal layer can then serve as the seed metal layer. During electroplating, an electric current can be applied to the seed metal layer, and an electroplating metal (taking copper as an example) can be used to electroplat the copper metal layer to obtain an electroplated metal layer in the form of a copper layer. This facilitates the preparation of the first target pad layer 11. In such an example, the prepared first target pad layer 11 can be a first target pad layer 11 in the form of a titanium-copper metal stack, wherein a portion of the copper layer is an electroplated metal.

[0144] In the metal foil lamination process, any metal material can be used to form the seed metal layer. For example, any metal material can be used, such as at least one of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, or an alloy of at least two of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead. In an optional example, copper foil can be used for metal foil lamination, and the seed metal layer can be formed by laminating copper foil onto the wafer. During electroplating, an electric current can be applied to the seed metal layer, and an electroplating metal material (taking copper as an example) can be used to electroplat the copper metal layer to obtain an electroplated metal layer in the form of a copper layer. This facilitates the preparation of the first target pad layer 11. In such an example, the prepared first target pad layer 11 can be a first target pad layer 11 in the form of a copper layer, wherein a portion of the copper layer is electroplated metal.

[0145] The enclosure layer can be made of any material. For example, it can be made of an exposing organic material, including but not limited to photoresist. Taking an exposing organic material layer as an example, an entire exposing organic material layer can be formed on the seed metal layer through processes including but not limited to coating, printing, attaching, and molding. Then, through processes such as exposure and development, the exposing organic material layer is patterned to form an enclosure layer that defines at least one enclosure opening, so as to facilitate electroplating operations on the seed metal layer within the enclosure opening.

[0146] S1024: n first substrate dielectric layers are sequentially formed above the first target pad layer formed on the wafer. Between each two adjacent first substrate dielectric layers in the first to n-1 layers, a first circuit layer is formed by electroplating. A first connection circuit layer is formed between the n-1 to n layers of the first substrate dielectric layers by electroplating. The first target pad layer, at least one first circuit layer, and the first connection circuit layer are electrically connected layer by layer. Wherein, n≥3 and n is an integer.

[0147] Optionally, the first substrate layer 1 can be a SiO2 layer, and correspondingly, the aforementioned n-layer first substrate dielectric layer 201 can be a SiO2 layer. When forming the first substrate dielectric layer 201, SiO2 can be grown using processes including but not limited to PECVD, HDPCVD, LPCVD, etc., to form the first substrate dielectric layer 201 in the form of a SiO2 layer.

[0148] Optionally, the process of the first circuit layer 12 can be understood with reference to the aforementioned embodiments, and will not be repeated here.

[0149] Optionally, in the above-mentioned n-layer first substrate dielectric layer 201, during the fabrication process of the first substrate layer 1, the first substrate dielectric layer 201 can cover the first target pad layer 11, the second to n-1 first substrate dielectric layers 201 can respectively cover the first to n-2 first circuit layers 12, and the nth first substrate dielectric layer 201 can cover the first connection circuit layer 13. For example, refer to... Figures 12A to 12N The preparation process shown is explained.

[0150] This application does not limit the specific implementation of step S1042. In some optional embodiments, the step S1024 above, "forming one first circuit layer between every two adjacent first substrate dielectric layers in the first substrate dielectric layers from the 1st to the (n-1th)th layers by electroplating", may include: forming the i-th first circuit layer 12 by the following steps S1024A to S1024E, where 1≤i≤n-2:

[0151] S1024A: Open a window in the first substrate dielectric layer of the i-th layer so that the first target portion of the first target pad layer or the first circuit layer covered by the first substrate dielectric layer of the i-th layer is exposed.

[0152] For ease of explanation, the following steps will first be described as an overall process (hereafter referred to as Overall Process A). Refer to... Figures 12A to 12N The fabrication process shown, for example taking n=4, that is, 4 first substrate dielectric layers 201 and 2 first circuit layers 12, is as follows:

[0153] The first substrate dielectric layer 201 formed covers the first target pad layer 11. The first substrate dielectric layer 201 can be windowed (at least one of etching, grinding, exposure, laser drilling, etc.) to form an opening, so that it covers a portion of the first target pad layer 11 (i.e. the first target portion) to expose, so as to facilitate the fabrication of the first circuit layer 12 and the electrical connection between the first circuit layer 12 and the first target pad layer 11.

[0154] After the first circuit layer 12 is fabricated, the second substrate dielectric layer 201 is formed. The second substrate dielectric layer 201 covers the first circuit layer 12. A window can be made in the second substrate dielectric layer 201 to form an opening, so that a portion of the first circuit layer 12 (i.e., the first target portion) is exposed, so as to facilitate the fabrication of the second circuit layer 12 and the electrical connection between the second circuit layer 12 and the first circuit layer 12.

[0155] After the second layer first circuit layer 12 is fabricated, the third layer first substrate dielectric layer 201 is formed. The third layer first substrate dielectric layer 201 covers the second layer first circuit layer 12. A window can be made in the third layer first substrate dielectric layer 201 to form an opening, so that a part of the second layer first circuit layer 12 (i.e., the first target part) is exposed, so as to facilitate the fabrication of the first connection line layer 13 and the electrical connection between the first connection line layer 13 and the second layer first circuit layer 12.

[0156] After the first interconnection layer 13 is fabricated, the fourth first substrate dielectric layer 201 is formed, and the fourth first substrate dielectric layer 201 covers the first interconnection layer 13.

[0157] The above is the general process for easy understanding. The optional manufacturing process of the first circuit layer 12 can be explained below in conjunction with the above general process A.

[0158] Optionally, before opening a window in the i-th layer of the first substrate dielectric layer 201, the surface of the i-th layer of the first substrate dielectric layer 201 can be ground flat before opening the window. For example, an entire surface of an exposeable organic layer can be formed on the surface of the i-th layer of the first substrate dielectric layer 201 through processes including but not limited to coating, printing, bonding, and molding. Then, through an exposure and development process, the exposeable organic layer is patterned to form at least one opening. The portion of the i-th layer of the first substrate dielectric layer 201 covering the first target portion is exposed through the at least one opening. Then, an etching process is performed to etch away the portion of the i-th layer of the first substrate dielectric layer 201 covering the first target portion (i.e., the portion located within the at least one opening), thereby exposing the first target portion of the first target pad layer 11 or the first circuit layer 12 covered by the i-th layer of the first substrate dielectric layer 201.

[0159] For example, in Figures 12A to 12N In the preparation process shown, such as... Figure 12B The diagram illustrates a first target portion of the first target pad layer 11 covered by the first target substrate dielectric layer 201 after a window is made in the first substrate dielectric layer 201. The same logic applies when i is a different value.

[0160] S1024B: A first seed metal layer is formed above the first substrate dielectric layer of the i-th layer, wherein the first seed metal layer covers the first target portion.

[0161] Optionally, the first seed metal layer is formed by a sputtering process or a metal foil process.

[0162] Optionally, a full-surface first seed metal layer 31 can be formed on the first substrate dielectric layer 201 of the i-th layer by low-temperature sputtering or metal foil pressing, so that the first seed metal layer 31 can cover the first target portion exposed by the first target pad layer 11 or the first target portion exposed by the first circuit layer 12, so as to realize the electrical connection between the first circuit layer 12 and the first target pad layer 11, and between the first circuit layers 12.

[0163] In the cryogenic sputtering process, any metal material can be used to form the first seed metal layer 31. For example, at least one of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, or an alloy of at least two of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, can be used. In an optional example, the cryogenic sputtering can use titanium and copper metals. First, a full-layer titanium metal layer is cryogenically sputtered on the i-th layer of the first substrate dielectric layer 201, and then a full-layer copper metal layer is cryogenically sputtered on the titanium metal layer. Then, the titanium metal layer and the copper metal layer can be the first seed metal layer 31. During electroplating, the first seed metal layer 31 can be energized, and an electroplating metal material (taking copper as an example) can be used to electroplat the copper metal layer to obtain an electroplated metal layer in the form of a copper layer. This facilitates the fabrication of the first circuit layer 12. In such an example, the fabricated first circuit layer 12 can be a titanium-copper metal stacked first circuit layer 12, wherein a portion of the copper layer is an electroplated metal.

[0164] In the metal foil pressing process, any metal material can be used to form the first seed metal layer 31. For example, any metal material can be used to form the first seed metal layer, such as at least one of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, or an alloy of at least two of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead. In an optional example, copper foil can be used for metal foil pressing, and the first seed metal layer 31 can be formed by pressing copper foil onto the i-th layer of the first substrate dielectric layer 201. During electroplating, the first seed metal layer 31 can be energized, and an electroplating metal material (taking copper as an example) can be used to electroplat the copper metal layer to obtain an electroplated metal layer in the form of a copper layer. This facilitates the fabrication of the first circuit layer 12. In such an example, the first circuit layer 12 obtained can be a first circuit layer 12 in the form of a copper layer, wherein a portion of the copper layer is electroplated metal.

[0165] Taking the fabrication of the first circuit layer 12 in the above-described overall process A as an example. Optionally, a first seed metal layer 31 can be formed over the first substrate dielectric layer 201 by low-temperature sputtering or metal foil pressing. The first seed metal layer covers the first target portion of the exposed first target pad layer 11 to facilitate the fabrication of the first circuit layer 12 in subsequent steps.

[0166] Taking the fabrication of the second first circuit layer 12 in the overall process A above as an example. Optionally, a full-layer first seed metal layer 31 can be formed above the second first substrate dielectric layer 201 by low-temperature sputtering or metal foil pressing, so that the first seed metal layer 31 covers the exposed first target portion of the first first circuit layer 12, so as to facilitate the subsequent steps of fabricating the second first circuit layer 12. Other layers can be fabricated in the same way.

[0167] For example, in Figures 12A to 12N In the preparation process shown, such as... Figure 12C As shown, a first seed metal layer 31 is formed above the first substrate dielectric layer 201, wherein the first seed metal layer 31 covers a first target portion of the first target pad layer 11 exposed from the opening of the first substrate dielectric layer 201. The same principle applies when i is a different value.

[0168] S1024C: A first barrier layer is formed on a first seed metal layer, wherein the first barrier layer defines at least one first barrier opening, wherein the vertical projection of the at least one first barrier opening on the wafer overlaps with the vertical projection of the first target portion on the wafer.

[0169] The first barrier layer 41 can be made of any material. For example, it can be made of an exposing organic material, including but not limited to photoresist. Taking an exposing organic material layer as an example, an exposing organic material layer can be formed on the first seed metal layer 31 through processes including but not limited to coating, printing, attaching, and molding. Then, through processes such as exposure and development, the exposing organic material layer is patterned to form a first barrier layer 41 that defines at least one first barrier opening 411, so that electroplating can be performed on the first seed metal layer 31 within the first barrier opening 411.

[0170] Optionally, the first enclosure layer 41 may be made of at least one of the following materials: polyimide, poly(p-phenylenebenzodioxazole), epoxy resin, acrylic resin, or organosiloxane composite material.

[0171] In this application, the vertical projection of at least one first enclosure opening 411 on the wafer 10 overlaps with the vertical projection of the first target portion on the wafer 10, which facilitates the formation of an electrical connection between the first circuit layer 12, which is subsequently electroplated, and thus achieves circuit interconnection between different layers.

[0172] Taking the fabrication of the first circuit layer 12 in the overall process A above as an example. Optionally, an exposeable organic layer can be formed on the first seed metal layer 31 on the first substrate dielectric layer 201 through processes such as coating, printing, attaching, and molding. Then, through processes such as exposure and development, the exposeable organic layer is patterned to form a first barrier layer 41 that defines at least one first barrier opening 411, so that electroplating can be performed on the first seed metal layer 31 within the first barrier opening 411. Other layers can be fabricated similarly.

[0173] For example, in Figures 12A to 12N In the preparation process shown, such as... Figure 12DAs shown, a first barrier layer 41 can be formed on the first seed metal layer 31, the first barrier layer 41 defining at least one first barrier opening 411, wherein the vertical projection of at least one first barrier opening 411 on the wafer 10 overlaps with the vertical projection of the first target portion on the wafer 10.

[0174] S1024D: A first electroplated metal layer is formed on a first portion of a first seed metal layer within a first enclosure opening by electroplating.

[0175] The first part, namely the portion of the first seed metal layer 31 within the first enclosure opening 411, can be electrically applied to the first seed metal layer 31 and electroplated using an electroplating metal material to form a first electroplated metal layer on the first portion within the first enclosure opening 411.

[0176] Optionally, the electroplating metal material may be at least one of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, or an alloy of at least two of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead. Alternatively, other feasible metal materials may be used, as long as they meet the requirements.

[0177] For example, as mentioned above, copper can be used as an example of electroplating metal material, and a first electroplated metal layer in the form of a copper layer can be obtained by electroplating.

[0178] For example, in Figures 12A to 12N In the preparation process shown, such as... Figure 12E As shown, a first electroplated metal layer 121 can be formed on a first portion of the first seed metal layer 31 within the first enclosure opening 411 by electroplating.

[0179] S1024E: Remove the first enclosure layer and the second portion of the first seed metal layer other than the first portion, so as to form the i-th first circuit layer through the first portion of the first seed metal layer and the first electroplated metal layer.

[0180] After the first electroplated metal layer 121 is fabricated, the excess portion (i.e., the second portion other than the first portion of the first electroplated metal layer 121) in the first enclosure layer 41 and the first seed metal layer 31 can be removed to obtain the i-th first circuit layer 12. The i-th first circuit layer 12 is composed of the first portion of the first seed metal layer and the first electroplated metal layer, and the circuit of the i-th first circuit layer 12 includes electroplated metal circuits.

[0181] Optionally, the circuits in the first circuit layer 12 formed above include metal stacked circuits, and at least one metal layer of the metal stacked circuit is an electroplated metal layer. For example, the metal stacked circuit may include a first metal layer and a second metal layer, the first metal layer and the second metal layer being made of different materials; and at least a portion of the second metal layer is an electroplated metal layer, the thickness of the electroplated metal layer being greater than the thickness of the first metal layer. Optionally, the second metal layer is a copper layer, and the first metal layer is a titanium layer. For example, in some cases, such a metal stacked circuit can be obtained by using a titanium layer as the seed metal layer for electroplating and electroplating copper on the titanium layer. It can be understood that in this case, the titanium layer in the metal stacked circuit is the "first part of the first seed metal layer" in step S1024D above, and the copper layer in the metal stacked circuit is the "first electroplated metal layer". In other cases, a titanium-copper metal stack can be used as the first seed metal layer for electroplating and electroplating copper on the copper layer in the first seed metal layer. It can be understood that in this case, the titanium layer and a part of the copper layer in the metal stacked circuit is the "first part of the first seed metal layer", and the copper layer obtained by electroplating the other part of the metal stacked circuit is the "first electroplated metal layer".

[0182] Optionally, the circuits in the first circuit layer 12 formed above include a single-layer metal circuit, at least a portion of which is electroplated metal. For example, one implementation of the single-layer metal circuit being electroplated metal is that the seed metal layer and the electroplating metal material are the same metal. For example, in some cases, a copper layer can be used as the seed metal layer for electroplating, and copper can be used as the electroplating metal material to electroplat the copper layer that serves as the seed metal layer. It is understood that in this case, a portion of the copper layer in the single-layer metal circuit is the "first portion of the first seed metal layer", and the copper layer obtained by electroplating the other portion of the single-layer metal circuit is the "first electroplated metal layer".

[0183] For example, in Figures 12A to 12N In the preparation process shown, such as... Figure 12F As shown, the first enclosure layer 41 and the second portion of the first seed metal layer 31 (excluding the first portion) can be removed to form the first circuit layer 12 through the first portion of the first seed metal layer 31 and the first electroplated metal layer 121. The same principle applies when i is a different value.

[0184] Based on this, in this application, the first line layer 12 of the i-th layer can be effectively electroplated through the above steps S1024A to S1024E, and each first line layer 12 in the first substrate layer 1 can be effectively obtained in this way. Moreover, the first target pad layer 11 and at least one first line layer 12 can be electrically connected layer by layer. In addition, the first line layer 12 obtained by electroplating in the above way is easy to manufacture and has good conductivity and signal integrity. The surface flatness of the electroplated metal line is high, which can effectively reduce the impedance mismatch problem in signal transmission.

[0185] For example, in Figures 12A to 12N In the preparation process shown, such as... Figure 12G , Figure 12H , Figure 12I As shown, the second and third first substrate dielectric layers 201 and the second first circuit layer 12 can be fabricated in a similar manner to the first circuit layer 12, until all first circuit layers 12 are fabricated.

[0186] Optionally, the first interconnection layer 13 can be formed by electroplating between the first substrate dielectric layers 201 of the n-1 to nth layers. For example, in one example, a seed metal layer can be formed on the entire surface of the (n-1)th layer of the first substrate dielectric layer 201 by a low-temperature sputtering process or a metal foil process. Then, a barrier layer is formed on the seed metal layer, and the barrier layer defines at least one barrier opening. After that, the seed metal layer can be energized and electroplated with an electroplating metal material to form an electroplated metal layer on the seed metal layer within the at least one barrier opening. The vertical projection of the barrier opening on the wafer 10 overlaps with the vertical projection of the first target portion of the first circuit layer 12 exposed from the (n-1)th layer of the first substrate dielectric layer 201 on the wafer 10, so as to realize the electrical connection between the first circuit layer 12 and the fabricated first connection circuit layer 13. Then, the barrier layer and the portion of the seed metal layer covered by the barrier layer are removed. The portion of the seed metal layer remaining on the (n-1)th layer of the first substrate dielectric layer 201 can effectively form the first connection circuit layer 13 on the (n-1)th layer of the first substrate dielectric layer 201.

[0187] It should be noted that the electroplating process here is similar in principle to the electroplating method of the first target pad layer 11 and the first circuit layer 12 mentioned above (such as steps S1024A to S1024E), and can also be understood in conjunction with the previous text.

[0188] After the first interconnection layer 13 is prepared, the nth first substrate dielectric layer 201 can be prepared on the first interconnection layer 13, and the nth first substrate dielectric layer 201 can fully cover the first interconnection layer 13.

[0189] For example, in Figures 12A to 12N In the preparation process shown, such as... Figure 12I As shown, a first interconnect layer 13 can be fabricated, and the fabricated n=4th first substrate dielectric layer 201 covers the first interconnect layer 13.

[0190] S1026: Remove a portion of the nth first substrate dielectric layer to expose at least a portion of the first interconnection layer to form the first substrate layer.

[0191] A portion of the nth first substrate dielectric layer 201 can be removed to expose at least a portion of the first connection line layer 13 it covers, facilitating electrical connection with the second connection line layer 21 of the subsequently fabricated second substrate layer 2. After exposing at least a portion of the first connection line layer 13, the nth first substrate dielectric layer 201 can then be used as the first substrate layer 1. It is understood that the nth first substrate dielectric layer 201 can form the first substrate layer 1.

[0192] Optionally, a window can be made in the nth layer of the first substrate dielectric layer 201 to remove a portion of the nth layer of the first substrate dielectric layer 201, exposing at least a portion of the first interconnection layer 13.

[0193] Optionally, before opening a window in the nth layer of the first substrate dielectric layer 201, the surface of the nth layer of the first substrate dielectric layer 201 can be ground smooth before opening the window. For example, an entire surface of an exposeable organic layer can be formed on the surface of the nth layer of the first substrate dielectric layer 201 through processes including but not limited to coating, printing, bonding, and molding. Then, through an exposure and development process, the exposeable organic layer is patterned to form at least one opening, exposing a portion of the nth layer of the first substrate dielectric layer 201 through the at least one opening. Then, an etching process is performed to etch away a portion of the nth layer of the first substrate dielectric layer 201 (i.e., the portion located within the at least one opening), thereby exposing at least a portion of the first interconnection layer 13 covered by the nth layer of the first substrate dielectric layer 201.

[0194] For example, in Figures 12A to 12N In the preparation process shown, such as... Figure 12J As shown, a portion of the n=4th first substrate dielectric layer 201 can be removed, thereby exposing at least a portion of the first interconnection layer 13, and subsequently, the first substrate layer 1 can be formed based on the n=4th first substrate dielectric layer 201. It should be understood that here... Figures 12A to 12N The layers shown in the preparation process are merely examples and are not intended to limit the embodiments of this application.

[0195] It should be understood that, through the optional solutions of steps S1022 to S1026 described above, this application can effectively prepare a first substrate layer 1 embedded with a first target pad layer 11, at least one first circuit layer 12, and a first connection circuit layer 13 that are electrically interconnected layer by layer, such that the first target pad layer 11 is located on the first surface of the first substrate layer 1, and the first connection circuit layer 13 is located on the second surface of the first substrate layer 1 and exposed from the second surface of the first substrate layer 1, thereby facilitating the preparation of the substrate structure 110; on the other hand, the above optional technical solutions prepare the first circuit layer 12 by electroplating. The first interconnecting line layer 13 is easy to manufacture and has good conductivity and signal integrity. The surface flatness of the electroplated metal lines is high, which can effectively reduce impedance mismatch problems in signal transmission. Furthermore, the above-mentioned alternative solution can easily manufacture a first line layer 12 with a small line width and / or line spacing when preparing the first substrate layer 1, which is conducive to realizing high-density lines and interconnections, and is beneficial to improving the integration of the substrate structure 110. It does not rely on the through silicon via (TSV) process, so the manufacturing cost is low, the manufacturing process complexity is low, and the yield is good.

[0196] In this application, after the first substrate layer 1 is prepared in step S102, the second substrate layer 2 can be prepared in step S104.

[0197] The specific process and beneficial effects of the second substrate layer 2 can be referred to the foregoing embodiments, and will not be repeated here. Optionally, the second substrate layer 2 can be an organic insulating layer to meet insulation requirements. The second substrate layer 2 can be fabricated using organic insulating materials using processes including but not limited to coating, printing, bonding, and molding. For example, the organic insulating layer is made of at least one of polyimide (PI) materials, epoxy resin materials, and silane materials.

[0198] Optionally, the second substrate layer 2 may be embedded with 1 to 10 second circuit layers 22.

[0199] In some optional embodiments, the linewidth of the lines in the second line layer 22 is 2µm to 8µm.

[0200] In some optional embodiments, the linewidth of the lines in the second connection layer 21 is 2µm to 8µm.

[0201] In some optional embodiments, the line spacing in the second line layer 22 is 2µm to 8µm.

[0202] In some optional embodiments, the line spacing in the second connection line layer 21 is 2µm to 8µm.

[0203] In some alternative embodiments, the second target pad layer 23 is used to connect other external circuit structures.

[0204] It should be understood that the contents and beneficial effects of the second circuit layer 22, the second connection circuit layer 21, and the second target pad layer 23 can also be referred to the description in the previous embodiment of substrate structure 110, and will not be repeated here.

[0205] This application does not limit the specific fabrication method of the second substrate layer 2. In some optional embodiments, refer to... Figure 8 As shown in the flowchart, the second substrate layer 2 can be implemented through the following steps S1042 to S1046, specifically:

[0206] S1042: On the second side of the first substrate layer, a second connection line layer is formed by electroplating, which is electrically connected to the first connection line layer exposed from the second side of the first substrate layer.

[0207] For example, such as Figures 12A to 12N The fabrication process of some examples of substrate structure 110 is shown. For example, in... Figure 12K As shown, a second connection layer 21, which is electrically connected to the first connection layer 13 exposed from the second surface of the first substrate layer 1, can be formed on the second surface of the first substrate layer 1 by electroplating.

[0208] For example, in one example, a seed metal layer can be formed on the second surface of the first substrate layer 1 (e.g., the second surface of the first substrate layer 1 can be formed by the nth first substrate dielectric layer 201) by a low-temperature sputtering process or a metal foil process. Then, a barrier layer is formed on the seed metal layer, and the barrier layer defines at least one barrier opening. After that, the seed metal layer can be energized and electroplated with an electroplating metal material to form an electroplated metal layer on the seed metal layer within at least one barrier opening. The vertical projection of the barrier opening on the wafer 10 overlaps with the vertical projection of the portion of the first interconnection layer 13 exposed from the second surface of the first substrate layer 1 on the wafer 10, so as to realize the electrical connection between the first interconnection layer 13 and the fabricated second interconnection layer 21. Then, the barrier layer and the portion of the seed metal layer covered by the barrier layer are removed. The portion of the seed metal layer remaining on the second surface of the first substrate layer 1 and the electroplated metal layer can be effectively formed on the second surface of the first substrate layer 1.

[0209] It should be noted that the electroplating process here is similar in principle to the electroplating method of the second circuit layer 22 described below (such as steps S1044A to S1044E), and can also be understood in conjunction with the previous text.

[0210] S1044: m second substrate dielectric layers are sequentially formed above the second connection line layer, and between each two adjacent second substrate dielectric layers in the first to m-1 layers, a second line layer is formed by electroplating, and a second target pad layer is formed between the m-1 to m layers, and the second connection line layer, at least one second line layer and the second target pad layer are electrically connected layer by layer, wherein m≥3 and m is an integer.

[0211] Optionally, the second substrate layer 2 can be an organic insulating layer, and correspondingly, the aforementioned m-layer second substrate dielectric layer 202 can be an organic insulating layer. When forming the second substrate dielectric layer 202, processes including but not limited to coating, printing, bonding, and encapsulation can be used to fabricate the second substrate dielectric layer 202 using organic insulating materials.

[0212] Optionally, in the above-mentioned m-layer second substrate dielectric layer 202, during the fabrication process of the second substrate layer 2, the first layer of the second substrate dielectric layer 202 may cover the second interconnection line layer 21, the second to m-1 layers of the second substrate dielectric layer 202 may respectively cover the first to m-2 layers of the second circuit layer 22, and the m-layer second substrate dielectric layer 202 may cover the second target pad layer 23. For example, refer to... Figures 12A to 12N The preparation process shown is explained.

[0213] This application does not limit the specific implementation of step S1044. In some optional embodiments, the step S1044 described above, "forming one second circuit layer between every two adjacent second substrate dielectric layers in the first to m-1 layers by electroplating," may include: forming the j-th second circuit layer by the following steps S1044A to S1044E, where 1≤j≤m-2:

[0214] S1044A: A window is made in the dielectric layer of the j-th second substrate so that the dielectric layer of the j-th second substrate exposes the second target portion of the second interconnection line layer or the second line layer it covers.

[0215] For ease of explanation, the following steps will first be described as an overall process (hereafter referred to as Overall Process B). See reference... Figures 12A to 12N The fabrication process shown, for example taking m=5, that is, 5 layers of second substrate dielectric layer 202 and 3 layers of second circuit layer 22, is as follows:

[0216] The first layer of the second substrate dielectric layer 202 covers the second connection line layer 21. The first layer of the second substrate dielectric layer 202 can be windowed (at least one of etching, grinding, exposure, laser drilling, etc.) to form an opening, so that it covers a portion of the second connection line layer 21 (i.e. the second target portion) to expose, so as to facilitate the fabrication of the first layer of the second circuit layer 22 and the electrical connection between the first layer of the second circuit layer 22 and the second connection line layer 21.

[0217] After the first layer of second circuit layer 22 is fabricated, the second layer of second substrate dielectric layer 202 is formed. The second layer of second substrate dielectric layer 202 covers the first layer of second circuit layer 22. A window can be made in the second layer of second substrate dielectric layer 202 to form an opening, so that a portion of the first layer of second circuit layer 22 (i.e., the second target portion) is exposed, so as to facilitate the fabrication of the second layer of second circuit layer 22 and the electrical connection between the second layer of second circuit layer 22 and the first layer of second circuit layer 22.

[0218] After the second circuit layer 22 is fabricated, the third substrate dielectric layer 202 is formed. The third substrate dielectric layer 202 covers the second circuit layer 22. A window can be made in the third substrate dielectric layer 202 to form an opening, so that a portion of the second circuit layer 22 (i.e., the second target portion) is exposed, so as to facilitate the fabrication of the third circuit layer 22 and the electrical connection between the third circuit layer 22 and the second circuit layer 22.

[0219] After the third second circuit layer 22 is fabricated, the fourth second substrate dielectric layer 202 is formed. The fourth second substrate dielectric layer 202 covers the third second circuit layer 22. A window can be made in the fourth second substrate dielectric layer 202 to form an opening, so that a portion of the third second circuit layer 22 (i.e., the second target portion) is exposed, so as to facilitate the fabrication of the second target pad layer 23 and the electrical connection between the second target pad layer 23 and the third second circuit layer 22.

[0220] After the second target pad layer 23 is fabricated, the fifth second substrate dielectric layer 202 is formed, and the formed fifth second substrate dielectric layer 202 covers the second target pad layer 23.

[0221] The above is the general process for easy understanding. The optional manufacturing process of the second circuit layer 22 can be explained below in conjunction with the above general process B.

[0222] Optionally, before opening a window in the j-th layer of the second substrate dielectric layer 202, the surface of the j-th layer of the second substrate dielectric layer 202 can be ground smooth before opening the window. For example, an entire surface of an exposeable organic layer can be formed on the surface of the j-th layer of the second substrate dielectric layer 202 through processes including but not limited to coating, printing, bonding, and molding. Then, through an exposure and development process, the exposeable organic layer is patterned to form at least one opening, exposing the portion of the j-th layer of the second substrate dielectric layer 202 that covers the second target portion. Then, an etching process is performed to etch away the portion of the j-th layer of the second substrate dielectric layer 202 that covers the second target portion (the portion located within the at least one opening), thereby exposing the second target portion of the second interconnection layer 21 or the second circuit layer 22 covered by the j-th layer of the second substrate dielectric layer 202.

[0223] S1044B: A second seed metal layer is formed above the second substrate dielectric layer of the j-th layer, wherein the second seed metal layer covers the second target portion.

[0224] Optionally, the second seed metal layer is formed by a sputtering process or a metal foil process.

[0225] Optionally, a full-surface second seed metal layer can be formed on the second substrate dielectric layer 202 of the j-th layer by low-temperature sputtering or metal foil pressing, so that the second seed metal layer can cover the exposed second target portion of the second connection line layer 21 or the exposed second target portion of the second line layer 22, so as to realize the electrical connection between the second line layer 22 and the second connection line layer 21, and between the second line layer 22 and the second line layer 22.

[0226] In the cryogenic sputtering process, any metal material can be used to form the second seed metal layer. For example, at least one of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, or an alloy of at least two of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, can be used. In an optional example, the cryogenic sputtering can use titanium and copper. First, a full-layer titanium metal layer is cryogenically sputtered on the j-th layer of the second substrate dielectric layer 202, and then a full-layer copper metal layer is cryogenically sputtered on the titanium metal layer. The titanium metal layer and the copper metal layer can then serve as the second seed metal layer. During electroplating, an electric current can be applied to the second seed metal layer, and an electroplating metal material (taking copper as an example) can be used to electroplat the copper metal layer to obtain an electroplated metal layer in the form of a copper layer. This facilitates the fabrication of the second circuit layer 22. In such an example, the fabricated second circuit layer 22 can be a titanium-copper metal stacked second circuit layer 22, wherein a portion of the copper layer is an electroplated metal.

[0227] In the metal foil lamination process, any metal material can be used to form the second seed metal layer. For example, any metal material can be used, such as at least one of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead, or an alloy of at least two of copper, tin, nickel, gold, silver, indium, chromium, zinc, titanium, and lead. In an optional example, copper foil can be used for the metal foil lamination, and the second seed metal layer can be formed by laminating copper foil onto the j-th layer of the second substrate dielectric layer 202. During electroplating, an electric current can be applied to the second seed metal layer, and an electroplating metal material (taking copper as an example) can be used to electroplat the copper metal layer to obtain an electroplated metal layer in the form of a copper layer. This facilitates the fabrication of the second circuit layer 22. In such an example, the fabricated second circuit layer 22 can be a second circuit layer 22 in the form of a copper layer, wherein a portion of the copper layer is electroplated metal.

[0228] Taking the fabrication of the first layer second circuit layer 22 in the above-described overall process B as an example. Optionally, a full-layer second seed metal layer can be formed above the first layer second substrate dielectric layer 202 by low-temperature sputtering or metal foil pressing. The second seed metal layer covers the second target portion of the exposed second connection circuit layer 21 to facilitate the subsequent fabrication of the first layer second circuit layer 22.

[0229] Taking the fabrication of the second circuit layer 22 in the overall process B described above as an example, optionally, a full-layer second seed metal layer can be formed above the second substrate dielectric layer 202 by low-temperature sputtering or metal foil lamination, so that the second seed metal layer covers the exposed second target portion of the first second circuit layer 22, so as to facilitate the subsequent fabrication of the second circuit layer 22. Other layers can be fabricated in the same manner.

[0230] S1044C: A second enclosure layer is formed on the second seed metal layer, wherein the second enclosure layer defines at least one second enclosure opening, wherein the vertical projection of the at least one second enclosure opening on the wafer overlaps with the vertical projection of the second target portion on the wafer.

[0231] The second enclosure layer can be made of any material. For example, it can be made of an exposing organic material, including but not limited to photoresist. Taking an exposing organic material layer as an example, an entire exposing organic material layer can be formed on the second seed metal layer through processes including but not limited to coating, printing, attaching, and molding. Then, through processes such as exposure and development, the exposing organic material layer is patterned to form a second enclosure layer that defines at least one second enclosure opening, so that electroplating can be performed on the second seed metal layer within the second enclosure opening.

[0232] Optionally, the second enclosure layer may be made of at least one of the following materials: polyimide, poly(p-phenylenebenzodioxazole), epoxy resin, acrylic resin, or organosiloxane composite material.

[0233] In this application, the vertical projection of the second enclosure opening on the wafer overlaps with the vertical projection of the second target portion on the wafer, which facilitates the formation of an electrical connection between the second circuit layer 22, which is subsequently electroplated, and the second target portion, thereby achieving interconnection between different layers.

[0234] Taking the fabrication of the first layer, second circuit layer 22, in the overall process B described above as an example, optionally, an exposeable organic layer can be formed on the second seed metal layer on the first layer, second substrate dielectric layer 202, through processes such as coating, printing, attaching, and molding. Then, through processes such as exposure and development, the exposeable organic layer is patterned to form a second barrier layer defining at least one second barrier opening, so as to facilitate electroplating operations on the second seed metal layer within the second barrier opening. Other layers can be fabricated similarly.

[0235] S1044D: A second electroplated metal layer is formed on the third portion of the second seed metal layer inside the second enclosure opening by electroplating.

[0236] The third part is the portion of the second seed metal layer within the second enclosure opening. Optionally, the second seed metal layer can be energized and electroplated using an electroplating metal material to form a second electroplated metal layer on the third part within the second enclosure opening.

[0237] For example, as mentioned above, if copper is taken as an example of the electroplating metal material, a second electroplated metal layer in the form of a copper layer can be obtained by electroplating.

[0238] S1044E: Remove the second enclosure layer and the fourth portion of the second seed metal layer other than the third portion, so as to form the j-th second circuit layer through the third portion of the second seed metal layer and the second electroplated metal layer.

[0239] After the second electroplated metal layer is made, the excess part of the second enclosure layer and the second seed metal layer (that is, the fourth part other than the third part of the second electroplated metal layer) can be removed to obtain the j-th second circuit layer 22. The j-th second circuit layer 22 is composed of the third part of the second seed metal layer and the second electroplated metal layer. The circuit of the j-th second circuit layer 22 includes electroplated metal circuits.

[0240] Optionally, the circuits in the second circuit layer 22 formed above include metal stacked circuits, and at least one metal layer of the metal stacked circuit is an electroplated metal layer. For example, the metal stacked circuit may include a first metal layer and a second metal layer, the first metal layer and the second metal layer being made of different materials; and at least a portion of the second metal layer is an electroplated metal layer, the thickness of the electroplated metal layer being greater than the thickness of the first metal layer. Optionally, the second metal layer is a copper layer, and the first metal layer is a titanium layer. For example, in some cases, such a metal stacked circuit can be obtained by using a titanium layer as the seed metal layer for electroplating and electroplating copper on the titanium layer. It can be understood that in this case, the titanium layer in the metal stacked circuit is the "third part of the second seed metal layer" in step S1044D above, and the copper layer in the metal stacked circuit is the "second electroplated metal layer". In other cases, a titanium-copper metal stack can be used as the second seed metal layer for electroplating, and electroplating copper on the copper layer in the second seed metal layer can be obtained. It can be understood that in this case, the titanium layer and a part of the copper layer in the metal stacked circuit is the "third part of the second seed metal layer", and the copper layer obtained by electroplating the other part of the metal stacked circuit is the "second electroplated metal layer".

[0241] Optionally, the circuits in the second circuit layer 22 formed above include a single-layer metal circuit, at least a portion of which is electroplated metal. For example, one implementation of the single-layer metal circuit being electroplated metal is that the seed metal layer and the electroplating metal material are the same metal. For example, in some cases, a copper layer can be used as the seed metal layer for electroplating, and copper can be used as the electroplating metal material to electroplat the copper layer that serves as the seed metal layer. It is understood that in this case, a portion of the copper layer in the single-layer metal circuit is the "third part of the second seed metal layer", and the copper layer obtained by electroplating the other portion of the single-layer metal circuit is the "second electroplated metal layer".

[0242] Based on this, the j-th second circuit layer 22 can be effectively electroplated through the above steps S1044A to S1044E in this application. Furthermore, each second circuit layer 22 in the second substrate layer 2 can be effectively obtained in this manner, enabling the second connection circuit layer 21 and at least one second circuit layer 22 to achieve layer-by-layer electrical connection. In addition, the second circuit layer 22 obtained by electroplating in the above manner is easy to manufacture and has good conductivity and signal integrity. The surface flatness of the electroplated metal circuit is high, which can effectively reduce impedance mismatch problems in signal transmission. Moreover, since the above optional technical solution involves the sequential superposition of the first connection circuit layer 13 and the second connection circuit layer 21 fabrication processes, it facilitates a more stable electrical connection between the first connection circuit layer 13 and the second connection circuit layer 21, resulting in better electrical connection performance. It can also form an electrical connection without relying on solder, thus avoiding the appearance of a solder interface between the first substrate layer 1 and the second substrate layer 2. Therefore, it avoids the disadvantages of unstable packaging structure of the substrate structure 110 caused by soldering and effectively reduces packaging costs.

[0243] It should be understood that the above steps S1044A to S1044E can also be combined with the fabrication of the second circuit layer 22. Figures 12A to 12N The example fabrication process of the first circuit layer 12 is explained in the context of the fabrication process. The principles of these two parts are similar, so they will not be shown separately in the figure.

[0244] Optionally, a second target pad layer 23 may be formed between the second substrate dielectric layers 202 of the m-1 to m layers by electroplating. For example, in one example, a full-surface seed metal layer can be formed on the (m-1)th layer of the second substrate dielectric layer 202 by a low-temperature sputtering process or a metal foil process. Then, a barrier layer is formed on the seed metal layer, and the barrier layer defines at least one barrier opening. After that, the seed metal layer can be energized and electroplated with an electroplating metal material to form an electroplated metal layer on the seed metal layer within at least one barrier opening. The vertical projection of the barrier opening on the wafer 10 overlaps with the vertical projection of the second target portion of the second circuit layer 22 exposed from the (m-1)th layer of the second substrate dielectric layer 202 on the wafer 10, so as to realize the electrical connection between the second circuit layer 22 and the fabricated second target pad layer 23. Then, the barrier layer and the portion of the seed metal layer covered by the barrier layer are removed. The portion of the seed metal layer remaining on the (m-1)th layer of the second substrate dielectric layer 202 can effectively form the second target pad layer 23 on the (m-1)th layer of the second substrate dielectric layer 202.

[0245] It should be noted that the electroplating process here is similar in principle to the electroplating method of the second circuit layer 22 mentioned above (such as steps S1044A to S1044E), and can also be understood in conjunction with the previous text.

[0246] After the second target pad layer 23 is prepared, the m-th second substrate dielectric layer 202 can be prepared on the second target pad layer 23, and the m-th second substrate dielectric layer 202 can fully cover the second target pad layer 23.

[0247] For example, in Figures 12A to 12N In the preparation process shown, such as... Figure 12L As shown, m=5 layers of second substrate dielectric layer 202, 3 layers of second circuit layer 22 and 1 layer of second target pad layer 23 can be prepared by the aforementioned optional method, and the second connection circuit layer 21, the 3 layers of second circuit layer 22 and the 1 layer of second target pad layer 23 are electrically connected layer by layer, and the prepared m=5th layer of second substrate dielectric layer 202 covers the second target pad layer 23.

[0248] S1046: Remove a portion of the m-th second substrate dielectric layer to expose at least a portion of the second target pad layer to form the second substrate layer.

[0249] A portion of the m-th second substrate dielectric layer 202 can be removed to expose at least a portion of the second target pad layer 23 it covers, facilitating electrical connection with an external circuit structure. After exposing at least a portion of the second target pad layer 23, the m-th second substrate dielectric layer 202 can be used as the second substrate layer 2. It is understood that the m-th second substrate dielectric layer 202 can form the second substrate layer 2.

[0250] Optionally, before opening a window in the m-th layer of the second substrate dielectric layer 202, the surface of the m-th layer of the second substrate dielectric layer 202 can be ground smooth before opening the window. For example, an entire surface of an exposeable organic layer can be formed on the surface of the m-th layer of the second substrate dielectric layer 202 through processes including but not limited to coating, printing, bonding, and molding. Then, through an exposure and development process, the exposeable organic layer is patterned to form at least one opening, exposing a portion of the m-th layer of the second substrate dielectric layer 202 through the at least one opening. Then, an etching process is performed to etch away a portion of the m-th layer of the second substrate dielectric layer 202 (i.e., the portion located within the at least one opening), thereby exposing at least a portion of the second target pad layer 23 covered by the m-th layer of the second substrate dielectric layer 202.

[0251] For example, in Figures 12A to 12N In the preparation process shown, such as... Figure 12M As shown, a portion of the m=5th second substrate dielectric layer 202 can be removed, thereby exposing at least a portion of the second target pad layer 23, and subsequently, based on the m=5th second substrate dielectric layer 202, the second substrate layer 2 can be formed. It should be understood that here... Figures 12A to 12N The layers shown in the preparation process are merely examples and are not intended to limit the embodiments of this application.

[0252] It should be understood that, through the optional solutions of steps S1042 to S1046 described above, on the one hand, a second substrate layer 2 embedded with a second interconnecting line layer 21, at least one second line layer 22, and a second target pad layer 23 can be effectively fabricated, so that the second interconnecting line layer 21 and the first interconnecting line layer 13 can be effectively electrically connected, and the second target pad layer 23 is at least partially exposed, thereby facilitating the fabrication of the substrate structure 110; on the other hand, the above optional technical solutions fabricate the second line layer 22 and the second interconnecting line layer 21 by electroplating, which is convenient to manufacture and has good conductivity and signal integrity. The electroplated metal lines have high surface flatness, which can effectively reduce impedance mismatch problems in signal transmission. Furthermore, since the above-mentioned optional technical solutions are fabrication processes of the first connection line layer 13 and the second connection line layer 21 in sequence, it is easier to make the electrical connection between the first connection line layer 13 and the second connection line layer 21 more stable and the electrical connection performance better. Moreover, the electrical connection can be formed without relying on solder, so that the solder interface between the first substrate layer 1 and the second substrate layer 2 can be avoided. Therefore, the disadvantage of unstable packaging structure of substrate structure 110 caused by soldering can be avoided, and packaging costs can also be effectively reduced.

[0253] In this application, after the second substrate layer 2 is prepared in step S104, the wafer 10 can be removed in step S106. Removal can be performed in any manner, such as etching or polishing. The entire wafer 10 can be removed, or only a portion of the wafer 10 can be removed if necessary.

[0254] In some optional embodiments, step S106 may include: thinning the wafer 10 that is in contact with the first surface of the first substrate layer 1 until the thickness is less than or equal to 30 μm; and etching the thinned wafer 10 to expose the first target pad layer 11 from the first surface of the first substrate layer 1 outward.

[0255] The etching process for wafer 10 can be performed using dry etching, wet etching, or a combination of both. For example, in some examples, sulfur hexafluoride gas can be used to etch wafer 10, or a hydrofluoric acid-containing agent can be used for etching.

[0256] It should be understood that in this application, the wafer 10 is first thinned to less than or equal to 30 μm, and then the thinned wafer 10 is etched. This can effectively remove at least part of the wafer 10 to expose the first target pad layer 11 from the first surface of the first substrate layer 1. This makes it easier for the first target pad layer 11 of the obtained substrate structure 110 to be electrically connected to the chip 3, including but not limited to external components. It can also ensure the stress balance of the substrate structure 110 after removing the wafer 10, reduce the risk of cracking the first substrate layer 1 when removing the wafer 10, and thus improve the quality of the substrate structure 110.

[0257] For example, in Figures 12A to 12N In the preparation process shown, such as... Figure 12N As shown, it can be Figure 12M The structure prepared in the process is inverted so that wafer 10 faces upwards. Wafer 10 is then thinned and etched to remove it, exposing the first target pad layer 11 from the first surface of the first substrate layer 1. This process yields the substrate structure 110. It should be understood that here... Figures 12A to 12N The layers shown in the preparation process are merely examples and are not intended to limit the embodiments of this application.

[0258] It is understood that the above description of the preparation method of the embodiments of this application is only as some optional exemplary description of the technical solution of the embodiments of this application, and is not intended to limit the embodiments of this application.

[0259] According to a sixth aspect of the embodiments of this application, a method for fabricating a substrate structure is provided. This fabrication method can fabricate the substrate structure 110 described in the first aspect above. For example... Figure 9 The flowchart shown illustrates that the preparation method includes the following steps S202 and S204, specifically:

[0260] S202: A second substrate layer is formed, which is embedded with a second connection line layer with sequential electrical connections, at least one second line layer and a second target pad layer, and the second connection line layer and the second target pad layer are exposed outward from two surfaces of the second substrate layer perpendicular to the thickness direction, respectively.

[0261] S204: On the side of the second substrate layer where the second connection line layer is exposed, a first substrate layer is formed with a first connection line layer, at least one first line layer and a first target pad layer embedded therein, so as to obtain a substrate structure, wherein the first connection line layer is electrically connected to the second connection line layer, and the first target pad layer is exposed outward from the first substrate layer.

[0262] The prepared substrate structure 110 also satisfies at least one of the following conditions: the minimum linewidth of the lines in the second line layer 22, the minimum linewidth of the lines in the second connection line layer 21, and the minimum linewidth of the lines in the first connection line layer 13 are all greater than the minimum linewidth of the lines in the first line layer 12; the minimum line spacing of the lines in the second line layer 22, the minimum line spacing of the lines in the second connection line layer 21, and the minimum line spacing of the lines in the first connection line layer 13 are all greater than the minimum line spacing of the lines in the first line layer 12.

[0263] It should be understood that, through the preparation method of steps S202 to S204 described above in this application, a substrate structure 110 including a first substrate layer 1 and a second substrate layer 2 can be effectively prepared. The first substrate layer 1 is embedded with a first target pad layer 11, at least one first circuit layer 12, and a first connection line layer 13, which are electrically connected layer by layer. The second substrate layer 2 is embedded with a second connection line layer 21, at least one second circuit layer 22, and a second target pad layer 23, which are electrically connected layer by layer. The second connection line layer 21 is electrically connected to the first connection line layer 13. Furthermore, the substrate structure 110 satisfies the following conditions: "the minimum linewidth of the lines in the second circuit layer 22, the minimum linewidth of the lines in the second connection line layer 21, and the minimum linewidth of the lines in the first connection line layer 13 are all greater than the minimum linewidth of the lines in the first circuit layer 12," and "the minimum line spacing of the lines in the second circuit layer 22, the minimum line spacing of the lines in the second connection layer 22, and the minimum linewidth of the lines in the second connection layer 13 are all greater than the minimum linewidth of the lines in the first circuit layer 12," and "the minimum line spacing of the lines in the second circuit layer 22, the minimum line spacing of the lines in the second connection layer 22, and the minimum line spacing ...." The minimum line spacing of the lines in the circuit layer 21 and the minimum line spacing of the lines in the first interconnecting circuit layer 13 are both greater than at least one of the minimum line spacing of the lines in the first circuit layer 12. This results in a smaller line width and / or line spacing of the lines in the first circuit layer 12, which facilitates the realization of high-density circuits and interconnections, and is beneficial to improving the integration of the prepared substrate structure 110. On the other hand, since the preparation of the substrate structure 110 in the above preparation method does not rely on the through silicon via (TSV) process, the preparation cost is lower, the manufacturing process complexity is lower, and the substrate structure 110 can have a better yield. Furthermore, since the substrate structure 110 prepared by the above preparation method has a better integration and yield, when the substrate structure 110 is used with the chip 3 to make the chip packaging module 100, the chip packaging module 100 can also have a better integration and yield.

[0264] To facilitate understanding of the fabrication method of the substrate structure 110 in the sixth aspect, it can be combined with Figures 13A to 13N The example fabrication process of the substrate structure shown is for understanding purposes; alternatively, this example fabrication process can be used to fabricate, for example... Figure 2B The substrate structure 110 shown is shown.

[0265] It should be understood that, unlike the preparation method provided in the fifth aspect, the preparation method of the substrate structure 110 provided in the sixth aspect of this application can first form the second substrate layer 2 and then prepare the first substrate layer 1.

[0266] Optionally, the second substrate layer 2 can be an organic insulating layer. The second substrate layer 2 can be fabricated using organic insulating materials through processes including but not limited to coating, printing, bonding, and molding, as described in the foregoing embodiments, and will not be repeated here. For example, the organic insulating layer is made of at least one of polyimide (PI) materials, epoxy resin materials, and silane materials.

[0267] Optionally, the second substrate layer 2 may be embedded with 1 to 10 second circuit layers 22.

[0268] In some optional embodiments, the linewidth of the lines in the second line layer 22 is 2µm to 8µm.

[0269] In some optional embodiments, the linewidth of the lines in the second connection layer 21 is 2µm to 8µm.

[0270] In some optional embodiments, the line spacing in the second line layer 22 is 2µm to 8µm.

[0271] In some optional embodiments, the line spacing in the second connection line layer 21 is 2µm to 8µm.

[0272] In some alternative embodiments, the second target pad layer 23 is used to connect other external circuit structures.

[0273] It should be understood that the contents and beneficial effects of the second circuit layer 22, the second connection circuit layer 21, and the second target pad layer 23 can also be referred to the description in the previous embodiment of substrate structure 110, and will not be repeated here.

[0274] In some alternative embodiments, refer to Figure 10 As shown in the flowchart, the second substrate layer 2 can be implemented through the following steps S2022 to S2026, specifically:

[0275] S2022: On the first substrate, a second interconnect layer is formed by electroplating.

[0276] In this application, the first carrier plate 51 can be used as a support structure to facilitate the fabrication of the first substrate layer 1. After the first substrate layer 1 is fabricated, the first carrier plate 51 can be removed.

[0277] For example, such as Figures 13A to 13N The fabrication process of some other examples of substrate structure 110 is shown. For example, in one of them... Figure 13AAs shown, a second interconnection layer 21 can be formed on the first substrate 51 by electroplating.

[0278] For example, in one example, a seed metal layer can be formed on the entire surface of the first substrate 51 by a low-temperature sputtering process or a metal foil process, and then a barrier layer can be formed on the seed metal layer, such that the barrier layer defines at least one barrier opening. Then, the seed metal layer can be energized and electroplated with an electroplating metal material to form an electroplated metal layer on the seed metal layer within at least one barrier opening. Then, the barrier layer and the portion of the seed metal layer covered by the barrier layer are removed, along with the portion of the seed metal layer remaining on the first substrate and the electroplated metal layer, so that the second connection line layer 21 can be effectively formed on the first substrate 51.

[0279] It should be noted that the electroplating process here is similar in principle to the electroplating method of the second circuit layer 22 described below (such as steps S2024A to S2024E), and can also be understood in conjunction with the previous text.

[0280] S2024: On the first substrate on which the second connection line layer is formed, m second substrate dielectric layers are formed sequentially, and between each two adjacent second substrate dielectric layers in the first to m-1 layers, one second line layer is formed by electroplating, and a second target pad layer is formed between the m-1 to m layers, and the second connection line layer, at least one second line layer and the second target pad layer are electrically connected layer by layer, wherein m≥3 and m is an integer.

[0281] Optionally, the second substrate layer 2 can be an organic insulating layer, and correspondingly, the aforementioned m-layer second substrate dielectric layer 202 can be an organic insulating layer. When forming the second substrate dielectric layer 202, processes including but not limited to coating, printing, bonding, and encapsulation can be used to fabricate the second substrate dielectric layer 202 using organic insulating materials.

[0282] Optionally, in the above-mentioned m-layer second substrate dielectric layer 202, during the preparation of the second substrate layer 2, the first layer of the second substrate dielectric layer 202 may cover the second connection line layer 21, the second to m-1 layers of the second substrate dielectric layer 202 may respectively cover the first to m-2 layers of the second line layer 22, and the m-layer of the second substrate dielectric layer 202 may cover the second target pad layer 23.

[0283] In some optional embodiments, step S2024, "forming one second circuit layer between every two adjacent second substrate dielectric layers in the first to m-1 layers by electroplating," may include: forming the j-th second circuit layer by the following steps S2024A to S2024E, where 1≤j≤m-2:

[0284] S2024A: A window is made in the dielectric layer of the j-th second substrate so that the dielectric layer of the j-th second substrate exposes the second target portion of the second interconnection line layer or the second line layer it covers.

[0285] For example, in Figures 13A to 13N In the preparation process shown, such as... Figure 13B The diagram illustrates a second target portion of the second interconnection layer 21 exposed by the first layer second substrate dielectric layer 202 after a window is made in the first layer second substrate dielectric layer 202. The same logic applies when j is a different value.

[0286] S2024B: A second seed metal layer is formed above the second substrate dielectric layer of the j-th layer, wherein the second seed metal layer covers the second target portion.

[0287] Optionally, the second seed metal layer is formed by a sputtering process or a metal foil process.

[0288] For example, in Figures 13A to 13N In the preparation process shown, such as... Figure 13C As shown, a second seed metal layer 32 is formed above the first layer second substrate dielectric layer 202, wherein the second seed metal layer 32 covers the second target portion of the second interconnection layer 21 exposed from the opening in the first layer second substrate dielectric layer 202. The same principle applies when j is a different value.

[0289] S2024C: A second enclosure layer is formed on the second seed metal layer, wherein the second enclosure layer defines at least one second enclosure opening, wherein the vertical projection of the at least one second enclosure opening on the first carrier plate overlaps with the vertical projection of the second target portion on the first carrier plate.

[0290] For example, in Figures 13A to 13N In the preparation process shown, such as... Figure 13D As shown, a second enclosure layer 42 can be formed on the second seed metal layer 32, the second enclosure layer 42 defining at least one second enclosure opening 421, wherein the vertical projection of at least one second enclosure opening 421 on the first carrier plate 51 overlaps with the vertical projection of the second target portion on the first carrier plate 51.

[0291] S2024D: A second electroplated metal layer is formed on the third portion of the second seed metal layer inside the second enclosure opening by electroplating.

[0292] For example, in Figures 13A to 13N In the preparation process shown, such as... Figure 13EAs shown, a second electroplated metal layer 221 can be formed on the third portion of the second seed metal layer 32 within the second enclosure opening 421 by electroplating.

[0293] S2024E: Remove the second enclosure layer and the fourth portion of the second seed metal layer except for the third portion, so as to form the j-th second circuit layer through the third portion of the second seed metal layer and the second electroplated metal layer.

[0294] For example, in Figures 13A to 13N In the preparation process shown, such as... Figure 13F As shown, the second enclosure layer 42 and the fourth portion of the second seed metal layer 32, excluding the third portion, can be removed to form the first second circuit layer 22 through the third portion of the second seed metal layer 32 and the second electroplated metal layer 221. This can be deduced similarly for other values ​​of j.

[0295] The steps S2024A to S2024E above can be understood by referring to the relevant explanations of steps S1044A to S1044E in the fifth aspect above. The principles and implementation processes of the two are similar, so they will not be repeated here.

[0296] Based on this, in this application, the j-th second circuit layer 22 can be effectively electroplated through the above steps S2024A to S2024E, and each second circuit layer 22 in the second substrate layer 2 can be effectively obtained in this manner. Furthermore, the second connection circuit layer 21 and at least one second circuit layer 22 can be electrically connected layer by layer. In addition, the second circuit layer 22 obtained by electroplating in the above manner is easy to manufacture and has good conductivity and signal integrity. The surface flatness of the electroplated metal circuit is high, which can effectively reduce the impedance mismatch problem in signal transmission.

[0297] For example, in Figures 13A to 13N In the preparation process shown, such as... Figure 13G , Figure 13H , Figure 13I As shown, the second, third, and fourth second substrate dielectric layers 202, as well as the second and third second circuit layers 22, can be fabricated in a similar manner to the first second circuit layer 22, until all second circuit layers 22 are fabricated.

[0298] Optionally, a second target pad layer 23 may be formed between the second substrate dielectric layers 202 of the m-1 to m layers by electroplating. For example, in one example, a seed metal layer can be formed on the entire surface of the second substrate dielectric layer 202 of the (m-1)th layer by a low-temperature sputtering process or a metal foil process. Then, a barrier layer is formed on the seed metal layer, and the barrier layer defines at least one barrier opening. After that, the seed metal layer can be energized and electroplated with an electroplating metal material to form an electroplated metal layer on the seed metal layer within at least one barrier opening. The vertical projection of the barrier opening on the first carrier board 51 overlaps with the vertical projection of the second target portion of the second circuit layer 22 exposed from the second substrate dielectric layer 202 on the first carrier board 51, so as to realize the electrical connection between the second circuit layer 22 and the fabricated second target pad layer 23. Then, the barrier layer and the portion of the seed metal layer covered by the barrier layer are removed. The portion of the seed metal layer remaining on the second substrate dielectric layer 202 can effectively form the second target pad layer 23 on the second substrate dielectric layer 202.

[0299] It should be noted that the electroplating process here is similar in principle to the electroplating method of the second circuit layer 22 mentioned above (such as steps S2024A to S2024E), and can also be understood in conjunction with the previous text.

[0300] After the second target pad layer 23 is prepared, the m-th second substrate dielectric layer 202 can be prepared on the second target pad layer 23, and the m-th second substrate dielectric layer 202 can fully cover the second target pad layer 23.

[0301] For example, in Figures 13A to 13N In the preparation process shown, such as... Figure 13I As shown, a second target pad layer 23 can be prepared, and the prepared m=5th second substrate dielectric layer 202 covers the second target pad layer 23.

[0302] S2026: Remove a portion of the m-th second substrate dielectric layer to expose at least part of the second target pad layer, and then remove the first carrier board to form the second substrate layer.

[0303] A portion of the m-th second substrate dielectric layer 202 can be removed to expose at least a portion of the second target pad layer 23 it covers, facilitating electrical connection with an external circuit structure. After exposing at least a portion of the second target pad layer 23, the m-th second substrate dielectric layer 202 can be used as the second substrate layer 2. It is understood that the m-th second substrate dielectric layer 202 can form the second substrate layer 2. The first carrier board is removed to expose the second interconnection layer 21, facilitating further fabrication of the first substrate layer 1.

[0304] Optionally, before opening a window in the m-th layer of the second substrate dielectric layer 202, the surface of the m-th layer of the second substrate dielectric layer 202 can be ground smooth before opening the window. For example, an entire surface of an exposeable organic layer can be formed on the surface of the m-th layer of the second substrate dielectric layer 202 through processes including but not limited to coating, printing, bonding, and molding. Then, through an exposure and development process, the exposeable organic layer is patterned to form at least one opening, exposing a portion of the m-th layer of the second substrate dielectric layer 202 through the at least one opening. Then, an etching process is performed to etch away a portion of the m-th layer of the second substrate dielectric layer 202 (i.e., the portion located within the at least one opening), thereby exposing at least a portion of the second target pad layer 23 covered by the m-th layer of the second substrate dielectric layer 202.

[0305] For example, in Figures 13A to 13N In the preparation process shown, such as... Figure 13J As shown, a portion of the m=4th second substrate dielectric layer 202 can be removed, thereby exposing at least a portion of the second target pad layer 23, and the first carrier board 51 can then be removed. Based on the m=5th second substrate dielectric layer 202, the second substrate layer 2 can be formed. It should be understood that here... Figures 13A to 13N The layers shown in the preparation process are merely examples and are not intended to limit the embodiments of this application.

[0306] It should be understood that, through the optional solutions of steps S2022 to S2026 above, this application can effectively prepare a second substrate layer 2 embedded with a second connection line layer 21, at least one second line layer 22, and a second target pad layer 23 that are electrically connected layer by layer, so that the second connection line layer 21 and the first connection line layer 13 can be effectively electrically connected, and the second target pad layer 23 is at least partially exposed, thereby facilitating the preparation of the substrate structure 110. On the other hand, the above optional technical solutions prepare the second line layer 22 and the second connection line layer 21 by electroplating, which is convenient to manufacture and has good conductivity and signal integrity. The surface flatness of the electroplated metal lines is high, which can effectively reduce the impedance mismatch problem in signal transmission.

[0307] In this application, after the second substrate layer 2 is prepared in step S202, the first substrate layer 1 can be prepared in step S204.

[0308] The first substrate layer 1 can be formed using any suitable material. Optionally, in step S202 of this application, forming the first substrate layer 1 on the exposed side of the second connection line layer 21 on the second substrate layer 2 can be a SiO2 layer forming the first substrate layer 1 on the exposed side of the second connection line layer 21 on the second substrate layer 2. The specific process and beneficial effects can be referred to the foregoing embodiments, and will not be repeated here. Optionally, the first substrate layer 1 can be embedded with 1 to 10 first line layers 12.

[0309] In some alternative embodiments, the linewidth of the lines in the first line layer 12 is less than or equal to 2 μm.

[0310] In some optional embodiments, the linewidth of the lines in the first line layer 12 is 0.2µm to 2µm.

[0311] In some optional embodiments, the line width of the lines in the first connection line layer 13 is 2µm to 8µm.

[0312] In some alternative embodiments, the line spacing in the first line layer 12 is less than or equal to 2 μm.

[0313] In some optional embodiments, the line spacing in the first line layer 12 is 0.2µm to 2µm.

[0314] In some optional embodiments, the line spacing in the first connection line layer 13 is 2µm to 8µm.

[0315] In some alternative embodiments, the first target pad layer 11 is used to connect the chip.

[0316] It should be understood that the contents and beneficial effects of the first circuit layer 12, the first connection circuit layer 13, and the first target pad layer 11 can also be referred to the description in the previous embodiment of the substrate structure 110, and will not be repeated here.

[0317] This application does not limit the specific fabrication method of the first substrate layer 1. Optionally, when fabricating the first substrate layer 1, the second substrate layer 2 can be disposed on the second carrier plate, and the exposed side of the first target pad layer 11 of the second substrate layer 2 can be attached to the second carrier plate 52. That is, the second substrate layer 2 prepared in step S202 can be placed upside down on the second carrier plate, and the second carrier plate 52 supports the second substrate layer 2 to facilitate the subsequent fabrication of the first substrate layer 1.

[0318] In some alternative embodiments, refer to Figure 11 The flowchart shown illustrates that the first substrate layer 1 can be implemented through the following steps S2042 to S2046, specifically:

[0319] S2042: On the side of the second substrate layer where the second connection line layer is exposed, a first connection line layer that is electrically connected to the second connection line layer is formed by electroplating.

[0320] For example, such as Figures 13A to 13N The fabrication process of some examples of substrate structure 110 is shown. For example, in... Figure 13K As shown, it can be Figure 13JThe structure of the prepared second substrate layer 2 is inverted on the second carrier plate 52, so that the first connection line layer 13, which is electrically connected to the second connection line layer 21, is formed on the second side of the second substrate layer 2 by electroplating.

[0321] For example, in one example, a seed metal layer can be formed on the exposed side of the second connection line layer 21 on the second substrate layer 2 (e.g., this side can be formed by the m-th layer of the first substrate dielectric layer 201) by low-temperature sputtering or metal foil pressing. Then, a barrier layer is formed on the seed metal layer, and the barrier layer defines at least one barrier opening. After that, the seed metal layer can be energized and electroplated with an electroplating metal material to form an electroplated metal layer on the seed metal layer within at least one barrier opening. The vertical projection of the barrier opening on the second substrate layer 2 overlaps with the vertical projection of the portion of the second connection line layer 21 exposed from the second substrate layer 2 on the second substrate layer 2, so as to realize the electrical connection between the second connection line layer 21 and the fabricated first connection line layer 13. Then, the barrier layer and the portion of the seed metal layer covered by the barrier layer are removed. The portion of the seed metal layer remaining on the second substrate layer 2 and the electroplated metal layer can be effectively formed on the exposed side of the second connection line layer 21 on the second substrate layer 2.

[0322] It should be noted that the electroplating process here is similar in principle to the electroplating method of the first circuit layer 12 described below (such as steps S2044A to S2044E), and can also be understood in conjunction with the previous text.

[0323] S2044: n first substrate dielectric layers are sequentially formed above the first interconnection line layer formed on the second substrate layer, and between each two adjacent first substrate dielectric layers in the first to n-1 layers, a first line layer is formed by electroplating, and a first target pad layer is formed between the n-1 to n layers, and the first interconnection line layer, at least one first line layer, and the first target pad layer are electrically connected layer by layer, wherein n≥3 and n is an integer.

[0324] Optionally, the first substrate layer 1 can be a SiO2 layer, and its process is as described in the previous embodiments, and will not be repeated here.

[0325] Optionally, in the above-mentioned n-layer first substrate dielectric layer 201, during the fabrication process of the first substrate layer 1, the first substrate dielectric layer 201 may cover the first interconnection line layer 13, the second to n-1 first substrate dielectric layers 201 may respectively cover the first to n-2 first line layers 12, and the n-layer first substrate dielectric layer 201 may cover the first target pad layer 11. For example, refer to... Figures 13A to 13N The preparation process shown is explained.

[0326] This application does not limit the specific implementation of step S1042. In some optional embodiments, step S2044, "forming one first circuit layer between every two adjacent first substrate dielectric layers in the first to n-1 first substrate dielectric layers by electroplating", may include: forming the i-th first circuit layer by the following steps S2044A to S2044E, where 1≤i≤n-2:

[0327] S2044A: A window is made in the first substrate dielectric layer of the i-th layer, so that the first interconnect line layer or the first target portion of the first line layer covered by the first substrate dielectric layer is exposed.

[0328] S2044B: A first seed metal layer is formed above the first substrate dielectric layer of the i-th layer, wherein the first seed metal layer covers the first target portion;

[0329] Optionally, the first seed metal layer is formed by sputtering or metal foil pressing.

[0330] S2044C: A first enclosure layer is formed on a first seed metal layer, wherein the first enclosure layer defines at least one first enclosure opening, wherein the vertical projection of at least one first enclosure opening on a second substrate layer overlaps with the vertical projection of the first target portion on a second substrate layer.

[0331] S2044D: A first electroplated metal layer is formed on a first portion of a first seed metal layer within a first enclosure opening by electroplating.

[0332] S2044E: Remove the first enclosure layer and the second portion of the first seed metal layer other than the first portion, so as to form the i-th first circuit layer through the first portion of the first seed metal layer and the first electroplated metal layer.

[0333] The steps S2044A to S2044E above can be understood by referring to the relevant explanations of steps S1024A to S1024E in the fifth aspect above. The principles and implementation processes of the two are similar, and will not be repeated here. The difference between the first target part here and the first target part in the fifth aspect above is that the first target part here is the first target part of the first connection line layer 13 or the first target part of the first line layer 12, while the first target part in the fifth aspect above is the first target part of the first target pad layer 11 or the first target part of the first line layer 12.

[0334] Based on this, the first circuit layer 12 of the i-th layer can be effectively electroplated through the above steps S2044A to S2044E in this application, and each first circuit layer 12 in the first substrate layer 1 can be effectively obtained in this way. It can also make the first connection circuit layer 13 and at least one first circuit layer 12 electrically connected layer by layer. In addition, the first circuit layer 12 obtained by electroplating in the above way is easy to manufacture and has good conductivity and signal integrity. The surface flatness of the electroplated metal circuit is high, which can effectively reduce the impedance mismatch problem in signal transmission. Furthermore, since the above optional technical solution is the sequential superposition of the fabrication processes of the second connection circuit layer 21 and the first connection circuit layer 13, it is easier to make the electrical connection between the first connection circuit layer 13 and the second connection circuit layer 21 more stable and the electrical connection performance better. Moreover, it can form an electrical connection without relying on solder, so that the solder interface between the first substrate layer 1 and the second substrate layer 2 can be avoided. Therefore, the disadvantage of unstable packaging structure of substrate structure 110 caused by soldering can be avoided, and packaging costs can also be effectively reduced.

[0335] Optionally, a first target pad layer 11 may be formed between the n-1 to nth first substrate dielectric layers 201 by electroplating. For example, in one example, a seed metal layer can be formed on the entire surface of the (n-1)th layer of the first substrate dielectric layer 201 by a low-temperature sputtering process or a metal foil process. Then, a barrier layer is formed on the seed metal layer, and the barrier layer defines at least one barrier opening. After that, the seed metal layer can be energized and electroplated with an electroplating metal material to form an electroplated metal layer on the seed metal layer within the at least one barrier opening. The vertical projection of the barrier opening on the second substrate layer 2 overlaps with the vertical projection of the first target portion of the first circuit layer 12 exposed from the (n-1)th layer of the first substrate dielectric layer 201 on the second substrate layer 2, so as to realize the electrical connection between the first circuit layer 12 and the fabricated first target pad layer 11. Then, the barrier layer and the portion of the seed metal layer covered by the barrier layer are removed. The portion of the seed metal layer remaining on the (n-1)th layer of the first substrate dielectric layer 201 can effectively form the first target pad layer 11 on the (n-1)th layer of the first substrate dielectric layer 201.

[0336] It should be noted that the electroplating process here is similar in principle to the electroplating method of the first circuit layer 12 mentioned above (such as steps S2044A to S2044E), and can also be understood in conjunction with the previous text.

[0337] After the first target pad layer 11 is prepared, the nth first substrate dielectric layer 201 can be prepared on the first target pad layer 11, and the nth first substrate dielectric layer 201 can fully cover the first target pad layer 11.

[0338] For example, in Figures 13A to 13N In the preparation process shown, such as... Figure 13L As shown, n=4 layers of first substrate dielectric layer 201, 2 layers of first circuit layer 12 and 1 layer of first target pad layer 11 can be prepared by the aforementioned optional method, and the first connection circuit layer 13, the 2 layers of first circuit layer 12 and the 1 layer of first target pad layer 11 are electrically connected layer by layer, and the prepared n=4th layer of first substrate dielectric layer 201 covers the first target pad layer 11.

[0339] S2046: Remove a portion of the nth first substrate dielectric layer to expose at least a portion of the first target pad layer to form the first substrate layer.

[0340] A portion of the nth first substrate dielectric layer 201 can be removed to expose at least a portion of the first target pad layer 11 it covers, facilitating electrical connection with the chip 3. After exposing at least a portion of the first target pad layer 11, the nth first substrate dielectric layer 201 can be used as the first substrate layer 1. It is understood that the nth first substrate dielectric layer 201 can form the first substrate layer 1.

[0341] Optionally, before opening a window in the nth layer of the first substrate dielectric layer 201, the surface of the nth layer of the first substrate dielectric layer 201 can be ground flat before opening the window. For example, an entire surface of an exposeable organic layer can be formed on the surface of the nth layer of the first substrate dielectric layer 201 through processes including but not limited to coating, printing, bonding, and molding. Then, the exposeable organic layer can be patterned through an exposure and development process to form at least one opening, exposing a portion of the nth layer of the first substrate dielectric layer 201 through the at least one opening. Then, an etching process can be performed to etch away a portion of the nth layer of the first substrate dielectric layer 201 (i.e., the portion located within the at least one opening), thereby exposing at least a portion of the first target pad layer 11 covered by the nth layer of the first substrate dielectric layer 201.

[0342] For example, in Figures 13A to 13N In the preparation process shown, such as... Figure 13M As shown, a portion of the n=4th first substrate dielectric layer 201 can be removed, thereby exposing at least a portion of the first target pad layer 11, and subsequently, the first substrate layer 1 can be formed based on the n=4th first substrate dielectric layer 201. It should be understood that here... Figures 13A to 13N The layers shown in the preparation process are merely examples and are not intended to limit the embodiments of this application.

[0343] It should be understood that, through the optional solutions of steps S2042 to S2046 described above, this application can effectively prepare a first substrate layer 1 embedded with a first connection line layer 13, at least one first line layer 12, and a first target pad layer 11, which are electrically connected layer by layer. This allows the first connection line layer 13 and the second connection line layer 21 to be effectively electrically connected, and at least partially exposes the first target pad layer 11, thereby facilitating the preparation of the substrate structure 110. Furthermore, the optional technical solutions described above prepare the first line layer 12 and the first connection line layer 13 through electroplating, which is convenient to manufacture and provides good conductivity and signal integrity. The electroplated metal lines have high surface flatness, which can effectively reduce impedance mismatch problems in signal transmission. Furthermore, since the above-mentioned optional technical solutions are fabrication processes of the second connection line layer 21 and the first connection line layer 13 in sequence, it is easier to make the electrical connection between the first connection line layer 13 and the second connection line layer 21 more stable and the electrical connection performance better. Moreover, the electrical connection can be formed without relying on solder, so that the solder interface between the first substrate layer 1 and the second substrate layer 2 can be avoided. Therefore, the disadvantages of unstable packaging structure of substrate structure 110 caused by soldering can be avoided, and packaging costs can also be effectively reduced.

[0344] Optionally, when a second carrier plate is used, it can be removed after the first substrate layer 1 is fabricated to obtain the substrate structure 110. For example, in Figures 13A to 13N In the preparation process shown, such as... Figure 13N As shown, the second carrier plate 52 is removed to obtain the substrate structure 110. It should be understood that here... Figures 13A to 13N The layers shown in the preparation process are merely examples and are not intended to limit the embodiments of this application.

[0345] It is understood that the above description of the preparation method of the embodiments of this application is only as some optional exemplary description of the technical solution of the embodiments of this application, and is not intended to limit the embodiments of this application.

[0346] The optional embodiments of the present application have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present application are not limited thereto. It should be noted that, for the convenience of explaining the embodiments of the present application, the various drawings of the embodiments of the present application are not necessarily drawn to scale, and are only used to facilitate the explanation of the technical solution, and are not intended to limit the embodiments of the present application in any way. Within the scope of the technical concept of the embodiments of the present application, various simple modifications can be made to the technical solutions of the embodiments of the present application. The various technical features included in the different embodiments of the present application can be combined and / or separated in any suitable manner. In order to avoid unnecessary repetition, the embodiments of the present application will not describe the various possible combinations separately. However, these simple modifications and combinations should also be regarded as the content disclosed in the embodiments of the present application, and all fall within the protection scope of the embodiments of the present application.

[0347] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". It should be noted that the concepts of "first", "second", etc., mentioned in this application are only used to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies. It should be noted that the modifications "a" and "a plurality" mentioned in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly indicated in the context, they should be understood as "one or more".

[0348] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A substrate structure, comprising: The first substrate layer includes a first surface and a second surface perpendicular to the thickness direction, wherein the first surface and the second surface of the first substrate layer are opposite to each other. The first substrate layer is embedded with a first target pad layer, at least one first circuit layer and a first connection circuit layer that are electrically connected layer by layer. The first target pad layer is located on the first side of the first substrate layer and the first connection circuit layer is located on the second side of the first substrate layer. The second substrate layer is adjacent to the second side of the first substrate layer and is embedded with a second connection line layer, at least one second line layer and a second target pad layer that are electrically connected layer by layer. The second connection line layer is electrically connected to the first connection line layer. The substrate structure also satisfies at least one of the following conditions: The minimum linewidth of the lines in the second line layer, the minimum linewidth of the lines in the second connecting line layer, and the minimum linewidth of the lines in the first connecting line layer are all greater than the minimum linewidth of the lines in the first line layer. The minimum line spacing of the lines in the second line layer, the minimum line spacing of the lines in the second connecting line layer, and the minimum line spacing of the lines in the first connecting line layer are all greater than the minimum line spacing of the lines in the first line layer.

2. The substrate structure according to claim 1, wherein, The circuitry in at least one of the first circuit layer, the first connection circuit layer, the second connection circuit layer, and the second circuit layer includes electroplated metal circuitry.

3. The substrate structure according to claim 2, wherein, The circuits in at least one of the first circuit layer, the first connection circuit layer, the second connection circuit layer, and the second circuit layer include metal stacked circuits, and at least one metal layer of the metal stacked circuit is an electroplated metal layer.

4. The substrate structure according to claim 3, wherein, The metal stacked circuit includes a first metal layer and a second metal layer, and the first metal layer and the second metal layer are made of different materials; Furthermore, at least a portion of the second metal layer is the electroplated metal layer, and the thickness of the electroplated metal layer is greater than the thickness of the first metal layer; The second metal layer is a copper layer, and the first metal layer is a titanium layer.

5. The substrate structure according to claim 2, wherein, The circuits in at least one of the first circuit layer, the first connection circuit layer, the second connection circuit layer, and the second circuit layer are single-layer metal circuits, and at least a portion of the single-layer metal circuits are electroplated metal.

6. The substrate structure according to any one of claims 1-5, wherein, The substrate structure satisfies at least one of the following conditions: The first substrate layer is a SiO2 layer; The second substrate layer is an organic insulating layer, wherein the organic insulating layer is made of at least one of polyimide materials, epoxy resin materials, and silane materials; The first substrate layer is embedded with 1 to 10 first circuit layers; The second substrate layer is embedded with 1 to 10 second circuit layers; The line width of the lines in the first line layer is less than or equal to 2µm; The line width of the lines in the first line layer is 0.2um to 2um; The line width of the lines in the first connection line layer is 2um to 8um; The line width of the lines in the second connection layer is 2µm to 8µm; The linewidth of the lines in the second line layer is 2µm to 8µm; The line spacing in the first line layer is less than or equal to 2 μm; The line spacing in the first line layer is 0.2um to 2um; The line spacing in the first connection line layer is 2um to 8um; The line spacing in the second connection layer is 2µm to 8µm; The line spacing in the second line layer is 2µm to 8µm; The first target pad layer is used to connect the chip.

7. A substrate mother plate, comprising: The substrate structures are as described in any one of claims 1-6, wherein the substrate structures are arranged in a strip-like interval along a predetermined direction, or the substrate structures are arranged in a panel-level matrix, or the substrate structures are distributed within a predetermined circumference.

8. A chip packaging module, comprising: The substrate structure as described in any one of claims 1-6; The chip is electrically connected to the first target pad layer or the second target pad layer of the substrate structure.

9. An electronic device, comprising: The chip packaging module as described in claim 8.

10. A method for fabricating a substrate structure, comprising: A first substrate layer is formed on a wafer. The first substrate layer is embedded with a first target pad layer, at least one first circuit layer, and a first connection circuit layer that are electrically connected layer by layer. The first substrate layer includes a first surface and a second surface perpendicular to the thickness direction. The first surface and the second surface of the first substrate layer are opposite to each other. The first surface of the first substrate layer is in contact with the wafer. The first target pad layer is located on the first surface of the first substrate layer. The first connection circuit layer is located on the second surface of the first substrate layer and is exposed from the second surface of the first substrate layer. On the second side of the first substrate layer, a second substrate layer is formed with a second connection line layer, at least one second line layer and a second target pad layer embedded in it, and the second connection line layer is electrically connected to the first connection line layer exposed from the second side of the first substrate layer, and the second target pad layer is exposed outward from the second substrate layer. At least partially remove the wafer that is in contact with the first side of the first substrate layer, so that the first target pad layer is exposed outward from the first side of the first substrate layer to obtain a substrate structure; The prepared substrate structure also satisfies at least one of the following conditions: The minimum linewidth of the lines in the second line layer, the minimum linewidth of the lines in the second connecting line layer, and the minimum linewidth of the lines in the first connecting line layer are all greater than the minimum linewidth of the lines in the first line layer. The minimum line spacing of the lines in the second line layer, the minimum line spacing of the lines in the second connecting line layer, and the minimum line spacing of the lines in the first connecting line layer are all greater than the minimum line spacing of the lines in the first line layer.

11. The method according to claim 10, wherein, The first substrate layer is formed in the following manner: A first target pad layer is formed on the wafer; Above the first target pad layer formed on the wafer, n first substrate dielectric layers are sequentially formed. Between each two adjacent first substrate dielectric layers in the first to n-1 layers, a first circuit layer is formed by electroplating. Between the n-1 to n first substrate dielectric layers, a first connection circuit layer is formed by electroplating. The first target pad layer, at least one first circuit layer, and the first connection circuit layer are electrically connected layer by layer. Wherein, n≥3 and n is an integer. A portion of the nth first substrate dielectric layer is removed to expose at least a portion of the first interconnect layer in order to form the first substrate layer.

12. The method according to claim 11, wherein, Between each pair of adjacent first substrate dielectric layers in the first substrate layers 1 to n-1, a first circuit layer is formed by electroplating, including: The first line layer of the i-th layer is formed in the following way, where 1≤i≤n-2: A window is made in the first substrate dielectric layer of the i-th layer, so that the first target portion of the first target pad layer or the first circuit layer covered by the first substrate dielectric layer is exposed; A first seed metal layer is formed above the first substrate dielectric layer of the i-th layer, wherein the first seed metal layer covers the first target portion, and the first seed metal layer is formed by sputtering or metal foil pressing. A first enclosure layer is formed on the first seed metal layer, wherein the first enclosure layer defines at least one first enclosure opening, wherein the vertical projection of the at least one first enclosure opening on the wafer overlaps with the vertical projection of the first target portion on the wafer. A first electroplated metal layer is formed on a first portion of the first seed metal layer within the first enclosure opening by electroplating. Remove the first enclosure layer and the second portion of the first seed metal layer other than the first portion, so as to form the i-th first circuit layer through the first portion of the first seed metal layer and the first electroplated metal layer.

13. The method according to claim 10, wherein, The second substrate layer is formed in the following manner: On the second side of the first substrate layer, a second connection line layer is formed by electroplating, which is electrically connected to the first connection line layer exposed from the second side of the first substrate layer; m second substrate dielectric layers are sequentially formed above the second connection line layer. Between each two adjacent second substrate dielectric layers in the first to m-1 layers, a second line layer is formed by electroplating. A second target pad layer is formed between the m-1 to m layers. The second connection line layer, at least one second line layer, and the second target pad layer are electrically connected layer by layer. Here, m ≥ 3 and m is an integer. A portion of the m-th second substrate dielectric layer is removed to expose at least a portion of the second target pad layer, thereby forming the second substrate layer.

14. The method according to claim 13, wherein, Between each pair of adjacent second substrate dielectric layers in layers 1 to m-1, a second circuit layer is formed by electroplating, including: The second line layer of the j-th layer is formed in the following manner, where 1≤j≤m-2: A window is made in the dielectric layer of the j-th second substrate so that the dielectric layer of the j-th second substrate exposes the second connection line layer or the second target portion of the second line layer that it covers; A second seed metal layer is formed above the j-th layer of the second substrate dielectric layer, wherein the second seed metal layer covers the second target portion, and the second seed metal layer is formed by sputtering or metal foil pressing. A second enclosure layer is formed on the second seed metal layer, wherein the second enclosure layer defines at least one second enclosure opening, wherein the vertical projection of the at least one second enclosure opening on the wafer overlaps with the vertical projection of the second target portion on the wafer. A second electroplated metal layer is formed on the third portion of the second seed metal layer inside the second enclosure opening by electroplating. Remove the second enclosure layer and the fourth portion of the second seed metal layer other than the third portion, so as to form the j-th second circuit layer through the third portion of the second seed metal layer and the second electroplated metal layer.

15. The method according to any one of claims 10-14, wherein, The step of at least partially removing the wafer in contact with the first surface of the first substrate layer, so that the first target pad layer is exposed outward from the first surface of the first substrate layer, includes: The wafer in contact with the first side of the first substrate layer is thinned until the thickness is less than or equal to 30 μm. The thinned wafer is etched to expose the first target pad layer from the first surface of the first substrate layer.

16. The method according to any one of claims 10-14, wherein, The prepared substrate structure also satisfies at least one of the following conditions: The first substrate layer is a SiO2 layer; The second substrate layer is an organic insulating layer, wherein the organic insulating layer is made of at least one of polyimide materials, epoxy resin materials, and silane materials; The first substrate layer is embedded with 1 to 10 first circuit layers; The second substrate layer is embedded with 1 to 10 second circuit layers; The line width of the lines in the first line layer is 0.2um to 2um; The line width of the lines in the first connection line layer is 2um to 8um; The line width of the lines in the second connection layer is 2µm to 8µm; The linewidth of the lines in the second line layer is 2µm to 8µm; The line spacing in the first line layer is 0.2um to 2um; The line spacing in the first connection line layer is 2um to 8um; The line spacing in the second connection layer is 2µm to 8µm; The line spacing in the second line layer is 2µm to 8µm; The first target pad layer is used to connect the chip.

17. A method for preparing a substrate structure, comprising: A second substrate layer is formed, which is embedded with a second connection line layer, at least one second line layer and a second target pad layer, wherein the second connection line layer and the second target pad layer are exposed outward from two surfaces of the second substrate layer perpendicular to the thickness direction; On the side of the second substrate layer where the second interconnection layer is exposed, a first substrate layer is formed with a first interconnection layer, at least one first line layer and a first target pad layer embedded therein, so as to obtain a substrate structure, wherein the first interconnection layer is electrically connected to the second interconnection layer, and the first target pad layer is exposed outward from the first substrate layer. The prepared substrate structure also satisfies at least one of the following conditions: The minimum linewidth of the lines in the second line layer, the minimum linewidth of the lines in the second connecting line layer, and the minimum linewidth of the lines in the first connecting line layer are all greater than the minimum linewidth of the lines in the first line layer. The minimum line spacing of the lines in the second line layer, the minimum line spacing of the lines in the second connecting line layer, and the minimum line spacing of the lines in the first connecting line layer are all greater than the minimum line spacing of the lines in the first line layer.

18. The preparation method according to claim 17, wherein, The second substrate layer, which is embedded with a second interconnection layer, at least one second circuit layer, and a second target pad layer, includes: On the first substrate, a second interconnect layer is formed by electroplating; On the first substrate on which the second connection line layer is formed, m second substrate dielectric layers are formed sequentially. Between each two adjacent second substrate dielectric layers in the first to m-1 layers, one second line layer is formed by electroplating. A second target pad layer is formed between the m-1 to m layers. The second connection line layer, at least one second line layer, and the second target pad layer are electrically connected layer by layer. Where m ≥ 3 and m is an integer. A portion of the m-th second substrate dielectric layer is removed to expose at least a portion of the second target pad layer, and then the first carrier board is removed to form the second substrate layer.

19. The preparation method according to claim 18, wherein, Between each pair of adjacent second substrate dielectric layers in layers 1 to m-1, a second circuit layer is formed by electroplating, including: The second line layer of the j-th layer is formed in the following manner, where 1≤j≤m-2: A window is made in the dielectric layer of the j-th second substrate so that the dielectric layer of the j-th second substrate exposes the second connection line layer or the second target portion of the second line layer that it covers; A second seed metal layer is formed above the j-th layer of the second substrate dielectric layer, wherein the second seed metal layer covers the second target portion, and the second seed metal layer is formed by sputtering or metal foil pressing. A second enclosure layer is formed on the second seed metal layer, wherein the second enclosure layer defines at least one second enclosure opening, wherein the vertical projection of the at least one second enclosure opening on the first carrier plate overlaps with the vertical projection of the second target portion on the first carrier plate. A second electroplated metal layer is formed on the third portion of the second seed metal layer inside the second enclosure opening by electroplating. Remove the second enclosure layer and the fourth portion of the second seed metal layer other than the third portion, so as to form the j-th second circuit layer through the third portion of the second seed metal layer and the second electroplated metal layer.

20. The preparation method according to claim 17, wherein, The first substrate layer, on the side of the second substrate layer where the second interconnection layer is exposed, forms a first substrate layer embedded with a first interconnection layer electrically connected layer by layer, at least one first circuit layer, and a first target pad layer, including: On the side of the second substrate layer where the second connection line layer is exposed, a first connection line layer electrically connected to the second connection line layer is formed by electroplating. Above the first interconnection layer formed on the second substrate layer, n first substrate dielectric layers are sequentially formed. Between each two adjacent first substrate dielectric layers in the first to n-1 layers, one first circuit layer is formed by electroplating. A first target pad layer is formed between the n-1 to n first substrate dielectric layers. The first interconnection layer, at least one first circuit layer, and the first target pad layer are electrically connected layer by layer. Wherein, n≥3 and n is an integer. A portion of the nth first substrate dielectric layer is removed to expose at least a portion of the first target pad layer, thereby forming the first substrate layer.

21. The preparation method according to claim 20, wherein, Between each pair of adjacent first substrate dielectric layers in the first substrate layers 1 to n-1, a first circuit layer is formed by electroplating, including: The first line layer of the i-th layer is formed in the following way, where 1≤i≤n-2: A window is made in the first substrate dielectric layer of the i-th layer, so that the first interconnect line layer or the first target portion of the first line layer covered by the first substrate dielectric layer is exposed. A first seed metal layer is formed above the first substrate dielectric layer of the i-th layer, wherein the first seed metal layer covers the first target portion, and the first seed metal layer is formed by sputtering or metal foil pressing. A first enclosure layer is formed on the first seed metal layer, wherein the first enclosure layer defines at least one first enclosure opening, wherein the vertical projection of the first enclosure opening on the second substrate layer overlaps with the vertical projection of the first target portion on the second substrate layer. A first electroplated metal layer is formed on a first portion of the first seed metal layer within the first enclosure opening by electroplating. Remove the first enclosure layer and the second portion of the first seed metal layer other than the first portion, so as to form the i-th first circuit layer through the first portion of the first seed metal layer and the first electroplated metal layer.

22. The method according to any one of claims 17-21, wherein, The prepared substrate structure also satisfies at least one of the following conditions: The first substrate layer is a SiO2 layer; The second substrate layer is an organic insulating layer, wherein the organic insulating layer is made of at least one of polyimide materials, epoxy resin materials, and silane materials; The first substrate layer is embedded with 1 to 10 first circuit layers; The second substrate layer is embedded with 1 to 10 second circuit layers; The line width of the lines in the first line layer is 0.2um to 2um; The line width of the lines in the first connection line layer is 2um to 8um; The line width of the lines in the second connection layer is 2µm to 8µm; The linewidth of the lines in the second line layer is 2µm to 8µm; The line spacing in the first line layer is 0.2um to 2um; The line spacing in the first connection line layer is 2um to 8um; The line spacing in the second connection layer is 2µm to 8µm; The line spacing in the second line layer is 2µm to 8µm; The first target pad layer is used to connect the chip.

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