A glass-based heterogeneous integrated packaging structure for enhanced heat dissipation and its fabrication method

Abstract

This invention relates to a glass-based heterogeneous integrated packaging structure and its fabrication method for enhanced heat dissipation. The invention includes a glass PCB motherboard; a first diamond heat dissipation film layer disposed on the surface of the glass PCB motherboard; a glass interposer substrate, on the upper and lower surfaces of which a second and third diamond heat dissipation film layer are respectively disposed, the third diamond heat dissipation film layer being connected to the first diamond heat dissipation film layer; the glass interposer substrate having an array of through-hole (TGV) structures, a portion of which is filled with metal conductors, and a titanium-tungsten buffer layer is disposed between the TGV structures and the metal conductors; the remaining portion of which is open as heat dissipation vias; and a CPU / GPU chip and an HBM module connected to the second diamond heat dissipation film layer. This invention achieves a balance between high-density interconnection, low signal loss, high reliability, and efficient heat dissipation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a glass-based heterogeneous integrated packaging structure and its preparation method that enhances heat dissipation. Background Technology

[0002] With the surge in demand for computing power and bandwidth from artificial intelligence (AI) computing and high-performance computing, traditional organic substrates and silicon interposers are no longer sufficient to meet the evolving needs of packaging technology. Organic substrates suffer from issues such as a mismatch between their thermal expansion coefficients and those of silicon chips, high high-frequency signal loss, and poor scalability; while silicon interposers face bottlenecks such as high cost, warpage during large-area fabrication, and low utilization rates in panel-level packaging. In 2.5D / 3D packaging, the increased chip stacking density leads to increasingly prominent issues related to signal integrity, thermal management (especially heat dissipation bottlenecks under high heat flux densities), and mechanical reliability. Existing substrate materials and heat dissipation solutions have become key factors restricting breakthroughs in system performance.

[0003] Currently, Chip-on-Wafer-on-Substrate (CoWoS) is a common 2.5D integration method that integrates high-density high-end CPUs / GPUs (Central Processing Units / Graphics Processing Units) onto a wafer interposer, then onto a substrate, and finally to a PCB. A typical example is the NVIDIA H200. The biggest drawback of this method is the difference in materials between the chip (Si), substrate, and PCB, resulting in significant differences in their coefficients of thermal expansion (CTE). During chip packaging integration, this mismatch in CTE leads to high stress or warpage, ultimately causing warpage and package reliability issues. Furthermore, in System-on-Wafer (SOW) integration, [further details are needed]. Figure 2 As shown, similar issues exist. Therefore, it is necessary to adjust the difference in coefficient of thermal expansion (CTE) using a PCB adapter to make the system CTE more compatible; otherwise, high-yield system integration cannot be achieved.

[0004] Glass materials possess advantages such as low coefficient of thermal expansion, high flatness, low dielectric loss, excellent chemical stability, and potential for large-scale production. Their surface roughness is less than 10 nanometers, allowing for panel-level packaging area utilization of up to 93%, and reducing costs by more than 66% compared to silicon substrates. However, existing glass substrate technologies suffer from low processing efficiency of through-glass vias (TGV), poor interfacial compatibility with heterogeneous materials, and fragility. Furthermore, they lack efficient heat dissipation designs adapted to glass substrate architectures, and have not yet achieved efficient heterogeneous integration with CPU and GPU chips or achieved heat dissipation balance under high heat flux densities.

[0005] Therefore, developing a glass-based packaging structure and fabrication method that balances high-density interconnection, low signal loss, high reliability, and efficient heat dissipation has become a pressing technical challenge for the industry. Summary of the Invention

[0006] Therefore, the present invention provides a glass-based heterogeneous integrated packaging structure and preparation method for enhancing heat dissipation, which takes into account high-density interconnection, low signal loss, high reliability and efficient heat dissipation.

[0007] To address the aforementioned technical problems, this invention provides a glass-based heterogeneous integrated packaging structure for enhanced heat dissipation, comprising: Glass PCB motherboard; A first diamond heat dissipation film layer is disposed on the surface of the glass PCB motherboard; A glass interposer substrate has a second diamond heat dissipation film layer and a third diamond heat dissipation film layer respectively disposed on its upper and lower surfaces. The third diamond heat dissipation film layer is connected to the first diamond heat dissipation film layer. The glass interposer substrate has an array of glass via (TGV) structures. A portion of the glass via (TGV) structures is filled with a metal conductor, and a titanium-tungsten buffer layer is disposed between the glass via (TGV) structure and the metal conductor. The other portion of the glass via (TGV) structures is open as heat dissipation vias. The CPU / GPU chip and HBM module are connected to the second diamond heat dissipation film layer.

[0008] In one embodiment of the present invention, a first solder ball array is disposed between the third diamond heat dissipation film layer and the first diamond heat dissipation film layer, and a second solder ball array is disposed between the CPU / GPU chip and the HBM module and the second diamond heat dissipation film layer, respectively.

[0009] In one embodiment of the present invention, the first solder ball array and the second solder ball array are made of tin material.

[0010] In one embodiment of the present invention, thermally conductive copper plating is respectively provided on the surfaces of the first diamond heat dissipation film layer and the second diamond heat dissipation film layer.

[0011] In one embodiment of the present invention, the glass interlayer substrate is made of chemically strengthened glass material with a surface roughness ≤10nm, thermal conductivity ≥20W / (m·K), and dielectric constant ≤5.0.

[0012] In one embodiment of the present invention, the diameter of the glass through-hole TGV structure is no greater than 10 micrometers and the aspect ratio is no less than 1:15.

[0013] In one embodiment of the present invention, the glass via TGV structure adopts a wavy interconnect pattern to reduce the increase in equivalent resistance caused by the high-frequency skin effect.

[0014] In one embodiment of the present invention, the metal conductor is a copper conductor.

[0015] In one embodiment of the present invention, a redistribution layer RDL is provided on the glass interposer substrate, and the CPU chip and the GPU chip are interconnected through the RDL.

[0016] This invention also provides a method for fabricating a glass-based heterogeneous integrated packaging structure with enhanced heat dissipation, comprising: The glass interlayer substrate pretreatment step involves chemically strengthening the borosilicate glass and improving its edge mechanical strength, and then using a polishing process to ensure that the surface roughness meets the requirements. The TGV structure fabrication steps involve femtosecond laser-induced modification and wet etching to form a glass-through-hole TGV structure; after depositing a titanium-tungsten buffer layer on the hole wall of the glass-through-hole TGV structure, copper electroplating is used to achieve metal conductor filling. The fabrication steps of the circuit and optical waveguide are as follows: a redistribution layer RDL is prepared on the surface of a glass interlayer substrate, and a buried optical waveguide is fabricated on a glass PCB motherboard by silver ion exchange method. In the 2.5D integration step, a diamond heat dissipation film layer is bonded to the upper surface of the glass PCB motherboard and the upper and lower surfaces of the glass interlayer substrate through a titanium-tungsten transition layer. The bonding adopts a low-temperature bonding process of 40 degrees Celsius. The CPU / GPU chip is connected to the glass interlayer substrate by low-temperature differential thermocompression bonding to complete the HBM module connection and installation.

[0017] The technical solution of the present invention has the following advantages compared with the prior art: This invention discloses a glass-based heterogeneous integrated packaging structure and its fabrication method for enhanced heat dissipation. The structure uses modified and strengthened glass as the core carrier and achieves 2.5D interposer integration and 3D stacking integration of CPU, GPU, AI chips, high-bandwidth memory (HBM), and optical interconnect modules through glass via (TGV) 3D interconnect technology, optical waveguide integration technology, and heterogeneous interface buffer design. Simultaneously, a diamond heat dissipation film is added between the chip and the glass interposer to enhance heat dissipation in high heat flux density areas. The low coefficient of thermal expansion (3-9ppm / K) of the glass substrate is highly compatible with silicon chips, effectively solving the warpage problem of traditional organic substrates. Its low dielectric constant and low dielectric loss characteristics reduce signal transmission loss at 10GHz by more than 45%. The glass PCB employs high-precision fine-line processing technology, supporting line widths and spacings below 5μm / 5μm, fully meeting the requirements of high-density interconnection. This invention overcomes the bottlenecks of existing packaging technologies in bandwidth density, power efficiency, and size scalability, and can be widely applied in high-end scenarios such as AI computing, high-performance servers, GPUs, and CPUs. Attached Figure Description

[0018] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0019] Figure 1 This is a schematic diagram of the glass-based heterogeneous integrated packaging structure for enhanced heat dissipation according to the present invention.

[0020] Figure 2 This is a schematic diagram of a typical 2.5D (CoWoS) integrated package structure.

[0021] Explanation of reference numerals on the accompanying drawings: 1. Glass PCB motherboard; 11. Thermally conductive copper plating; 2. First diamond heat dissipation film layer; 3. Glass interposer substrate; 31. Glass through-hole (TGV) structure; 32. Heat dissipation via; 33. Metal conductor; 4. Second diamond heat dissipation film layer; 5. Third diamond heat dissipation film layer; 6. CPU / GPU chip; 7. HBM module; 81. First solder ball array; 82. Second solder ball array. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0023] In this invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this invention, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0024] In this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc., are understood to exclude the stated number; "above," "below," "within," etc., are understood to include the stated number. In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0025] In this invention, unless otherwise explicitly defined, the terms "setting," "installing," and "connecting" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this invention based on the specific content of the technical solution.

[0026] Reference Figure 1 As shown, a glass-based heterogeneous integrated packaging structure for enhanced heat dissipation according to the present invention includes: Glass PCB motherboard 1; A first diamond heat dissipation film layer 2 is disposed on the surface of the glass PCB motherboard 1; A glass interposer substrate 3 has a second diamond heat dissipation film layer 4 and a third diamond heat dissipation film layer 5 respectively disposed on its upper and lower surfaces. The third diamond heat dissipation film layer 5 is connected to the first diamond heat dissipation film layer 2. The glass interposer substrate 3 is provided with an array of glass through-hole (TGV) structures 31. A portion of the glass through-hole TGV structures 31 is filled with a metal conductor 33, and a titanium-tungsten buffer layer is disposed between the glass through-hole TGV structures 31 and the metal conductor 33. The other portion of the glass through-hole TGV structures 31 is open as heat dissipation vias 32. The CPU / GPU chip 6 and the HBM module 7 are connected to the second diamond heat dissipation film layer 4.

[0027] In one embodiment, a first solder ball array 81 is provided between the third diamond heat dissipation film layer 5 and the first diamond heat dissipation film layer 2, and a second solder ball array 82 is provided between the CPU / GPU chip 6 and the HBM module 7 and the second diamond heat dissipation film layer 4, respectively.

[0028] In one embodiment, the first solder ball array 81 and the second solder ball array 82 are made of tin.

[0029] In one embodiment, thermally conductive copper plating 11 is respectively provided on the surfaces of the first diamond heat dissipation film layer 2 and the second diamond heat dissipation film layer 4.

[0030] In one embodiment, the glass interlayer substrate 3 is made of chemically strengthened glass material with a surface roughness ≤10nm, thermal conductivity ≥20W / (m·K), and dielectric constant ≤5.0.

[0031] In one embodiment, the diameter of the glass through-hole TGV structure 31 is no greater than 10 micrometers, and the aspect ratio is no less than 1:15.

[0032] In one embodiment, the glass via TGV structure 31 employs a wavy interconnect pattern to reduce the increase in equivalent resistance caused by the high-frequency skin effect.

[0033] In one embodiment, the metal conductor 33 is a copper conductor.

[0034] In one embodiment, a redistribution layer RDL is provided on the glass interposer substrate 3, and the CPU chip and the GPU chip are interconnected through the RDL.

[0035] In one embodiment, the glass PCB motherboard 1 integrates a buried optical waveguide structure, fabricated using an ion-exchange method, achieving a propagation loss as low as 0.06 dB / cm at communication wavelengths, enabling efficient optical signal transmission. The glass PCB motherboard 1 has a reserved interface for a fiber optic array unit (FAU), achieving precise coupling with the optical I / O chip through V-groove positioning technology. The optical interconnect unit includes an optical I / O chip and a fiber optic array unit (FAU). The optical I / O chip has a V-groove and a metamaterial spot size converter at its edge, docking with the FAU through active coupling technology, achieving an insertion loss ≤ -2.5 dB.

[0036] The FAU was actively coupled to the optical I / O chip and fixed with a hybrid adhesive. The average insertion loss was -2.4 dB with a standard deviation of 0.3 dB.

[0037] Replacing the silicon-based wafer interposer with a glass interposer using glass wafer vias (TGV) minimizes the thermal expansion coefficient mismatch during heterogeneous integration of high-density silicon chips and glass TGV structures. After completing CoG (Chip On Glass) integration, the glass PCB employs a typical mSAP (modified semi-additive process) and combines it with a PVD (Physical Vapor Deposition) thin copper seed layer for HDI (High Density Interconnect) process to achieve high-precision wiring. Simultaneously, passive and active devices can be embedded within the glass TGV and glass PCB, thereby achieving higher CTE matching at the system level and significantly reducing thermal stress and warpage during packaging manufacturing and service.

[0038] By employing a near-junction heat dissipation design with a diamond thermal film, low thermal resistance heat dissipation channels can be constructed in high heat flux density areas of the chip, reducing the junction temperature by more than 25 degrees Celsius. Furthermore, the heat dissipation efficiency of the 2.5D integrated structure is improved by more than 60% compared to traditional solutions. After 3D stacking, a three-dimensional heat dissipation network composed of the diamond thermal film, copper-filled thermal vias, and interlayer interface thermal paths further enhances heat diffusion and vertical heat conduction, effectively suppressing heat buildup caused by high-density stacking. Simultaneously, the diamond thermal film exhibits good compatibility with the glass substrate and silicon chip, improving heat dissipation capacity while avoiding the introduction of additional thermal stress, thus achieving a balance between high integration, low signal loss, and high heat dissipation efficiency.

[0039] It should be noted that existing CoWoS typically uses a silicon interposer in conjunction with an organic substrate to connect to the PCB. The thermal expansion coefficients of silicon, organic substrate, and PCB are significantly different, which can easily generate high thermal stress and warping during hot-press bonding, reflow soldering, and temperature cycling, leading to problems such as solder joint fatigue, interface delamination, and decreased reliability.

[0040] This invention uses a glass interlayer and a glass PCB motherboard 1 as the core carrier to form a glass-based packaging system, which significantly improves the matching of the thermal expansion coefficients of the key packaging layers, reduces thermal stress concentration and warping from the structural source, and improves the manufacturing yield and service reliability of large-size panel-level packaging. It is especially suitable for high-computing power chips and high-density integration scenarios such as HBM.

[0041] CoWoS relies on high-end organic substrates, which are costly, limit size expansion, and are difficult to control warpage during large-area fabrication, resulting in limited effective area utilization. This invention employs a glass interlayer combined with an HDI glass PCB motherboard 1 based on mSAP (modified semi-additive process). This reduces reliance on high-cost organic substrate materials while achieving high-density interconnects, resulting in a simpler system hierarchy, more area-expansion-friendly design, and improved large-size packaging and mass production capabilities, thereby reducing overall packaging costs.

[0042] Organic substrates exhibit significant dielectric losses at high frequencies, and the trace dimensions are limited by process capabilities, making it difficult to simultaneously achieve high bandwidth and low loss. While silicon interposers can achieve high-density interconnects, cost and warpage issues restrict their application over larger areas.

[0043] This invention forms a high-precision redistribution layer on a glass interposer and uses mSAP to achieve high-density interconnect wiring on a glass PCB motherboard 1. The glass material itself has low dielectric loss and good dimensional stability, which can maintain impedance consistency and wiring accuracy over a large area, thereby improving the signal integrity of high-speed links, reducing insertion loss and crosstalk risk, and meeting the bandwidth density requirements of AI and high-performance computing.

[0044] CoWoS relies heavily on external components and board-level implementation during system-level integration, making it difficult to achieve higher-level functional integration and path shortening within the package. This invention embeds passive components such as resistors, capacitors, and inductors within the glass TGV structure and glass PCB, and can integrate some active functional units in combination with the design. This results in shorter power supply decoupling paths, lower parasitic parameters, further improved power integrity and high-speed signal quality, while reducing the number of external components and board area, thus improving system integration and miniaturization.

[0045] With increased chip stacking density, existing packages exhibit more concentrated hotspots and limited vertical heat dissipation paths, leading to heat buildup. Traditional heat dissipation solutions struggle to balance thermal resistance reduction with structural reliability. This invention introduces a near-junction heat dissipation design using a diamond thermal film. This design directly addresses high heat flux density areas of the chip, creating low thermal resistance channels for rapid hotspot diffusion and outflow, effectively reducing junction temperature and improving the heat dissipation efficiency of the 2.5D structure. In further 3D stacking, a three-dimensional heat dissipation network is constructed using the diamond thermal film, copper-filled thermal vias, and interlayer thermal paths, enhancing lateral diffusion and vertical heat conduction capabilities and significantly suppressing heat buildup in the stacked structure. Simultaneously, diamond exhibits good thermal expansion compatibility with glass and silicon systems, improving heat dissipation while avoiding the introduction of additional thermal stress, thus balancing thermal performance and reliability.

[0046] Silicon interposers rely on wafer-level processes, resulting in high costs and limitations on large-area expansion. Traditional board-level solutions also struggle to achieve the interconnect precision and performance of interposers. This invention employs glass through-hole (TEH) and glass HDI (High-Density Interconnect) processes, enabling the evolution towards panel-level manufacturing and mass production while maintaining high-density interconnects and low losses, thereby improving packaging consistency and cost competitiveness.

[0047] This embodiment also provides a method for fabricating a glass-based heterogeneous integrated packaging structure to enhance heat dissipation, including: The glass interlayer substrate 3 pretreatment step involves chemically strengthening the borosilicate glass and improving its edge mechanical strength, and then using a polishing process to ensure that the surface roughness meets the requirements. Borosilicate glass with a thickness of 500 micrometers was chemically strengthened for 2 hours and its surface roughness was reduced to 8 nanometers by mechanical polishing; the edges were optimized by laser cutting. The TGV structure fabrication steps involve femtosecond laser-induced modification and wet etching to form a glass-through-hole TGV structure 31. The femtosecond laser wavelength is 1030 nm with an energy density gradient of 1-3 μJ / pulse. Hydrofluoric acid solution is used for wet etching to form a glass-through-hole TGV structure 31 with a diameter of 8 μm and an aspect ratio of 1:20. The dimensional tolerance of the glass-through-hole TGV structure 31 is controlled within ±0.5 μm. The formation efficiency of the glass-through-hole TGV structure 31 is three times higher than that without laser-induced gradient modification. After depositing a titanium-tungsten buffer layer on the hole wall of the glass-through-hole TGV structure 31, copper electroplating is used to fill the metal conductor 33. The circuit and optical waveguide fabrication steps are as follows: a redistribution layer RDL is prepared on the surface of a glass interlayer substrate 3. The linewidth and line spacing of the redistribution layer RDL are 2 micrometers and 2 micrometers, respectively. A buried optical waveguide is fabricated on a glass PCB motherboard 1 by silver ion exchange method, so that the propagation loss of the buried optical waveguide is 0.05dB / cm. In the 2.5D integration step, a diamond heat dissipation film layer is bonded to the upper surface of the glass PCB motherboard 1 and the upper and lower surfaces of the glass interlayer substrate 3 through a titanium-tungsten transition layer. The thickness of the diamond heat dissipation film is 200 micrometers, and the thickness of the titanium-tungsten transition layer is 50 nanometers. The bonding adopts a low-temperature bonding process of 40 degrees Celsius. The CPU / GPU chip 6 is connected to the glass interlayer substrate 3 by low-temperature differential thermocompression bonding, wherein the temperature difference between the CPU / GPU chip 6 and the glass interlayer substrate 3 is no more than 50 degrees Celsius. The connection and installation of the HBM module 7 are completed.

[0048] By deeply integrating glass-based materials, diamond-enhanced heat dissipation, and packaging technology, a brand-new solution is provided for the high-density integration of CPUs and GPUs. It has significant advantages in high integration, high energy efficiency, low cost, and high heat dissipation efficiency, and can drive the semiconductor packaging industry towards high integration, high energy efficiency, low power consumption, and high reliability.

[0049] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A glass-based heterogeneous integrated packaging structure for enhanced heat dissipation, characterized in that, include: Glass PCB motherboard (1); A first diamond heat dissipation film layer (2) is disposed on the surface of the glass PCB motherboard (1); A glass interlayer substrate (3) has a second diamond heat dissipation film layer (4) and a third diamond heat dissipation film layer (5) respectively disposed on its upper and lower surfaces. The third diamond heat dissipation film layer (5) is connected to the first diamond heat dissipation film layer (2). The glass interlayer substrate (3) is provided with an array of glass through-hole TGV structures (31). A portion of the glass through-hole TGV structures (31) is filled with metal conductors (33), and a titanium tungsten buffer layer is disposed between the glass through-hole TGV structures (31) and the metal conductors (33). Another portion of the glass through-hole TGV structures (31) is open as heat dissipation vias (32). The CPU / GPU chip (6) and the HBM module (7) are connected to the second diamond heat dissipation film layer (4).

2. The glass-based heterogeneous integrated packaging structure for enhanced heat dissipation according to claim 1, characterized in that, A first solder ball array (81) is provided between the third diamond heat dissipation film layer (5) and the first diamond heat dissipation film layer (2), and a second solder ball array (82) is provided between the CPU / GPU chip (6) and the HBM module (7) and the second diamond heat dissipation film layer (4), respectively.

3. The glass-based heterogeneous integrated packaging structure for enhanced heat dissipation according to claim 2, characterized in that, The first solder ball array (81) and the second solder ball array (82) are made of tin.

4. The glass-based heterogeneous integrated packaging structure for enhanced heat dissipation according to claim 1, characterized in that, The first diamond heat dissipation film layer (2) and the second diamond heat dissipation film layer (4) are respectively provided with a thermally conductive copper plating layer (11).

5. The glass-based heterogeneous integrated packaging structure for enhanced heat dissipation according to claim 1, characterized in that, The glass interlayer substrate (3) is made of chemically strengthened glass material with a surface roughness ≤10nm, thermal conductivity ≥20W / (m·K) and dielectric constant ≤5.

0.

6. The glass-based heterogeneous integrated packaging structure for enhanced heat dissipation according to claim 1, characterized in that, The diameter of the glass through-hole TGV structure (31) is no greater than 10 micrometers and the aspect ratio is no less than 1:

15.

7. The glass-based heterogeneous integrated packaging structure for enhanced heat dissipation according to claim 1, characterized in that, The glass through-hole TGV structure (31) adopts a wavy interconnect pattern to reduce the increase in equivalent resistance caused by the high-frequency skin effect.

8. The glass-based heterogeneous integrated packaging structure for enhanced heat dissipation according to claim 1, characterized in that, The metal conductor (33) is a copper conductor.

9. The glass-based heterogeneous integrated packaging structure for enhanced heat dissipation according to claim 1, characterized in that, The glass interposer substrate (3) is provided with a redistribution layer RDL, and the CPU chip and the GPU chip are interconnected through the RDL.

10. A method for fabricating a glass-based heterogeneous integrated packaging structure with enhanced heat dissipation, characterized in that, include: The glass interlayer substrate (3) pretreatment step is to chemically strengthen the borosilicate glass and improve the edge mechanical strength, and to use a polishing process to make the surface roughness meet the standard. The TGV structure fabrication steps involve using femtosecond laser-induced modification and wet etching to form a glass through-hole TGV structure (31); after depositing a titanium-tungsten buffer layer on the hole wall of the glass through-hole TGV structure (31), copper electroplating is used to fill the metal conductor (33); The fabrication steps of the circuit and optical waveguide are as follows: a redistribution layer RDL is prepared on the surface of a glass interlayer substrate (3), and a buried optical waveguide is fabricated on a glass PCB motherboard (1) by silver ion exchange method. 2.5D integration step: diamond heat dissipation film layer is bonded to the upper surface of glass PCB motherboard (1) and the upper and lower surfaces of glass interlayer substrate (3) through titanium tungsten transition layer; CPU / GPU chip (6) is connected to glass interlayer substrate (3) by low temperature differential thermocompression welding to complete the connection and installation of HBM module (7).

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