Chip structure and method of manufacturing the same

Abstract

A chip structure and its fabrication method are disclosed. The chip structure includes a base layer, multiple chip units spaced apart on the base layer, each chip unit including a first surface and a third surface disposed opposite to each other, the third surface being disposed close to the base layer, and the first surface being the working surface of the chip unit; and a protective layer disposed at least on the sidewall of each chip unit, the protective layer being made of a material with a hardness value of 300HB to 500HB. This chip structure effectively improves the chip's bending resistance, effectively solves the chip cracking problem in chip stacking, reduces the chip cracking defect rate, and is conducive to maximizing the chip's storage capacity.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, specifically to a chip structure and its fabrication method. Background Technology

[0002] 3D memory chip technology offers significant advantages in storage density, performance, and energy efficiency. The thicker internal circuitry of 3D chips optimizes signal transmission and management, improving data processing performance and system stability. However, current manufacturing processes limit the minimum thickness of mass-produced chips to 38μm. With the increasing thickness of the internal circuitry in 3D chips—currently around 24μm—the silicon dioxide layer becomes thinner, reducing the chip's ability to withstand bending stress during production and use. This results in poorer chip toughness and stability, leading to lower product yields. Summary of the Invention

[0003] In view of this, this application provides a chip structure with good bending resistance.

[0004] In addition, this application also provides a method for fabricating the aforementioned chip structure.

[0005] This application provides a chip structure, which includes:

[0006] grassroots

[0007] Multiple chip units are spaced apart on the substrate. Each chip unit includes a first surface and a third surface disposed opposite to each other. The third surface is disposed close to the substrate, and the first surface is the working surface of the chip unit.

[0008] A protective layer is provided on at least the sidewall of each of the chip units, and the material of the protective layer has a hardness value of 300HB to 500HB.

[0009] In some possible embodiments, the protective layer also extends to the third surface.

[0010] In some possible embodiments, the thickness of the protective layer is 3 μm to 20 μm.

[0011] In some possible embodiments, the protective layer is made of a metallic material.

[0012] In some possible embodiments, the metallic material includes at least one of chromium, tungsten, titanium, and steel.

[0013] Additionally, this application also provides a method for fabricating a chip structure, comprising the following steps:

[0014] A groove is formed from a first surface of the wafer toward a second surface of the wafer, wherein the first surface and the second surface are disposed opposite to each other.

[0015] A carrier plate is formed on the first surface;

[0016] A portion of the wafer is removed from one side of the second surface toward the first surface to form a plurality of spaced-apart chip cells on the carrier. Each chip cell includes the first surface and a third surface disposed opposite to the first surface, wherein the first surface is the working surface of the chip cell.

[0017] A protective layer is formed on at least one sidewall of each of the chip cells, the protective layer being made of a material with a hardness value of 300 HB to 500 HB; and

[0018] A base layer is formed on the surface of all the chip cells facing away from the carrier, and the carrier is removed to obtain the chip structure.

[0019] In some possible embodiments, in the step of forming a protective layer on at least the sidewall of each of the chip cells, the protective layer further extends to the third surface.

[0020] In some possible embodiments, the step of forming the protective layer on at least the sidewalls of each of the chip cells includes:

[0021] The protective layer is formed on the sidewall of each chip cell and on the third surface; and

[0022] The protective layer located on the third surface is removed, and a portion of the chip cell is removed from the third surface toward the first surface to thin the chip cell.

[0023] In some possible embodiments, the method for forming the protective layer includes vapor deposition.

[0024] In some possible embodiments, the thickness of the protective layer is 3 μm to 20 μm.

[0025] Compared to existing technologies, the chip structure provided in this application uses a material with a high hardness of 300HB to 500HB to form a protective layer on at least the sidewalls of the chip unit. This effectively improves the chip structure's resistance to bending, making it suitable for ultra-thin chips and balancing the requirements of lightweight and high strength. This chip structure not only improves the chip's mechanical properties and reduces the risk of breakage due to external impacts, but also provides excellent external protection against chemical corrosion and physical wear, thereby ensuring the long-term stability and reliability of the chip in various application scenarios. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a chip structure provided in an embodiment of this application.

[0027] Figure 2 This is a schematic diagram of a chip structure provided in another embodiment of this application.

[0028] Figure 3 This is a process flow diagram of a chip structure fabrication method according to an embodiment of this application.

[0029] Figure 4 This is a schematic diagram of the structure of a wafer provided in one embodiment of this application.

[0030] Figure 5 In order to be in Figure 4 The diagram shows a structure with grooves formed on the wafer.

[0031] Figure 6 For Figure 5 The diagram shows a structure in which a carrier plate is formed on the first surface of the wafer.

[0032] Figure 7 To remove Figure 6 A schematic diagram of the structure of a chip unit formed by the middle part of the wafer.

[0033] Figure 8 For Figure 7 A schematic diagram of the structure in which a protective layer is formed on the sidewalls and third surface of the chip unit.

[0034] Figure 9 For Figure 8 A schematic diagram of the structure in which a base layer is formed on the surface of the chip unit away from the carrier board.

[0035] Figure 10 To remove Figure 6 A schematic diagram of the structure of a chip unit formed by the middle part of the wafer.

[0036] Figure 11 For Figure 10 A schematic diagram of the structure in which a protective layer is formed on the sidewalls and third surface of the chip unit.

[0037] Figure 12 To Figure 11 A schematic diagram of the chip unit being thinned.

[0038] Figure 13 For Figure 12 A schematic diagram of the structure in which a base layer is formed on the surface of the chip unit away from the carrier board. Detailed Implementation

[0039] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0040] Please see Figure 1 As shown, this application embodiment provides a chip structure 100, which includes: a base layer 30, a plurality of chip units 10 disposed at intervals on the base layer 30, each chip unit 10 including a first surface 11 and a third surface 13 disposed opposite to each other, the third surface 13 being disposed close to the base layer 30, and the first surface 11 being the working surface of the chip unit 10; and a protective layer 20 disposed on at least the sidewall 14 of each chip unit 10, the protective layer 20 having a hardness value of 300HB to 500HB.

[0041] The chip structure 100 effectively improves its bending resistance by using a protective layer 20 with a hardness of 300 HB to 500 HB on at least the sidewalls 14 of the chip unit 10. When the hardness of the protective layer 20 is too low (less than 300 HB), its tensile strength and impact resistance are insufficient, which may make the chip structure 100 more susceptible to damage or deformation from external impacts, thus affecting the overall performance and reliability of the chip structure 100. Conversely, when the hardness of the protective layer 20 is too high (greater than 500 HB), although it enhances the bending resistance of the protective layer 20, it leads to increased brittleness, increasing the risk of brittle cracking of the chip structure 100 under certain environments, and reducing the durability and lifespan of the chip structure 100.

[0042] Specifically, in this embodiment, the protective layer 20 is located on the sidewall 14 and the third surface 13. Compared with the first surface 11, which is the main working surface, the third surface 13 of the chip unit 10 is generally used for heat dissipation and support. By providing the protective layer 20 on the third surface 13, not only is the bending resistance and durability of the overall structure of the chip structure 100 further enhanced, but the damage to the third surface 13 caused by external impact is also effectively prevented.

[0043] In some embodiments, the thickness of the protective layer 20 can be 3 μm to 20 μm. This thickness range helps to further maintain the good mechanical properties of the protective layer 20 and provide the chip structure 100 with bending resistance and heat dissipation performance. An appropriate thickness also helps to effectively block external physical damage and chemical corrosion, reducing the risk of chip structure 100 breakage, without significantly increasing the overall weight of the chip structure 100. The thickness of the protective layer 20 can further be 5 μm to 15 μm, and exemplary thicknesses can be 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, or 20 μm, etc.

[0044] In some embodiments, the protective layer 20 may be made of a metallic material, which can improve the mechanical strength of the chip structure 100, enhance its resistance to bending, and protect the internal chip unit 10 from damage.

[0045] In some embodiments, the aforementioned metallic material may include at least one of chromium, tungsten, titanium, and steel. These metallic materials possess excellent mechanical properties, corrosion resistance, and thermal conductivity, effectively improving the strength and toughness of the protective layer 20, enhancing the bending resistance of the chip structure 100, and improving the heat dissipation effect of the chip structure 100.

[0046] In some embodiments, the base layer 30 may include a die-attach film (DAF) with a thickness of 3 μm to 60 μm for encapsulation. Because the chip structure 100 has good compressive strength and bending resistance, a thinner DAF will not break or deform under stress, allowing for a reduction in the DAF adhesive layer thickness without sacrificing reliability. Therefore, a DAF with a thickness of 3 μm to 10 μm can be considered to further save space for stacking. For example, a 3 μm DAF, which is currently the thinnest achievable, is advantageous for stacking more chips within the same physical space, improving integration.

[0047] Compared to existing technologies, the chip structure 100 provided in this application embodiment improves the bending resistance of the chip structure 100 by providing a protective layer 20 with a material hardness value of 300HB to 500HB on at least the sidewalls 14. The presence of the protective layer 20 makes the chip structure 100 more robust and less prone to breakage when subjected to external stress, improving the yield rate and significantly reducing cracking, thereby enhancing overall reliability and reducing production costs. The chip structure 100 can also be further integrated with the ultra-thin DAF base layer 30, enabling the chip structure 100 to not only achieve miniaturization in size but also maximize storage capacity, making it suitable for high-density integrated circuit applications.

[0048] The aforementioned advantages enable the chip structure 100 provided in this application embodiment to have broad application potential in modern electronic products, meet the market's demand for high performance, high integration and high reliability of chips, and promote the development of electronic devices towards thinner, lighter and more powerful directions.

[0049] Please see Figure 2 As shown, this application embodiment also provides a chip structure 200, which differs from the chip structure 100 of the aforementioned embodiment in that the protective layer 20 is located only on the sidewall 14.

[0050] Compared to the aforementioned embodiments, the chip structure 200 in this embodiment, by forming a protective layer 20 on the sidewall 14, not only effectively improves the bending resistance of the chip structure 200, but also further reduces the thickness of the chip structure 200.

[0051] Please see Figure 3 As shown, please refer to the following: Figures 4 to 9 As shown in the embodiments of this application, a method for fabricating a chip structure 100 is also provided, which specifically includes the following steps:

[0052] Step S11, as follows Figures 4 to 5 As shown, a groove 2 is formed from the first surface 11 of wafer 1 toward the second surface 12 of wafer 1, with the first surface 11 and the second surface 12 being positioned opposite each other.

[0053] In this process, a groove 2 is formed in wafer 1 to enable the separation of wafer 1 and to form a single chip unit 10 (combined with...). Figure 7 (As shown).

[0054] In some embodiments, the depth of the groove 2 can be 50 μm to 300 μm. The depth of the groove 2 can further be 50 μm to 80 μm, and can be, for example, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 200 μm or 300 μm.

[0055] In some embodiments, the groove 2 can be formed by cutting the wafer 1.

[0056] Step S12, as follows Figure 6 As shown, a carrier plate 3 is formed on the first surface 11. The carrier plate 3 helps to fix and support the wafer 1, while protecting the first surface 11.

[0057] Specifically, a carrier plate 3 can be formed on the first surface 11 of the wafer 1 to support the wafer 1. The carrier plate 3 can provide a certain support force during the fabrication of the chip unit 10, which is beneficial to improving the stability and alignment accuracy of the wafer 1 during the fabrication process. At the same time, it protects the first surface 11, preventing particles, debris and grinding equipment from causing scratches, contamination and other damage to the first surface 11 during the fabrication process, and reducing the risk of damage.

[0058] In some embodiments, back grinding tape (BG tape) can be selected as the carrier 3 to fix and protect the wafer 1. The back grinding tape can reduce stress during processing, prevent wafer 1 from cracking, help maintain the integrity of wafer 1, and facilitate subsequent processing, thus improving production efficiency. In addition, the back grinding tape is easy to peel off and can be easily removed in subsequent processes without leaving residue. Understandably, the material of the carrier 3 can be selected to have both fixing and protective functions, while also being easy to remove later.

[0059] Step S13, as follows Figure 7 As shown, a portion of the wafer 1 is removed from one side of the second surface 12 toward the first surface 11 to form a plurality of spaced chip units 10 on the carrier 3. Each chip unit 10 includes a first surface 11 and a third surface 13 disposed opposite to the first surface 11, wherein the first surface 11 is the working surface of the chip unit 10.

[0060] Specifically, in this embodiment, a portion of the wafer 1 is removed to achieve the formation of multiple independent chip units 10 with a target thickness in one step.

[0061] The target thickness of the chip unit 10 can be 25μm to 48μm. A thinner chip unit 10 is beneficial for reducing the thickness of the chip structure 100. The thickness of the chip unit 10 can further be 25μm to 30μm, and can be, for example, 25μm, 28μm, 30μm, 35μm, 40μm, 45μm, or 48μm.

[0062] One method for removing part of wafer 1 is grinding and thinning.

[0063] Step S14, as follows Figure 8 As shown, a protective layer 20 is formed on at least one sidewall 14 of each chip unit 10, and the material of the protective layer 20 has a hardness value of 300HB to 500HB. The protective layer 20 can effectively improve the bending resistance of the chip unit 10.

[0064] In this embodiment, a high-hardness material with a hardness value of 300HB to 500HB is deposited on the sidewall 14 and the third surface 13 of the chip unit 10 to form a protective layer 20. The high-hardness material forms a protective layer 20 attached to the surface of the chip unit 10, thereby providing strong protection for the chip unit 10 and improving the bending resistance of the final chip structure 100. At the same time, the high-hardness material does not actually "penetrate" into the interior of the chip unit 10, and has a relatively small impact on the performance of the chip unit 10.

[0065] Because the chip unit 10 itself is thin, the bending pressure that the chip unit 10 can withstand is very small. The formed protective layer 20 can effectively improve the bending resistance of the chip structure 100, effectively solve the problem of chip cracking in chip stacking, reduce the defect rate of chip cracking, and facilitate the large-scale production and application of ultra-thin chips.

[0066] In terms of physical protection, the protective layer 20 is scratch-resistant, ensuring the appearance and precision of the chip structure 100. It also absorbs and disperses energy when the chip structure 100 is subjected to impact, enhancing its resistance to bending. In terms of chemical protection, the protective layer 20 is corrosion-resistant and oxidation-resistant, isolating it from external corrosive substances and oxygen. In terms of electrical protection, the protective layer 20 acts as an electrostatic shield to prevent damage from electrostatic discharge and also provides electromagnetic shielding to reduce external electromagnetic interference.

[0067] In some embodiments, the protective layer 20 can be formed by chemical vapor deposition (CVD). CVD offers good controllability, allowing adjustment of the deposition rate and material composition, which facilitates precise control of the thickness, uniformity, and composition of the protective layer 20 to meet different application requirements and ensure protection of the chip unit 10. Furthermore, the precise temperature control of CVD improves the quality of the protective layer 20, enhancing its adhesion and density. CVD offers advantages such as high efficiency, economy, and flexibility.

[0068] In some embodiments, the vapor deposition method includes at least one of chemical vapor deposition (CVD) and physical vapor deposition (PVD). Chemical vapor deposition (CVD) utilizes gaseous materials to undergo a chemical reaction under conditions such as high temperature, catalyst, or plasma to generate atoms or molecules of a high-hardness material, which are then deposited on the surface of the chip cell 10 to form a protective layer 20. Physical vapor deposition (PVD), on the other hand, involves sputtering or evaporating material in atomic or molecular form from a source material (target), which is then deposited on the surface of the chip cell 10 to form the protective layer 20. It is understood that the vapor deposition method can also be a combination of various single CVD and PVD methods; any method capable of vapor deposition to form the protective layer 20 on the chip cell 10 is acceptable.

[0069] In some embodiments, physical vapor deposition can be a vacuum sputtering method, in which high-energy particles bombard a target material in a vacuum environment, causing atoms or molecules on the target surface to gain sufficient energy to escape and then deposit onto the surface of the chip unit 10. Vacuum sputtering can form a uniform and dense protective layer 20 with strong adhesion, further improving the protective effect of the protective layer 20.

[0070] In some embodiments, the protective layer 20 may be made of a metallic material, which has good thermal conductivity and corrosion resistance.

[0071] In some embodiments, the aforementioned metallic material may include at least one of chromium, tungsten, titanium, and steel. These metallic materials possess excellent hardness, ductility, high-temperature resistance, and oxidation resistance, effectively improving the bending resistance of the chip structure 100 and reducing the cracking rate of the chip structure 100, thereby improving the production yield and service life of the chip structure 100.

[0072] In some embodiments, the thickness of the protective layer 20 can be 3μm to 20μm, which can effectively balance the mechanical strength and performance of the chip structure 100, providing good protection without affecting the performance of the chip structure 100 itself. The thickness of the protective layer 20 can further be 5μm to 10μm, and exemplaryly can be 3μm, 5μm, 8μm, 10μm, 12μm, 15μm, 18μm, or 20μm, etc.

[0073] Step S15, as follows Figure 9 As shown, and in combination Figure 1 A base layer 30 is formed on the surface of all chip units 10 facing away from the carrier 3, and the carrier 3 is removed to obtain the chip structure 100.

[0074] Forming a base layer 30 can improve the stability of the chip structure 100, which is beneficial for subsequent packaging and use.

[0075] The substrate 30 can be a die-attach film (DAF).

[0076] In some embodiments, the thickness of the base layer 30 can be 3 μm to 60 μm. Because at least the sidewalls 14 of the chip structure 100 have a protective layer 20, the voltage resistance and bending resistance of the chip structure 100 are improved. This prevents the chip structure 100 from easily breaking or deforming due to external forces when used with a thinner base layer 30, allowing for a reduction in the thickness of the base layer 30 without sacrificing reliability. Therefore, a base layer 30 with a thickness of 3 μm to 20 μm can be considered, further saving space for stacking. The thickness of the base layer 30 can further be 3 μm to 10 μm. The base layer 30 can, exemplarily, be a 3 μm DAF (Digital Adhesive Foundation) of relatively thinness currently achievable, which facilitates stacking more chips in the same physical space and improves integration.

[0077] Compared with the prior art, the method for fabricating the chip structure 100 provided in this application has the following advantages:

[0078] 1. A high-quality protective layer 20 is efficiently and uniformly formed on at least the sidewalls 14 of the chip cell 10 using a vapor deposition method to fabricate the chip structure 100. This process allows for precise control of the thickness and composition of the protective layer 20, effectively improving its adhesion and density, thereby enhancing the bending resistance of the chip structure 100, solving problems such as chip cracking during chip structure 100 stacking, improving the yield of the chip structure 100, and providing higher reliability and performance assurance for the application of ultra-thin chips.

[0079] 2. By controlling the thickness of the chip unit 10 through a one-step thinning process, and combined with the protective layer 20, the thickness of the chip structure 100 and its bending resistance can be balanced, meeting the dual requirements of modern high-performance electronic devices for chip thickness and mechanical strength, achieving higher integration, and optimizing the application of ultra-thin chips in high-density packaging.

[0080] 3. Due to the presence of the protective layer 20, the chip unit 10 can be used in conjunction with an ultra-thin DAF (base layer 30) without reducing the reliability of the chip structure 100. In particular, the 3μm DAF, such an ultra-thin DAF, has not yet been mass-produced in the industry, so this application is beneficial to overcoming the thickness limitations of DAF in chip applications.

[0081] Please refer to it again. Figure 3 Please refer to both together. Figures 4 to 13 This application also provides a method for fabricating the aforementioned chip structure 200, which specifically includes the following steps:

[0082] Step S21, please refer to [reference needed]. Figure 4 and Figure 5 A groove 2 is formed on wafer 1. The specific steps are basically the same as step S11 in the previous embodiment. For details, please refer to step S11 in the previous embodiment. It will not be elaborated here.

[0083] Step S22, please refer to [link / reference] Figure 6 A carrier plate 3 is formed on the first surface 11. The specific steps are basically the same as step S12 in the previous embodiment. For details, please refer to step S12 in the previous embodiment. It will not be elaborated here.

[0084] Step S23, as Figure 10 As shown, a portion of the wafer 1 is removed from one side of the second surface 12 toward the first surface 11 to form a plurality of spaced chip units 10a on the carrier 3. Each chip unit 10a includes a first surface 11 and a third surface 13a disposed opposite to the first surface 11, wherein the first surface 11 is the working surface of the chip unit 10a.

[0085] Understandably, removing part of wafer 1 to divide wafer 1 into independent chip units 10a can improve yield.

[0086] The thickness of the chip unit 10a can be 50μm to 150μm, and more specifically 50μm to 80μm. Exemplarily, it can be 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 120μm, or 150μm.

[0087] Step S24, as Figure 11 As shown, a protective layer 20a is formed on the sidewall 14 and the third surface 13a of each chip cell 10a.

[0088] Specifically, the deposition process of the protective layer 20a in this step can be referred to step S14 of the above embodiment.

[0089] By appropriately maintaining a larger thickness for the chip unit 10a, it is easier to form a protective layer 20a on the surface of the chip unit 10a, thereby further improving the bonding force between the protective layer 20a and the chip unit 10a.

[0090] Step S25, as Figure 12 As shown, the protective layer 20a located on the third surface 13a is removed, and a portion of the chip unit 10a is removed from the third surface 13a toward the first surface 11 to thin the chip unit 10a.

[0091] Through further thinning processes, the chip unit 10a can be thinned to the target thickness, forming a chip unit 10 of the required thickness. By employing two thinning processes—one rough grinding and one fine grinding—not only is the deposition of the protective layer 20a facilitated, but the surface quality of the chip structure 200 is also improved. Since the protective layer 20a has been formed on the chip unit 10a, its mechanical strength is enhanced, which helps reduce the risk of cracks, damage, or failure of the chip unit 10a during the thinning process in step S25. This further improves the structural integrity, quality, and yield of the fabricated chip structure 200, as well as its reliability and stability in the final application.

[0092] In this embodiment, the target thickness can be 25μm to 48μm, which is beneficial for controlling the thickness of the chip structure 200. The target thickness can be further 25μm to 30μm, and can be exemplarily 25μm, 28μm, 30μm, 32μm, 35μm, 40μm, 45μm or 48μm, etc.

[0093] By performing the step-by-step thinning process on the chip unit 10a as described above, a chip unit 10 with a target thickness is obtained, which can further improve the yield of the chip structure 200 and further optimize the thickness of the chip structure 200 to meet specific application requirements, such as high-density packaging, improving heat dissipation efficiency, or maximizing storage capacity.

[0094] Step S26, as follows Figure 13 and Figure 2 As shown, a base layer 30 is formed on the surface of all chip units 10 facing away from the carrier plate 3, and the carrier plate 3 is removed to obtain the chip structure 200.

[0095] The material and thickness of the carrier plate 3 can be referenced from the carrier plate 3 in step S15 of the above scheme 1.

[0096] Compared with the fabrication method of chip structure 100 in the aforementioned embodiment, the fabrication method of chip structure 200 in this embodiment adopts a step-by-step thinning method, which involves two thinning processes: one rough grinding and one fine grinding. This not only facilitates the deposition of the protective layer 20a, but also improves the surface quality and grade of chip structure 200 and reduces damage to chip structure 200 during thinning.

[0097] The following specific examples further illustrate the aforementioned chip structure and its fabrication method.

[0098] Example 1

[0099] Step 1: Provide a wafer and cut a groove from the first surface of the wafer toward the second surface of the wafer. The groove has a depth of 80μm and the first surface and the second surface are positioned opposite each other.

[0100] Step 2: Fix BG tape onto the first surface of the wafer to form a carrier plate.

[0101] Step 3: Remove a portion of the wafer from one side of the second surface toward the first surface to form multiple spaced-apart chip cells on a carrier substrate. Each chip cell includes a first surface and a third surface opposite to the first surface, wherein the first surface is the working surface of the chip cell. The thickness of the chip cell is 28 μm.

[0102] Step 4: Vacuum sputtering is used to deposit chromium metal material onto the sidewalls and third surface of the chip unit to form a 5μm protective layer.

[0103] Step 5: Fix a 3μm layer of DAF onto the surface of the chip unit away from the carrier to form a base layer, remove the carrier to obtain the chip structure.

[0104] Example 2

[0105] Step 1: Provide a wafer and cut a groove from the first surface of the wafer toward the second surface of the wafer. The groove has a depth of 80μm and the first surface and the second surface are positioned opposite each other.

[0106] Step 2: Fix BG tape onto the first surface of the wafer to form a carrier plate.

[0107] Step 3: Remove a portion of the wafer from one side of the second surface toward the first surface to form a plurality of spaced chip units on a carrier. Each chip unit includes a first surface and a third surface disposed opposite to the first surface, wherein the first surface is the working surface of the chip unit and the thickness of the chip unit is 75 μm.

[0108] Step 4: Use vacuum sputtering to deposit steel metal material on the sidewalls and third surface of the chip unit to form a 10μm protective layer.

[0109] Step 5: Remove the protective layer on the third surface, and remove part of the chip cell from the third surface toward the first surface to further thin the chip cell to the target thickness of 30μm.

[0110] Step 6: Fix a 3μm layer of DAF onto the surface of the chip unit away from the carrier to form a base layer, remove the carrier to obtain the chip structure.

[0111] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A chip structure, characterized in that, include: grassroots Multiple chip units are spaced apart on the substrate. Each chip unit includes a first surface and a third surface disposed opposite to each other. The third surface is disposed close to the substrate. The first surface is the working surface of the chip unit. as well as A protective layer is provided on at least the sidewall of each of the chip units, and the material of the protective layer has a hardness value of 300HB to 500HB.

2. The chip structure according to claim 1, characterized in that, The protective layer also extends to the third surface.

3. The chip structure according to claim 1, characterized in that, The thickness of the protective layer is 3μm to 20μm.

4. The chip structure according to claim 1, characterized in that, The protective layer is made of metallic materials.

5. The chip structure according to claim 4, characterized in that, The metallic material includes at least one of chromium, tungsten, titanium, and steel.

6. A method for fabricating a chip structure, characterized in that, include: A groove is formed from a first surface of the wafer toward a second surface of the wafer, wherein the first surface and the second surface are disposed opposite to each other. A carrier plate is formed on the first surface; A portion of the wafer is removed from one side of the second surface toward the first surface to form a plurality of spaced-apart chip cells on the carrier. Each chip cell includes the first surface and a third surface disposed opposite to the first surface, wherein the first surface is the working surface of the chip cell. A protective layer is formed on at least one sidewall of each of the chip units, wherein the material of the protective layer has a hardness value of 300HB to 500HB; as well as A base layer is formed on the surface of all the chip cells facing away from the carrier, and the carrier is removed to obtain the chip structure.

7. The method for fabricating the chip structure according to claim 6, characterized in that, In the step of forming a protective layer on at least the sidewall of each of the chip cells, the protective layer further extends to the third surface.

8. The method for fabricating a chip structure according to claim 6, characterized in that, The step of forming the protective layer on at least the sidewall of each of the chip cells includes: The protective layer is formed on the sidewall of each chip cell and on the third surface; and The protective layer located on the third surface is removed, and a portion of the chip cell is removed from the third surface toward the first surface to thin the chip cell.

9. The method for fabricating a chip structure according to claim 6, characterized in that, Methods for forming the protective layer include vapor deposition.

10. The method for fabricating the chip structure according to claim 6, characterized in that, The thickness of the protective layer is 3μm to 20μm.

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