Wafer passivation venting process method based on atomic layer deposition

Abstract

The application belongs to the technical field of semiconductor manufacturing process, and particularly relates to a wafer passivation aeration process method based on atomic layer deposition. The scheme constructs a gradient passivation film with continuous transition of stress and component in a single process through a three-stage coordinated gradient deposition strategy, fundamentally avoiding the interface mutation problem of the traditional process. Secondly, through the introduced periodic low-temperature repair cycle, a high-activity oxidizing agent is used to selectively repair oxygen vacancies at low temperature, which significantly improves the film integrity without increasing the thermal budget. Thirdly, by adopting the combination of virtual partition timing and counterflow purging, the precursor distribution is intelligently controlled and the by-products are efficiently removed, which greatly improves the three-dimensional uniformity of the film. Finally, the in-situ gradient annealing is used to replace the traditional out-of-cavity annealing, and by slowly rising and falling temperature in a low-oxygen environment, the film is fully densified and the risk of secondary pollution is eliminated.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing process technology, specifically relating to a wafer passivation and ventilation process method based on atomic layer deposition. Background Technology

[0002] Current ALD (Atomic Layer Deposition) passivation technology primarily employs a standardized deposition process under isothermal and isobaric conditions, combined with a post-processing mode of high-temperature rapid annealing. Existing technologies can improve film quality to a certain extent by optimizing precursor ratios or pulse timing. However, under the stringent requirements of high-performance semiconductor devices regarding interface states, film uniformity, and thermal budget, these traditional approaches have the following drawbacks: First, standardized deposition processes struggle to achieve gradient control of stress and chemical composition. Passivation layers grown under constant process parameters exhibit abrupt changes in interface and host layer properties, leading to interface stress concentration and high defect density. Furthermore, a single oxygen source cannot effectively repair oxygen vacancies and dangling bonds generated during deposition. Second, the inherent airflow inhomogeneity of the equipment can only be partially compensated for through hardware modifications. Traditional unidirectional purging methods tend to leave byproducts in dead corners of the chamber, affecting film uniformity and step coverage. Third, while high-temperature annealing outside the chamber can improve film density, it introduces the risk of secondary contamination. Rapid heating and cooling processes are not conducive to the full repair of defects and also increase the overall thermal budget. Summary of the Invention

[0003] This invention addresses the problems existing in the prior art by providing a wafer passivation and ventilation process based on atomic layer deposition, which effectively solves the problems existing in the prior art.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows: The wafer passivation ventilation process based on atomic layer deposition specifically includes: In the atomic layer deposition equipment, according to the preset three-stage synergistic gradient deposition strategy, a gradient structure passivation film including a low-stress interface layer, a high-quality host layer, and an oxygen-rich stable surface layer is deposited layer by layer by synergistic gradual temperature, pressure and precursor timing. Among them, virtual partitioning timing and countercurrent purging are used to ensure the uniformity of the film layer throughout the deposition process, and low temperature repair cycles are periodically inserted during the deposition of the high-quality host layer. After deposition is completed, in-situ gradient annealing of the wafer is performed; wherein, the in-situ gradient annealing specifically involves: in the low oxygen partial pressure environment of the reaction chamber, the wafer is slowly raised from the deposition temperature to the preset annealing temperature, and then slowly cooled.

[0005] Furthermore, the low-temperature repair cycle specifically comprises: pausing the standard deposition process of the high-quality host layer; reducing the temperature of the reaction chamber to a preset repair temperature; introducing a highly active oxidant into the reaction chamber and maintaining it for a preset exposure time; wherein the repair temperature is lower than the temperature of the standard deposition process, and the activity of the highly active oxidant is higher than that of the oxidant used in the standard deposition process.

[0006] Furthermore, the three-stage synergistic gradient deposition strategy is specifically as follows: During the low-stress interface layer deposition stage, a first parameter combination of temperature, pressure, and precursor timing is used to form the low-stress interface layer. During the high-quality host layer deposition stage, temperature, pressure, and precursor timing are coordinated and adjusted to a second parameter combination to grow the high-quality host layer. During the deposition stage of the oxygen-rich stable surface layer, the temperature, pressure and precursor timing are coordinated and adjusted to a third parameter combination to form the oxygen-rich stable surface layer. Among them, the precursor timing parameters include at least the precursor pulse time and the purge time. The first, second and third parameter combinations are different from each other, and each parameter combination includes specific temperature values, pressure values ​​and precursor timing parameters.

[0007] Furthermore, the use of virtual partitioning timing and countercurrent purging to ensure film uniformity specifically involves: in the precursor pulse step of each deposition stage, virtual partitioning timing is used to control the delivery of precursors to different regions of the wafer; in the purging step, a countercurrent airflow opposite to the wafer rotation direction is used for purging.

[0008] Furthermore, the virtual partitioning timing is specifically as follows: the wafer surface is logically divided into multiple concentric ring regions, and when injecting the reaction precursor into the reaction chamber, the precursor is sequentially and separately introduced into different partitions; the countercurrent purging is specifically as follows: after each reaction precursor pulse step, when inert purging gas is introduced into the reaction chamber, the mainstream direction of the purging gas is opposite to the tangential airflow direction generated by the high-speed rotation of the wafer.

[0009] Furthermore, the periodic insertion of low-temperature repair cycles during the deposition of the high-quality host layer specifically means that, during the deposition of the high-quality host layer, after each preset number of high-temperature deposition cycles, a low-temperature repair cycle is periodically inserted in the continuous high-temperature atomic layer deposition cycle sequence.

[0010] Furthermore, the adjustments among the first parameter combination, the second parameter combination, and the third parameter combination satisfy at least one of the following cooperative gradient relationships: The temperature value changes monotonically from the first stage to the third stage; The pressure value changes monotonically from the first stage to the third stage. The precursor pulse time in the precursor timing parameters changes monotonically from the first stage to the third stage.

[0011] Furthermore, the monotonic change of the temperature value is set to increase incrementally, from 150°C to 250°C in the first stage to 300°C to 450°C in the third stage; The monotonic change of the pressure value is set to decrease, from 10Pa to 200Pa in the first stage, and then to 0.5Pa-30Pa in the third stage; The precursor pulse time in the precursor timing parameters is set to increase monotonically, from 0.1 to 0.5 seconds in the first parameter combination to 1.0 to 1.5 seconds in the third parameter combination.

[0012] Furthermore, in the low oxygen partial pressure environment of the reaction chamber, the wafer is slowly heated from the deposition temperature to a preset annealing temperature and then slowly cooled. Specifically, the wafer is gradually heated to an annealing temperature that is significantly higher than the deposition temperature for heat treatment, and then gradually cooled to a wafer removal temperature that is lower than the deposition temperature. The temperature change rate of both the heating and cooling processes is lower than the free heating and cooling rate.

[0013] Furthermore, after heating to the annealing temperature, the current temperature is maintained for a preset time period.

[0014] Compared with the prior art, the advantages and positive effects of the present invention are as follows: (1) The present invention provides a wafer passivation ventilation process based on atomic layer deposition. The method constructs a gradient passivation film with continuous stress and composition transition in a single process through a three-stage synergistic gradient deposition strategy, fundamentally avoiding the interface abruptness problem of traditional processes. Secondly, by introducing a periodic low-temperature repair cycle, a highly active oxidant is used to selectively repair oxygen vacancies at low temperatures, significantly improving film integrity without increasing the thermal budget. Furthermore, by adopting a combination of virtual partitioning timing and countercurrent purging, the precursor distribution is intelligently controlled and byproducts are efficiently removed, greatly improving the three-dimensional uniformity of the film. Finally, in-situ gradient annealing replaces traditional external cavity annealing, and by slowly heating and cooling in a low-oxygen environment, the film is fully densified and the risk of secondary contamination is eliminated.

[0015] (2) The scheme described in this invention adopts a three-stage synergistic gradient deposition strategy. Through the synergistic gradual change of temperature, pressure and precursor timing, a low-stress interface layer, a high-quality host layer and an oxygen-rich stable surface layer are constructed in situ within a single process cycle. This design directly solves the problem of abrupt changes in the properties of the interface and host layer caused by traditional standardized processes. At the same time, by periodically inserting low-temperature repair cycles, highly active oxidants are introduced to selectively repair oxygen vacancies at lower temperatures. Without excessively increasing the thermal budget, the defect density of the host layer is significantly reduced, and a gradual transition of stress and chemical composition is achieved.

[0016] (3) The solution described in this invention improves the uniformity of the film layer by combining virtual partitioning timing and countercurrent purging in two dimensions: software control and airflow design. Specifically, the virtual partitioning timing compensates for the inherent uneven airflow distribution of the equipment by logically partitioning different regions of the wafer and sequentially delivering the precursor; the countercurrent purging effectively cleans up the byproducts remaining in the dead corners of the chamber by using the reverse airflow opposite to the direction of wafer rotation. Through the synergistic effect of the two, the thickness uniformity of the film is significantly improved without the need for large-scale hardware modification.

[0017] (4) The present invention abandons the traditional high-temperature rapid out-of-cavity annealing method and adopts in-situ gradient annealing. This process is carried out in a low oxygen partial pressure environment in the reaction chamber. By slowly raising the wafer from the deposition temperature to a higher annealing temperature and then slowly cooling it, the defects of the thin film are fully repaired and densified. The present invention not only avoids the risk of secondary contamination caused by wafer transfer, but also improves the stress release and structural relaxation through slow heating and cooling rates. While achieving the same or even better thin film quality, it effectively controls the thermal budget of the overall process and meets the stringent requirements of advanced semiconductor devices for low-temperature processes. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below: Figure 1 This is a flowchart of a wafer passivation ventilation process based on atomic layer deposition, as described in an embodiment of the present invention. Figure 2 This is a basic flowchart of the low-temperature repair cycle described in the embodiments of the present invention; Figure 3 This is a flowchart of the three-stage collaborative gradient deposition strategy described in this embodiment of the invention; Figure 4 This is a flowchart of the in-situ gradient annealing process described in an embodiment of the present invention. Detailed Implementation

[0019] To better understand the above-mentioned objectives, features and advantages of the present invention, the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0020] Numerous specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways than those described herein, and therefore the invention is not limited to the specific embodiments disclosed in the following specification.

[0021] Terminology Explanation: Low-stress interface layer: Specifically refers to the initial thin film layer directly formed on the semiconductor substrate under the first deposition conditions described in this embodiment. The first deposition conditions specifically refer to: using precursor A and oxidant B, deposition is performed at temperature T1 and pressure P1, without introducing nitrogen-containing precursors. The main function of this layer is to achieve stress buffering and interface passivation. High-quality host layer: Specifically refers to the functional thin film host layer formed on the low-stress interface layer under the second deposition conditions described in this embodiment. The second deposition conditions specifically refer to: introducing a nitrogen-containing precursor C into the reaction atmosphere and adjusting the temperature to T2 and the pressure to P2, based on the first deposition conditions. The main function of this layer is to provide core dielectric and passivation properties.

[0022] Oxygen-rich stable surface layer: Specifically refers to the terminal thin film layer formed on the high-quality bulk layer under the third deposition condition described in this embodiment. The third deposition condition specifically refers to: based on the second deposition condition, stopping the introduction of nitrogen-containing precursor C, increasing the pulse dose or time of oxidant B, and optionally adjusting the temperature to T3. The outermost surface region of this layer has a higher oxygen content than the interior of the bulk layer, and its main function is to improve environmental stability and process compatibility.

[0023] It should be noted that the above three-layer structure is grown in one step through a continuous, in-situ atomic layer deposition process that transitions from the first deposition condition, through the second deposition condition, to the third deposition condition, with chemical gradient transitions between the layers.

[0024] Example 1 The wafer passivation ventilation process based on atomic layer deposition in Example 1 will be described in detail below with reference to the accompanying drawings.

[0025] like Figure 1 As shown, the wafer passivation ventilation process based on atomic layer deposition specifically includes: In the atomic layer deposition equipment, according to the preset three-stage synergistic gradient deposition strategy, a gradient structure passivation film including a low-stress interface layer, a high-quality host layer, and an oxygen-rich stable surface layer is deposited layer by layer by synergistic gradual temperature, pressure and precursor timing. Among them, virtual partitioning timing and countercurrent purging are used to ensure the uniformity of the film layer throughout the deposition process, and low temperature repair cycles are periodically inserted during the deposition of the high-quality host layer. After deposition is completed, in-situ gradient annealing of the wafer is performed; wherein, the in-situ gradient annealing specifically involves: in the low oxygen partial pressure environment of the reaction chamber, the wafer is slowly raised from the deposition temperature to the preset annealing temperature, and then slowly cooled.

[0026] In one or more embodiments, such as Figure 2 As shown, the low-temperature repair cycle specifically involves: pausing the standard deposition process of the high-quality host layer; lowering the reaction chamber temperature to a preset repair temperature; introducing a highly active oxidant (e.g., ozone O3, gaseous hydrogen peroxide H2O2) into the reaction chamber and maintaining it for a preset exposure time; wherein the repair temperature is lower than the temperature of the standard deposition process, and the activity of the highly active oxidant is higher than that of the oxidant used in the standard deposition process; the exposure time is sufficient to fill oxygen vacancies in the deposited film in situ and passivate dangling bonds, thereby interrupting the continuous accumulation of defects during film growth.

[0027] In one or more embodiments, such as Figure 3 As shown, the three-stage synergistic gradient deposition strategy is specifically as follows: During the low-stress interface layer deposition stage, a first parameter combination of temperature, pressure, and precursor timing is used to form the low-stress interface layer. During the high-quality host layer deposition stage, temperature, pressure, and precursor timing are coordinated and adjusted to a second parameter combination to grow the high-quality host layer. During the deposition stage of the oxygen-rich stable surface layer, the temperature, pressure and precursor timing are coordinated and adjusted to a third parameter combination to form the oxygen-rich stable surface layer. Among them, the precursor timing parameters include at least the precursor pulse time and the purge time. The first, second and third parameter combinations are different from each other, and each parameter combination includes specific temperature values, pressure values ​​and precursor timing parameters.

[0028] In one or more embodiments, the use of virtual partitioning timing and countercurrent purging to ensure film uniformity specifically involves: in the precursor pulse step of each deposition stage, virtual partitioning timing is used to control the delivery of precursors to different regions of the wafer; in the purging step, a countercurrent airflow opposite to the wafer rotation direction is used for purging.

[0029] It should be noted that in conventional atomic layer deposition processes, especially when depositing on large wafers (such as 300mm), uneven gas flow distribution of the reactive precursor in the chamber, temperature gradient between the wafer edge and center, and differences in the diffusion rate of the precursor on the wafer surface can easily lead to non-uniformity in the thickness and composition of the deposited film in the wafer radial direction (i.e., the "center-edge effect"). This can seriously affect the performance consistency and yield of the final semiconductor device.

[0030] Based on the above problems, the solution described in this embodiment uses the aforementioned virtual partitioning timing and countercurrent purging to ensure film uniformity. Specifically: The virtual partitioning timing is specifically as follows: the wafer surface is logically divided into multiple concentric ring regions (e.g., central region, middle region, and edge region). When injecting the reaction precursor into the reaction chamber, it is not a one-time global injection, but rather, through precisely controlled valves and gas flow pipelines, the precursor is sequentially and separately injected into different partitions according to a preset timing sequence. For example: In the A precursor pulse step of the deposition cycle, the control program is set to first introduce the A precursor into the edge zone for 100 milliseconds, then simultaneously introduce it into the middle zone and the center zone for 150 milliseconds, and finally stop the introduction of the precursor into the edge zone, and only introduce it into the center zone for 50 milliseconds.

[0031] Through precise timing control, the reaction rate differences caused by physical location can be actively compensated. For example, given the characteristics of short airflow paths and rapid consumption in edge regions, the time for which they exclusively use the precursor can be extended to ensure that the region obtains the same amount of reactants as the central region, thereby achieving high uniformity of film thickness across the entire wafer.

[0032] The countercurrent purging is specifically defined as follows: after each reaction precursor pulse step, when an inert purging gas (e.g., N2, Ar) is introduced into the reaction chamber, the mainstream direction of the purging gas is opposite to the direction of the tangential airflow generated by the high-speed rotation of the wafer.

[0033] Specifically, by setting the purge gas inlet on one side of the wafer's rotating plane (e.g., above or to the side), and controlling the main component of the airflow vector in its ejection direction to be opposite to the wafer's rotation direction, while the exhaust port is set in the opposite direction; under the above design, the wafer rotation will cause the gas molecules trapped on the surface to form a clockwise (or counterclockwise) "wind wall". Conventional co-directional purging may not be able to effectively penetrate this wind wall to remove the precursors remaining in the grooves or edges. However, the reverse airflow of the scheme described in this embodiment can generate stronger shear force and turbulence, physically removing unreacted byproducts and excess precursors in various regions (especially the bottom of complex three-dimensional features and the wafer edge).

[0034] Understandably, the combination of countercurrent purging and virtual partition timing control in the scheme described in this embodiment ensures that the residues can be efficiently removed after each partition has completed the reaction, preventing them from being carried to the next partition or participating in the next unintended parasitic reaction, thereby also ensuring the uniformity of the chemical composition and microstructure of the membrane.

[0035] In specific implementation, the virtual partitioning timing control and reverse purging process are applied throughout all three deposition stages of the scheme described in this embodiment: the low-stress interface layer, the high-quality host layer, and the oxygen-rich stable surface layer. Although the core parameters such as precursor chemistry, temperature, and pressure differ in the three stages, the uniformity control strategy remains consistent. This ensures that each sub-layer of the final "three-layer" passivation film has consistency at any location on the wafer, thereby guaranteeing the uniformity of the electrical performance of all chip units.

[0036] In one or more embodiments, the periodic insertion of a low-temperature repair cycle during the deposition of the high-quality host layer specifically means that, during the deposition of the high-quality host layer, in a continuous high-temperature atomic layer deposition cycle sequence, a low-temperature repair cycle is periodically inserted after each preset number of high-temperature deposition cycles.

[0037] In specific implementation, the preset number of times is greater than or equal to 5 times, and the process temperature of the low-temperature repair cycle is at least 50°C lower than the process temperature of the high-temperature deposition cycle.

[0038] In one or more embodiments, the adjustment among the first parameter combination, the second parameter combination, and the third parameter combination satisfies at least one of the following cooperative gradient relationships: The temperature value changes monotonically from the first stage to the third stage; The pressure value changes monotonically from the first stage to the third stage. The precursor pulse time in the precursor timing parameters changes monotonically from the first stage to the third stage.

[0039] In specific implementation, the monotonic change of the temperature value is set to increase incrementally, from 150°C to 250°C in the first stage to 300°C to 450°C in the third stage; The monotonic change of the pressure value is set to decrease, from 10Pa to 200Pa in the first stage, and then to 0.5Pa-30Pa in the third stage; The precursor pulse time in the precursor timing parameters is set to increase monotonically, from 0.1 to 0.5 seconds in the first parameter combination to 1.0 to 1.5 seconds in the third parameter combination.

[0040] In a specific implementation, the process of slowly raising the wafer from the deposition temperature to a preset annealing temperature under the low oxygen partial pressure environment of the reaction chamber and then slowly cooling it involves gradually raising the wafer to an annealing temperature significantly higher than the deposition temperature for heat treatment, and then gradually cooling it to a wafer removal temperature lower than the deposition temperature. The temperature change rate during both the heating and cooling processes is lower than the free heating and cooling rate.

[0041] Specifically, the annealing temperature is at least 200°C higher than the deposition temperature, with an optimal difference of 250°C to 500°C.

[0042] In one or more embodiments, after the temperature is raised to the annealing temperature, the current temperature is maintained for a preset time period.

[0043] In specific implementation, the in-situ gradient annealing is a process of programmed temperature control of the wafer-supporting stage (such as an electrostatic chuck) within the same reaction chamber after the deposition of the oxygen-rich stable surface layer, under a low oxygen partial pressure protective atmosphere maintained by a continuously introduced inert gas (such as high-purity N2 or Ar). Its core lies in achieving interface optimization and bulk layer modification of the thin film through controlled, non-transient temperature changes, while avoiding thermal shock damage and adverse oxidation reactions. Figure 4 As shown, it specifically includes: Phase 1: Controlled Temperature Increase Initial state: The wafer is at the deposition temperature of the oxygen-rich stable surface layer (e.g., in the range of 200°C to 400°C). Heating process: By adjusting the power of the heater (such as a resistance heater or a lamp heater), the wafer is gradually heated from the deposition temperature to the preset target annealing temperature at a controlled rate lower than the natural heating and cooling rate of the reaction chamber and heater in their free state. The controlled rate refers to a temperature change that is active, linear, or phased, rather than a rapid, natural temperature change after heating is turned off or on.

[0044] It should be noted that the above-mentioned slow heating process (as opposed to direct exposure to high temperatures) allows the thermal stress between the thin film layer and the underlying substrate / stack to be released gradually, reducing the risk of interface defects (such as microcracks or warping) caused by thermal expansion coefficient mismatch.

[0045] Second stage: Constant temperature heat treatment Isothermal stage: After the temperature reaches the target annealing temperature, the temperature holding stage is entered, which stabilizes the wafer temperature at the target annealing temperature for a preset period of time. It should be noted here that the heat preservation stage provides the necessary thermodynamic driving force and time window for the microstructure relaxation, atomic interdiffusion, and defect repair of the thin film, specifically manifested in: Interfacial interdiffusion: Promotes limited interdiffusion of atoms (such as metal cations and oxygen ions) at the interface between the bulk thin film and the substrate / lower thin film, forming a more stable chemical bond and gradient transition interface, thereby reducing the interface state density and improving electrical performance.

[0046] Thin film densification: promotes further reaction and bonding of unreacted precursors or weakly bound clusters within the film layers, eliminates micropores, and improves the density and mechanical stability of the film.

[0047] Crystallization control: If the thin film material is a crystallizable system, this stage can control the nucleation and growth of grains, thereby controlling the crystallinity and grain size of the thin film.

[0048] Phase 3: Controlled Cooling Cooling stage: After the isothermal stage, the power of the control heater is gradually reduced, and the wafer is gradually cooled from the target annealing temperature to a wafer removal temperature lower than the initial deposition temperature at a controlled rate lower than the free cooling rate.

[0049] It should be noted here that the purpose of the cooling stage described above is: Stress management: Slow cooling allows the film and substrate to smoothly coordinate deformation as they shrink from high temperature back to low temperature, avoiding "hot quenching" stress and new defects caused by excessively rapid cooling.

[0050] Structural "freezing": The microstructure optimized during the high-temperature annealing stage (such as dense amorphous networks, specific crystalline phases, and excellent interface states) is effectively "frozen" and preserved at a lower temperature.

[0051] Safe wafer removal: Cooling to a sufficiently low removal temperature ensures that the wafer will not suffer thermal stress damage or cause unnecessary secondary reactions due to excessive temperature differences when it is subsequently transported to the atmospheric environment.

[0052] In the scheme described in this embodiment, the entire in-situ gradient annealing process is completed continuously in the deposition chamber, avoiding the exposure of the wafer to the atmosphere, eliminating the influence of atmospheric pollution (water vapor, oxygen) on the active surface at high temperature, and ensuring the purity of the interface and the film and the repeatability of the process.

[0053] In practical implementation, the process method described in this embodiment can be implemented on existing commercial atomic layer deposition (ALD) equipment. Such equipment typically includes: a vacuum reaction chamber, a wafer stage (with heating function), a multi-path precursor and reactive gas injection system, high-precision temperature and pressure sensors, a programmable timing controller, and a vacuum pump assembly. Based on the characteristics of the process method described in this embodiment, simple functional extensions are required on the existing ALD equipment, including: Timing and formulation control: The control software of the equipment needs to be upgraded to support the insertion logic of the "three-stage synergistic gradient deposition strategy", "low temperature repair cycle" and "in-situ gradient annealing" described in this embodiment. This can be achieved by those skilled in the art through conventional programming, and will not be elaborated on here.

[0054] Virtual partitioning timing can be achieved by using an ALD device spray head that supports partitioned gas injection. The spray head only needs to have independently controllable multi-zone gas channels (the solution described in this embodiment is not limited to a specific spray head form, as long as it has multi-zone gas channels). This allows the timing of introducing precursors into the wafer center, middle, and edge regions to be independently programmed. Since this design is an extension of known technical means used by existing ALD devices to achieve large-area uniformity, its specific structure will not be described in detail here.

[0055] Implementation of countercurrent purging: By adjusting the inlet position and injection direction of the purging gas, the airflow direction is reversed with the wafer rotation direction to enhance the purging effect. This embodiment does not limit its specific structure, as long as it meets the function of countercurrent purging.

[0056] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A wafer passivation and ventilation process based on atomic layer deposition, characterized in that, Specifically, it includes: In the atomic layer deposition equipment, according to the preset three-stage synergistic gradient deposition strategy, a gradient structure passivation film including a low-stress interface layer, a high-quality host layer, and an oxygen-rich stable surface layer is deposited layer by layer by synergistic gradual temperature, pressure and precursor timing. Among them, virtual partitioning timing and countercurrent purging are used to ensure the uniformity of the film layer throughout the deposition process, and low temperature repair cycles are periodically inserted during the deposition of the high-quality host layer. After deposition is completed, in-situ gradient annealing of the wafer is performed; wherein, the in-situ gradient annealing specifically involves: in the low oxygen partial pressure environment of the reaction chamber, the wafer is slowly raised from the deposition temperature to the preset annealing temperature, and then slowly cooled.

2. The wafer passivation and ventilation process based on atomic layer deposition as described in claim 1, characterized in that, The low-temperature repair cycle specifically involves: pausing the standard deposition process of the high-quality host layer; lowering the temperature of the reaction chamber to a preset repair temperature; introducing a highly active oxidant into the reaction chamber and maintaining it for a preset exposure time; wherein the repair temperature is lower than the temperature of the standard deposition process, and the activity of the highly active oxidant is higher than that of the oxidant used in the standard deposition process.

3. The wafer passivation ventilation process based on atomic layer deposition as described in claim 1, characterized in that, The three-stage synergistic gradient deposition strategy is as follows: During the low-stress interface layer deposition stage, a first parameter combination of temperature, pressure, and precursor timing is used to form the low-stress interface layer. During the high-quality host layer deposition stage, temperature, pressure, and precursor timing are coordinated and adjusted to a second parameter combination to grow the high-quality host layer. During the deposition stage of the oxygen-rich stable surface layer, the temperature, pressure and precursor timing are coordinated and adjusted to a third parameter combination to form the oxygen-rich stable surface layer. Among them, the precursor timing parameters include at least the precursor pulse time and the purge time. The first, second and third parameter combinations are different from each other, and each parameter combination includes specific temperature values, pressure values ​​and precursor timing parameters.

4. The wafer passivation and ventilation process based on atomic layer deposition as described in claim 1, characterized in that, The method of using virtual partitioning timing and countercurrent purging to ensure film uniformity specifically involves: in the precursor pulse step of each deposition stage, virtual partitioning timing is used to control the delivery of precursors to different regions of the wafer; in the purging step, a countercurrent airflow opposite to the wafer rotation direction is used for purging.

5. The wafer passivation ventilation process based on atomic layer deposition as described in claim 4, characterized in that, The virtual partitioning timing is specifically as follows: the wafer surface is logically divided into multiple concentric ring regions, and when the reaction precursor is injected into the reaction chamber, the precursor is sequentially and separately introduced into different partitions; the countercurrent purging is specifically as follows: after each reaction precursor pulse step, when inert purging gas is introduced into the reaction chamber, the mainstream direction of the purging gas is opposite to the tangential airflow direction generated by the high-speed rotation of the wafer.

6. The wafer passivation ventilation process based on atomic layer deposition as described in claim 1, characterized in that, The process of periodically inserting low-temperature repair cycles during the deposition of the high-quality host layer is specifically as follows: during the deposition of the high-quality host layer, in the continuous high-temperature atomic layer deposition cycle sequence, a low-temperature repair cycle is periodically inserted after each preset number of high-temperature deposition cycles.

7. The wafer passivation ventilation process based on atomic layer deposition as described in claim 3, characterized in that, The adjustment among the first parameter combination, the second parameter combination, and the third parameter combination satisfies at least one of the following cooperative gradient relationships: The temperature value changes monotonically from the first stage to the third stage; The pressure value changes monotonically from the first stage to the third stage. The precursor pulse time in the precursor timing parameters changes monotonically from the first stage to the third stage.

8. The wafer passivation ventilation process based on atomic layer deposition as described in claim 7, characterized in that, The monotonic change of the temperature value is set to increase, from 150°C to 250°C in the first stage to 300°C to 450°C in the third stage. The monotonic change of the pressure value is set to decrease, from 10Pa to 200Pa in the first stage, and then to 0.5Pa-30Pa in the third stage; The precursor pulse time in the precursor timing parameters is set to increase monotonically, from 0.1 to 0.5 seconds in the first parameter combination to 1.0 to 1.5 seconds in the third parameter combination.

9. The wafer passivation ventilation process based on atomic layer deposition as described in claim 1, characterized in that, In the low oxygen partial pressure environment of the reaction chamber, the wafer is slowly heated from the deposition temperature to a preset annealing temperature and then slowly cooled. Specifically, the wafer is gradually heated to an annealing temperature that is significantly higher than the deposition temperature for heat treatment, and then gradually cooled to a wafer removal temperature that is lower than the deposition temperature. The temperature change rate of both the heating and cooling processes is lower than the free heating and cooling rate.

10. The wafer passivation ventilation process based on atomic layer deposition as described in claim 9, characterized in that, After the temperature is raised to the annealing temperature, the current temperature is maintained for a preset time period.

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