Reference current generation circuit, semiconductor device, and control method thereof
By designing a reference current generation circuit and using a mode control signal to switch between outputting normal or test reference current, the problem of current variation caused by integrated circuit process variations is solved, achieving high-precision testing and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2024-12-25
- Publication Date
- 2026-06-05
Smart Images
Figure CN122152052A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a reference current generating circuit, and more particularly to a reference current generating circuit, a semiconductor device, and a control method thereof that improves circuit accuracy. Background Technology
[0002] In the field of integrated circuit design, the introduction of a new process often brings numerous process variations, leading to a decline in overall circuit accuracy. To compensate for the effects of these process variations, integrated circuits employ testing procedures with a bandgap voltage reference source applied to mitigate this problem. However, some parameters cannot generate accurate reference values through the application of a bandgap voltage reference source. For example, integrated circuits often include circuits to generate reference currents, providing these currents to other circuits within the integrated circuit for timing control. However, with process miniaturization, the variation in reference currents between different chips increases significantly. To achieve precise timing control, a new testing procedure for measuring and compensating the reference current must be added to the integrated circuit testing process, and this compensated reference current is then used for other testing procedures. This increases testing costs. Therefore, it is imperative to propose a completely new solution to overcome the challenges faced by previous technologies. Summary of the Invention
[0003] In a preferred embodiment, the present invention provides a reference current generation circuit, comprising: a current generator that outputs a normal reference current; a test reference current generation circuit, comprising: an operational amplifier configured to receive a first potential and a second potential and generate a test reference current control signal; a first transistor configured to be controlled by the test reference current control signal to generate a test reference current according to the first potential; and a switching circuit coupled to the current generator, the test reference current generation circuit and the output node, and configured to determine whether to output a normal reference current or a test reference current at the output node according to a mode control signal.
[0004] In another preferred embodiment, the present invention provides a semiconductor device comprising: a resistor; a first pad coupled to the resistor and providing a first potential; a second pad providing a second potential; and a reference current generating circuit comprising: a current generator outputting a reference current; a test reference current generating circuit comprising: an operational amplifier configured to receive the first potential and the second potential and generate a test reference current control signal; a first transistor configured to be controlled by the test reference current control signal to generate a test reference current according to the first potential; and a switching circuit coupled to the current generator, the test reference current generating circuit, and the output node, and configured to determine whether to output a normal reference current or a test reference current at the output node according to a mode control signal.
[0005] In another preferred embodiment, the present invention provides a control method for a semiconductor device, comprising: determining, via a switching circuit, to output a normal reference current or a test reference current at the output node of a reference current generation circuit based on a mode control signal; when determining to output a normal reference current, outputting the normal reference current by connecting a current generator of the reference current generation circuit to the output node; when determining to output a test reference current, performing the following steps: receiving a first potential and a second potential via an operational amplifier of the reference current generation circuit, and generating a test reference current control signal; and generating a test reference current based on the first potential via a first transistor controlled by the test reference current control signal.
[0006] The reference current generating circuit, semiconductor device, and control method provided by the present invention can improve the accuracy of the test reference current, thereby reducing the test process and lowering the test cost. Attached Figure Description
[0007] Figure 1 This is a schematic diagram of a reference current generation circuit according to an embodiment of the present invention.
[0008] Figure 2 This is a circuit diagram of a reference current generating circuit according to an embodiment of the present invention.
[0009] Figure 3 This is a circuit diagram of a reference current generating circuit according to another embodiment of the present invention.
[0010] Figure 4 This is a circuit diagram of a semiconductor device according to an embodiment of the present invention.
[0011] Figure 5 A flowchart illustrating a control method for a semiconductor device according to an embodiment of the present invention is shown.
[0012] Symbol Explanation
[0013] 100, 200: Reference current generation circuit
[0014] 120, 220: Operational amplifiers
[0015] 130, 230: First transistor
[0016] 140, 241: Switching circuit
[0017] 150, 251: Test reference current generation circuit
[0018] 210: Resistor
[0019] 240: First Switcher
[0020] 250: Second Switch
[0021] 160, 260: Current generator
[0022] 190, 290: Internal circuitry
[0023] 292: Delay Circuit
[0024] 294: Second transistor
[0025] 296: Third transistor
[0026] 400: Semiconductor Device
[0027] 410: First solder pad
[0028] 420: Second solder pad
[0029] CMD: Mode control signal
[0030] CT: Test reference current control signal
[0031] IA: First Current
[0032] ID: Second Current
[0033] IE: Third Current
[0034] IREF: Normal reference current
[0035] IREFT: Test reference current
[0036] LC1: Virtual separator line
[0037] N1: First node
[0038] N2: Second node
[0039] N3: Third Node
[0040] NOUT: Output node
[0041] S1, S2, S3, S4: Steps
[0042] V1: First potential
[0043] V2: Second potential
[0044] V3: Third potential
[0045] VC1: First control signal
[0046] VC2: Second control signal
[0047] VSS: Grounding Potential Detailed Implementation
[0048] To make the objectives, features, and advantages of this invention more apparent, specific embodiments of the invention are described below in conjunction with the accompanying drawings. Certain terms are used in the specification and claims to refer to specific elements; those skilled in the art will understand that hardware manufacturers may use different terms to refer to the same element. This specification and claims do not distinguish elements by differences in name, but rather by differences in function. Furthermore, the term "coupled" in this specification includes any direct or indirect electrical connection means.
[0049] like Figure 1 The reference current generation circuit 100 shown according to an embodiment of the present invention can be applied to various semiconductor devices, such as mobile devices or memory devices, but is not limited thereto. The reference current generation circuit 100 is configured to generate a normal reference current IREF or a test reference current IREFT according to a mode control signal CMD, and may include a switching circuit 140, a test reference current generation circuit 150, and a current generator 160. The test reference current generation circuit 150 includes an operational amplifier 120 and a first transistor 130. It should be understood that, although not shown in… Figure 1 However, the reference current generation circuit 100 may also include other components, such as a processor or / and a power supply module.
[0050] Operational amplifier 120 is configured to receive a first potential V1 and a second potential V2, and generates a test reference current control signal CT. First transistor 130 is configured to be controlled by the test reference current control signal CT to generate a test reference current IREFT based on the first potential V1. Switching circuit 140 is coupled to current generator 160, test reference current generation circuit 150, and output node NOUT, and is configured to determine whether to output a normal reference current IREFT or a test reference current IREFT at output node NOUT based on a mode control signal CMD. Current generator 160 can output a normal reference current IREFT.
[0051] The output node NOUT of the reference current generation circuit 100 can be used to drive the internal circuit 190 in the semiconductor device. Based on actual measurement results, the reference current generation circuit 100 provided by this invention can improve the accuracy of the test reference current IREFT, thereby reducing testing costs and suppressing non-ideal errors caused by process variations. Especially in the development stage of introducing new processes, the reference current generation circuit 100 provided by this invention allows the test reference current IREFT to be directly obtained through the test reference current generation circuit 150, without the need for additional testing procedures to measure and compensate the reference current, and then using this compensated reference current for other testing procedures.
[0052] In detail, such asFigure 2 As shown, the switching circuit 241 of the reference current generation circuit 200 may include a first switch 240 and a second switch 250. The reference current generation circuit 200 may further include a resistor 210 coupled between the first node N1 and the third potential V3, and configured to receive the third potential V3 to generate the first potential V1, and provide the first potential V1 to the first node N1. The resistor 210 can provide a highly accurate resistance value, so that the test reference current IREFT generated by the first transistor 230 of the test reference current generation circuit 251 according to the first potential V1 also has high accuracy.
[0053] In this embodiment, the positive input terminal of the operational amplifier 220 of the test reference current generation circuit 251 of the reference current generation circuit 200 is coupled to the first node N1 to receive the first potential V1, the negative input terminal of the operational amplifier 220 is used to receive the second potential V2, and the output terminal of the operational amplifier 220 is coupled to the second node N2. In some embodiments, the third potential V3 may be greater than the second potential V2, and the resistor 210 may be configured to make the first potential V1 equal to or close to the second potential V2. For example, the ratio of the third potential V3 to the second potential V2 is between 1.1 and 2, and the ratio of the first potential V1 to the second potential V2 is between 0.95 and 1.05, but the present invention is not limited thereto.
[0054] The reference current generation circuit 200 can operate in two modes, such as a test mode and a normal mode. In this embodiment, to reduce unnecessary power consumption, the operational amplifier 220 can be configured to determine whether to be enabled based on the mode control signal CMD. For example, as Figure 2 As shown, when the mode control signal CMD indicates test mode, the operational amplifier 220 can be enabled by the first control signal VC1 at a high logic level. Figure 3 As shown, when the mode control signal CMD indicates the normal operating mode, the operational amplifier 220 can be disabled according to the first control signal VC1 with a low logic level.
[0055] In this embodiment, the first transistor 230 may be an N-type metal-oxide-semiconductor field-effect transistor. The control terminal (e.g., gate) of the first transistor 230 is coupled to the second node N2, the second terminal (e.g., source) of the first transistor 230 is coupled to the ground potential VSS, and the first terminal (e.g., drain) of the first transistor 230 is coupled to the first node N1.
[0056] The first terminal of the first switch 240 is coupled to the second node N2, and the second terminal is coupled to the output node NOUT. The first terminal of the second switch 250 is coupled to the third node N3, and the second terminal of the second switch 250 is coupled to the output node NOUT. The first switch 240 and the second switch 250 can be selectively turned on or off according to the mode control signal CMD. For example, as Figure 2 As shown, when the mode control signal CMD indicates test mode, the first switch 240 can be turned on according to the high logic level first control signal VC1 to couple the output node NOUT to the second node N2, and the second switch 250 can be turned off according to the low logic level second control signal VC2 to output the test reference current IREFT at the output node NOUT. Figure 3 As shown, when the mode control signal CMD indicates the normal operation mode, the first switch 240 can be turned off according to the first control signal VC1 with a low logic level, and the second switch 250 can be turned on according to the second control signal VC2 with a high logic level, so as to couple the output node NOUT to the third node N3, while the internal circuit 290 is driven by the normal reference current IREF from the current generator 260.
[0057] In this embodiment, the mode control signal CMD includes a first control signal VC1 and a second control signal VC2. The first control signal VC1 and the second control signal VC2 can be generated by the processor based on user input (not shown). In some embodiments, the first control signal VC1 and the second control signal VC2 can have complementary logic levels. For example, if the first control signal VC1 is a high logic level, then the second control signal VC2 can be a low logic level; conversely, if the first control signal VC1 is a low logic level, then the second control signal VC2 can be a high logic level. Therefore, when one of the first switch 240 and the second switch 250 is turned on, the other of the first switch 240 and the second switch 250 will necessarily be turned off.
[0058] Current generator 260 can output a normal reference current IREF to the third node N3. For example, current generator 260 can be implemented by a current source, but is not limited to this.
[0059] The output node NOUT of the reference current generation circuit 200 is coupled to other internal circuitry 290 of the semiconductor device, such that internal circuitry 290 can be driven by the reference current generation circuit 200. Internal circuitry 290 may include a delay circuit 292, a second transistor 294, and a third transistor 296. The internal structure of the delay circuit 292 is not particularly limited in this invention. For example, delay circuitry 292 may include one or more inverters connected in series. The second transistor 294 and the third transistor 296 may each be an N-type metal-oxide-semiconductor field-effect transistor. In other embodiments, internal circuitry 290 may also include more or fewer transistors.
[0060] The control terminal of the second transistor 294 is coupled to the output node NOUT, the first terminal of the second transistor 294 is coupled to the ground potential VSS, and the second terminal of the second transistor 294 is coupled to the delay circuit 292. In some embodiments, the second transistor 294 and the first transistor 230 may have the same transistor size.
[0061] The control terminal of the third transistor 296 is coupled to the output node NOUT, the first terminal of the third transistor 296 is coupled to the ground potential VSS, and the second terminal of the third transistor 296 is coupled to the delay circuit 292. In some embodiments, the third transistor 296 and the first transistor 230 may have the same transistor size.
[0062] In this embodiment, the first transistor 230 and the transistors of the internal circuit 290 are commonly controlled by the test reference current control signal CT. In other words, the first transistor 230 can be configured as the input transistor of the current mirror, while the transistors of the internal circuit 290 are configured as the output transistors of the current mirror. Specifically, the first transistor 230 and the second transistor 294 are configured to form a first current mirror, while the first transistor 230 and the third transistor 296 are configured to form a second current mirror. In test mode, the operating principle of the reference current generation circuit 200 can be described by the following equations (1) and (2):
[0063]
[0064] ID = IE = IA (2)
[0065] Where “IA” represents the current value of the first current IA flowing through the first transistor 230, “V3” represents the potential level of the third potential V3, “V2” represents the potential level of the second potential V2, “R” represents the resistance value of resistor 210, “ID” represents the current value of the second current ID flowing through the second transistor 294, and “IE” represents the current value of the third current IE flowing through the third transistor 296.
[0066] Because operational amplifier 220 has a feedback mechanism, a virtual short circuit will be formed between its positive and negative input terminals, and the potential at the first node N1 will be equal to the second potential V2. When the mode control signal CMD indicates test mode, according to Ohm's law, the first current IA flowing through resistor 210 and the first transistor 230 must be proportional to the potential difference between the third potential V3 and the second potential V2 (i.e., V3-V2). Because the resistance value of resistor 210 can be very precise, the first current IA will also have almost no error. Then, by using the aforementioned first and second current mirrors, the second current ID flowing through the second transistor 294 and the third current IE flowing through the third transistor 296 will also be essentially equal to the first current IA flowing through the first transistor 230. Therefore, when the reference current generation circuit 200 operates in test mode, the internal circuit 290 receiving this test reference current IREFT can be driven by a highly accurate output current (e.g., the second current ID and the third current IE), and the error value of the timing control of this internal circuit 290 can also be minimized at the same time.
[0067] like Figure 4 As shown, a semiconductor device 400 according to an embodiment of the present invention includes a first bonding pad 410, a second bonding pad 420, a resistor 210, and as shown in the figure. Figure 1 , Figure 2 , Figure 3 Either of the reference current generating circuits 100 and 200 shown. The first pad 410 and the second pad 420 can be made of metallic materials, but are not limited to them. Specifically, the first pad 410 is coupled to the resistor 210 and provides a first potential V1. In addition, the second pad 420 can be used to provide a second potential V2. In one embodiment, a third potential V3 and a second potential V2 can be provided to the resistor 210 and the second pad 420 respectively by an intermediate test stage, and a plurality of resistors 210 are arranged on the test fixture to be connected to the first pads 410 of a plurality of chips respectively. Furthermore, in one embodiment, the outer and inner sides of the chip are represented by the left and right sides of the virtual dividing line LC1, that is, the first pad 410, the second pad 420 and the resistor 210 can be located outside the chip, and the operational amplifier 220, the first transistor 230, the first switch 240, the second switch 250 and the current generator 260 can be located inside the chip. It must be understood that the various parameters of the aforementioned external components can be more easily set and calibrated to provide higher accuracy, and they are not negatively affected by variations in the manufacturing process of the relevant chips. Figure 4 The remaining features of the embodiments are all the same as Figure 1 , Figure 2 , Figure 3 The embodiments are similar, so they will not be repeated here.
[0068] Figure 5This illustration depicts a control method for a semiconductor device according to an embodiment of the present invention, which can be achieved as described above. Figures 1 to 4 These steps are performed by the reference current generating circuit 100, 200 or the semiconductor device 400. For example... Figure 5 As shown, in step S1, the switching circuit determines whether to output a normal reference current or a test reference current at the output node of the reference current generation circuit based on the mode control signal. When it is determined to output a normal reference current, in step S2, the normal reference current is output by connecting the current generator of the reference current generation circuit to the output node. When it is determined to output a test reference current, steps S3 and S4 are executed. In step S3, the operational amplifier of the reference current generation circuit receives a first potential and a second potential, and generates a test reference current control signal. In step S4, the first transistor controlled by the test reference current control signal generates a test reference current based on the first potential. Before step S1, if the semiconductor device is in test mode, the first potential can be provided via a first pad coupled to a resistor, and the second potential can be provided via a second pad. After step S2 or S4, the reference current or test reference current output by the output node can be copied, and the copied reference current or test reference current is provided to the delay circuit. The remaining steps and detailed descriptions of the control method for the semiconductor device according to an embodiment of the present invention can be found in the previous embodiments and will not be repeated here.
[0069] This invention proposes a novel reference current generation circuit, a semiconductor device, and a control method thereof, which can improve the accuracy of the test reference current, thereby reducing test procedures and lowering test costs. Particularly for miniaturized semiconductor devices, the test reference current generation circuit of this invention can directly provide an ideal or near-ideal test reference current without requiring additional test procedures for measuring and compensating the reference current, thus reducing test costs. Furthermore, according to this invention, since an ideal or near-ideal test reference current can be provided to the internal circuitry in test mode, problems in the internal circuitry can be identified more quickly and accurately, thereby improving the timing control accuracy of subsequent products and increasing yield.
[0070] Although the embodiments of the present invention use metal-oxide-semiconductor field-effect transistors as an example, those skilled in the art can use other types of transistors, such as junction field-effect transistors or fin field-effect transistors, without affecting the effect of the present invention.
[0071] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.
Claims
1. A reference current generating circuit, characterized in that, include: A current generator outputs a normal reference current; A test reference current generation circuit includes: An operational amplifier is configured to receive a first potential and a second potential, and to generate a test reference current control signal; and A first transistor is configured to generate a test reference current based on the first potential, controlled by the test reference current control signal; and A switching circuit is coupled to the current generator, the test reference current generation circuit and an output node, and is configured to determine whether to output the normal reference current or the test reference current at the output node according to a mode control signal.
2. The reference current generating circuit as described in claim 1, characterized in that, The operational amplifier is configured to determine whether to be enabled based on the mode control signal.
3. The reference current generating circuit as described in claim 1, characterized in that, The operational amplifier receives the first potential at a first input terminal via a first node, receives the second potential at a second input terminal, and has an output terminal coupled to a second node. The first transistor has a control terminal coupled to the second node, and a first terminal coupled to the first node.
4. The reference current generating circuit as described in claim 3, characterized in that, The current generator is coupled to a third node, and the switching circuit includes: A first switch is disposed between the second node and the output node and is controlled by the mode control signal; and A second switch is located between the third node and the output node and is controlled by the mode control signal. Specifically, when the mode control signal indicates a test mode, the first switch is turned on and the second switch is turned off; when the mode control signal indicates a normal operation mode, the first switch is turned off and the second switch is turned on.
5. The reference current generating circuit as described in claim 3, characterized in that, Including: A resistor is coupled to the first node, wherein the resistor is configured to receive a third potential to generate the first potential, and the third potential is greater than the second potential.
6. The reference current generating circuit as described in claim 1, characterized in that, This second potential serves as the bandgap voltage reference source.
7. The reference current generating circuit as described in claim 1, characterized in that, The first potential is equal to the second potential.
8. The reference current generating circuit as described in claim 4, characterized in that, The mode control signal includes a first control signal and a second control signal. The first switch receives the first control signal, the second switch receives the second control signal, and the first control signal and the second control signal have complementary logic levels.
9. A semiconductor device, characterized in that, include: A resistor; A first solder pad is coupled to the resistor and provides a first potential; A second solder pad provides a second potential; and A reference current generating circuit, including: A current generator outputs a reference current; A test reference current generation circuit includes: An operational amplifier is configured to receive a first potential and a second potential, and to generate a test reference current control signal; A first transistor is configured to generate a test reference current based on the first potential, controlled by the test reference current control signal; and A switching circuit is coupled to the current generator, the test reference current generation circuit and an output node, and is configured to determine, based on a mode control signal, whether to output a normal reference current or the test reference current at the output node.
10. The semiconductor device as claimed in claim 9, characterized in that, Including: A delay circuit; as well as A second transistor, wherein a control terminal of the second transistor is coupled to the output node, and a first terminal of the second transistor is coupled to the delay circuit.
11. The semiconductor device as claimed in claim 9, characterized in that, The operational amplifier, the first transistor, the switching circuit, and the current generator are located inside a chip, while the resistor, the first pad, and the second pad are located outside the chip.
12. The semiconductor device as claimed in claim 9, characterized in that, The operational amplifier is configured to determine whether to be enabled based on the mode control signal.
13. The semiconductor device as claimed in claim 9, characterized in that, The operational amplifier receives the first potential at a first input terminal via a first node, receives the second potential at a second input terminal, and has an output terminal coupled to a second node. The first transistor has a control terminal coupled to the second node, and a first terminal coupled to the first node.
14. The semiconductor device as claimed in claim 13, characterized in that, The current generator is connected to a third node, and the switching circuit includes: A first switch is disposed between the second node and the output node and is controlled by the mode control signal; and A second switch is located between the third node and the output node and is controlled by the mode control signal. Specifically, when the mode control signal indicates a test mode, the first switch is turned on and the second switch is turned off; when the mode control signal indicates a normal operation mode, the first switch is turned off and the second switch is turned on.
15. The semiconductor device as claimed in claim 14, characterized in that, The mode control signal includes a first control signal and a second control signal. The first switch receives the first control signal, the second switch receives the second control signal, and the first control signal and the second control signal have complementary logic levels.
16. A method for controlling a semiconductor device, characterized in that, include: A switching circuit determines, based on a mode control signal, whether to output a normal reference current or a test reference current at an output node of a reference current generation circuit. When it is decided to output the normal reference current, the normal reference current is output by connecting a current generator of the reference current generation circuit to the output node. Once you decide to output the test reference current, perform the following steps: An operational amplifier in the reference current generation circuit receives a first potential and a second potential, and generates a test reference current control signal. and The test reference current is generated according to the first potential via a first transistor controlled by the test reference current control signal.
17. The control method for a semiconductor device as claimed in claim 16, characterized in that, Including: The operational amplifier is activated or deactivated based on the mode control signal.
18. The control method for a semiconductor device as claimed in claim 16, characterized in that, When the mode control signal indicates a test mode, the test reference current is output at the output node, and when the mode control signal indicates a normal operation mode, the normal reference current is output at the output node.
19. The control method for a semiconductor device as claimed in claim 16, characterized in that, Including: The first potential is provided via a first pad coupled to a resistor; The second potential is provided via a second solder pad; and The normal reference current or the test reference current output by the output node is copied, and the copied normal reference current or the test reference current is provided to a delay circuit.