An RTL code generation method, a computer device and a readable storage medium
By constructing a structure graph and a bidirectional mapping index, and combining large models and EDA tool feedback, the problems of low efficiency and insufficient automation in existing RTL code generation are solved, achieving efficient and automated RTL code generation and repair.
Patent Information
- Application Number
- CN202610605128.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-06
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2046-05-06
AI Technical Summary
Existing methods for generating RTL code based on large language models suffer from implicit expression of design elements, lack of early static checks, and unstructured feedback reports from EDA tools, resulting in low automation, long iteration cycles, and a lack of incremental updates and impact analysis, making it difficult to achieve efficient RTL code generation.
Compliance checks are performed by constructing a structure diagram, initial RTL code is generated and comprehensive performance checks are conducted, and RTL code is generated by combining a large model and rules. A bidirectional mapping index between the structure diagram and the initial RTL code is established, and EDA tool reports are automatically parsed to form a closed-loop iterative optimization.
It enables early detection of design problems, improves the efficiency and automation of RTL code generation, reduces manual intervention, lowers iteration costs, and supports flexible incremental updates and efficient error location and repair.
Smart Images
Figure CN122152323B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of software code development, and in particular to the technology of electrical digital data processing. Specifically, it relates to an RTL code generation method and a computer device and computer-readable storage medium for implementing the method. Background Technology
[0002] With the development of intelligent and digital technologies, artificial intelligence technology has been widely applied. Currently, large language models based on artificial intelligence have the ability to directly convert natural language specifications into HDL / RTL code. Therefore, Spec-to-RTL (from protocol to RTL design) is gradually becoming an exploration direction to improve chip design efficiency, which can lower the threshold and shorten the chip iteration cycle.
[0003] However, due to the extremely high requirements for interface, protocol, timing, and clock domain consistency in chip hardware design, the implementation of Spec-to-RTL is still constrained by various factors. For example, constraint information (interface direction, bit width, protocol fields, timing constraints) is often scattered in text and difficult to express in a unified structure. Basic errors usually only become apparent during simulation or synthesis. Once an anomaly is discovered, the RTL code needs to be repaired, resulting in excessively long RTL code generation time. In addition, existing generation methods lack a closed loop of constraint verification before generation and location / repair write-back after generation, making quality highly dependent on prompts and data coverage. Furthermore, feedback from tools such as synthesis / STA / Lint after code generation is mainly log reports, which are difficult to directly map to design elements and drive local updates, resulting in high code iteration costs and still requiring significant manual intervention.
[0004] One existing method for generating RTL based on a large language model is a fine-tuning method based on the large language model. Specifically, the large model is fine-tuned on hardware data to improve the accuracy of RTL generation. However, in this approach, key constraints such as chip design interfaces, protocols, and timing are still easily hidden in the text, lacking a unified structured representation and pre-verification, thus limiting generalization ability.
[0005] Another approach is based on multi-agent collaboration, where multiple AI agents are assigned to cover different design phases. However, this approach lacks a unified intermediate representation or consistency constraints, making it difficult to structure and accumulate collaborative information, which can easily lead to global inconsistencies. Furthermore, the coordination costs at each stage are high.
[0006] Another approach is iterative optimization based on EDA tool feedback. This method uses EDA feedback such as synthesis and simulation to drive optimization or iterative training. However, the logs and reports generated by this method are mostly unstructured text, making it difficult to automate the localization-repair mapping. Furthermore, the lack of early checks leads to a longer iteration cycle.
[0007] In general, existing RTL code generation methods based on large models suffer from the following problems: First, the implicit expression of design elements makes it difficult to achieve automated consistency verification and reuse of design elements; second, the lack of static checks before code generation means that rules such as chip design direction compatibility, bit width matching (including legal conversion), protocol field integrity, and clock domain / reset binding lack pre-verification, making it difficult to detect basic errors early; third, the feedback reports of EDA tools do not form a closed loop, and the output results of tools such as synthesis and STA are difficult to structure and fall into specific design elements, and error location and repair suggestions rely on manual work, resulting in low automation; fourth, the lack of incremental updates and impact analysis means that once the generated RTL code needs to be locally modified, it often triggers large-scale regeneration and repeated verification, lacking impact scope assessment and cache reuse mechanisms based on dependency relationships; fifth, insufficient traceability means that existing methods usually include three stages: "requirements - intermediate representation - code", and there is a lack of stable mapping chains between the stages, resulting in low efficiency in problem backtracking and change evaluation. Summary of the Invention
[0008] The primary objective of this invention is to provide an RTL code generation method that facilitates early problem detection and backtracking for problem discovery.
[0009] A second objective of the present invention is to provide a computer device for implementing the above-described RTL code generation method.
[0010] A third objective of this invention is to provide a readable storage medium for implementing the above-described RTL code generation method.
[0011] To achieve the first objective of this invention, the RTL code generation method provided by this invention includes the following steps performed by a processor: acquiring natural language, analyzing the natural language and constructing a structure graph based on the analysis results, the structure graph containing nodes, edges, and attribute information of nodes and edges; performing a compliance check on the structure graph to determine whether the design information represented by the structure graph meets the requirements of connection requirements and / or constraint rules; if the structure graph fails the compliance check, identifying the abnormal location and repairing the structure graph; if the structure graph passes the compliance check, generating initial RTL code based on the structure graph; performing a comprehensive performance check on the initial RTL code; if the initial RTL code fails the comprehensive performance check, identifying the error location and repairing the code at the error location; if the initial RTL code passes the comprehensive performance check, outputting the initial RTL code as the final RTL code.
[0012] As can be seen from the above scheme, this invention parses natural language and first constructs a result graph. Before generating RTL code, it performs a compliance check on the structure graph, that is, it first determines whether there are any errors in the structure graph. If errors are found, the structure graph is corrected first, and then RTL code is generated based on the corrected result graph. In this way, by checking the structure graph in advance and discovering problems before generating RTL code, it avoids the problem of discovering and fixing problems after the RTL code is generated. By discovering problems in advance and correcting the structure graph in advance, it avoids the problem of modifying the RTL code back and forth, thus improving the efficiency of RTL code generation.
[0013] Furthermore, when performing a comprehensive performance check on the initial RTL code, the error locations in the initial RTL code will also be identified. Based on these error locations, the scope that needs to be fixed can be quickly determined, which can further improve the efficiency of RTL code generation.
[0014] A preferred approach is to generate initial RTL code based on the structure diagram, which includes: obtaining interface and interconnect structure information from the structure diagram, generating RTL code for the interface and interconnect structure according to the rules determined by the design specifications and interface protocols; obtaining the logical structure of the structure diagram, and generating RTL code for the logical structure based on a preset large model.
[0015] Therefore, for the interface and interconnection structures in the structure diagram, RTL code is directly generated based on protocol rules. For more complex logical structures, RTL code is generated based on a large model. Thus, the RTL code generation process is implemented by combining rules and a large model, making RTL code generation more flexible. In this way, this invention fully utilizes the intelligent processing capabilities of the large model while abstracting key rules and processes to constrain its behavior. This ensures that the large model possesses both broad flexibility and guarantees high-quality and deterministic output in professional RTL design.
[0016] A further approach is to establish a bidirectional mapping index between each node of the structure graph and the initial RTL code when generating the initial RTL code based on the structure graph.
[0017] A further approach involves performing a comprehensive performance check on the initial RTL code, including: parsing the logs that generated the initial RTL code, obtaining the error locations and object names in the initial RTL code, and using bidirectional mapping indexes to determine the error nodes and / or error edges in the structure graph based on unstructured error information.
[0018] Therefore, by constructing a bidirectional mapping index relationship between each node of the structure graph and the initial RTL code, when performing comprehensive performance checks on the subsequent RTL code, if an anomaly is found in the RTL code, the location of the erroneous node and / or erroneous edge in the structure graph can be quickly determined through this bidirectional mapping index, thereby quickly repairing the structure graph and improving the generation efficiency of RTL code.
[0019] A further approach is to obtain the EDA tool's inspection report when performing a comprehensive performance check on the initial RTL code, parse the inspection report, and drive the update of the structure graph based on the parsing results of the inspection report.
[0020] Therefore, it can be seen that the system that generates RTL code can automatically obtain and parse the inspection report, and can also automatically drive the update of the structure diagram based on the parsing results. It does not require manual review of the report and manual updating of the structure diagram, and the system has a high degree of automation.
[0021] A further approach is to store the attribute information of nodes and edges in the structure graph in the form of key-value pairs.
[0022] Storing node and edge attribute information in key-value pairs allows for the direct addition of new types of constraint attributes such as power consumption and physical location of nodes and edges without changing the graph topology definition, providing extremely high flexibility in setting node and edge attributes.
[0023] A further approach is to conduct compliance checks on the architecture diagram, including at least one of the following: direction consistency check, bit width matching check, protocol integrity check, and clock domain binding check.
[0024] Therefore, by performing multiple checks on nodes and edges, the logic of the structure graph can be comprehensively checked before generating RTL code, thereby discovering potential problems and avoiding repeated code modifications due to issues in the later generation of RTL code.
[0025] A further approach involves performing a comprehensive performance check on the initial RTL code and then fixing the code at the error location. This includes: determining the impact of the error location on the RTL code to form an affected set; performing a comprehensive performance check on the modules within the affected set and regenerating the RTL code; and merging the regenerated RTL code into the global RTL code.
[0026] Therefore, this invention only performs local repair on the problematic RTL code, rather than performing overall repair on all RTL code. After performing local repair on the RTL code, the repaired RTL code can be merged into the global RTL code, reducing the computational load of RTL code generation.
[0027] To achieve the second objective described above, the computer device provided by the present invention includes a processor and a memory, the memory storing a computer program, which, when executed by the processor, implements the various steps of the RTL code generation method described above.
[0028] To achieve the third objective mentioned above, the storage medium provided by the present invention stores a computer program, which, when executed by a processor, implements the various steps of the RTL code generation method described above. Attached Figure Description
[0029] Figure 1 This is a flowchart of an embodiment of the RTL code generation method of the present invention.
[0030] Figure 2 This is a flowchart of compliance checks in an embodiment of the RTL code generation method of the present invention.
[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation
[0032] The RTL code generation method of this invention is applied in the integrated circuit manufacturing process. It uses a large language model to generate RTL code based on natural language and combines artificial intelligence technology to improve the efficiency of RTL code generation. The method of this invention can be implemented on a computer device having a processor and a memory. The memory is a readable storage medium of this invention, storing a computer program. When the computer program is executed by the processor, it represents the various steps of the aforementioned RTL code generation method.
[0033] Example of RTL code generation method: This embodiment is executed by the processor, that is, by the computer's processor. Figure 1 and Figure 2 The steps shown.
[0034] See Figure 1 In this embodiment, step S11 is first executed to acquire natural language. The natural language in this embodiment can be text input by the user on the human-computer interaction interface or speech input via a microphone. When acquiring natural language, the user's input text information can be obtained through the human-computer interaction interface, or the user's speech can be obtained through a microphone, and the acquired natural language is then parsed. Preferably, the natural language provided by the user needs to include a description of the function to be implemented, interface information, and constraint information. When parsing the natural language, the function description, interface information, and constraint information need to be extracted from the natural language, and the chip's design specifications need to be analyzed, as well as key elements such as interfaces, protocols, and timing sequences.
[0035] Then, step S12 is executed to construct a structure graph based on the parsing result of step S11. In this embodiment, the structure graph can be a relationship graph, attribute graph, knowledge graph, JSON-IR, etc. The structure graph needs to support the setting of node attributes and edge attributes, and needs to have traceable indexing functionality. Taking a relationship graph as an example, step S12 needs to construct each node and each edge of the relationship graph based on the parsing structure of natural language, and set the attributes of each node and each edge.
[0036] Specifically, the association graph in this embodiment is formally represented using a directed attribute graph structure, defined as follows: ,in For a set of nodes, Let be the set of edges. These are the attribute functions of a node. These are the attribute functions of the edges. The type definition of the node set V is shown in Table 1, and the edge set... The type definitions are shown in Table 2.
[0037] Table 1. Definition of Node Set V
[0038] Table 2 Edge Set Type definition table
[0039] The attribute functions of a node are represented as follows: The attribute function of the edge is represented as This involves mapping nodes and edges to their attribute sets. Preferably, the attributes of nodes and edges are stored in the form of key-value pairs, such as a list of key-value pairs. This allows for the direct addition of new constraint attributes, such as power consumption and physical location, without changing the topological definition of the association graph (i.e., the set of nodes and edges). This makes the extension of node and edge attributes highly flexible.
[0040] In step S12, based on the parsing results of natural language, the interface definition and timing requirements obtained from natural language parsing are mapped to nodes and corresponding attributes in the association graph by matching the preset protocol template and constraint rules, thereby ensuring the accuracy of converting natural language into an association graph.
[0041] After constructing the association graph, compliance checks need to be performed, such as static consistency checks. The purpose of this is to determine whether the design information represented by the association graph meets the basic connection requirements and constraint rules. In some embodiments, it may only be necessary to check whether the basic connection requirements or constraint rules are met. During this check, key information such as interfaces, protocols, and clock domains is typically examined. Specifically, when performing static consistency checks, it is necessary to traverse the pre-defined key nodes and associated edges in the association graph, or traverse all nodes and edges in the association graph, and verify the logical completeness represented by the association graph by identifying specific subgraph structures, such as cross-clock domain connection paths. Preferably, the compliance checks on the association graph mainly perform direction consistency checks, bit width matching checks, protocol integrity checks, and clock domain binding checks.
[0042] The process includes several key aspects: Directional consistency checking ensures that the attributes of each edge meet the requirements from the target port (Output) to the source port (Input). Specifically, it involves traversing each edge in the graph and determining if its attributes satisfy the rules for traversing from the target port to the source port. Bit width matching checking verifies whether the bit widths of the two connected sides of each edge are consistent, or whether there are valid bit width conversions, such as high-order truncation or zero extension. Protocol integrity checking, in the case of a standard protocol (such as AXI4), checks whether each node contains all necessary control and data signals, such as AWVALID and AWREADY. This check requires examining the set of interface nodes labeled with specific protocol attributes based on a pre-defined list of protocol signals, verifying that these nodes contain all the necessary signals defined in the template. Clock domain binding checking checks whether cross-clock domain connections contain necessary synchronization logic, such as FIFO or dual-flip-flop synchronization. This check is achieved by identifying the synchronization logic structure on the connection path. For example, if the clock domain attributes of the nodes at both ends of an edge are inconsistent, it further checks whether a synchronization structure conforming to the CDC specification exists on that path.
[0043] Protocol integrity checks can be performed not only on the AXI4-Lite protocol, but also on various chip protocol specifications, such as AXI4, APB, TileLink, or custom protocols. Static consistency checks can also add new check items, such as CDC, reset strategy, timing exceptions, etc.
[0044] See Figure 2When performing a static consistency check on the association graph, step S21 is executed first to obtain the association graph constructed in step S12. Then, step S22 is executed to determine whether there are any unchecked edges in the association graph. If there are still unchecked edges, step S23 is executed to obtain an unchecked edge as the edge to be checked, and to obtain the attribute information of the edge to be checked. Then, step S24 is executed to perform a static consistency check on the edge to be checked, and to record the violations that occur during the check process, that is, to record the violations that occur in the direction consistency check, bit width matching check, protocol integrity check, and clock domain binding check. If the judgment result of step S22 is negative, it means that all edges in the association graph have been checked, and then step S25 is executed to directly output the check report.
[0045] After the compliance check is performed, step S13 is executed to determine whether the association graph has passed the compliance check. If it has passed the compliance check, step S14 is executed. If it has not passed the compliance check, step S15 is executed to determine the reason for failing the compliance check, that is, to find the location of the anomaly and to fix the anomaly. This means to locate the location of the anomaly, determine the specific problem of the anomaly, and provide a fixation suggestion. Then, the process returns to step S12 to rebuild the association graph based on the fixation suggestion.
[0046] If the association graph passes the compliance check, step S14 requires generating mapping logic based on the association graph, that is, mapping the compliance-compliant association graph to the implementation logic of RTL. In step S14, the RTL implementation logic is generated using a combination of rule mapping and model assistance. Specifically, for structured parts such as interfaces and interconnect structures, rules determined by design specifications and interface protocols are used to generate the corresponding logic; for complex internal logic, a large model is used to assist in generating the corresponding logic. Furthermore, during the generation of the RTL implementation logic, a bidirectional mapping index needs to be established between each node of the association graph and the generated RTL code, providing a foundation for subsequent error location and incremental updates.
[0047] Then, step S16 is executed to generate RTL code that can be verified by tools based on the mapping logic generated in step S14, which is to form the initial RTL code. It can be seen that in this embodiment, the process of generating the initial RTL code is based on the rules determined by the pre-set design specifications and interface protocols to generate the RTL code for the interface and interconnection structure, and uses a preset large model to generate the RTL code for the internal control logic structure. The large model used in this embodiment can be obtained through a large model or by fine-tuning a general large model. After generating the initial RTL code, the initial RTL code, constraints, and verification results can be stored in a cache.
[0048] Next, the generated initial RTL code needs to undergo a synthesis performance check. Specifically, EDA tools are used to synthesize, perform static timing analysis, and conduct Lint checks on the initial RTL code. This embodiment can use existing EDA tools to ensure the accuracy of the check. After the check, step S17 is executed to determine whether the generated initial RTL code passes the synthesis performance check. If it passes, step S18 is executed to use the initial RTL code that passes the synthesis performance check as the final RTL code and output it. In addition to outputting the RTL code, the system also outputs the corresponding constraint files and design documents. If the initial RTL code fails the synthesis performance check, step S19 is executed to determine the location that caused the failure, and step S20 is executed to locally update the structure diagram.
[0049] In step S19, the system can automatically obtain the inspection report of the EDA tool and parse the obtained inspection report. Based on the parsing result of the inspection report, the system drives the update of the association diagram. In this way, by constructing an automated closed loop from EDA tool feedback to design correction, the system realizes the automatic parsing of the inspection report output by the EDA tool and drives the update of the association diagram, replacing the traditional process of manually reading the report and manually modifying the association diagram, which can significantly improve the efficiency of RTL code generation.
[0050] In addition, in step S19, once the EDA tool is found to have an error, the error location and object name in the log are parsed, and the bidirectional mapping index established when constructing the logical structure of the association graph in step S14 is used to accurately locate the unstructured error information to the specific node or edge of the association graph. In this way, error location can be achieved quickly.
[0051] When parsing logs output by EDA tools, template rules, AST / IR parsers, or large language models can be used to assist in parsing, as long as structured "location + repair instructions" can be output. Furthermore, the parsing module can output structured data containing location information and repair actions. Specific parsing implementations (template rules / AST / large language models) can be replaced without affecting the universality of the closed-loop process.
[0052] Furthermore, in step S20, this embodiment only updates the scope of the error locally, rather than regenerating all the RTL code. In this way, based on the feedback information from the EDA tool or the change in requirements, the part of the association diagram that needs to be updated is locally updated, and the incremental regeneration mechanism is triggered. The scope of the impact of the error location on the RTL code is determined to form an affected set, and the process returns to step S14. After re-performing the comprehensive performance check on the modules in the affected set, the RTL code within the affected scope is regenerated, and then this regenerated part of the RTL code is merged into the global RTL code.
[0053] Specifically, once the EDA tool's inspection report shows an error in the RTL code, an impact analysis is first performed to determine the scope of the error's impact on the RTL code. The triggering condition is a change in node attributes or connection relationships, such as changing the interface width from 32 bits to 64 bits. At this point, the system traverses and calculates along the dependency edges, starting from the node that needs to be changed. For direct dependencies, such as nodes directly connected to the affected node by a connection edge or dependency edge, these nodes need to be marked. For indirect dependencies, such as a node that can reach another node through multiple levels of connections, whether to mark the node depends on the type of dependency edge. Specifically, if the dependency path is a data path or control logic connection, the node is marked; if a node is only associated with the affected node by timing or physical constraints, it does not need to be marked; nodes without dependencies are not marked. After the above operations, an affected set S_affected is formed, containing all marked nodes, while unmarked nodes form an unaffected set S_unaffected.
[0054] When performing local regeneration of the association graph, only the affected set S_affected is calculated. Specifically, the affected set S_affected is grouped according to module boundaries, and each module node independently performs a re-static consistency check and regenerates its RTL code and constraint file. If the interface of the current module is not a source of change, the interface of the current module remains unchanged, and the locally generated RTL code is merged with the global RTL code, and interface consistency is checked.
[0055] For modules within the unaffected set S_unaffected, the generated RTL code and passed verification results are directly reused, such as the module hash value, generated RTL code, and verification status recorded in the cache. It is evident that if the node attributes, module input interface, or dependent module interface within a module change, the cached data for that module will become invalid. This embodiment only requires regenerating RTL code for modules whose cache has become invalid. Furthermore, the granularity of incremental RTL code regeneration can be selected between the module level, subgraph level, or signal level, thereby flexibly setting the amount of RTL code to be regenerated in different scenarios.
[0056] As can be seen, this invention, through multiple methods such as intermediate representation of the association graph, static consistency checking, EDA feedback loop, and incremental regeneration, forms a Spec-to-RTL process that can be implemented in engineering. Compared with traditional RTL code generation methods, it has the following advantages: First, the present invention can utilize a large model to perform operations such as constructing association graphs, generating RTL code, generating bidirectional mapping indexes, and updating association graphs. The large model enables operations such as association graph analysis and inspection report interpretation, thereby improving the efficiency of RTL code generation.
[0057] Secondly, this invention transforms implicit design attributes (such as interface direction and protocol type) into explicit modeling as association graph attributes and constructs verifiable association graphs. This converts unstructured natural language specifications into structured graph models, supporting formal static checks and incremental generation. Based on this, the static check rules implemented by the association graph (such as direction matching and protocol field alignment) can detect fundamental errors early in the design process. It can identify and correct fundamental errors such as interface direction, bit width, protocol fields, and cross-clock domain errors before RTL code generation, avoiding the rework costs caused by delayed problem exposure in traditional methods.
[0058] Third, this invention constructs a closed-loop operation from EDA tool verification to RTL code optimization. Specifically, it converts the error logs and timing reports of the EDA tool into structured repair instructions for nodes in the association graph (such as "adjust timing constraints" and "correct port direction" instructions). The outputs of synthesis, STA, and Lint are then converted into structured repair instructions and written back to the association graph, forming a closed-loop iteration that improves optimization efficiency and reduces manual intervention. This invention analyzes the error characteristics in the EDA report, converting them into specific operations for the association graph, such as modifying attributes and adding nodes. These instructions are automatically executed to complete the repair, achieving a semantic conversion from textual feedback to model updates. Furthermore, it can automatically guide large language models to perform precise local updates, achieving highly automated iterative optimization.
[0059] Fourth, if the association diagram is incorrect or requires local adjustments, this invention only needs to make local adjustments to the parts that need to be updated. For the unaffected parts, the data recorded in the cache can be reused directly, which significantly reduces the cost of changing RTL code.
[0060] Fifth, this invention constructs a bidirectional mapping index between nodes, edges, attribute information in the association graph and RTL code, thereby establishing a mapping link from requirements to interfaces / constraints to code. Once a problem occurs in the association graph or RTL code, the location of the problem can be quickly determined through the bidirectional mapping index, and the scope that needs to be updated can be quickly assessed.
[0061] Sixth, this invention can eliminate the ambiguity of natural language expression, making various design elements reviewable, reusable, and quantifiable, and enabling designers to intuitively understand the design logic.
[0062] Computer device embodiment: The computer device in this embodiment can be various types of computer devices, such as desktop computers, laptops, data processing servers, etc. The computer device has a processor, a memory, and a computer program stored in the memory and executable on the processor, such as an information processing program for implementing the above-described information processing method. When the processor executes the computer program, it implements each step of the above-described RTL code generation method.
[0063] For example, a computer program can be divided into one or more modules, one or more of which are stored in memory and executed by a processor to complete the various modules of the present invention. One or more modules can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in a terminal device.
[0064] The processor referred to in this invention can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting various parts of the terminal device through various interfaces and lines.
[0065] Memory can be used to store computer programs and / or modules. The processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory. Memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function, etc.; the data storage area may store data created based on the use of the mobile phone, etc. In addition, memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital cards (SD cards), flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.
[0066] Storage medium examples: If a computer program stored in a computer device is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. This computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the various steps of the above RTL code generation method.
[0067] Computer programs include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in computer-readable media can be appropriately added to or subtracted according to the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.
[0068] Finally, it should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. An RTL code generation method, characterized in that, This includes the following steps performed by the processor: Natural language is acquired, the natural language is analyzed, and a structural graph is constructed based on the analysis results. The structural graph includes nodes and edges, as well as the attribute information of the nodes and the attribute information of the edges. The structure diagram is subjected to a compliance check to determine whether the design information represented by the structure diagram meets the requirements of connection requirements and / or constraint rules. If the structure diagram fails the compliance check, the abnormal location is identified and the structure diagram is repaired. RTL code is generated based on the corrected structure diagram. If the structure diagram passes the compliance check, then initial RTL code is generated based on the structure diagram, and a bidirectional mapping index between each node of the structure diagram and the initial RTL code is established. The initial RTL code undergoes a comprehensive performance check. If the initial RTL code fails the comprehensive performance check, the error location is identified, and the error node and / or error edge in the structure graph is determined using the bidirectional mapping index. The impact range of the error location on the RTL code is determined to form an affected set, and the code at the error location is repaired. If the initial RTL code passes the comprehensive performance check, the initial RTL code is output as the final RTL code.
2. The RTL code generation method according to claim 1, characterized in that: Generating the initial RTL code based on the structure diagram includes: Obtain the interface and interconnection structure information in the structure diagram, and generate the RTL code of the interface and interconnection structure according to the rules determined by the design specifications and interface protocols; Obtain the logical structure of the structure diagram, and generate RTL code for the logical structure based on a preset large model.
3. The RTL code generation method according to claim 2, characterized in that: A comprehensive performance check of the initial RTL code includes: The logs that generate the initial RTL code are parsed to obtain the error locations and object names in the initial RTL code. The error nodes and / or error edges in the structure graph are determined based on the unstructured error information using the bidirectional mapping index.
4. The RTL code generation method according to claim 3, characterized in that: When performing a comprehensive performance check on the initial RTL code, the check report from the EDA tool is also obtained and parsed. The update of the structure diagram is driven based on the parsing results of the check report.
5. The RTL code generation method according to any one of claims 1 to 4, characterized in that: In the structural diagram, the attribute information of the nodes and the attribute information of the edges are stored in the form of key-value pairs.
6. The RTL code generation method according to any one of claims 1 to 4, characterized in that: The compliance check of the structure diagram shall include at least one of the following: direction consistency check, bit width matching check, protocol integrity check, and clock domain binding check.
7. The RTL code generation method according to any one of claims 1 to 4, characterized in that: After performing a comprehensive performance check on the initial RTL code, the code at the error locations is repaired, including: After determining the scope of the impact of the error location on the RTL code and forming an affected set, the modules within the affected set are re-integrated for performance checks and the RTL code is regenerated. The regenerated RTL code is then merged into the global RTL code.
8. A computer device, characterized in that, It includes a processor and a memory, the memory storing a computer program, which, when executed by the processor, implements the various steps of the RTL code generation method as described in any one of claims 1 to 7.
9. A readable storage medium having a computer program stored thereon, characterized in that: When a computer program is executed by a processor, it implements the steps of the RTL code generation method as described in any one of claims 1 to 7.