Decoupling atomicity from operation size

Abstract

The present disclosure relates to decoupling atomicity from operation size. In one embodiment, a processor implements an atomicity size that is different from an operation size (for memory consistency order). More specifically, the processor can implement an atomicity size that is smaller than the operation size. For example, for a multiple register load, the atomicity size can be a register size. As another example, a vector element size can be the atomicity size for a vector load instruction. As yet another example, a number of contiguous vector elements (but less than all vector elements in a vector register) can be the atomicity size for a vector load instruction.

Description

[0001] This application is a divisional application of patent application No. 202180043174.4 entitled "Decoupling Atomicity from Operation Size", filed on May 27, 2021. Technical Field

[0002] The implementation scheme described herein relates to processors, and more specifically to processing sorting within processors to meet memory coherence model requirements. Background Technology

[0003] Processors achieve high performance by executing instructions out of program order when possible. For most arithmetic / logic (ALU) type instructions, branch instructions, and other non-memory instructions, execution can proceed in any order that produces the same result as if the instructions were executed in program order. Instruction set architectures (ISAs) also include memory instructions / operations, such as load and store instructions for reading and writing memory respectively in most ISAs, or instructions with memory operands in other ISAs. For memory instructions / operations, the ordering model (or memory consistency model) is somewhat more complex because the result of a memory write is visible at some point to other threads (e.g., threads executing on other processors in a multiprocessor environment). The memory consistency model specifies a set of acceptable outcomes for intra-thread and inter-thread memory visibility. The memory consistency model used in this paper is also more briefly referred to as the memory model, memory ordering model, or ordering model.

[0004] In the most stringent ordering model (sequential consistency), all memory instructions must behave as if they have been executed in program order. Other ordering models are more lenient. For example, in a Full Memory Order (TSO), a processor can move its own reads before its own writes, but a given write must be visible to all processors at the same logical moment (e.g., become the result of a read). One requirement for ensuring TSO or other more stringent memory models is that a given read receives its bytes from the same source (e.g., storage in a memory queue, or cache or main memory). When the same source requirement is met for a given read, the given read logically receives all its bytes before or after the given write is executed. If bytes from more than one source are allowed to mix, a given read may observe an incorrect order during multiple writes.

[0005] Another performance enhancement technique is instruction fusion. For example, some ISAs support load instructions that write to multiple registers (e.g., load pair instructions in the ARM ISA, load multiple or load string instructions in the Power ISA, etc.). Because such load instructions have large operation sizes, they are unlikely to obtain all their bytes from a single source in a processor that implements a memory queue. Similarly, vector instructions typically have large operation sizes to support a large number of vector elements in vector registers (e.g., 128 bits, 256 bits, 512 bits, etc.). The performance of multiple register loads or vector loads is thus compromised because slower execution is required to maintain the atomicity of more stringent ordering models such as TSO. Summary of the Invention

[0006] In one implementation, the processor implements an atomicity size (for memory coherence ordering) different from the operation size. More specifically, the processor may implement an atomicity size smaller than the operation size. For example, for multiple register loads, the atomicity size could be the register size. Similarly, the vector element size could be the atomicity size for a vector load instruction. Furthermore, multiple consecutive vector elements (but fewer than all vector elements in a vector register) could be the atomicity size for a vector load instruction. The atomicity of the load can be satisfied when the data source for each atomic element of the operation originates from a single source (e.g., a memory queue or cache / memory), thus allowing the load to complete without retries or flushes. In one implementation, processor performance can be improved when performing such loads. Attached Figure Description

[0007] The following detailed description refers to the accompanying drawings, which will now be briefly described.

[0008] Figure 1 This is a block diagram of the processor.

[0009] Figure 2 This is a block diagram illustrating the decoupling atomicity and operation size for one implementation.

[0010] Figure 3 This is a flowchart illustrating the operation of one implementation of the processor during the execution of a loading operation.

[0011] Figure 4 This is a block diagram illustrating an exemplary loading of data within and across cache lines.

[0012] Figure 5 This is a flowchart illustrating one implementation of a processor for ensuring the load order for access across cache lines.

[0013] Figure 6This is a block diagram of one implementation of a load / store unit and a decode / map unit including a reorder buffer (ROB).

[0014] Figure 7 This is a flowchart illustrating one implementation of a processor for performing sequential loading processing for microcode loading.

[0015] Figure 8 It includes Figure 1 A block diagram of one implementation of the processor system shown.

[0016] Figure 9 It is a block diagram of one implementation scheme of computer-accessible storage media.

[0017] Although the embodiments described herein may be subject to various modifications and alternatives, specific embodiments thereof are shown by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that the drawings and specific embodiments thereof are not intended to limit the embodiments to the particular forms disclosed, but rather, the invention is intended to cover all modifications, equivalents, and alternatives falling within the substance and scope of the appended claims. The headings used herein are for organizational purposes only and are not intended to limit the scope of the specification. As used throughout this patent application, the word “may” is used in a permissive sense (i.e., meaning possible) rather than a mandatory sense (i.e., meaning must). Similarly, the words “include,” “including,” and “includes” mean including but not limited to. As used herein, the terms “first,” “second,” etc., serve as labels for the nouns that follow them and do not imply any kind of ordering (e.g., spatial, temporal, logical, etc.) unless expressly indicated.

[0018] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or claimed to be “configured to” perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing, such as an electronic circuit). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured to” perform a task even if the structure is not currently being operated. “A clock circuit configured to generate an output clock signal” is intended to cover, for example, a circuit that performs this function during operation, even if the circuit in the discussion is not currently in use (e.g., the circuit is not connected to power). Therefore, an entity described or stated as “configured to” perform a task refers to a physical thing used to perform that task, such as a device, circuit, memory storing executable program instructions, etc. This phrase is not used herein to refer to intangible things. Typically, the circuit forming the structure corresponding to “configured to” may include hardware circuitry. Hardware circuitry may include any combination of the following: combinational logic circuits, clock storage devices (such as flip-flops, registers, latches, etc.), finite state machines, memories (such as static random access memory or embedded dynamic random access memory), custom-designed circuits, analog circuits, programmable logic arrays, etc. Similarly, for ease of description, various units / circuits / components may be described as performing one or more tasks. Such descriptions should be interpreted as including the phrase "configured to".

[0019] The term "configured as" is not intended to mean "configurable as". For example, an unprogrammed FPGA is not considered "configured as" to perform a particular function, although it may be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform that function.

[0020] In one implementation, the hardware circuit according to this disclosure can be implemented by encoding a description of the circuit in a hardware description language (HDL) such as Verilog or VHDL. The HDL description can be synthesized against a cell library designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that can be transferred to a factory to generate a mask and ultimately produce an integrated circuit. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit can include transistors and may also include other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete elements may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a field-programmable gate array (FPGA) and implemented in the FPGA.

[0021] As used herein, the terms “based on” or “depending on” are used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase “A is determined based on B.” This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase “based on” is synonymous with the phrase “at least partially based on.”

[0022] This specification includes references to various embodiments to indicate that this disclosure is not intended to refer to a particular specific embodiment, but rather to a range of embodiments falling within the spirit of this disclosure, including the appended claims. Specific features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0023] This specification may use the words “an” or “a kind” to refer to an element, or the word “the” to refer to an element. These words are not intended to mean that only one instance of the element exists. More than one may exist in various embodiments. Therefore, unless explicitly described as only one, “an,” “a kind,” and “the” should be interpreted as meaning “one or more.”

[0024] This specification may describe various components, units, circuits, etc., as coupled. In some embodiments, components, units, circuits, etc., may be coupled if they are electrically coupled (e.g., directly connected or indirectly connected through one or more other circuits) and / or communicatively coupled. Detailed Implementation

[0025] Turn now Figure 1 The diagram illustrates a block diagram of one embodiment of processor 12. In the illustrated embodiment, processor 12 includes fetch address generation circuitry 14, instruction cache (“ICache”) 18, decode / map unit 22 (including reorder buffer (ROB) 20), branch prediction unit 26, one or more reservation stations 24A-24N, one or more execution units 28A-28B, register file 29, data cache (“DCache”) 16, and load / store unit (LSU) 42. LSU 42 includes load queue (LQ) 30, store queue (SQ) 32, and execution circuitry 34 coupled to LQ 30 and SQ 32.

[0026] The address generation circuit 14 is coupled to ICache 18, which is coupled to the decoding / mapping unit 22, which is coupled to the reservation stations 24A-24N. For example... Figure 1 As shown, reservation stations 24A-24B are coupled to execution units 28A-28B, and reservation station 24N is coupled to LSU 42. Reservation stations 24A-24N are also coupled to register file 29, which is coupled to execution units 28A-28B and LSU 42. LSU 42 is also coupled to DCache 16, which is coupled to register file 29. Branch prediction unit 26 is coupled to fetch address generation circuit 14. One or more of execution units 28A-28B may be coupled to provide redirection to fetch address generation circuit 14 and decoding / mapping unit 22 (e.g., in one embodiment, in the event of branch misprediction or other microarchitectural anomalies). In the illustrated embodiment, LSU 42 may provide refresh instructions to fetch address generation circuit 14 and decoding / mapping unit 22. Alternatively, refresh instructions may be provided to decoding / mapping unit 22, which may refresh op after a refresh point and provide a re-fetch address to fetch address generation circuit 14.

[0027] As discussed in more detail below, LSU 42 can be configured to perform load / store operations, including enforcing a memory ordering model implemented by processor 12. In one embodiment, processor 12 may implement a TSO model, or may have one or more modes in which TSO is implemented and one or more other modes in which other memory ordering models are implemented (e.g., a local ordering model of an ISA implemented by processor 12). However, processor 12 may employ an atomicity size smaller than the operation size for some memory operations. For example, for a load operation targeting multiple registers, the atomicity size may be implemented as the register size. That is, each register targeted for a load may obtain each byte accessed by the load and written to that register from a single source (e.g., storage in storage queue 32, or a cache line in DCache 16). If a register has more than one source, the load may be retried and the load may wait until the previous storage has been exhausted from storage queue 32. In one embodiment, load queue 30 may include the function of holding a load until storage queue 32 has been exhausted before retrying the load, or until the storage hit by the load has been exhausted. In other implementations, loading can be retried periodically until a register is successfully sourced from a single source. Thus, LSU 42 can allow partial data for the operation size to be forwarded from the storage queue, provided that each register receives all bytes written to it from a single source (e.g., storage in storage queue 32, or cache lines in DCache 16).

[0028] In some cases, compilers have used multiple register loads to merge logically disparate loads into a single instruction. Therefore, each load depends on a different store operation (and typically, the store remains a separate instruction rather than being merged into multiple register store instructions). In one implementation, by defining the atomicity size as the register size, so that the atomic element is the register targeted by multiple register loads, correct programming operations can be observed while improving the performance of multiple register loads.

[0029] In one implementation, a vector load operation can be implemented with an atomic size smaller than the operation size. A vector load can access multiple vector elements of a vector (e.g., multiple vector elements may be present in a given vector register). The vector register can be wide, for example, 128 bytes, 256 bytes, 512 bytes, or larger. The number of vector elements in the vector depends on the size of the vector register and the size of the vector elements, which can be one byte, two bytes, four bytes, etc. In one implementation, the atomic size can be the size of one vector element. In another implementation, the atomic size can be multiple vector elements, but fewer than all the vector elements in the vector register. For example, a given atomic element in the vector register can be multiple vector elements (such as adjacent vector elements in the register). In yet another implementation, similar to the other registers described above, the atomic size of the vector register can be defined.

[0030] In one implementation, both multiple register loads and vector loads can be implemented with an atomic size smaller than the operation size. In other implementations, only multiple register loads can be implemented with an atomic size smaller than the operation size. In yet another implementation, only vector loads can be implemented with an atomic size smaller than the operation size.

[0031] In this context, the operation size can refer to the total number of bytes accessed by a memory operation (op). In contrast, the atomicity size can be the total number of bytes accessed atomically. That is, an atomic access either reflects the effect of a given memory across all bytes of that memory or does not. One requirement for satisfying the atomicity property is accessing bytes from a single source, as described above. In one implementation, the atomicity size can be an integer greater than one, thus specifying multiple bytes (since bytes can be accessed atomically by definition, as a byte is the smallest unit of memory). More specifically, the atomicity size of a load / store operation can be a value between one byte and the operation size. The atomicity size defines a minimum granularity that the LSU 42 can use to determine the single-source criterion required by TSO and other stringent memory consistency models. Allowing multiple atomic units within a larger operation size allows the LSU 42 to have a different single source for each atomic unit without violating TSO or other stringent memory consistency models. The operation size can be another integer greater than the atomicity size (and can be an integer multiple of the atomicity size, and more specifically, a power of two multiples of the atomicity size).

[0032] If a DCache miss is detected for a load, the data source can actually be another level of cache or main memory itself. DCache 16 may load the data while it is being forwarded to the target load register. In this case, atomicity can be measured in the same way as for a DCache hit. Atomicity can also be measured in the same way even if DCache 16 is not updated with data (e.g., for an access that is not cacheable).

[0033] The fetch address generation circuit 14 can be configured to generate a fetch address (fetch PC) to fetch instructions from ICache 18 for execution by processor 12. The fetch address generation circuit 14 can implement various prediction structures to predict the fetch path. For example, a next fetch predictor can be used to predict the fetch address based on previously executed instructions. In such implementations, branch prediction unit 26 can be used to verify the next fetch prediction. Alternatively, if a next fetch predictor is not used, branch prediction unit 26 can be used to predict the next fetch address.

[0034] Branch prediction unit 26 may include one or more branch predictors, such as a branch direction predictor, an indirect branch predictor, and a return address stack predictor. Various embodiments may include any subset of the above-described branch predictors and / or other predictors. The branch direction predictor may be configured to predict the adoption / non-adoption result of a conditional branch. Based on the adoption / non-adoption result, the next fetch address may be either a branch target address or a next sequential address. The target address may be the address specified by the branch instruction (or more simply, the branch), to which the fetch will be directed when the branch is adopted (or, for unconditional branches, the target address is the location to which the fetch will always be directed). The next sequential address may be an address whose numerical order follows the PC of the branch, and may be the next fetch address if the branch is not adopted (similar to non-branch instructions that fetch in sequential order). The return address stack may predict the fetch address for a return instruction based on the previously called instruction. Call and return instructions may be used, for example, to call a subroutine / function and return from it. The call instruction may push the return address onto the stack (e.g., to the next sequential instruction after the call), and the return instruction may pop the top of the stack to generate the return address. The stack can be in memory or simulated via a register written to by the called instruction and read by the returned instruction. An indirect branch predictor predicts the target address of an indirect branch instruction. In one implementation, the indirect branch predictor can be a tag geometry (TAGE) type branch predictor with multiple memories. The base memory can be indexed by a PC or a hash of the PC, and other memories can be indexed by PCs hashed with different branch history values. The base memory may not be tagged, but other memories may be tagged. If a tag hit is detected in one or more of the other memories, the branch target address is predicted to be the target address from the memory indexed with the largest history value and also the memory with the tag hit for the branch. If no tag hit is detected, the branch target address is predicted to be the target address from the base memory. Other implementations can implement other types of indirect branch predictors. For example, a single table indexed by the branch PC and branch history, or simply by the branch PC, can be used. A single tag table can be used.

[0035] The decoding / mapping unit 22 can be configured to decode instructions fetched from ICache 18 into instruction operations. In some implementations, a given instruction can be decoded into one or more instruction operations, depending on the complexity of the instruction. In some implementations, particularly complex instructions can be micro-coded. In such implementations, micro-coding routines for instructions can be encoded within instruction operations. In other implementations, each instruction in the instruction set architecture implemented by processor 12 can be decoded into a single instruction operation, so an instruction operation can be substantially synonymous with an instruction (although it can be formally modified by the decoder). The term "instruction operation" may be more briefly referred to herein as "op".

[0036] The decoding / mapping unit 22 can be configured to map operations (ops) to speculative resources (e.g., physical registers) to allow out-of-order and / or speculative execution, and can dispatch ops to reservation stations 24A-24N. Ops can be mapped from architecture registers used in the corresponding instructions to physical registers in register file 29. That is, register file 29 can implement a set of physical registers, the number of which can be greater than the architecture registers specified by the instruction set architecture implemented by processor 12. The decoding / mapping unit 22 manages the mapping from architecture registers to physical registers. In one embodiment, separate physical registers may exist for different operand types (e.g., integer, vector, floating-point, etc.). In other embodiments, physical registers may be shared across operand types. The decoding / mapping unit 22 can also be responsible for tracking speculative execution and exiting or flushing ops with incorrect speculative values. For example, ROB 20 can be used to track the program order of ops and manage exits / flushes.

[0037] When the source operands for an op are ready, the op can be scheduled for execution. In the illustrated implementation, distributed scheduling is used for each of execution units 28A-28B and LSU 42, for example, in reservation stations 24A-24N. Other implementations may implement a centralized scheduler if needed. Scheduled ops may read their source operands from register file 29 and / or may have operands forwarded from previous ops executed by execution units 28A-28B and / or LSU 42. The result of an op with a destination register may be written to register file 29 and / or forwarded to the relevant op.

[0038] LSU 42 can be configured to perform load / store memory operations. Generally, a memory operation (memory operation) can be an instruction operation specifying an access to memory (although memory access can be performed in a cache such as data cache 16). A load memory operation specifies a data transfer from a memory location to a register, while a store memory operation specifies a data transfer from a register to a memory location. A load memory operation can be referred to as a load memory operation, load operation, or load; and a store memory operation can be referred to as a store memory operation, store operation, or store. In one implementation, a store operation can be performed as a store address operation and a store data operation. A store address operation can be defined as generating the address of the store, probing the initial cache hit / miss determination, and updating the store queue 32 using the address and cache information. Therefore, a store address operation can use an address operand as the source operand. A store data operation can be defined as delivering store data to the store queue. Therefore, a store data operation can use a store data operand as the source operand instead of an address operand. In many cases, the stored address operand may be available before the stored data operand, so the address can be determined and become available earlier than the stored data. In some implementations, for example, if the stored data operand is provided before one or more operands in the stored address operands, the stored data op may be executed before the corresponding stored address op. Although in some implementations a storage operation can be executed as a stored address op and a stored data op, other implementations may not implement a stored address / stored data split.

[0039] The execution circuit 34 in LSU 42 can execute load / store operations initiated by reservation station 24N. The execution circuit 34 can access data cache 16 to determine the hit / miss of the load / store operation and forward the data for loading. The execution circuit 34 can check storage queue 32 for ordering problems of the load being executed and forward data from one or more storages that are updated compared to one or more storages in storage queue 32 and whose addresses match the storages in storage queue 32. Similarly, the execution circuit 34 can check load queue 30 to detect ordering problems of the storage being executed. When an ordering problem is detected, if the operation being executed is one that needs to complete later than an operation in one of queues 30-32, the operation can be correctly ordered using internal retries. If an operation in queues 30-32 needs to complete later than the operation being executed, a flush is often required (e.g., if a load has already forwarded data and is in load queue 30, and an older storage is executed and updates the same data or a portion of the data, then erroneous data has been forwarded).

[0040] Storage queue 32 can queue storage operations that have already been executed (e.g., probed the cache) and are waiting to be committed to the data cache (e.g., in various implementations, once a given storage operation exits, or is about to exit). LSU 42 / execution circuitry 34 can forward data from storage queue 32 for updated load operations. If storage has an address that matches the load address but no available data, LSU 42 / execution circuitry 34 can retry the load based on the matching in storage queue 32 and wait for the storage data to become available. Storage queue 32 can also be used to detect loading ordering problems.

[0041] Similarly, load queue 30 can queue load operations that have already been executed. Load queue 30 can include load operations that have been retried and will be executed again as soon as possible or after a subsequent event related to the cause of the detected retry occurs. LSU 42 can also use load queue 30 to detect storage ordering problems, such as flushable loads that have been completed (e.g., irreversibly forwarding data to the destination) and have ordering problems. Ordering problems detected using load queue 30 and storage queue 32 can include memory ordering model problems and / or problems related to the consistency of memory locations read by load operations and written by storage operations in the same thread or code sequence executed by processor 12.

[0042] In various implementations, execution units 28A-28B may include any type of execution unit. For example, execution units 28A-28B may include integer, floating-point, and / or vector execution units. Integer execution units may be configured to execute integer operations. Typically, an integer operation is an operation that performs a defined operation (e.g., arithmetic, logical, shift / rotation, etc.) on integer operands. Integers may be numerical values, where each value corresponds to a mathematical integer. Integer execution units may include branch processing hardware for processing branch operations, or a separate branch execution unit may exist.

[0043] A floating-point execution unit can be configured to perform floating-point operations. Generally, a floating-point operation can be an operation that has been defined to operate on floating-point operands. A floating-point operand is an operand represented as the mantissa (or significant number of bits) multiplied by the exponent of the base. The exponent, the sign of the operand, and the mantissa / significant number of bits can be explicitly represented in the operand, and the base (e.g., in one embodiment, base 2) can be implicit.

[0044] Vector execution units can be configured to execute vector operations. Vector processing is characterized by performing the same processing on large amounts of data, where each data item is a relatively small value (e.g., 8 bits or 16 bits, compared to the 32 to 64 bits of an integer). Therefore, vector operations typically consist of single-instruction multiple-data (SIMD) or vector operations on operands representing multiple data items.

[0045] Therefore, each execution unit 28A-28B may include hardware configured to perform an operation defined as an operation that limits a particular execution unit to processing. Execution units are generally independent of each other in that each execution unit can be configured to operate on an operation initiated for that execution unit and independent of other execution units. Alternatively, each execution unit may be an independent pipeline for executing an operation. Different execution units may have different execution delays (e.g., different pipeline lengths). Furthermore, at the pipeline stage where bypassing occurs, different execution units may have different delays, so the clock cycle for speculative scheduling of related operations may vary based on the operation and the type of execution unit 28 that will execute that operation.

[0046] It should be noted that any number and type of execution units 28A-28B may be included in various implementation schemes (including implementation schemes with one execution unit and implementation schemes with multiple execution units).

[0047] A cache line can be a unit of allocation / deallocation within the cache. That is, data within a cache line can be allocated / deallocated within the cache as a unit. The size of a cache line can vary (e.g., 32 bytes, 64 bytes, 128 bytes, or larger or smaller cache lines). Different caches can have different cache line sizes. ICache 18 and DCache 16 can each be caches with any desired capacity, cache line size, and configuration. In various implementations, additional levels of cache may exist between DCache 16 / ICache 18 and main memory.

[0048] At each point, an operation is considered either newer or older than other operations. If the first operation follows the second operation in sequence, then the first operation is considered newer than the second operation. Similarly, if the first operation precedes the second operation in sequence, then the first operation is considered older than the second operation.

[0049] Now go to Figure 2 The diagram illustrates the decoupling operation size and atomicity size for one implementation. Figure 2 At the top, a load pair instruction (Ldp) is shown (illustrated as 50). A load pair instruction has register targets Xa and Xb, and one or more source operands specify the memory address to be read by the load pair instruction (e.g., address A in this example). Therefore, the operation size of a load pair instruction ( Figure 2The Opsize (52) in the example is twice the register width. On the other hand, for this example, the atomicity size can be the register width, so there are two atomic elements 54A-54B in the data at address A. Xa and Xb do not need to be adjacent registers in the register file (e.g., load pair instructions can support specifying register addresses for Xa and Xb respectively). In one implementation, multiple other register load instructions can support more than two register targets, and therefore can have more than two atomic elements.

[0050] Figure 2 The diagram also shows the vector load instruction (LdVec, reference numeral 56). The vector load instruction has a target vector register Va, and the width of the vector register is the operation size ( Figure 2 Opsize 58 in the example. In this example, the vector element size can be atomic, so each vector element can be an atomic element (see reference numerals 60A-60n). Alternatively, multiple adjacent vector elements can be atomic elements. For example, in... Figure 2 At the bottom, two adjacent vector elements are atomic elements (see reference numerals 62A-62m). Other implementations may use other numbers of adjacent vector elements as atomic elements.

[0051] Figure 3 This is a flowchart illustrating one embodiment of the LSU 42 (and more specifically, execution circuit 34) for performing the loading operation. However, for ease of understanding, the block diagram is shown in a specific order, but other orders may be used. The blocks can be executed in parallel within combinational logic circuitry within the LSU 42 / execution circuit 34. The blocks, combinations of blocks, and / or the flowchart as a whole can be pipelined over multiple clock cycles. The LSU 42 / execution circuit 34 can be configured to implement... Figure 3 The operation shown is illustrated.

[0052] If the load has an operation size larger than the atomic size (Decision Box 70, "Yes" branch), LSU 42 may attempt to load and determine if each atomic element (among multiple atomic elements within the operation) has received its byte from a single source (Decision Box 72). Different atomic elements may receive their bytes from different sources, as long as each atomic element has a single source. If each atomic element receives its byte from a single source (Decision Box 72, "Yes" branch), LSU 42 may complete the load operation (Box 74). Completing the load operation may include forwarding the result to the load's destination register and reporting the status to ROB 20 for final exit. If at least one atomic element has multiple sources for its byte (Decision Box 72, "No" branch), LSU 42 may prevent completion (e.g., retry the load) (Box 76). The load may be retried at a later time (e.g., a re-initiation from load queue 30). In one implementation, LSU 42 may mark the retried load with the storage on which some (but not all) of its bytes depend to control when a re-initiation is performed. In another implementation, LSU 42 may periodically re-initiate the load until it completes successfully. Alternatively, if the load has an operation size equal to the atomic size (decision box 70, "No" branch), LSU 42 may determine whether all bytes of the operation size have a single source (decision box 78). If yes (decision box 78, "Yes" branch), LSU 42 may complete the load operation (box 72). If no (decision box 78, "No" branch), LSU 42 may prevent completion (box 76). In one implementation, TSO (or a more stringent ordering model) may be implemented in one or more modes of processor 12, and a more lenient ordering model may be implemented in other modes. In such implementations, decisions 70 and 72 may be conditional, based on the mode implementing the more stringent ordering model being active.

[0053] While multiple register loads and / or vector loads can have atomicity smaller than the operation size, memory ordering models still require atomic elements to behave as if they have been read sequentially. For example, in the case of multiple register loads, the first column register in the instruction (e.g., Xa) needs to behave as if it were read simultaneously with or before the second column register in the instruction (e.g., Xb). Therefore, if registers are read from, for example, different cache lines or different memory, and one or more lines in the underlying cache line are lost before the multiple register load is completed, ordering may not be guaranteed.

[0054] Figure 4 Two examples are shown. Figure 4At the top, both atomic elements of the loaded instruction pair are in the same cache line (including the cache line containing address A, reference numeral 80). Therefore, the atomic elements of the loaded instruction pair appear to complete simultaneously, and thus sequentially. On the other hand, at reference numeral 82, one of the atomic elements (register Xa) is read from the cache line containing address A and the other atomic element (register Xb) is read from the next consecutive cache line (labeled A+1). If the cache line containing Xa fails (e.g., due to storage by another processor or other coherent agent), it can be observed that the order of Xa and Xb is Xb before Xa, which does not conform to the TSO model. Therefore, in one embodiment, processor 12 may include circuitry for checking these conditions and ensuring correct operation.

[0055] Figure 5 This is a flowchart illustrating one embodiment of the LSU 42 (and more specifically, execution circuit 34) for ensuring the ordered operation of a load with multiple atomic elements. However, for ease of understanding, the block diagram is shown in a specific order, but other orders may be used. The blocks can be executed in parallel within combinational logic circuitry within the LSU 42 / execution circuit 34. The blocks, combinations of blocks, and / or the flowchart as a whole can be pipelined over multiple clock cycles. The LSU 42 / execution circuit 34 can be configured to implement... Figure 5 The operation shown is illustrated.

[0056] If the size and address of the load access operation cause it to cross cache line boundaries (so one or more atomic elements loaded may exist in one cache line while other atomic elements exist in different cache lines) (Decision Box 84, "Yes" branch), then LSU 42 can monitor cache lines and ensure that the order between cache lines is maintained, such that the first cache line is accessed before the second cache line (e.g., the first cache line is not invalidated while the second cache line is in the cache). If the order is not maintained (Decision Box 88, "No" branch), then LSU 42 can flush the load op and related ops, which can be re-fetched and re-executed (Box 90). If the order is maintained (Decision Box 88, "Yes" branch), then the op can remain complete and can exit (Box 92).

[0057] In some implementations, processor 12 can simplify more complex load instructions by decoding / microcoding load instructions into multiple load operations that execute portions of the load instructions. For example, wide vector load instructions (such as those described above) can be microcoded into multiple smaller loads, so that the data path in the processor does not need to be as wide as the vector register. Multiple load operations can still take advantage of decoupling of operation size and atomicity size, if this applies to the size of the smaller loads. However, multiple load operations may also need to behave as if they are executed sequentially to conform to the TSO model. One way to implement the ordering would be to execute the load operations corresponding to the complex load instructions sequentially. However, such a specific implementation would involve additional hardware and would incur a performance penalty for detecting that load operations are microcoded according to the same load instruction and ensuring that the load operations remain ordered, the performance penalty of which is unnecessary if out-of-order execution appears ordered to an observer. Another problem that may occur is livelock if an older load in the sequence is flushed due to an ordering problem, and the flushing is repeated (e.g., due to another processor being livelocked at the same address).

[0058] In one implementation, processor 12 (and more specifically, LSU 42) can be configured to allow out-of-order execution of load operations microcoded according to the same load instruction. If an ordering problem is encountered after executing a load operation, LSU 42 can refresh the load operation, and ROB 20 can detect that the load operation is part of a microcoded sequence. If the load is near the head of ROB 20, the number of possible reasons for a refresh (other than a livelock situation) is reduced. Using proximity to the head of ROB as a heuristic, ROB 20 can signal that reacquired load instructions (and their microcoded load operations) will be executed sequentially. Load operations can be marked as sequential by LSU 42, which can enforce sequential execution of load operations. Further refreshes can be avoided.

[0059] Figure 6 This is a block diagram illustrating one embodiment of the LSU 42 and the decoding / mapping unit 22 (which includes ROB 20). When a refresh load (reference numeral 100) is required, the LSU 42 can signal the decoding / mapping unit 22. For example, the LSU 42 can provide the ROB 20 with a reorder buffer tag (Flush_Load_ROB_Tag) associated with the load being refreshed. The ROB 20 can refresh the load and any subsequent operations, and can cause these operations to be re-fetched by the address generation circuit 14. Various speculative states are also restored to the refresh point.

[0060] ROB 20 can receive a reorder buffer flag, perform a flush, and cause speculative state restoration. Additionally, if the reorder buffer flag identifies an entry near the head of ROB 20 (where the head of ROB 20 represents the oldest instruction), ROB 20 can signal that load instructions should be executed sequentially. Figure 6 (See In_Order_Load, reference numeral 102). If an entry is within a threshold number of entries (e.g., N entries, where N is an integer greater than one) in the header of ROB 20, then the entry may be near the header. In various embodiments, the number of entries (“N”) may be programmable in ROB 20 or may be fixed in hardware. The number of entries may also be specified in other ways (e.g., a percentage of entries).

[0061] The In_Order_Load indicator can be provided to other circuits in the decoding / mapping unit 22. For example, when a load instruction is re-fetched from the ICache 18 by the address generation circuit 14, the decoder can receive a load instruction that has already been refreshed. The decoder can decode the load instruction into two or more micro-coded load operations and can use the In_Order_Load indicator to mark the load operations to force them to be executed sequentially. For example, the reservation station 24N can use this indicator to prevent loads from being initiated until they are the oldest in the reservation station 24N.

[0062] Figure 7 This is a flowchart illustrating one embodiment of the decoding / mapping unit 22 for loading operations marked for sequential execution. However, for ease of understanding, the block diagram is shown in a specific order, and other orders may be used. The blocks can be executed in parallel within combinational logic circuitry within the decoding / mapping unit 22. The blocks, combinations of blocks, and / or flowcharts as a whole can be pipelined over multiple clock cycles. The decoding / mapping unit 22 can be configured to implement... Figure 7 The operation shown is illustrated.

[0063] If LSU 42 initiates a refresh for the load op (decision box 104, "Yes" branch), and the load op is within the N entries in the header of ROB 20 (decision box 106, "Yes" branch), then the decoding / mapping unit 22 can be configured to mark the load op generated according to the re-fetch load instruction as executed sequentially (box 108). If LSU 42 initiates a refresh for the load op (decision box 104, "Yes" branch), and the load op is not within the N entries in the header of ROB 20 (decision box 106, "No" branch), then the decoding / mapping unit 22 can be configured not to mark the load op generated according to the re-fetch load instruction as executed sequentially (box 110). That is, the load op can be executed out of order. If LSU 42 does not initiate a refresh for the load op (decision box 104, "No" branch), the operation of the decoding / mapping unit 22 continues as normal. As previously mentioned, in various embodiments, N can be an integer greater than one and can be fixed or programmable.

[0064] system

[0065] Next turn Figure 8 The diagram illustrates a block diagram of one embodiment of system 150. In the illustrated embodiment, system 150 includes at least one example of a system-on-a-chip (SOC) 152 coupled to one or more peripheral devices 154 and external memory 158. A power supply 156 is provided to supply power voltage to the SOC 152 and to supply one or more power voltages to the memory 158 and / or peripheral devices 154. In some embodiments, more than one instance of SOC 152 may be included (and more than one memory 158 may also be included). SOC 152 may include, as shown below: Figure 1 One or more instances of the processor 12 shown.

[0066] Depending on the type of system 150, peripheral device 154 may include any desired circuitry. For example, in one embodiment, system 150 may be a mobile device (e.g., a personal digital assistant (PDA), smartphone, etc.), and peripheral device 154 may include devices for various types of wireless communications, such as Wi-Fi, Bluetooth, cellular, GPS, etc. Peripheral device 154 may also include additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 154 may include user interface devices, such as displays, including touch displays or multi-touch displays, keyboards or other input devices, microphones, speakers, etc. In other embodiments, system 150 may be any type of computing system (e.g., a desktop PC, laptop, workstation, network set-top box, etc.).

[0067] External memory 158 may include any type of memory. For example, external memory 158 may be SRAM, dynamic RAM (DRAM) (such as synchronous DRAM (SDRAM)), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, RAMBUSDRAM, low-power versions of DDR DRAM (such as LPDDR, mDDR, etc.), etc. External memory 158 may include one or more memory modules to which memory devices can be mounted, such as single in-line memory modules (SIMM), dual in-line memory modules (DIMM), etc. Alternatively, external memory 158 may include one or more memory devices mounted on SOC 152 in a chip-on-chip or package-on-package embodiment.

[0068] Computer-readable storage media

[0069] Turn now Figure 9 This diagram illustrates a block diagram of one embodiment of a computer-readable storage medium 200. Generally, a computer-readable storage medium can include any storage medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, a computer-readable storage medium can include storage media such as magnetic or optical media, such as discs (fixed or removable), tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-ray discs. Storage media can also include volatile or non-volatile memory media such as RAM (e.g., Synchronous Dynamic RAM (SDRAM), Rambus DRAM (RDRAM), Static RAM (SRAM), etc.), ROM, or flash memory. The storage medium may be physically included within a computer to which instructions / data are provided. Alternatively, the storage medium may be connected to a computer. For example, the storage medium may be connected to a computer via a network or wireless link such as a network-attached storage device. The storage medium may be connected via a peripheral interface such as a Universal Serial Bus (USB). Typically, computer-accessible storage medium 200 can store data in a non-transitory manner, where non-transitory in this context can mean not transmitting instructions / data via signals. For example, a non-transitory storage device can be volatile (and may lose stored instructions / data in response to a power outage) or non-volatile.

[0070] Figure 9The computer-accessible storage medium 200 can store a database 204 representing the SOC 152. Typically, the database 204 can be a database that can be read by a program and used directly or indirectly to manufacture hardware including the SOC 152. For example, the database can be a behavioral-level description or register-transfer-level (RTL) description of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. This description can be read by a synthesis tool, which can synthesize the description to generate a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including the SOC 152. The netlist can then be placed and routed to generate a dataset describing the geometry to be applied to a mask. The mask can then be used in various semiconductor manufacturing steps to produce semiconductor circuits corresponding to the SOC 152. Alternatively, the database 204 on the computer-accessible storage medium 200 can be a netlist (with or without a synthesis library) or a dataset, as needed.

[0071] Although computer-accessible storage medium 200 stores a representation of SOC 152, other implementations may carry a representation of any part of SOC 152 as needed, including processor 12, any subset of processor 12, or a portion thereof. Database 204 may represent any of the aforementioned parts.

[0072] Based on the above description, in one embodiment, the processor may include a data cache and a load / store unit coupled to the data cache and configured to perform memory operations. The load / store unit includes a storage queue configured to queue one or more memory operations that have been executed and are awaiting submission to the data cache. The load / store unit is configured to access the storage queue and the data cache during the execution of a load-memory operation, wherein the load-memory operation has an operation size specifying the amount of data read by the load-memory operation. The load / store unit implements an atomicity size conforming to a memory ordering model adopted by the processor. The atomicity size is smaller than the operation size for the load-memory operation. In one embodiment, the operation size may be an integer multiple of the atomicity size. In one embodiment, the data read by the load-memory operation comprises multiple atomic elements having an atomicity size, and the execution of the load-memory operation conforms to a memory ordering model when each of the multiple atomic elements is read from a single source among multiple sources. In one embodiment, a cache line in the data cache is one of multiple sources. In one embodiment, the load / store unit is configured to ensure that multiple atomic elements are ordered in response to a load-memory operation receiving bytes from multiple cache lines. In one embodiment, the first load-memory operation in the memory queue is one of multiple sources. In one embodiment, the load-memory operation targets multiple registers. The atomicity size can be the size of the registers, and a given atomic element can include bytes written to a given register among the multiple registers. In one embodiment, the load-memory operation is a vector load-memory operation, and the atomicity size is based on the vector element size of the vector elements in the vector read by the load-memory operation. In one embodiment, the atomicity size is the vector element size, and the multiple atomic elements are vector elements. In one embodiment, the atomicity size is a multiple of the vector element size, and a given atomic element among the multiple atomic elements is multiple adjacent vector elements. In one embodiment, the processor further includes a reordering buffer. The load-memory operation can be one of multiple load-memory operations corresponding to a load instruction, and the load / store unit is configured to signal a refresh of the load-memory operation upon detection of an order violation. The reordering buffer can be configured to force the sequential execution of multiple load memory operations in response to the detection that a load memory operation is within a threshold number of entries in the head of the reordering buffer when a refresh is signaled.

[0073] In one embodiment, the load / store unit includes a storage queue and execution circuitry coupled to the storage queue, the storage queue being configured to queue one or more memory operations that write data to one or more memory locations. The execution circuitry is configured to perform a load-memory operation and to detect when the load-memory operation reads at least one byte written by a first memory operation represented in the storage queue. The load-memory operation targets multiple registers as targets for data read during the execution of the load-memory operation, and the execution circuitry is configured to allow forwarding of data from the first memory operation in the storage queue for the load-memory operation if the data from the storage queue is a portion of the data for the load-memory operation and the remaining data for the load-memory operation originates from a different source than the first memory operation, provided that each of the multiple registers obtains a complete dataset from a single source. In one embodiment, the different source is a data cache coupled to the load / store unit. In one embodiment, the execution circuitry is configured to perform a vector load-memory operation to load a vector having multiple vector elements. The execution circuitry is configured to allow forwarding of vector elements from the storage queue, provided that each vector element obtains a complete dataset from a single source. The execution circuitry is configured to perform a vector load-memory operation to load a vector having multiple vector elements, wherein the multiple vector elements include multiple atomic elements, and wherein each atomic element includes multiple adjacent vector elements within the multiple vector elements. The execution circuitry is configured to allow forwarding of a given atomic element from the multiple atomic elements from the storage queue, provided that each atomic element has received a complete dataset from a single source. In one embodiment, if at least one of the multiple registers has not received a complete dataset from a single source, the execution circuitry is configured to suspend the load-memory operation until the storage queue is emptied.

[0074] In one embodiment, a method includes: performing a load-memory operation of an operation size; verifying that each of a plurality of atomic elements within data of the operation size originates entirely from a memory operation in a memory queue or originates entirely from a different source; and allowing forwarding from the memory queue in response to the verification. In one embodiment, the method further includes performing a second load-memory operation of an operation size; detecting that at least one of the plurality of atomic elements within data of the operation size does not originate entirely from a memory operation in a memory queue or does not originate entirely from a different source, but at least one of the plurality of atomic elements originates from the memory queue; and preventing completion of the second load-memory operation. In one embodiment, continuation is prevented until the memory queue is emptied. In one embodiment, the plurality of atomic elements correspond to a plurality of registers targeted by the load-memory operation.

[0075] Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. This disclosure is intended to make the following claims interpretable as encompassing all such variations and modifications.

Claims

1. A processor, comprising: A decoder circuit configured to decode a load instruction into a load memory operation; and Load / store unit, the load / store unit being configured as follows: The load memory operation is performed, and the load memory operation has an operation size larger than the atomic size implemented to conform to the memory sorting model; To conform to the memory sorting model, it is verified that each of the plurality of atomic elements associated with the load memory operation is entirely derived from the memory operation in the memory queue or from a different source, wherein the plurality of atomic elements have the atomicity size; as well as In response to verifying that each of the plurality of atomic elements originates entirely from a storage memory operation in the storage queue or from a different source, forwarding from the storage queue is permitted.

2. The processor of claim 1, wherein the load / store unit is configured as follows: The memory loading operation is prevented from completing in response to the detection of the following: At least one of the plurality of atomic elements is not entirely derived from a single source; and At least one of the plurality of atomic elements originates from the storage queue.

3. The processor of claim 2, wherein the load / store unit is configured to prevent the completion of the load memory operation until one or more memory operations targeted by the load memory operation have been dequeued from the memory queue.

4. The processor of claim 1, wherein the load memory operation targets a plurality of registers, wherein the atomicity size is the size of the registers, and wherein a given atomic element includes a byte written to a given register among the plurality of registers.

5. The processor of claim 1, wherein the load memory operation is a vector load memory operation, and the atomicity size is the size of the vector elements in the vector read by the load memory operation.

6. The processor of claim 1, wherein at least one of the plurality of atomic elements is entirely derived from storage memory operations in the storage queue, and at least one of the plurality of atomic elements is entirely derived from the different sources.

7. The processor according to claim 1 further includes a data cache corresponding to the different sources.

8. The processor of claim 1, wherein the load / store unit is configured to ensure that the plurality of atomic elements are ordered in response to the load memory operation receiving bytes from the plurality of cache lines.

9. The processor according to claim 1, further comprising: A reordering buffer, wherein the load memory operation is one of a plurality of load memory operations corresponding to the load instruction, wherein the load / store unit is configured to signal a refresh of the load memory operation upon detection of a sorting violation, and wherein the reordering buffer is configured to force sequential execution of the plurality of load memory operations in response to detection that the load memory operation is within a threshold number of entries in the head of the reordering buffer when the refresh is signaled.

10. A load / store unit, comprising: A storage queue, configured to queue one or more storage memory operations that write data to one or more memory locations; and Execution circuitry, coupled to the storage queue and configured to: Perform a load memory operation, the load memory operation having an operation size larger than the atomicity size achieved to conform to the memory sorting model; To conform to the memory sorting model, it is verified that each of the plurality of atomic elements associated with the load memory operation is entirely derived from the memory operation in the memory queue or from a different source, wherein the plurality of atomic elements have the atomicity size; as well as In response to verifying that each of the plurality of atomic elements originates entirely from a storage memory operation in the storage queue or from a different source, data from a specific storage memory operation in the storage queue is permitted to be forwarded for the load memory operation.

11. The load / store unit of claim 10, wherein the execution circuitry is configured to suspend the load memory operation until the storage queue is emptied in response to detecting that at least one of the plurality of atomic elements is not entirely derived from a storage memory operation in the storage queue or is derived from a different source.

12. The load / store unit of claim 10, wherein the load memory operation targets a plurality of registers, and the atomicity size is the size of the registers.

13. The load / store unit of claim 10, wherein the load memory operation is a vector load memory operation, and the atomicity size is based on the vector element size of the vector elements in the vector read by the load memory operation.

14. The load / store unit of claim 13, wherein the atomicity size is the vector element size, and a given atomic element among the plurality of atomic elements corresponds to a vector element in the vector.

15. The load / store unit of claim 13, wherein the atomicity size is a multiple of the vector element size, and a given atomic element among the plurality of atomic elements corresponds to a plurality of adjacent vector elements in the vector.

16. The load / store unit of claim 10, wherein the operation size is an integer multiple of the atomicity size.

17. A method comprising: The processor performs a load memory operation, wherein the load memory operation has an operation size greater than the atomicity size implemented to conform to the memory sorting model, and wherein the load memory operation is one of a plurality of load memory operations corresponding to a load instruction. The processor detects sorting violations based on a plurality of atomic elements associated with the load memory operation; In response to the detection, the processor signals the refresh of the load memory operation; as well as When the refresh is signaled, the processor forces the sequential execution of the plurality of load memory operations in response to detecting that the load memory operation is within a threshold number of entries in the head of the processor's reordering buffer.

18. The method of claim 17, wherein the operation size and the address accessed by the load memory operation cause a crossing of cache line boundaries between a plurality of cache lines, and wherein the order violation is detected in response to the plurality of atomic elements receiving out-of-order bytes from the plurality of cache lines.

19. The method of claim 17, wherein the coercion comprises: The processor marks the plurality of load memory operations with sequential load instructions to force the plurality of load memory operations to be executed sequentially.

20. The method of claim 17, wherein the number of thresholds is programmable in the reordering buffer.

21. A processor, comprising: A data cache, wherein the data cache comprises multiple cache lines; and An execution circuit configured to perform a load-memory operation on a plurality of atomic elements of access data, wherein a given atomic element among the plurality of atomic elements has an atomicity size smaller than the operation size of the load-memory operation, and wherein the execution circuit is configured to: The operation size and the address accessed by the load memory operation are detected to cause a crossover of the cache line boundary, such that a first portion of the data is located in a first cache line of the plurality of cache lines and a second portion of the data is located in a second cache line of the plurality of cache lines; Monitoring ensures that the access order of the first cache line is maintained before that of the second cache line; as well as In response to the detection that the access order is not maintained, the load memory operation is refreshed.

22. The processor of claim 21, wherein the load memory operation targets a plurality of registers, and wherein the atomicity size is the size of the registers, and the given atomic element corresponds to a corresponding register among the plurality of registers.

23. The processor of claim 21, wherein the load memory operation targets a plurality of vector elements, and wherein the atomicity size is based on the size of the vector elements.

24. The processor of claim 23, wherein the atomicity size is the size of the vector element, and the given atomic element corresponds to a corresponding vector element among the plurality of vector elements.

25. The processor of claim 23, wherein the atomicity size is a multiple of the size of the vector element, and the given atomic element corresponds to a plurality of adjacent vector elements among the plurality of vector elements.

26. The processor of claim 21, wherein the execution circuitry is configured to: Perform a second load-memory operation to access a second plurality of atomic elements of data, wherein a given atomic element among the second plurality of atomic elements has an atomicity size smaller than the operation size of the second load-memory operation; and In response to the detection that data for at least one of the second plurality of atomic elements was read from more than one source, the completion of the second load memory operation is prevented.

27. The processor of claim 26, further comprising: A storage queue, wherein the execution circuitry is configured to prevent the completion of the second load memory operation until one or more memory operations targeted by the second load memory operation have been removed from the storage queue.

28. The processor of claim 26, wherein at least one of the second plurality of atomic elements is entirely derived from storage memory operations in the storage queue, and at least one of the second plurality of atomic elements is entirely derived from the data cache.

29. The processor of claim 21, further comprising: A reordering buffer is configured to, after the refresh, force sequential execution of a plurality of load memory operations, including the load memory operation, in response to detecting that the load memory operation is within a threshold number of entries from the head of the reordering buffer.

30. The processor of claim 29, wherein the number of thresholds is programmable in the reordering buffer.

31. A method comprising: A load-memory operation is performed to access data from multiple atomic elements, wherein a given atomic element among the multiple atomic elements has an atomicity size smaller than the operation size of the load-memory operation; A crossing of a cache line boundary for the load memory operation is detected based on the fact that a first atomic element among the plurality of atomic elements is accessed from a first cache line and a second atomic element among the plurality of atomic elements is accessed from a second cache line. Monitoring ensures that the first cache line is accessed before the second cache line; and The load memory operation is flushed in response to the detection that the first cache line has not been accessed before the second cache line.

32. The method of claim 31, wherein the load memory operation is a multi-register load memory operation, and the atomicity size is the size of one of the multiple registers targeted by the load memory operation.

33. The method of claim 31, wherein the load memory operation is a vector load memory operation, and the atomicity size is the size of the vector elements in the vector to which the load memory operation is targeted.

34. The method of claim 31, wherein the load memory operation is a vector load memory operation, and the atomicity size is a multiple of the size of the vector elements in the vector to which the load memory operation is targeted.

35. The method of claim 31, wherein the operation size is an integer multiple of the atomicity size.

36. A load / store unit, comprising: An execution circuit configured to perform a load-memory operation on a plurality of atomic elements of access data, wherein a given atomic element among the plurality of atomic elements has an atomicity size smaller than the operation size of the load-memory operation, and wherein the execution circuit is configured to: The detection results in a first portion of the data being located in a first cache line out of a plurality of cache lines and a second portion of the data being located in a second cache line out of a plurality of cache lines, crossing a cache line boundary for the load memory operation; Ensure that the first cache line and the second cache line are accessed in a specific order; as well as The load memory operation is flushed in response to the detection that the first cache line and the second cache line were not accessed in the specific order.

37. The load / store unit of claim 36, wherein the given atomic element corresponds to a corresponding register among a plurality of registers targeted by the load memory operation.

38. The load / store unit of claim 36, wherein the given atomic element corresponds to a corresponding vector element among a plurality of vector elements within a vector targeted by the load memory operation.

39. The load / store unit according to claim 36, further comprising: A storage queue configured to store one or more storage memory operations, wherein the execution circuitry is configured to prevent the completion of the load memory operation based on the detection that at least one of the plurality of atomic elements does not originate entirely from a single source and that at least one of the plurality of atomic elements originates from the storage queue.

40. The load / store unit of claim 36, wherein the load memory operation is one of a plurality of load memory operations corresponding to a load instruction, and wherein the load / store unit is configured to mark the plurality of load memory operations to force the sequential execution of the plurality of load memory operations.

41. A method comprising: A load-memory operation is performed to access data from multiple atomic elements, wherein a given atomic element among the multiple atomic elements has an atomicity size smaller than the operation size of the load-memory operation; A specific atomic element among the plurality of atomic elements was detected to originate partly from the storage queue and partly from the data cache; as well as In response to the detection, the loading memory operation is stopped until one or more memory operations in the storage queue have been dequeued, so that the particular atomic element can be derived entirely from a single source.

42. A processor, comprising: Storage queue; and An execution circuit configured to perform a vector loading operation targeting a vector register with a vector width, wherein the execution circuit is configured to: Achieve an atomic size smaller than the vector width; as well as In response to verifying that a given vector element of the vector loading operation originates entirely from a single source, such that no individual vector element originates from multiple sources, forwarding from the storage queue is permitted, wherein the given vector element has the atomicity size.

Images