Method for storing synaptic connection relationship and weight of brain-like processor and storage medium

Abstract

The application discloses a synapse connection relationship and weight storage method and storage medium for a brain-like processor, and the method comprises the following steps: S1, storage space division and address mapping; the logical storage is divided into a direct index area and a multi-connection area to eliminate source ID redundancy and realize 0 or 1 direct addressing; S2, data format and minimal Hint coding; a 2-bit Hint code is used to uniformly identify a storage state, distinguish storage types and replace a pointer array; S3, adaptive access control; single / multi-connection access logic is adaptively executed according to the Hint code to realize single-connection zero jump, multi-connection continuous traversal and minimization of memory access times. The storage medium is realized based on the above method. The application has the advantages of high compression ratio, low memory access overhead, high scalability and the like.

Description

Technical Field

[0001] This invention mainly relates to the field of neuromorphic computing technology, specifically a method and storage medium for storing synaptic connections and weights in neuromorphic processors. It is primarily a method for compressed storage, fast access, and hardware implementation of synaptic connections and weights in neuromorphic processors, oriented towards spiking neural networks. Background Technology

[0002] Neuromorphic processors achieve low-power intelligent computing by simulating the connection characteristics of biological neurons and synapses, combining event-driven computing and in-memory computing. However, the neuronal and synaptic connections still require significant storage resources. Neuromorphic chips generally employ in-memory / near-memory computing methods, storing synaptic weights in cross-arrays (such as ReRAM) or SRAM. However, as the scale of neural network models continues to expand (e.g., networks with millions of neurons), issues such as SRAM capacity and memory access efficiency become prominent. Therefore, achieving efficient synaptic connection compression and access is a core challenge. This not only involves storage efficiency but also affects the overall power consumption, latency, and scalability of the chip.

[0003] Many existing implementations primarily revolve around sparse matrix storage formats and indexing methods for compressing and accessing synaptic connections in neuromorphic chips. These schemes aim to reduce memory footprint by leveraging the sparsity of SNNs, but still suffer from redundancy and efficiency issues. Several typical schemes are described in detail below: (1) COO format: This is a basic sparse matrix storage method that stores only the coordinates (row index, column index) and values ​​of non-zero elements, forming a list of triples. For example, for a sparse matrix, COO records the source neuron ID, target neuron ID, and weight value for each synaptic connection. This format is simple to implement and supports dynamic insertion and deletion of connections. It is often used for initial compression in the simulation environment of neuromorphic chips. In neuromorphic chips such as SpiNNaker or similar processors, COO is often used as an intermediate format, but it needs to be converted into a more compact form to optimize storage.

[0004] CSR Format: CSR is an improvement on COO, reducing redundancy by compressing row indices. It uses three arrays: one to store non-zero values, one to store column indices, and one to store row pointers (representing the starting offset of each row's non-zero element). In the context of synaptic connections, this is equivalent to treating source neurons as rows and target neurons as columns, enabling efficient row traversal access. For example, in neural network simulations, CSR allows for the rapid location of the output synapses of specific neurons, making it suitable for event-driven SNN computations. CSR is widely used in memory compression in neuromorphic chips, such as in the STACS simulator or the SpiNNaker2 prototype, to handle large-scale sparse networks, significantly reducing memory usage.

[0005] The aforementioned existing technologies still have the following shortcomings: 1. Regarding data compression, there are issues such as storage redundancy and high indirect overhead. The COO format suffers from coordinate redundancy; each non-zero synaptic connection requires explicit storage of the complete IDs (coordinates) of the source and target neurons. This results in a considerable amount of memory waste in large-scale networks due to the excessive storage of this coordinate information. While the CSR format compresses row coordinates, it introduces an array of row pointers (row_ptr). The size of this pointer array is proportional to the number of neurons, and it does not itself carry valid synaptic data, representing indirect overhead. For cases where each neuron has only one postsynaptic connection, the storage share of pointers can reach 1 / 3.

[0006] 2. In terms of memory access efficiency, the COO format is inefficient and has unpredictable latency. The COO format requires traversing an unordered list, which is characterized by non-contiguous memory access and strong computational dependency, resulting in high and unpredictable memory access latency. Although the CSR format can quickly locate the start point of a row, it still requires linear search or indirect jumps when accessing specific synapses within a row. Moreover, as the number of synaptic connections decreases, the number of pointer jumps does not decrease. When each neuron has only one postsynaptic connection, the memory access advantage over COO is no longer significant.

[0007] Both approaches suffer from high redundancy, disordered memory access, complex traversal, and high hardware overhead, failing to meet the high-efficiency deployment requirements of SNNs with millions of neurons. Summary of the Invention

[0008] The technical problem to be solved by this invention is: in view of the technical problems existing in the prior art, this invention provides a storage method and storage medium for storing synaptic connection relationships and weights for neuromorphic processors with high compression ratio, low memory access overhead and high scalability.

[0009] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A method for storing synaptic connections and weights in a neuromorphic processor, comprising: Step S1: Storage space partitioning and address mapping; used to divide logical storage into direct index area and multiple connection area to eliminate source ID redundancy and achieve 0 or 1 direct addressing; Step S2: Data format and simplified Hint encoding; use 2-bit Hint codes to uniformly identify storage status, distinguish storage types, and replace pointer arrays; Step S3: Adaptive access control; Adaptively execute single / multiple connection access logic according to the hint code, realize zero jump for single connection, continuous traversal for multiple connection, and minimize the number of memory accesses.

[0010] As a further improvement of the present invention: In step S1, the entire storage space is divided into two continuous and non-overlapping logical regions; the first region is called the direct index region, whose address range is from 0 to N-1, where N represents the total number of neurons in the neural network; in this region, each address corresponds one-to-one with a unique source neuron ID; the size of each storage unit is determined according to the actual data field requirements; the second region is the multi-connection region, whose starting address starts from N and the ending address is M-1.

[0011] As a further improvement of the present invention: the mapping mode in step S1 includes: The unified mapping mode stores two logical regions contiguously in the same physical memory, forming a unified address space; The separate mapping mode maps the direct index area to high-speed, small-capacity SRAM, while mapping the multi-link area to large-capacity but slower DRAM, with address translation achieved through the memory management unit; The hierarchical mapping mode establishes a three-level storage hierarchy: the direct index area is stored in on-chip SRAM as the first-level storage, the hot data of the multi-link area is placed in the second-level cache, and the complete link data is stored in off-chip DRAM. The system automatically schedules the migration of data between the various levels of storage through a hardware cache management mechanism.

[0012] As a further improvement of the present invention: In step S2, each storage unit in the direct index area contains two parts: a main data segment and a 2-bit Hint code; when the Hint code is 11, it indicates that the neuron has only a single output connection, and the storage unit directly contains connection information, including weight value, target neuron ID and other attributes; when the Hint code is 00, it indicates that the neuron has multiple output connections, and the storage unit stores the starting address pointer of the multi-connection area.

[0013] As a further improvement of the present invention: the data format in the multi-connection area remains uniform, and each storage unit also includes a weight value field, a target neuron ID field, other attribute fields, and a Hint code; the Hint code has two values: 01 indicates that the unit is the middle node in the linked list, and 10 indicates that the unit is the end node of the linked list.

[0014] As a further improvement of the present invention: the weight value field stores the weight parameters of the synaptic connection, and its bit width is determined according to the accuracy requirements; The target neuron ID field records the index of the connected target neuron, and its bit width is the result of rounding up log2N. The other attribute fields are optional and may include information such as delay parameters and connection type identifiers; The hint code occupies 2 bits and is located in the lowest two bits of the storage unit.

[0015] As a further improvement of the present invention: In step S3, when the system needs to read the output connection information of a certain neuron, the system first uses the source neuron ID as input, locates the corresponding storage unit through direct indexing, and calculates the address as equal to the neuron ID; after reading the data at the address, the lowest 2 bits are extracted to obtain the Hint code; If the hint code is 11, it indicates that this is a single-connection direct storage case; the system shifts the data right by 2 bits to remove the hint bit, directly obtains the connection information and returns it, and the whole process only requires one memory access; If the hint code is 00, it indicates the case of multiple linked indirect storage; the system extracts the pointer address from the data and then enters the linked list traversal process; During the traversal, the system starts from the address pointed to by the pointer and reads each memory unit in sequence. For each unit, the system extracts its hint code and connection information, and adds the connection information to the result list. If the hint code is 10, it means that the end of the linked list has been reached, and the traversal ends. If the hint code is 01, it means that there are subsequent nodes, and the address is incremented by 1 to continue reading the next unit. If other hint values ​​are found, an error is reported.

[0016] As a further improvement of the present invention: it includes a hardware architecture construction step, wherein the execution module of the hardware architecture includes: The address generation unit is used to calculate the next access address based on the input neuron ID, hint code, and current address; The Hint decoder is used to receive 2-bit Hint codes as input and output corresponding control signals to guide subsequent data access behavior. The prefetch control unit utilizes the predictive nature of hint codes; when a hint code of 0 or 1 is detected, the system immediately initiates a prefetch request for the next address, preloading the data into the cache or register, thus hiding subsequent memory access delays. The storage management unit, in terms of address mapping, translates logical addresses into physical storage addresses, supporting separate mapping and hierarchical mapping modes; in terms of boundary checking, it ensures that the access address of the direct index area is less than N, and the access address of the multi-connection area is greater than or equal to N and less than M; when multiple neurons access in parallel, it is used to arbitrate access requests to shared storage resources.

[0017] As a further improvement of the present invention: an initialization step is included, that is, during the initialization phase, i.e., when building the network, the system needs to initialize the storage space according to the complete neural network connection relationship; this initialization step includes: The system counts the number of output connections for each neuron; Start allocating multi-connection region space, starting from address N. For each neuron with an output connection number greater than 1, allocate a continuous address range, the size of which is equal to its connection number. At the same time, record the mapping relationship between the starting address and the neuron, and update the next free address. Fill the direct index area; for each neuron, if its output connection number is equal to 1, store the connection information at its corresponding address after shifting it left by 2 bits and performing an OR operation with 11; if the output connection number is greater than 1, store the pointer address recorded in the mapping table after shifting it left by 2 bits and performing an OR operation with 00; if there is no output connection, store a special flag such as all 0s or all 1s. Fill the multi-connection region; for each neuron with more than 1 output connection, the system obtains its starting address from the mapping table and then fills each connection in turn; except for the last connection, the hint codes of other connections are set to 01; the hint code of the last connection is set to 10 to indicate the end of the linked list.

[0018] The present invention also provides a storage medium that can be read by a computer or processor, wherein the storage medium stores a computer program for executing any of the above methods.

[0019] Compared with the prior art, the advantages of the present invention are as follows: 1. The present invention provides a method and storage medium for storing synaptic connection relationships and weights in neuromorphic processors. This method is a hierarchical compression storage method for neuronal connections with high compression ratio, low memory access overhead, and scalability. It achieves near-zero redundancy storage under extremely sparse connections through an adaptive two-level indexing mechanism and lightweight Hint encoding technology, and optimizes access locality, thereby significantly improving the storage efficiency and system energy efficiency of large-scale SNNs in neuromorphic chips.

[0020] 2. The storage method and storage medium for storing synaptic connection relationships and weights in neuromorphic processors of the present invention have higher storage efficiency and lower access latency. In terms of access performance, the present invention shows a significant advantage over the COO and CSR compression methods. COO requires multiple discontinuous memory accesses. When accessing the connection of a neuron, the CSR method first needs to locate the starting position of the neuron in the column index array through the row pointer array, and then sequentially read the column indices and corresponding weights of all connections. For a neuron with k connections, the CSR method requires an average of 2+k memory accesses (weights and target neuron IDs are stored together). In the present invention, for a single-connection neuron, only one fast access to the direct index region is needed to obtain complete connection information. For a multi-connection neuron, an average of 1+k memory accesses are required. The first access requires one memory operation to read the pointer and obtain the first connection; the subsequent k connections can fully utilize the prefetching mechanism by leveraging data locality, reducing the average number of memory accesses.

[0021] 3. The storage method and storage medium for storing synaptic connections and weights in neuromorphic processors according to the present invention have stronger scalability. Through a hierarchical storage structure and a flexible hint bit mechanism, the present invention can support seamless expansion from hundreds to millions of neurons. The direct index region can be dynamically adjusted according to the number of neurons, while the chained structure of the multi-connection region naturally supports data storage of any scale of connections. More importantly, the present invention can adapt to different storage hierarchies, including on-chip SRAM, off-chip DRAM, and high-bandwidth memory (HBM), optimizing the access characteristics of different storage media by adjusting the prefetch strategy and caching mechanism.

[0022] 4. The storage method and storage medium for storing synaptic connections and weights in neuromorphic processors of the present invention, in terms of network topology compatibility, are not only applicable to traditional fully connected neural networks, but also efficiently support local connection patterns in convolutional neural networks and various sparse network structures. Although the CSR method also supports sparse storage, it does not fully utilize this structural characteristic for optimization when handling regular sparse patterns (such as convolutional layers and residual connections). The present invention, through flexible encoding of hint bits, performs customized optimization for different connection patterns, achieving higher storage efficiency and access performance. Attached Figure Description

[0023] Figure 1 This is a flowchart illustrating the present invention in a specific embodiment.

[0024] Figure 2 This is a schematic diagram of a two-level storage area in a specific embodiment of the present invention.

[0025] Figure 3 This is a schematic diagram of the data reading process in a specific embodiment of the present invention. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] This paper addresses the challenges of high memory overhead and high access latency in storing synaptic connections and weights in neuromorphic processors. Specifically, when running massively multi-spiking neural networks (SNNs), the storage size of synaptic weights is O(N²) compared to O(N) for neuron states. This gap widens as the number of neurons increases, with the storage space occupied by synaptic data differing by several orders of magnitude from that of neuron states (e.g., in networks with millions of neurons). Due to the high sparsity of the connections between neurons, synaptic connections and weights can be further compressed. However, current storage compression methods, such as COO (CoordinateList) or CSR (CompressedSparseRow) formats, suffer from problems such as redundant coordinate information, redundant pointers, and complex chained traversal, requiring improvement in storage, latency, and power consumption.

[0028] like Figures 1-3 As shown, this invention discloses a method for storing synaptic connection relationships and weights for neuromorphic processors, comprising: Step S1: Storage space partitioning and address mapping; used to divide logical storage into direct index area and multiple connection area to eliminate source ID redundancy, realize 0(1) direct addressing, and improve spatial locality; Step S2: Data format and minimal Hint encoding; use 2-bit Hint codes to uniformly identify storage status, distinguish storage types with minimal overhead, replace pointer arrays, and simplify hardware control.

[0029] Step S3: Adaptive access control; Adaptively execute single / multiple connection access logic according to the hint code, realize zero jump for single connection, continuous traversal for multiple connection, and minimize the number of memory accesses.

[0030] In a specific application example, in step S1, the multi-level connection storage scheme based on direct indexing of neuron IDs divides the entire storage space into two continuous and non-overlapping logical regions. The first region is called the direct index region, and its address range is from 0 to N-1, where N represents the total number of neurons in the neural network. In this region, each address corresponds one-to-one with a unique source neuron ID. The calculation method for the address is extremely simple and direct, that is, the address of the direct index region is equal to the source neuron ID itself. The size of each storage unit is determined according to the actual data field requirements, with typical values ​​between 32 and 64 bits.

[0031] like Figure 2As shown, following the direct index region (whose space is determined by the total number of neurons) is the multi-connection region (expandable to DRAM), starting at address N and ending at address M-1. The value of M is dynamically determined based on the actual total number of connections and available storage capacity. This region employs a sequential allocation strategy to ensure no address gaps, thereby improving storage efficiency. For ease of hardware implementation, the storage cell size of the multi-connection region is consistent with that of the direct index region.

[0032] Furthermore, as a preferred embodiment, this solution provides three flexible implementation modes for physical storage mapping, including: The unified mapping mode stores two logical regions contiguously in the same physical memory, forming a unified address space, which is suitable for small to medium-sized neural networks. The separate mapping mode maps the direct index area to high-speed, small-capacity SRAM, while mapping the multi-connection area to large-capacity but slower DRAM. Address translation is achieved through the memory management unit to meet the needs of large-scale networks. The most complex hierarchical mapping model establishes a three-level storage hierarchy: the direct index area is stored in on-chip SRAM as the first-level storage, the hot data of the multi-link area is placed in the second-level cache, and the complete link data is stored in off-chip DRAM. The system automatically schedules the migration of data between the various levels of storage through a hardware cache management mechanism.

[0033] In a specific application example, the specific meaning of the Hint code identifier bit in step S2 is as follows:

[0034] Each storage unit in the direct index region contains two parts: a main data segment and a 2-bit hint code. When the hint code is 11, it indicates that the neuron has only a single output connection. In this case, the storage unit directly contains connection information, including weight values, the target neuron ID, and other attributes. When the hint code is 00, it indicates that the neuron has multiple output connections. In this case, the storage unit stores a pointer to the starting address of the multi-connection region.

[0035] Furthermore, the data format remains consistent across the multi-connection region, with each storage unit also containing weight values, target neuron IDs, other attributes, and a hint code. The difference lies in the hint code's two possible values: 01 indicates the unit is an intermediate node in the linked list, and 10 indicates the unit is the end node of the linked list.

[0036] Detailed explanations of each field are as follows: The weight value field stores the weight parameters of the synaptic connection, and its bit width is determined according to the accuracy requirements. The target neuron ID field records the index of the target neuron being connected, and its bit width is the result of rounding up to log2N. Other attribute fields are optional and can include information such as delay parameters and connection type identifiers; Hint codes occupy a fixed 2 bits and are located in the lowest two bits of the storage unit.

[0037] In a specific application example, in step S3, when the system needs to read the output connection information of a neuron, the system first uses the source neuron ID as input and locates the corresponding storage unit through direct indexing, calculated as address equal to neuron ID. After reading the data at that address, the lowest two bits are extracted to obtain the hint code.

[0038] If the hint code is 11, it indicates a single-connection direct storage case. The system right-shifts the data by 2 bits to remove the hint bit, directly obtains the connection information, and returns it. The entire process requires only one memory access.

[0039] If the hint code is 00, it indicates a case of multiple joins indirect storage. The system extracts the pointer address from the data and then proceeds with the linked list traversal process.

[0040] During traversal, the system starts from the address pointed to by the pointer and reads each memory unit sequentially. For each unit, the system extracts its hint code and connection information, and adds the connection information to the result list. If the hint code is 10, it means that the end of the linked list has been reached, and the traversal ends; if the hint code is 01, it means that there are subsequent nodes, and the address is incremented by 1 to continue reading the next unit; if any other hint value is encountered, an error is reported.

[0041] This design requires only one memory access for a single-connection scenario. For a multi-connection scenario with K connections, it requires 1+K memory accesses, where the first access reads the pointer, and the subsequent K accesses read the connection data sequentially. Compared to traditional fixed-format storage, which requires accessing K fixed locations that may be scattered throughout the storage space, this solution, although adding one extra access overhead in multi-connection scenarios, achieves significant prefetching benefits through contiguous storage.

[0042] In a specific application example, the present invention further includes a hardware architecture construction step, namely, constructing an execution module for the hardware architecture; the execution module for the hardware architecture includes: The address generation unit calculates the next access address based on the input neuron ID, hint code, and current address. The initial address is directly equal to the neuron ID, implementing direct indexing. If the hint code is 00, the next address is taken from the pointer value in the data field; if the hint code is 01, the next address is the current address plus 1, implementing sequential increment; if the hint code is 10 or 11, the access ends.

[0043] The Hint decoder receives 2-bit Hint codes as input and outputs corresponding control signals to guide subsequent data access behavior. This decoder essentially translates the Hint codes into operation instructions that the hardware system can directly execute. The specific decoding rules are as follows: When the Hint code is 00, it indicates that pointer-type data is being read. In this case, the jump enable signal is set to 1, instructing the address generation unit to jump to the target address pointed to by the pointer, rather than simply incrementing the current address; simultaneously, the continue flag is set to 1, indicating that the data access process is not yet complete and subsequent content needs to be read. When the Hint code is 11, it indicates that directly stored single-connection data is being read. In this case, the jump enable signal is set to 0, indicating that no address jump is needed; the continue flag is also set to 0, indicating that data access is complete and the reading process can be terminated. When the Hint code is 01, it indicates that the connection data of the middle node of the linked list is being read. In this case, the jump enable signal is set to 0, instructing the address generation unit to calculate the next address using a sequential increment method; the continue flag is set to 1, indicating that the linked list is not yet complete and the next adjacent memory unit needs to be read. When the hint code is 10, it indicates that the current data being read is the connection data of the last node in the linked list. At this time, the jump enable signal is set to 0, and the continue flag is also set to 0, indicating that this is the last data unit. After reading is completed, the access process terminates. The hardware implementation of this decoder only requires simple combinational logic gates, without sequential logic or state machines. Therefore, the critical path latency is extremely small, and it can complete decoding and output control signals within one clock cycle, without becoming a performance bottleneck for the system.

[0044] The prefetch control unit utilizes the predictive nature of hint codes; when a hint code of 0 or 1 is detected, the system immediately initiates a prefetch request for the next address (current address plus 1), preloading the data into the cache or register, thereby hiding subsequent memory access latency and further improving performance.

[0045] The storage management unit performs several important functions. In address mapping, it translates logical addresses into physical storage addresses, supporting both split mapping and hierarchical mapping modes. Regarding boundary checks, it ensures that the access address of a directly indexed region is less than N, and the access address of a multi-joined region is greater than or equal to N and less than M. When multiple neurons access resources in parallel, it also arbitrates access requests to shared storage resources.

[0046] In a specific application example, the present invention further includes an initialization step, namely, during the initialization phase, i.e., network construction, the system needs to initialize the storage space based on the complete neural network connection relationships; this initialization step includes: First, the system counts the number of output connections for each neuron; Then, the multi-connection region space is allocated. Starting from address N, for each neuron with an output connection number greater than 1, a continuous address range is allocated, the size of which is equal to its connection number. At the same time, the mapping relationship between the starting address and the neuron is recorded, and the next free address is updated.

[0047] Next, the direct index area is filled. For each neuron, if its output connection count is equal to 1, the connection information is stored at its corresponding address after shifting left by 2 bits and performing an OR operation with 11; if the output connection count is greater than 1, the pointer address recorded in the mapping table is stored after shifting left by 2 bits and performing an OR operation with 00; if there are no output connections, a special flag such as all 0s or all 1s is stored.

[0048] Finally, the multi-connection regions are filled; for each neuron with more than one output connection, the system retrieves its starting address from the mapping table and then fills each connection sequentially. Except for the last connection, the hint codes for all other connections are set to 0 or 1; the hint code for the last connection is set to 10 to indicate the end of the linked list.

[0049] Furthermore, for neuromorphic systems that support online learning, this invention also provides an optional dynamic update mechanism. Connection weight updates can directly modify the weight field of the corresponding storage unit.

[0050] This invention compares and analyzes it with COO and CSR compression methods. Assuming a neural network contains N=1000 neurons, where the percentage of neurons with only one connection is α, and the average connectivity of neurons with more than one connection is k, then the average connectivity is... For the COO compression method, the amount of data that needs to be stored is 3N. For CSR compression, the amount of data that needs to be stored is 2N. +N+1. In contrast, the HHS compression method proposed in this invention requires storing 2Nα+N(1-α)+2Nk(1-α). It can be seen that this invention combines the advantages of both COO and CSR, and is the optimal method among the three in various situations.

[0051] The present invention also provides a storage medium that can be read by a computer or processor, wherein the storage medium stores a computer program for executing any of the above methods.

[0052] Those skilled in the art will understand that the above embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0053] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A method for storing synaptic connection relationships and weights for neuromorphic processors, characterized in that, include: Step S1: Storage space allocation and address mapping; It is used to divide logical storage into direct index area and multiple connection area to eliminate source ID redundancy and realize 0 or 1 direct addressing; Step S2: Data format and minimalist Hint encoding; Use 2-bit Hint codes to uniformly identify storage status and distinguish storage types, replacing pointer arrays; Step S3: Adaptive access control; Adaptively execute single / multiple connection access logic according to the hint code, realize zero jump for single connection, continuous traversal for multiple connection, and minimize the number of memory accesses.

2. The method for storing synaptic connections and weights for neuromorphic processors according to claim 1, characterized in that, In step S1, the entire storage space is divided into two continuous and non-overlapping logical regions. The first region is called the direct index region, with an address range from 0 to N-1, where N represents the total number of neurons in the neural network. In this region, each address corresponds to a unique source neuron ID. The size of each storage unit is determined according to the actual data field requirements. The second region is the multi-connection region, with its starting address starting from N and ending at address M-1.

3. The method for storing synaptic connections and weights for a neuromorphic processor according to claim 2, characterized in that, The mapping patterns in step S1 include: The unified mapping mode stores two logical regions contiguously in the same physical memory, forming a unified address space; The separate mapping mode maps the direct index area to high-speed, small-capacity SRAM, while mapping the multi-link area to large-capacity but slower DRAM, with address translation achieved through the memory management unit; The hierarchical mapping mode establishes a three-level storage hierarchy: the direct index area is stored in on-chip SRAM as the first-level storage, the hot data of the multi-link area is placed in the second-level cache, and the complete link data is stored in off-chip DRAM. The system automatically schedules the migration of data between the various levels of storage through a hardware cache management mechanism.

4. The method for storing synaptic connections and weights for a neuromorphic processor according to claim 2 or 3, characterized in that, In step S2, each storage unit in the direct index area contains two parts: a main data segment and a 2-bit Hint code. When the Hint code is 11, it indicates that the neuron has only a single output connection. In this case, the storage unit directly contains connection information, including weight values, target neuron ID, and other attributes. When the Hint code is 00, it indicates that the neuron has multiple output connections. In this case, the storage unit stores the starting address pointer of the multi-connection area.

5. The method for storing synaptic connections and weights for a neuromorphic processor according to claim 4, characterized in that, The data format in the multi-connection area remains consistent. Each storage unit also contains a weight value field, a target neuron ID field, other attribute fields, and a hint code. The hint code has two values: 01 indicates that the unit is the middle node in the linked list, and 10 indicates that the unit is the end node in the linked list.

6. The method for storing synaptic connections and weights for a neuromorphic processor according to claim 5, characterized in that, The weight value field stores the weight parameters of the synaptic connection, and its bit width is determined according to the accuracy requirements. The target neuron ID field records the index of the connected target neuron, and its bit width is the result of rounding up log2N. The other attribute fields are optional and may include one or more of the following: delay parameters and connection type identification information; The hint code occupies 2 bits and is located in the lowest two bits of the storage unit.

7. The method for storing synaptic connections and weights for a neuromorphic processor according to claim 1, 2, or 3, characterized in that, In step S3, when the system needs to read the output connection information of a neuron, the system first uses the source neuron ID as input, locates the corresponding storage unit through direct indexing, and calculates the address as equal to the neuron ID; after reading the data at that address, the lowest 2 bits are extracted to obtain the Hint code; If the hint code is 11, it indicates that this is a single-connection direct storage case; the system shifts the data right by 2 bits to remove the hint bit, directly obtains the connection information and returns it, and the whole process only requires one memory access; If the hint code is 00, it indicates the case of multiple linked indirect storage; the system extracts the pointer address from the data and then enters the linked list traversal process; During the traversal, the system starts from the address pointed to by the pointer and reads each memory unit in sequence. For each unit, the system extracts its hint code and connection information, and adds the connection information to the result list. If the hint code is 10, it means that the end of the linked list has been reached, and the traversal ends. If the hint code is 01, it means that there are subsequent nodes, and the address is incremented by 1 to continue reading the next unit. If other hint values ​​are found, an error is reported.

8. The method for storing synaptic connections and weights for a neuromorphic processor according to claim 1, 2, or 3, characterized in that, It includes hardware architecture setup steps, and the execution module of the hardware architecture includes: The address generation unit is used to calculate the next access address based on the input neuron ID, hint code, and current address; The Hint decoder is used to receive 2-bit Hint codes as input and output corresponding control signals to guide subsequent data access behavior. The prefetch control unit utilizes the predictive nature of hint codes; when a hint code of 0 or 1 is detected, the system immediately initiates a prefetch request for the next address, preloading the data into the cache or register, thus hiding subsequent memory access delays. The storage management unit, in terms of address mapping, translates logical addresses into physical storage addresses, supporting separate mapping and hierarchical mapping modes; in terms of boundary checking, it ensures that the access address of the direct index area is less than N, and the access address of the multi-connection area is greater than or equal to N and less than M; when multiple neurons access in parallel, it is used to arbitrate access requests to shared storage resources.

9. The method for storing synaptic connections and weights for a neuromorphic processor according to claim 8, characterized in that, This includes an initialization step, which occurs during the network construction phase when the system needs to initialize the storage space based on the complete neural network connectivity. This initialization step includes: The system counts the number of output connections for each neuron; Start allocating multi-connection region space, starting from address N. For each neuron with an output connection number greater than 1, allocate a continuous address range, the size of which is equal to its connection number. At the same time, record the mapping relationship between the starting address and the neuron, and update the next free address. Fill the direct index area; for each neuron, if its output connection number is equal to 1, store the connection information at its corresponding address after shifting it left by 2 bits and performing an OR operation with 11; if the output connection number is greater than 1, store the pointer address recorded in the mapping table after shifting it left by 2 bits and performing an OR operation with 00; if there is no output connection, store a special flag such as all 0s or all 1s. Fill the multi-connection region; for each neuron with more than 1 output connection, the system obtains its starting address from the mapping table and then fills each connection in turn; except for the last connection, the hint codes of other connections are set to 01; the hint code of the last connection is set to 10 to indicate the end of the linked list.

10. A storage medium capable of being read by a computer or processor, characterized in that, The storage medium stores a computer program for executing the storage method according to any one of claims 1 to 9.

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