ATS endpoint optimizations for storage workloads

Abstract

Rather than simply providing address translation caches (ATCs) in a global approach that ignores the needs of the clients or providing static ATCs that ignore performance changes, the ATC allocation can be dynamically adjusted. The dynamic allocation optimizes overall system performance, constraining the performance of each individual client when necessary. The dynamic approach involves periodically or strategically determining whether the ATC allocation currently in use results in desired performance. The dynamic reallocation of the ATC maximizes the efficiency and benefit of the ATC by achieving the maximum performance results of the applications and / or workloads.

Description

Background Technology Technical Field

[0001] The implementation scheme disclosed herein generally involves improved address translation.

[0002] Description of related technologies

[0003] One use case for multitenant devices is where a solid-state drive (SSD) is shared across multiple tenants (i.e., virtual machines (VMs)) without any hypervisor layer between the SSD and the VM. Several optimizations exist surrounding memory usage that will be implemented when the host operating system (OS) (e.g., Windows Server) implements page movement capabilities. These capabilities require Address Translation Service (ATS) and Page Request Interface (PRI) functionality in any peripheral component Fast Interconnect (PCIe) device directly accessed by guest VMs. Moving memory pages means the device will receive PCIe addresses that need to be translated.

[0004] When using ATS+PRI, the translated address can be stored in the Address Translation Cache (ATC). ATC is very expensive because it requires a large amount of memory (approximately several megabytes (MB)) for cache buffering and high-performance lookup operations. ATC significantly increases the device's area, cost, and power consumption.

[0005] One approach to effectively utilize ATC is global ATC, where all clients worldwide are served regardless of their client identifier (ID). Another approach is the static ATC attribute method, where the same amount of memory is allocated to each client in the cache. Both approaches face challenges in achieving optimal performance results.

[0006] There is a need for improved address translation in this field. Summary of the Invention

[0007] Instead of simply providing an Address Translation Caching (ATC) cache globally that ignores client needs or a static ATC that ignores performance changes, ATC allocation can be dynamically adjusted. Dynamic allocation optimizes overall system performance while constraining the performance of each individual client where necessary. The dynamic approach involves periodically or strategically determining whether the currently used ATC allocation results in the desired performance. Dynamic reallocation of the ATC maximizes its efficiency and benefits by achieving the best performance outcome for the application and / or workload.

[0008] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: select a configuration for operating the data storage device for address translation cache (ATC) attributes; use the configuration to operate the data storage device; use the configuration to measure the performance of the data storage device; change the configuration from the configuration to a different configuration for the ATC attributes based on the measurement; and repeat the operation, the measurement, and the change.

[0009] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller includes a host interface module (HIM), the host interface module including: a calibration logic module configured to adjust cache configurations, measure the performance of the data storage device, and intelligently select an optimal cache configuration; a performance monitor module configured to monitor the performance of the data storage device; and an address translation cache (ATC) configuration module configured to maintain one or more cache configurations to be used by the calibration logic module for the adjustment.

[0010] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: measure the performance of the data storage device; change address translation cache (ATC) attributes based on the measurement; operate the data storage device using the changed ATC attributes; save the ATC attributes; repeat the measurement, the change, the operation, and the saving once or multiple times; select an optimal ATC attribute; and operate the data storage device using the selected optimal ATC attribute. Attached Figure Description

[0011] To gain a more detailed understanding of the features of this disclosure, the above-briefly summarized disclosure can be described in more detail by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of this disclosure and should therefore not be considered as limiting the scope of this disclosure, as other equivalent embodiments are permissible.

[0012] Figure 1 This is a schematic block diagram illustrating a storage system in which a data storage device can be used as a storage device for a host device, according to certain implementation schemes.

[0013] Figure 2 This is a schematic diagram illustrating a multi-tenant system that supports ATS functionality according to certain implementation schemes.

[0014] Figure 3 This is a schematic diagram of ATC attribute calibration according to an implementation plan.

[0015] Figure 4 This is a flowchart illustrating ATC attribute calibration according to one implementation scheme.

[0016] Figure 5 It is a schematic diagram of a system block diagram based on an implementation scheme.

[0017] Figure 6 This is a flowchart illustrating dynamic ATC allocation according to an implementation scheme.

[0018] For ease of understanding, the same reference numerals have been used where possible to designate common elements in the figures. It is contemplated that elements disclosed in one embodiment may be advantageously used in other embodiments without being specifically enumerated. Detailed Implementation

[0019] In the following text, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, any combination of the following features and elements (whether or not different embodiments are involved) is contemplated to realize and practice this disclosure. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions and / or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit this disclosure. Therefore, the following aspects, features, embodiments, and advantages are merely illustrative and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to “this disclosure” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims.

[0020] Instead of simply providing an Address Translation Caching (ATC) cache globally that ignores client needs or a static ATC that ignores performance changes, ATC allocation can be dynamically adjusted. Dynamic allocation optimizes overall system performance while constraining the performance of each individual client where necessary. The dynamic approach involves periodically or strategically determining whether the currently used ATC allocation results in the desired performance. Dynamic reallocation of the ATC maximizes its efficiency and benefits by achieving the best performance outcome for the application and / or workload.

[0021] Figure 1This is a schematic block diagram illustrating a storage system 100 having a data storage device 106 according to some embodiments, which can be used as a storage device for a host device 104. For example, the host device 104 may utilize non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes host dynamic random access memory (DRAM) 138. In some examples, the storage system 100 may include multiple storage devices, such as the data storage device 106, which can operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 configured as a redundant array of inexpensive / disk-only (RAID) that collectively serve as a high-capacity storage device for the host device 104.

[0022] Host device 104 can store data to or retrieve data from one or more storage devices (such as data storage device 106). Figure 1 As shown, host device 104 can communicate with data storage device 106 via interface 114. Host device 104 can include any of a wide range of devices, including computer servers, network attached storage (NAS) units, desktop computers, laptops, tablets, set-top boxes, handsets (such as so-called "smart" phones, so-called "smart" boards), televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices capable of sending or receiving data from data storage devices.

[0023] Host DRAM 138 may optionally include a main memory buffer (HMB) 150. HMB 150 is part of host DRAM 138 allocated to data storage device 106 for dedicated use by the controller 108 of data storage device 106. For example, controller 108 may store mapped data, buffered commands, logical-to-physical (L2P) tables, metadata, etc., in HMB 150. In other words, HMB 150 may be used by controller 108 to store data that would typically be stored in volatile memory 112, buffer 116, or the controller 108's internal memory (such as static random access memory (SRAM)). In an example where data storage device 106 does not include DRAM (i.e., optional DRAM 118), controller 108 may utilize HMB 150 as DRAM for data storage device 106.

[0024] Data storage device 106 includes a controller 108, an NVM 110, a power supply 111, volatile memory 112, an interface 114, a write buffer 116, and optional DRAM 118. In some examples, data storage device 106 may include additional components, not shown for clarity. Figure 1 As shown in the diagram. For example, data storage device 106 may include a printed circuit board (PCB) to which components of data storage device 106 are mechanically attached, and the PCB includes conductive traces that electrically interconnect the components of data storage device 106, etc. In some examples, the physical dimensions and connector configuration of data storage device 106 may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5” data storage devices (e.g., HDDs or SSDs), 2.5” data storage devices, 1.8” data storage devices, peripheral component interconnect (PCI), PCI expansion (PCI-X), PCI fast (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe mini-cards, mini PCI, etc.). In some examples, data storage device 106 may be directly coupled (e.g., directly soldered or inserted into a connector) to the motherboard of host device 104.

[0025] Interface 114 may include one or both of a data bus for exchanging data with host device 104 and a control bus for exchanging commands with host device 104. Interface 114 may operate according to any suitable protocol. For example, interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI, PCIe, Non-Volatile Memory Fast Channel (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. Interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to controller 108, thereby providing an electrical connection between host device 104 and controller 108, allowing data exchange between host device 104 and controller 108. In some examples, the electrical connection of interface 114 may also allow data storage device 106 to receive power from host device 104. For example, as Figure 1 As shown, power supply 111 can receive power from host device 104 via interface 114.

[0026] The NVM 110 may include multiple memory devices or memory cells. The NVM 110 may be configured to store and / or retrieve data. For example, a memory cell of the NVM 110 may receive data from controller 108 and a message instructing the memory cell to store data. Similarly, a memory cell may receive a message from controller 108 instructing the memory cell to retrieve data. In some examples, each memory cell in the memory cell may be referred to as a die. In some examples, the NVM 110 may include multiple dies (i.e., multiple memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0027] In some examples, each memory cell may include any type of non-volatile memory device, such as flash memory device, phase-change memory (PCM) device, resistive random access memory (ReRAM) device, magnetoresistive random access memory (MRAM) device, ferroelectric random access memory (F-RAM), holographic memory device, and any other type of non-volatile memory device.

[0028] NVM 110 may include multiple flash memory devices or memory cells. The NVM flash memory devices may include NAND- or NOR-based flash memory devices and may store data based on the charge in the floating gate of the transistors contained in each flash memory cell. In the NVM flash memory device, the flash memory device may be divided into multiple dies, each of which includes multiple physical or logical blocks, which may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define one page among the multiple pages. A corresponding cell in each of the multiple pages may be electrically connected to a corresponding bit line. Furthermore, the NVM flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), or four-level cell (QLC). Controller 108 may write data to and read data from the NVM flash memory device at the page level and erase data from the NVM flash memory device at the block level.

[0029] Power supply 111 can provide power to one or more components of data storage device 106. When operating in standard mode, power supply 111 can use power provided by an external device (such as host device 104) to supply power to one or more components. For example, power supply 111 can use power received from host device 104 via interface 114 to supply power to one or more components. In some examples, power supply 111 may include one or more power storage components configured to supply power to one or more components when operating in a shutdown mode (such as when power reception from external devices is stopped). In this way, power supply 111 can be used as an onboard backup power source. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the amount of electrical energy that can be stored by one or more power storage components may vary with the cost and / or size (e.g., area / volume) of one or more power storage components. In other words, as the amount of electrical energy stored by one or more power storage components increases, the cost and / or size of one or more power storage components also increases.

[0030] Controller 108 may use volatile memory 112 to store information. Volatile memory 112 may include one or more volatile memory devices. In some examples, controller 108 may use volatile memory 112 as a cache. For example, controller 108 may store cached information in volatile memory 112 until the cached information is written to NVM 110. Figure 1 As shown, volatile memory 112 can consume power received from power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)). Similarly, optional DRAM 118 can be used to store mapped data, buffered commands, logical-to-physical (L2P) tables, metadata, cached data, etc. In some examples, data storage device 106 does not include optional DRAM 118, making data storage device 106 DRAM-free. In other examples, data storage device 106 includes optional DRAM 118.

[0031] Controller 108 may manage one or more operations of data storage device 106. For example, controller 108 may manage reading data from and / or writing data to NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 may initiate a data storage command to store data in NVM 110 and monitor the progress of the data storage command. Controller 108 may determine at least one operating characteristic of storage system 100 and store at least one operating characteristic in NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 may temporarily store the data associated with the write command in internal memory or write buffer 116 before sending the data associated with the write command to NVM 110. Controller 108 may include circuitry or a processor configured to execute programs for operating data storage device 106.

[0032] Controller 108 may include optional second volatile memory 120. Optional second volatile memory 120 may be similar to volatile memory 112. For example, optional second volatile memory 120 may be SRAM. Controller 108 may allocate a portion of the optional second volatile memory to host device 104 as a controller memory buffer (CMB) 122. CMB 122 may be directly accessed by host device 104. For example, instead of maintaining one or more submission queues in host device 104, host device 104 may utilize CMB 122 to store one or more submission queues that are typically maintained in host device 104. In other words, host device 104 may generate commands and store the generated commands (with or without associated data) in CMB 122, wherein controller 108 accesses CMB 122 to retrieve the stored generated commands and / or associated data.

[0033] ATC is a feature in PCIe where a data storage device receives untranslated addresses from a host device, and these addresses need to be translated by a Translation Agent (TA) before being used. The TA maintains a table of translated addresses and their corresponding untranslated addresses. The host device, for example, sends a command to an endpoint (i.e., the data storage device), and this command contains the untranslated addresses. Before using the addresses, the endpoint first needs to obtain the translated addresses. The endpoint interacts with the TA to obtain the translated addresses. Upon receiving the translated addresses from the TA, the endpoint is able to use the translated addresses and store them in the ATC.

[0034] To improve performance and reduce link overhead, the data storage device negotiates with the TA to obtain a translated address. Before initiating negotiation with the TA, the endpoint first checks if the translated address is in the ATC. If the translated address is in the ATC, the endpoint will use the translated address stored in the ATC. Otherwise, the endpoint will begin interacting with the TA.

[0035] In multi-host or multi-tenant devices, such as when there are multiple functions, multiple physical functions, multiple virtual functions, or multiple hosts in the system, the system uses only a single ATC for all hosts or functions, so that all hosts or functions have access to the same ATC. This disclosure relates to how to optimize a system for performance quality from a QoS perspective. In other words, this disclosure relates to how to improve performance while managing ATCs.

[0036] As mentioned above, with global ATC, all functions will be able to use ATC without any special policies. For example, data will be evicted from ATC based on Least Recently Used (LRU) or some other criterion. However, there is no space reserved for any specific function in global ATC. Another approach mentioned above is static ATC attributes, where ATC is allocated to functions / hosts at the beginning, such as when a function requires a higher QoS compared to other functions. For a function requiring higher QoS, perhaps half of the ATC can be allocated to that function and the remainder to the remaining functions, allowing one function to provide better performance compared to others. In the case of static ATC attributes, the ATC distribution remains unchanged. This disclosure focuses on the dynamic allocation of ATC to improve performance.

[0037] Figure 2 This is a schematic diagram illustrating a multitenant system 200 supporting ATS functionality according to certain implementation schemes. TA serves memory translation requests. ATC is referred to as the Translation Backer Buffer (TLB) in TA. When an ATS-enabled SSD device accesses system memory, the SSD caches the translated address in its internal ATC. ATC is different from the TLB translation cache used by the host. ATS-enabled SSD devices implement and maintain a designated ATC to minimize performance dependence on TA and alleviate TA resource pressure.

[0038] Examples of PCIe addresses to be converted include: cached ranges of Submit Queues (SQ) and Complete Queues (CQ); SQ entry decoding includes standard decoding of data pointers for reading or writing that immediately submit conversion requests, decoding of data pointers and following linked lists, and conversion caps for each large command matching the PRI conversion at a rate equal to the maximum Gen5 bandwidth (BW) value, as well as DIX conversion requests for metadata pointers and associated linked lists.

[0039] ATC is used as a global resource shared among multiple clients, including PCIe functions and applications. The performance and QoS of a memory device depend on the selected attributes of the shared resource. There are significant advantages to employing algorithms that can detect the optimal ATC attributes that produce the best performance results.

[0040] As discussed in this paper, the device is designed to sophisticatedly calibrate ATC properties to optimize overall system performance while constraining the performance of each individual client as needed. The dynamic calibration process can be performed at regular intervals or otherwise triggered to ensure that the current ATC properties are seamlessly aligned with the current set of workload, configuration, system conditions, and operational constraints.

[0041] This algorithm not only considers the immediate environment but also analyzes historical data to gain a comprehensive understanding of the system's performance trends over time. By doing so, the algorithm effectively adapts to changing conditions, thereby ensuring continuous optimization of ATC properties.

[0042] At the heart of this device is the algorithm's ability to determine and recommend the optimal ATC size and eviction policy for each PCIe function or application. This approach ensures that the unique characteristics and requirements of each client are addressed, thereby contributing to the maximization of overall system performance. A key advantage is maximizing the benefits and efficiency of ATC by selecting the best cache attributes, thus achieving the highest performance outcome for the current application or workload.

[0043] As discussed in this article, ATC can be used dynamically to maximize performance and QoS by finding the correct attributes for each host or function from an ATC perspective. Dynamic calibration involves processing the ATC configuration, whether the ATC starts with a global configuration, static ATC attributes, or other attributes, to obtain the optimal configuration. For example, one might consider the size of the ATC used for each host or function and the eviction policy used for each host or function. For instance, one host might have one eviction policy, while another host might have a different eviction policy. Optimization involves attempting to process these configurations to find the optimal configuration for a particular system, where optimal means achieving the best performance and best QoS results.

[0044] Figure 3 This is a schematic diagram illustrating ATC attribute calibration according to one implementation scheme. Figure 3The process involves several repetitive phases. First, the system is configured based on the eviction policy for each host, especially ATC, and the size allocated to each host is determined. Then, the configuration is used for operation, the results are measured, and after a period of time, the configuration is tuned. Overall, configuration, operation, measurement, and tuning constitute the calibration process. The calibration process will be repeated until a point sufficiently good for the particular system is reached. Additionally, calibration will be repeated periodically to recalibrate the system.

[0045] To perform calibration, there are several parameters to consider, such as the maximum allowed bandwidth for each client in the system, the namespace for each client, priority, performance QoS requirements for each host, utilization, capacity, frequency, and historical data collected for a specific host.

[0046] As noted above, the system can be calibrated periodically to find the optimal ATC attributes. Initially, the ATC attributes are configured with a set of default parameters. Then, the system is activated and transmissions are performed on the link. During this time, performance is measured, results are analyzed, and the ATC attributes are adjusted. This process is repeated until the optimal configuration is found.

[0047] If the default ATC configuration is global ATC, all clients are initially granted unrestricted access to ATC by ignoring the client ID. This initial configuration is evaluated as a baseline. Subsequently, the configuration is systematically tuned and measured multiple times to explore potential improvements. The configuration that produces the best results is then selected.

[0048] When defining the optimal cache configuration, several parameters should be considered, in particular: the maximum allowed bandwidth for each client; the attached namespace for each client; client priority; client utilization (e.g., capacity, frequency, etc.); and historical data collection on the client.

[0049] It should be noted that the client can be a physical or virtual PCIe function. Additionally, the client can be a specific process address space identifier (PASID) used to identify a particular application in a paravirtualized environment. For the purposes of this disclosure, the virtual function ID, physical function ID, and process address space ID can all be used depending on the use case and host configuration.

[0050] Figure 4 A flowchart 400 outlining a method for calibrating ATC attributes according to one implementation is illustrated. In summary, the process begins by measuring the performance results of a default configuration that does not consider the client ID in ATC management. Subsequently, based on these results, the configuration is adjusted and re-evaluated. The iterative process continues until the optimal configuration is identified and selected for use. Periodic recalibration may occur to maintain optimal performance over time.

[0051] More specifically, the process begins with initialization at box 402. Then, at box 404, the system operates with a default configuration for ATC attributes. For example, the default could be global ATC. Next, at box 406, the system measures performance based on some traffic (such as read / write commands on the bus). Based on this measurement, and after a period of time, the ATC attribute configuration is adjusted based on the results at box 408, and performance is measured again at box 410. Then, at box 412, a check is performed to see if the final experiment has occurred. If not, the process returns to box 408, where the system adjusts and changes the configuration, then measures the results until the final experiment is complete. Once the final experiment is complete, at box 414, the optimal ATC configuration is selected based on the measured results. The system continues to operate in the selected mode and then checks to see if recalibration is beneficial. Recalibration may occur from time to time, such as hourly or if some inefficiency or performance degradation exists in the results. Based on the recalibration decision, the process is repeated again.

[0052] Figure 5 It is a schematic diagram of a system block diagram 500 based on an implementation scheme. Figure 5 The system block diagram 500 includes a Host Interface Module (HIM), which includes a calibration logic performance monitor for measuring results and QoS performance. The HIM also has ATC attribute configurations to be changed.

[0053] HIM integrates ATC and dynamic calibration logic modules. The calibration logic module proactively adjusts cache configuration, measures performance, and intelligently selects the optimal cache configuration. The goal is to achieve best performance results tailored to the unique characteristics of a specific system, workload, and configuration.

[0054] The optimal configuration for ATC can be workload-dependent. Reconfiguration may be necessary when workload changes, as the optimal configuration for ATC depends on the workload. There are also some static configurations that can affect the outcome, such as what namespaces are attached for latency-sensitive functions, and therefore, the result will be allocating more cache size to those specific functions, and so on. For example, regardless of whether the namespace is SLC or associated with an SLC, SLC generally offers more performance and therefore requires more allocation compared to TLC or QLC. Cache size can also adapt eviction policies to specific namespaces. Finally, the frequency with which calibration is triggered can depend on several attributes. For example, the system can be recalibrated if it detects any performance degradation, any change in workload, or simply from time to time or even if nothing is detected.

[0055] In one implementation, functional cache allocation is workload-driven and based on historical analysis. Such allocations are particularly valuable in enterprise computing use cases where the benefits of ATS within a specific function can be derived by analyzing previous I / O transactions.

[0056] In another implementation, feature cache allocation is influenced by static configuration. For example, a specific namespace attached to a feature may indicate greater sensitivity to latency and a higher allocation of ATS resources. Specific use cases include automotive multi-host environments, where some tenants may be pre-configured to use SLC namespaces. In the automotive multi-host environment example, the allocation of ATS resources will be biased towards features pre-defined as requiring more responsiveness.

[0057] In another implementation, the frequency at which the proposed calibration scheme is triggered can be modified based on various factors. For example, calibration can be triggered at a higher rate when the measured performance is relatively low, and at a lower rate when the measured performance is relatively high. A threshold can be provided to determine low / high performance. This value can also be continuous.

[0058] The frequency of calibration can also depend on external conditions and workload type. When the workload is highly intensive and requires system resources to maintain it, the calibration frequency can be lower, while when the workload is less intensive, calibrations can be performed more frequently.

[0059] Figure 6 This is flowchart 600 illustrating dynamic ATC allocation according to one implementation scheme. Initially, at box 602, initial ATC attributes are selected or set. Initial ATC attributes can be any ATC attribute distribution, such as global ATC, static ATC, or simply the last ATC attribute setting utilized by the system, to name a few. Once the initial ATC attributes are set, at box 604, the system uses those ATC attributes for operation. In terms of operation, this is understood to mean any general operation used to test the ATC attribute settings, such as actual read / write command processing or system-generated pseudo-commands. The performance of system operation using the ATC attribute settings is measured.

[0060] Then, determine system efficiency at box 606. Essentially, determine if the system is operating as efficiently as possible. If the system is not operating as efficiently as possible, change the ATC attribute at box 608, and at box 606, the system operates using the new ATC attribute.

[0061] If the system operates as efficiently as possible, it continues to operate using the same ATC properties at box 610. The system tracks any changes that may occur and / or whether a time threshold has been exceeded. If any system parameter has been changed at box 612, the process returns to box 606; otherwise, the process continues to box 614 to determine if a time threshold has been exceeded. If the time threshold has been exceeded, the process returns to box 606; otherwise, it continues operating at box 610. It should be noted that boxes 612 and 614 can occur in any order, and both boxes do not need to exist.

[0062] By dynamically allocating ATC through selecting the optimal cache attributes, ATC achieves the maximum performance result for the current application or workload. Efficiency can be measured in terms of performance when assuming the same ATC size.

[0063] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: select a configuration for operating the data storage device based on address translation cache (ATC) attributes; operate the data storage device using the configuration; measure the performance of the data storage device using the configuration; change the configuration from the configuration to a different configuration for the ATC attributes based on the measurement; and repeat the operation, the measurement, and the change. The configuration is a global ATC configuration. The configuration is a static ATC attribute configuration. The controller is configured to: select a working ATC configuration; operate the data storage device using the working configuration; and determine whether recalibration should occur after operating the data storage device using the working ATC configuration. After determining that recalibration should occur, the controller is configured to: change the working ATC configuration to a new configuration for these ATC attributes; operate the data storage device using the new configuration; measure the performance of the data storage device using the new configuration; select a new working ATC configuration for the data storage device; and operate the data storage device using the selected new working ATC configuration. The controller is configured to repeat the change to a new configuration, operate using the new configuration, and measure performance using the new configuration. The controller includes a Host Interface Module (HIM), in which the ATC is set. The HIM includes an ATC attribute configuration module, a performance monitoring module, and a calibration logic module. The controller is configured to interact with one or more of the following: virtual functions; physical functions; process address space identifiers (PASIDs); and combinations thereof. This configuration prioritizes functions that are intended to require higher responsiveness compared to other functions.

[0064] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller includes a host interface module (HIM), the host interface module including: a calibration logic module configured to adjust cache configuration, measure the performance of the data storage device, and intelligently select an optimal cache configuration; a performance monitor module configured to monitor the performance of the data storage device; and an address translation cache (ATC) configuration module configured to maintain one or more cache configurations to be used by the calibration logic module for the adjustment. The calibration logic module is configured to adjust the cache configuration based on workload from historical analysis. The calibration logic module is configured to adjust the cache configuration using pre-configured weights that favor functions requiring more responsiveness compared to other functions requiring less responsiveness. Calibration performed by the calibration logic module is triggered at a higher rate when the measured performance is below a threshold, compared to when the measured performance is equal to or greater than a threshold. Calibration performed by the calibration logic module is triggered based on workload from external conditions and functions. The calibration frequency decreases as the workload increases. The module operates dynamically.

[0065] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: measure the performance of the data storage device; change address translation cache (ATC) attributes based on the measurement; operate the data storage device using the changed ATC attributes; save the ATC attributes; repeat the measurement, the change, the operation, and the saving once or multiple times; select an optimal ATC attribute; and operate the data storage device using the selected optimal ATC attribute. The controller is configured to determine whether a recalibration of the ATC attributes should occur, wherein the determination occurs after operating the data storage device using the selected optimal ATC attribute. The measurement, the change, the operation, and the saving occur in a host interface module (HIM) of the controller.

[0066] While the foregoing describes an embodiment of this disclosure, other and additional embodiments of this disclosure may be designed without departing from the basic scope of this disclosure, and the scope of this disclosure is defined by the appended claims.

Claims

1. A data storage device, the data storage device comprising: Memory devices; and A controller, coupled to the memory device, wherein the controller is configured to: Select the configuration for the Address Translation Cache (ATC) attribute to operate the data storage device; Use the above configuration to operate the data storage device; Use the configuration described above to measure the performance of the data storage device; Based on the measurement, change from the configuration to a different configuration for the ATC attribute; as well as Repeat the operation, the measurement, and the change.

2. The data storage device according to claim 1, wherein the configuration is a global ATC configuration.

3. The data storage device according to claim 1, wherein the configuration is a static ATC attribute configuration.

4. The data storage device according to claim 1, wherein the controller is configured to: Select the working ATC configuration; Use the aforementioned working configuration to operate the data storage device; and After operating the data storage device using the aforementioned working ATC configuration, it is determined whether a recalibration should occur.

5. The data storage device of claim 4, wherein after determining that a recalibration should occur, the controller is configured to: Change from the working ATC configuration to a new configuration for the ATC attributes; Use the new configuration to operate the data storage device; Use the new configuration to measure the performance of the data storage device; Select a new working ATC configuration for the data storage device; as well as Operate the data storage device using the selected new working ATC configuration.

6. The data storage device of claim 5, wherein the controller is configured to repeat the change to a new configuration, operate using the new configuration, and measure performance using the new configuration.

7. The data storage device of claim 1, wherein the controller includes a host interface module (HIM), and wherein the ATC is disposed in the HIM.

8. The data storage device according to claim 7, wherein the HIM includes an ATC attribute configuration module, a performance monitor module, and a calibration logic module.

9. The data storage device of claim 1, wherein the controller is configured to interact with one or more of the following: Virtual functions; Physical function; Process Address Space Identifier (PASID); and Their combination.

10. The data storage device of claim 1, wherein the configuration is biased towards functions that are intended to require higher responsiveness compared to other functions.

11. A data storage device, the data storage device comprising: Memory devices; and A controller coupled to the memory device, wherein the controller includes a host interface module (HIM), the host interface module (HIM) comprising: A calibration logic module configured to adjust cache configuration, measure the performance of the data storage device, and intelligently select the optimal cache configuration; A performance monitoring module, configured to monitor the performance of the data storage device; and An Address Translation Cache (ATC) configuration module is configured to maintain one or more cache configurations to be used by the calibration logic module for the adjustment.

12. The data storage device of claim 11, wherein the calibration logic module is configured to adjust the cache configuration based on the workload of historical analysis.

13. The data storage device of claim 11, wherein the calibration logic module is configured to adjust the cache configuration using pre-configured weights that favor functions that require more responsiveness compared to other functions that require less responsiveness.

14. The data storage device of claim 11, wherein when the measured performance is below the threshold, calibration performed by the calibration logic module is triggered at a higher rate than when the measured performance is equal to or greater than the threshold.

15. The data storage device of claim 11, wherein the calibration performed by the calibration logic module is triggered based on external conditions and functional workload.

16. The data storage device of claim 15, wherein the calibration frequency is reduced as the workload increases.

17. The data storage device according to claim 11, wherein the module operates dynamically.

18. A data storage device, the data storage device comprising: Memory devices; and A controller, coupled to the memory device, wherein the controller is configured to: Measure the performance of the data storage device; Based on the measurements, change the Address Translation Cache (ATC) attributes; The data storage device is operated using the modified ATC attributes; Save the ATC attributes; Repeat the measurement, the change, the operation, and the save once or multiple times; Select the best ATC attribute; as well as Operate the data storage device using the selected optimal ATC attributes.

19. The data storage device of claim 18, wherein the controller is configured to determine whether a recalibration of the ATC attribute should occur, wherein the determination occurs after the data storage device is operated using the selected optimal ATC attribute.

20. The data storage device of claim 18, wherein the measurement, the change, the selection, and the saving occur in the host interface module (HIM) of the controller.

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