Method and system for monitoring encapsulation exceptions of multi-layer stacked memory chips

Abstract

The present application relates to the technical fields of intelligent chip detection, and discloses a packaging abnormality monitoring method and system for multi-layer stacked memory chips, comprising: collecting the thermal compression bonding temperature and bonding pressure value of the chip in real time, determining the packaging process stress index of the chip by using the thermal compression bonding temperature and bonding pressure value, querying the multi-process cumulative duration and historical packaging failure information of the chip, analyzing the packaging process deviation coefficient of the chip by using the packaging process stress index and multi-process cumulative duration, constructing the monitoring cycle table of the chip based on the packaging process deviation coefficient and historical packaging failure information, measuring the electrical characteristics of the through silicon via structure of the chip, determining the impedance amplitude and phase angle of the chip based on the measurement data of the electrical characteristics measurement, and monitoring the packaging abnormality of the chip based on the impedance amplitude and phase angle to obtain an abnormality monitoring report. The present application can accurately locate the abnormal packaging position of the multi-layer stacked memory chip, thereby improving the efficiency of abnormality monitoring.

Description

Technical Field

[0001] This invention relates to a method and system for monitoring packaging anomalies in multilayer stacked memory chips, belonging to the field of intelligent chip detection technology. Background Technology

[0002] Multilayer stacked memory chips, with their advantages of high storage density and fast data transfer rates, are increasingly widely used in consumer electronics, artificial intelligence servers, and autonomous driving vehicle systems, becoming a core storage component supporting the operation of high-end electronic devices. However, due to the numerous processes involved in chip packaging, these chips are prone to anomalies such as layer misalignment, bond wire failure, and package cracking, which can lead to data transmission errors and memory module failures. Therefore, monitoring for anomalies during chip packaging is crucial.

[0003] Currently, the detection of packaging anomalies in multilayer stacked memory chips mainly relies on automated optical inspection methods to reconstruct the chip's surface morphology, followed by X-ray tomography to detect localized internal defects in the abnormal areas. However, X-ray tomography scans cover the entire chip and cannot accurately locate critical components, resulting in low efficiency. Summary of the Invention

[0004] This invention provides a method and system for monitoring packaging anomalies in multilayer stacked memory chips. Its main purpose is to accurately locate abnormal parts in the packaging of multilayer stacked memory chips, thereby improving the efficiency of anomaly monitoring.

[0005] To achieve the above objectives, the present invention provides a method for monitoring packaging anomalies in multilayer stacked memory chips, comprising: During the multi-layer stacked memory chip packaging process, the hot-press bonding temperature and bonding pressure values ​​of the chip are collected in real time. The packaging process stress index of the chip is determined using the hot-press bonding temperature and the bonding pressure values. The cumulative duration of multiple processes and historical packaging failure information of the multi-layer stacked memory chip are queried. The packaging process deviation coefficient of the chip is analyzed using the packaging process stress index and the cumulative duration of multiple processes. Based on the packaging process deviation coefficient and the historical packaging failure information, a monitoring cycle table of the chip is constructed. Based on the monitoring periodic table, the electrical characteristics of the through-silicon via structure of the chip are measured, and the impedance amplitude and phase angle of the chip are determined based on the measurement data of the electrical characteristics. Based on the impedance amplitude and the phase angle, the packaging anomaly monitoring of the multilayer stacked memory chip is performed to obtain an anomaly monitoring report of the chip.

[0006] Optionally, based on the impedance magnitude and the phase angle, packaging anomaly monitoring is performed on the multilayer stacked memory chip to obtain an anomaly monitoring report for the chip, including: A reference parameter table is constructed for the packaging of the multi-layer stacked memory chip, and the reference parameter table includes reference impedance magnitude and reference phase angle; Based on the impedance amplitude and the phase angle, and in conjunction with the reference parameter table, the parameter deviation of the multilayer stacked memory chip during packaging is calculated. Based on the parameter deviation, calculate the comprehensive anomaly index of the multilayer stacked memory chip during packaging; Based on the aforementioned anomaly comprehensive index, analyze the packaging anomaly state during the packaging of the multi-layer stacked memory chip; An anomaly monitoring report for multi-layer stacked memory chips is constructed using the aforementioned packaging anomaly status.

[0007] Optionally, based on the anomaly comprehensive index, the packaging anomaly state during the packaging of the multi-layer stacked memory chip is analyzed, including: The anomaly comprehensive index is used to analyze the anomaly level of the multi-layer stacked memory chip; Based on the anomaly level, typical failure mode characteristics of the multi-layer stacked memory chip are identified; By utilizing the characteristics of the typical failure modes, the abnormal packaging state during the packaging of the multi-layer stacked memory chip is determined.

[0008] Optionally, based on the measurement data obtained from the electrical characteristic measurements, the impedance magnitude and phase angle of the chip are determined, including: Using the measurement data, the response signal of the chip during electrical characteristic measurements is identified; Perform a Fast Fourier Transform on the response signal to obtain the electrical response spectrum; The real and imaginary parts of the current and voltage of the chip at various test frequency points are identified using the electrical response spectrum. The impedance amplitude of the chip is calculated based on the real part and the imaginary part. The phase angle of the chip is determined based on the ratio between the real part and the imaginary part.

[0009] Optionally, the packaging process stress index of the chip is determined using the hot-press bonding temperature and the bonding pressure value, including: The packaging structure material parameters of the chip are queried, and a thermo-mechanical coupling model of the chip is constructed using the packaging structure material parameters; After using the thermo-press bonding temperature and the bonding pressure value as the boundary conditions of the thermo-mechanical coupling model, the instantaneous thermal stress and mechanical stress of the chip are calculated using the thermo-mechanical coupling model. Based on the instantaneous thermal stress and the mechanical stress, the cumulative stress value of the chip is calculated; Based on the accumulated stress value, the packaging process stress index of the chip is determined.

[0010] Optionally, calculating the cumulative stress value of the chip based on the instantaneous thermal stress and the mechanical stress includes: The instantaneous thermal stress and the mechanical stress are transformed by stress tensor to obtain the instantaneous thermal stress tensor and the mechanical stress tensor; The instantaneous thermal stress tensor and the mechanical stress tensor are tensor synthesized to obtain the instantaneous equivalent stress; The cumulative stress value of the chip is calculated using the instantaneous equivalent stress.

[0011] Optionally, based on the packaging process deviation coefficient and the historical packaging failure information, a monitoring cycle table for the chip is constructed, including: Based on the historical packaging failure information, the historical failure rate corresponding to the packaging process deviation coefficient in different numerical ranges is calculated. Using the historical failure rate, a risk level mapping table for the chip is constructed; Based on the risk level mapping table and the packaging process deviation coefficient, the real-time risk level of different packaging structures of the chip is determined; Based on the real-time risk level, the monitoring frequency and monitoring area of ​​the chip under different packaging structures are constructed. Based on the monitoring frequency and the monitoring area, a monitoring cycle table for the chip is constructed.

[0012] Optionally, the packaging process deviation coefficient of the chip can be analyzed using the packaging process stress index and the cumulative time of the multi-process steps, including: Obtain the standard process stress range and standard process duration of the chip; The stress deviation of the chip is calculated using the packaging process stress index and the standard process stress range. The chip's time deviation is calculated using the standard process time and the cumulative time of the multiple processes. The stress deviation and the duration deviation are used as the packaging process deviation coefficients of the chip.

[0013] Optionally, based on the monitoring periodicity, electrical characteristic measurements are performed on the through-silicon via (TSV) structure of the chip, including: Identify the current monitoring frequency and key monitoring area set for the chip from the monitoring cycle table; Based on the monitoring frequency and the key monitoring area, configure the signal frequency and scanning path for the electrical testing equipment corresponding to the chip; Based on the signal frequency and the scanning path, the electrical characteristics of the through-silicon via (TSV) structure of the chip are measured using the electrical testing equipment. To address the above problems, the present invention also provides a packaging anomaly monitoring system for multi-layer stacked memory chips, the system comprising: The packaging stress analysis module is used to collect the hot-press bonding temperature and bonding pressure values ​​of the chip in real time during the packaging process of multi-layer stacked memory chips, and to determine the packaging process stress index of the chip using the hot-press bonding temperature and the bonding pressure values. The monitoring cycle table construction module is used to query the cumulative duration of multiple processes and historical packaging failure information of the multi-layer stacked memory chip, analyze the packaging process deviation coefficient of the chip using the packaging process stress index and the cumulative duration of multiple processes, and construct the monitoring cycle table of the chip based on the packaging process deviation coefficient and the historical packaging failure information. An electrical performance measurement module is used to measure the electrical characteristics of the through-silicon via structure of the chip based on the monitoring periodic table, and to determine the impedance amplitude and phase angle of the chip based on the measurement data of the electrical characteristics measurement. An anomaly monitoring module is used to perform packaging anomaly monitoring on the multilayer stacked memory chip based on the impedance amplitude and the phase angle, and to obtain an anomaly monitoring report for the chip.

[0014] Compared to the problems described in the background art, this invention first determines the packaging process stress index by collecting the chip's thermo-pressing bonding temperature and bonding pressure values. This step, through real-time collected temperature and pressure data, accurately reflects the dynamic stress state of the chip during bonding, avoiding the lag of offline data collection and providing a core quantitative basis for subsequent analysis of process deviations. This ensures that subsequent steps can be based on real process stress rather than relying on vague empirical judgments. Next, based on the packaging process stress index obtained in the first step, this invention analyzes the packaging process deviation coefficient and constructs a monitoring periodic table. This allows for precise location of the core sources of process deviations, further identifying high-risk processes and improving the accuracy of anomaly location. Then, guided by the monitoring periodic table, this invention performs electrical characteristic measurements on the chip's through-silicon via (TSV) structure and determines the impedance amplitude based on the measurement data. Impedance amplitude and phase angle are crucial for through-silicon vias (TSVs), which are key structures for interlayer data transmission in multilayer stacked chips. Packaging anomalies (such as delamination or poor contact) directly lead to abrupt changes in electrical characteristics. Traditional single-dimensional monitoring (such as temperature measurement alone) cannot cover internal electrical anomalies within TSVs. Therefore, this invention avoids missing dynamic anomalies during offline detection. Furthermore, the measured impedance amplitude and phase angle directly quantify the physical state of the TSV, providing specific and verifiable parameters for final anomaly monitoring. Finally, this invention uses impedance amplitude and phase angle for packaging anomaly monitoring. Compared to traditional methods relying on visual inspection or single parameters, impedance amplitude and phase angle directly correlate with the internal physical state of the TSV, enabling rapid identification of hidden packaging anomalies such as chip delamination, bonding failure, and insulation damage. Therefore, this invention can accurately locate packaging anomalies in multilayer stacked memory chips, thereby improving the efficiency of anomaly monitoring. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating a method for monitoring packaging anomalies in a multilayer stacked memory chip according to an embodiment of the present invention. Figure 2 This is a schematic diagram of a module for implementing a packaging anomaly monitoring method for multi-layer stacked memory chips according to an embodiment of the present invention.

[0016] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0017] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0018] This application provides a method for monitoring packaging anomalies in multi-layer stacked memory chips. The execution subject of this method includes, but is not limited to, at least one electronic device configured to execute the method provided in this application, such as a server or a terminal. In other words, the method for monitoring packaging anomalies in multi-layer stacked memory chips can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0019] Reference Figure 1 The diagram shown is a flowchart illustrating a method for monitoring packaging anomalies in a multilayer stacked memory chip according to an embodiment of the present invention. In this embodiment, the method for monitoring packaging anomalies in a multilayer stacked memory chip includes: S1. During the multi-layer stacked memory chip packaging process, the hot-press bonding temperature and bonding pressure values ​​of the chip are collected in real time, and the packaging process stress index of the chip is determined using the hot-press bonding temperature and the bonding pressure values.

[0020] This invention provides the most direct and real-time key data source for packaging process quality control by collecting the hot-press bonding temperature and bonding pressure values ​​of the chip in real time during the multi-layer stacked memory chip packaging process.

[0021] The hot-press bonding temperature refers to the actual temperature transmitted by the heating device to the bonding area of ​​the chip during the hot-press bonding process of multilayer stacked memory chip packaging, and the bonding pressure value refers to the vertical pressure applied by the pressure head to the bonding area of ​​the multilayer stacked memory chip during the hot-press bonding process.

[0022] Furthermore, by utilizing the thermocompression bonding temperature and the bonding pressure value, this embodiment of the invention determines the chip's packaging process stress index. This transforms key process parameters (temperature and pressure) in actual production into a comprehensive index that quantifies the stress level experienced by the chip during packaging, providing a direct basis for real-time assessment of current packaging process requirements. For example, during chip packaging, when the system detects that the bonding temperature is too high and the pressure is insufficient, the stress index will increase significantly, directly indicating that the current bonding interface is under abnormal thermomechanical load, providing operators with a clear basis for immediate adjustment of process parameters.

[0023] The packaging process stress index refers to the vertical pressure applied by the pressure head to the bonding area of ​​the multilayer stacked memory chip during the thermo-press bonding process.

[0024] As an embodiment of the present invention, the packaging process stress index of the chip is determined using the hot-press bonding temperature and the bonding pressure value, including: The packaging structure material parameters of the chip are queried, and a thermo-mechanical coupling model of the chip is constructed using the packaging structure material parameters; After using the thermo-press bonding temperature and the bonding pressure value as the boundary conditions of the thermo-mechanical coupling model, the instantaneous thermal stress and mechanical stress of the chip are calculated using the thermo-mechanical coupling model. Based on the instantaneous thermal stress and the mechanical stress, the cumulative stress value of the chip is calculated; Based on the accumulated stress value, the packaging process stress index of the chip is determined.

[0025] The packaging structure material parameters refer to the inherent physical property parameters of each layer of the chip package structure (such as chip, solder, substrate, molding compound, etc.). The thermo-mechanical coupling model refers to a computer simulation model that can simultaneously simulate the mutual influence and changes between the temperature field and the stress field. The instantaneous thermal stress refers to the internal stress generated inside the material during the thermo-press bonding process due to the mismatch of the thermal expansion coefficients of the chip layer materials. The mechanical stress refers to the internal stress generated by the bonding pressure applied from the outside directly acting on the chip structure during the thermo-press bonding process.

[0026] In detail, key material parameters can be extracted from the chip packaging design database. These parameters include at least the coefficient of thermal expansion, Young's modulus, and Poisson's ratio of each structural layer (such as chip, solder, and substrate). Then, a three-dimensional geometric model is built in finite element analysis software (such as ABAQUS) using these parameters to obtain a thermo-mechanical coupling model. The real-time collected thermo-pressing bonding temperature is used as a thermal boundary condition and applied to the corresponding bonding region in the model (such as the contact area of ​​interlayer microbumps). At the same time, the bonding pressure value is converted into a pressure distribution according to the actual area of ​​the pressure head and applied as a mechanical boundary condition in the same region. The instantaneous thermal stress caused by the temperature gradient is calculated by the thermal analysis module of the software, and the instantaneous mechanical stress under pressure is calculated by the structural analysis module. When calculating the packaging process stress index, the stress safety threshold under different material combinations can be determined first, and then the formula "packaging process stress index = cumulative stress value / stress safety threshold" can be used for calculation.

[0027] Preferably, calculating the cumulative stress value of the chip based on the instantaneous thermal stress and the mechanical stress includes: The instantaneous thermal stress and the mechanical stress are transformed by stress tensor to obtain the instantaneous thermal stress tensor and the mechanical stress tensor; The instantaneous thermal stress tensor and the mechanical stress tensor are tensor synthesized to obtain the instantaneous equivalent stress; The cumulative stress value of the chip is calculated using the instantaneous equivalent stress.

[0028] Furthermore, as another embodiment of the present invention, the formula for calculating the stress accumulation value is as follows:

[0029] in, This represents the cumulative stress value. It represents the instantaneous equivalent stress.

[0030] The instantaneous equivalent stress refers to the method of equating the complex multi-directional stress state generated at a certain point inside the chip due to heat and pressure into a simple unidirectional stress value at a specific instant.

[0031] In detail, the component data of thermal stress and mechanical stress of the chip at a specific process moment can be extracted from the simulation results of finite element analysis software (these data usually exist in the form of six independent components in the Cartesian coordinate system). Then, the original components are converted into instantaneous thermal stress tensors and mechanical stress tensors in the target coordinate system by using the direction cosine matrix combined with the coordinate transformation formula of the stress tensor. The corresponding components of the two stress tensors are algebraically added using the tensor addition principle, and then the equivalent stress is calculated based on the Mises yield criterion.

[0032] S2. Query the cumulative duration of multiple processes and historical packaging failure information of the multi-layer stacked memory chip. Analyze the packaging process deviation coefficient of the chip using the packaging process stress index and the cumulative duration of multiple processes. Based on the packaging process deviation coefficient and the historical packaging failure information, construct a monitoring cycle table for the chip.

[0033] This invention, through querying the cumulative time of multiple processes and historical packaging failure information of the multi-layer stacked memory chip, can obtain process data and past problem references for the entire packaging process of the multi-layer stacked memory chip. This allows the analysis of processes to be limited by the limitations of single process parameters, and enables the prediction of current packaging risks from the perspectives of "process accumulation" and "historical reference". For example, in 3D NAND chip packaging, if it is found that the cumulative time of multiple processes such as bonding and curing of a certain batch of chips exceeds the average of previous fault-free batches, and historical failure information shows that packaging delamination is likely to occur at this time, the potential delamination risk of the current batch can be anticipated in advance.

[0034] The cumulative time of the multi-process refers to the total time actually spent by the current multi-layer stacked memory chip from the moment it enters the packaging production line until it reaches the current process (such as thermoforming). This includes all the preceding processes (such as wafer mounting, wire bonding, etc.).

[0035] In detail, the execution time of each key process from the start of the packaging process to the current process can be retrieved through the manufacturing execution system of the chip production line, and the time of each process can be added up to obtain the cumulative time of multiple processes; historical packaging failure information can be obtained from the enterprise's packaging quality history database by querying the failure types and process parameters of chips of the same model and stack structure as the current chip in the past.

[0036] This invention utilizes the packaging process stress index and the cumulative duration of multiple processes to analyze the chip packaging process deviation coefficient. By combining the packaging process stress index, which reflects real-time process stress, with the cumulative duration of multiple processes, which reflects the cumulative effect of the process, the degree of deviation of the chip packaging from the standard process can be quantitatively analyzed, thereby quantitatively assessing the degree of deviation of the current chip packaging process from the ideal state.

[0037] The packaging process deviation coefficient is a comprehensive dynamic evaluation index used to quantify the degree to which the current chip packaging process conditions deviate from the ideal state or standard path.

[0038] As an embodiment of the present invention, the packaging process deviation coefficient of the chip is analyzed using the packaging process stress index and the cumulative time of the multi-process steps, including: Obtain the standard process stress range and standard process duration of the chip; The stress deviation of the chip is calculated using the packaging process stress index and the standard process stress range. The chip's time deviation is calculated using the standard process time and the cumulative time of the multiple processes. The stress deviation and the duration deviation are used as the packaging process deviation coefficients of the chip.

[0039] In detail, the standard process stress range and standard process duration of the chip can be obtained by calling the product process specification database; the actual obtained packaging process stress index is compared with the standard process stress range obtained in the first step to determine the median of the standard range (or the average of the upper and lower limits), and then the deviation is calculated by the formula "stress deviation = (actual stress index - standard median) / standard median"; the cumulative time of multiple processes in real time is compared with the standard process duration obtained in the first step, and the deviation is calculated by the formula "duration deviation = (cumulative time - standard time) / standard time".

[0040] Furthermore, by constructing a monitoring cycle table for the chip based on the packaging process deviation coefficient and the historical packaging fault information, this embodiment of the invention can combine the current chip packaging process deviation degree with the pattern of similar problems in the past to customize a monitoring cycle table that is suitable for the risk level of different chips, making the monitoring more accurate.

[0041] The monitoring period table refers to a time interval table for anomaly monitoring at different stages, customized for a single multi-layer stacked memory chip.

[0042] As an embodiment of the present invention, a monitoring cycle table for the chip is constructed based on the packaging process deviation coefficient and the historical packaging failure information, including: Based on the historical packaging failure information, the historical failure rate corresponding to the packaging process deviation coefficient in different numerical ranges is calculated. Using the historical failure rate, a risk level mapping table for the chip is constructed; Based on the risk level mapping table and the packaging process deviation coefficient, the real-time risk level of different packaging structures of the chip is determined; Based on the real-time risk level, the monitoring frequency and monitoring area of ​​the chip under different packaging structures are constructed. Based on the monitoring frequency and the monitoring area, a monitoring cycle table for the chip is constructed.

[0043] The risk level mapping table refers to a predefined query rule table that establishes the correspondence between the specific numerical range of the packaging process deviation coefficient and different risk levels. The real-time risk level is used to represent the current risk level of each packaging structure of the chip. The monitoring frequency refers to the number of times the chip packaging structure with different risk levels is detected per unit time. The monitoring area refers to the set of locations on the chip surface to be detected determined according to the historical fault distribution pattern and the real-time risk level.

[0044] In detail, historical packaging failure records of the same model and stacking structure as the current chip are extracted from the company's historical packaging quality database. These records are then grouped according to the numerical range of the packaging process deviation coefficient (e.g., 0-0.3, 0.3-0.6, 0.6-1.0, etc.), and the historical failure rate within each range is calculated. Based on the historical failure rate, risk level standards are established (e.g., failure rate ≤ 5%). The risk level is categorized into low risk (5%-15%), medium risk (>15%), and high risk (5%). Each packaging process deviation coefficient range is associated with its corresponding risk level to create a risk level mapping table. The risk level corresponding to each deviation coefficient range is retrieved from this table, and the current chip's packaging process deviation coefficient is matched with the range to determine the overall risk level. Based on the determined real-time risk level, the monitoring frequency is set according to preset rules (e.g., once every hour for high risk, once every 3 hours for medium risk, and once every 6 hours for low risk). Simultaneously, the high-frequency fault locations of each structure in historical fault information (e.g., the edges of through-silicon vias of a certain chip model are prone to failure) are referenced to identify areas requiring focused monitoring. The obtained monitoring frequencies and areas for each packaging structure are integrated, and the monitoring objects at different times are arranged chronologically to form a structured table containing monitoring time, object, and area.

[0045] S3. Based on the monitoring periodic table, perform electrical characteristic measurements on the through-silicon via structure of the chip, and determine the impedance amplitude and phase angle of the chip based on the measurement data of the electrical characteristic measurements.

[0046] This invention, through the monitoring periodic table, measures the electrical characteristics of the through-silicon via (TSV) structure of the chip. By following the monitoring periodic table, the electrical characteristics of the TSV structure, which is critical for interlayer data transmission, can be measured in a timely manner, thereby promptly detecting problems such as poor contact and abnormal impedance that may occur in the TSV.

[0047] As an embodiment of the present invention, based on the monitoring periodic table, the electrical characteristics of the through-silicon via (TSV) structure of the chip are measured, including: Identify the current monitoring frequency and key monitoring area set for the chip from the monitoring cycle table; Based on the monitoring frequency and the key monitoring area, configure the signal frequency and scanning path for the electrical testing equipment corresponding to the chip; Based on the signal frequency and the scanning path, the electrical characteristics of the through-silicon via (TSV) structure of the chip are measured using the electrical testing equipment.

[0048] The signal frequency refers to the frequency at which an electrical test device (such as an impedance analyzer) applies an AC test signal to a through-silicon via (TSV) when measuring its electrical characteristics. The scan path refers to the preset route along which the probe of the electrical test device moves on the chip surface.

[0049] In detail, an appropriate test signal frequency can be selected based on the monitoring frequency parameters (the specific settings need to be combined with the actual application). High-frequency monitoring corresponds to a wider frequency band scan. At the same time, the optimal measurement path is generated based on the coordinate information of the key monitoring area. The path generation can be analyzed using a genetic algorithm to ensure that the test probe can efficiently cover all key locations. After the parameters are configured, the test equipment automatically performs the measurement according to the set signal frequency and scan path.

[0050] Furthermore, in this embodiment of the invention, by using measurement data based on the electrical characteristics, the impedance amplitude and phase angle of the chip can be determined, transforming the raw data obtained from electrical measurements into key characteristic indicators that can quantitatively reflect the physical state of the internal interconnect structure of the chip, thereby improving monitoring efficiency.

[0051] The impedance amplitude refers to the total resistance of the through-silicon via (TSV) to alternating current when measuring the electrical characteristics of the TSV structure of a multilayer stacked memory chip. Its value directly reflects the conductivity of the TSV. For example, when the TSV has poor contact due to encapsulation stress, the impedance amplitude will be significantly higher than the standard value. If metal layer oxidation occurs, the impedance amplitude will also increase with the degree of oxidation. The phase angle refers to the phase difference between the alternating voltage applied across the TSV and the alternating current flowing through the TSV during the electrical characteristic measurement of the TSV.

[0052] As an embodiment of the present invention, determining the impedance amplitude and phase angle of the chip based on the measurement data of the electrical characteristic measurement includes: Using the measurement data, the response signal of the chip during electrical characteristic measurements is identified; Perform a Fast Fourier Transform on the response signal to obtain the electrical response spectrum; The real and imaginary parts of the current and voltage of the chip at various test frequency points are identified using the electrical response spectrum. The impedance amplitude of the chip is calculated based on the real part and the imaginary part. The phase angle of the chip is calculated based on the ratio between the real part and the imaginary part.

[0053] The electrical response spectrum refers to a graph describing how the impedance or admittance of a circuit or component changes with frequency. The real part of the complex impedance represents the real portion of the impedance; in a circuit, it represents the voltage component in phase with the current, typically corresponding to the resistive part and related to energy consumption. The imaginary part of the complex impedance represents the imaginary part of the impedance; in a circuit, it represents the voltage component in the impedance with a 90-degree phase difference from the current, typically corresponding to the reactive part (capacitive or inductive reactance) and related to energy storage and release.

[0054] In detail, a low-pass filter can be used to filter out the voltage and current response signals related to the through-silicon via (TSV) from the measurement data; a Fast Fourier Transform (FFT) is performed on the filtered response signals to transform them from the time domain to the frequency domain, generating an electrical response spectrum; in the electrical response spectrum, based on the principle of quadrature demodulation (such as IQ demodulation technology), the spectral signal at each test frequency point is decomposed into in-phase components (real parts) and quadrature components (imaginary parts); the real and imaginary values ​​of the voltage and current are substituted into the complex impedance calculation formula (impedance = voltage / current), and then the impedance amplitude is calculated using the following formula:

[0055] in, R represents the impedance magnitude, and I represents the real part of the impedance. Furthermore, the phase angle can be calculated using the following formula based on the ratio between the real and imaginary parts of the current:

[0056] in, R represents the phase angle, R represents the real part of the impedance, and I represents the imaginary part of the impedance.

[0057] S4. Based on the impedance amplitude and the phase angle, perform packaging anomaly monitoring on the multilayer stacked memory chip to obtain an anomaly monitoring report for the chip.

[0058] This invention provides an embodiment of the invention that monitors the packaging anomalies of the multilayer stacked memory chip based on the impedance amplitude and the phase angle. The resulting chip anomaly monitoring report can be directly correlated with the internal physical state of the through-silicon via, thereby quickly identifying hidden packaging anomalies such as chip delamination, bonding failure, and insulation damage.

[0059] As an embodiment of the present invention, based on the impedance amplitude and the phase angle, packaging anomaly monitoring is performed on the multilayer stacked memory chip to obtain an anomaly monitoring report of the chip, including: A reference parameter table is constructed for the packaging of the multi-layer stacked memory chip, and the reference parameter table includes reference impedance magnitude and reference phase angle; Based on the impedance amplitude and the phase angle, and in conjunction with the reference parameter table, the parameter deviation of the multilayer stacked memory chip during packaging is calculated. Based on the parameter deviation, calculate the comprehensive anomaly index of the multilayer stacked memory chip during packaging; Based on the aforementioned anomaly comprehensive index, analyze the packaging anomaly state during the packaging of the multi-layer stacked memory chip; An anomaly monitoring report for multi-layer stacked memory chips is constructed using the aforementioned packaging anomaly status.

[0060] The reference parameter table refers to a set of reference values ​​established by statistically analyzing the test data of qualified chip samples, including the reference impedance amplitude range and reference phase angle range at different test frequencies. The parameter deviation refers to the comprehensive value of the deviation of the measured impedance amplitude and phase angle from the reference parameters. The anomaly comprehensive index refers to the packaging quality assessment value calculated based on the parameter deviation. The packaging anomaly status refers to the specific defect type and level determined according to the magnitude and distribution characteristics of the anomaly comprehensive index, including typical failure modes such as through-silicon via connection anomalies, microbump failures, or interface delamination, and their severity classifications.

[0061] In detail, a batch of known good multilayer stacked memory chips can be selected from the packaging production line as a reference sample. Under standard test conditions, a large number of impedance amplitude and phase angle data of the through-silicon via (TSV) structure of the good chips are collected and then structured and stored to obtain a reference parameter table. The impedance amplitude and phase angle measured by the current chip are compared with the corresponding values ​​in the reference parameter table, and the parameter deviation is calculated through relative deviation. First, the packaging abnormality results obtained from the previous analysis (including whether there is an abnormality, the packaging process corresponding to the abnormality, etc.) are summarized, and the abnormality comprehensive index and parameter deviation raw data corresponding to the abnormality are associated. Then, this information is organized into a document combining text and graphics in the logical order of "packaging process - real-time parameters - deviation status - abnormality judgment" to obtain an abnormality monitoring report.

[0062] Furthermore, in another embodiment of the invention, the formula for calculating the anomaly comprehensive index is as follows:

[0063] in, Indicates the abnormal comprehensive index, This represents the composite deviation sensitivity coefficient. Indicates the peak abnormal amplification factor. Indicates the degree of impedance amplitude deviation. Indicates the phase angle deviation. This represents the median of the reference phase angle.

[0064] It should be further explained that the calculation formula for the anomaly comprehensive index integrates impedance amplitude deviation and phase angle deviation to comprehensively quantify the degree of anomaly in the packaging process of multilayer stacked memory chips. The first part uses square root operations to nonlinearly integrate impedance amplitude deviation (δ|Z|) and phase angle relative deviation (Δθ / θref), highlighting the cumulative effect of their deviations. α is a weighting coefficient calibrated based on historical fault data, and its influence weight can be adjusted according to frequently occurring anomaly types (such as common faults caused by impedance deviation), enhancing sensitivity to key anomalies. The second part introduces a logarithmic term, using a tree-like formula to handle the maximum value of the two deviations, avoiding extreme effects on the comprehensive index when a single parameter deviates excessively. β, also calibrated based on historical fault data, is used to adjust the strength of the logarithmic term, making the formula more closely reflect actual fault patterns.

[0065] Preferably, based on the anomaly comprehensive index, the packaging anomaly state during the packaging of the multi-layer stacked memory chip is analyzed, including: The anomaly comprehensive index is used to analyze the anomaly level of the multi-layer stacked memory chip; Based on the anomaly level, typical failure mode characteristics of the multi-layer stacked memory chip are identified; By utilizing the characteristics of the typical failure modes, the abnormal packaging state during the packaging of the multi-layer stacked memory chip is determined.

[0066] The typical failure mode characteristics refer to the quantifiable combination and variation patterns of parameters extracted from historical packaging failure data that are strongly correlated with specific types of defects (such as TSV microcracks, interface delamination, chip warping, etc.).

[0067] In detail, based on historical packaging fault data and the allowable deviation range of the process, thresholds corresponding to multiple abnormality levels can be preset (such as low level, medium level, and high level corresponding to different index ranges). Then, the calculated comprehensive abnormality index is compared with the preset thresholds to match the corresponding abnormality level. Typical fault mode data of the corresponding level are retrieved from the historical fault feature library, including key feature parameters such as impedance spectrum characteristics and phase angle distribution patterns. The similarity between the measured characteristics of the current chip and the typical fault mode characteristics is calculated using the Euclidean distance calculation formula. If the distance is less than 0.2, it is considered to be of the same category (the specific distance setting needs to be set according to the actual application).

[0068] like Figure 2 The diagram shown is a functional block diagram of the packaging anomaly monitoring system for multi-layer stacked memory chips of the present invention.

[0069] The multi-layer stacked memory chip packaging anomaly monitoring system 200 of this invention can be installed in an electronic device. Depending on the functions implemented, the multi-layer stacked memory chip packaging anomaly monitoring system may include a packaging stress analysis module 201, a monitoring periodicity table construction module 202, an electrical performance measurement module 203, and an anomaly monitoring module 204. The module described in this invention can also be referred to as a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and which are stored in the memory of the electronic device.

[0070] In this embodiment of the invention, the functions of each module / unit are as follows: The packaging stress analysis module 201 is used to collect the hot-press bonding temperature and bonding pressure values ​​of the chip in real time during the multi-layer stacked memory chip packaging process, and to determine the packaging process stress index of the chip using the hot-press bonding temperature and the bonding pressure values. The monitoring period table construction module 202 is used to query the cumulative duration of multiple processes and historical packaging failure information of the multi-layer stacked memory chip, analyze the packaging process deviation coefficient of the chip using the packaging process stress index and the cumulative duration of multiple processes, and construct the monitoring period table of the chip based on the packaging process deviation coefficient and the historical packaging failure information. The electrical performance measurement module 203 is used to measure the electrical characteristics of the through-silicon via structure of the chip based on the monitoring periodic table, and to determine the impedance amplitude and phase angle of the chip based on the measurement data of the electrical characteristics measurement. The anomaly monitoring module 204 is used to perform packaging anomaly monitoring on the multilayer stacked memory chip based on the impedance amplitude and the phase angle, and obtain an anomaly monitoring report of the chip.

[0071] In detail, the modules in the multi-layer stacked memory chip packaging anomaly monitoring system 200 described in this embodiment of the invention employ the same methods as described above during use. Figure 1 The method used is the same as the packaging anomaly monitoring method for multi-layer stacked memory chips described above, and can produce the same technical effect, so it will not be repeated here.

[0072] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0073] Finally, it should be noted that in the above embodiments, each embodiment can be combined with each other or independent. Deleting any one of them will not affect the technical implementation of other embodiments. The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for monitoring packaging anomalies in multilayer stacked memory chips, characterized in that, The method includes: During the multi-layer stacked memory chip packaging process, the hot-press bonding temperature and bonding pressure values ​​of the chip are collected in real time. The packaging process stress index of the chip is determined using the hot-press bonding temperature and the bonding pressure values. The cumulative duration of multiple processes and historical packaging failure information of the multi-layer stacked memory chip are queried. The packaging process deviation coefficient of the chip is analyzed using the packaging process stress index and the cumulative duration of multiple processes. Based on the packaging process deviation coefficient and the historical packaging failure information, a monitoring cycle table of the chip is constructed. Based on the monitoring periodic table, the electrical characteristics of the through-silicon via structure of the chip are measured, and the impedance amplitude and phase angle of the chip are determined based on the measurement data of the electrical characteristics. Based on the impedance amplitude and the phase angle, the packaging anomaly monitoring of the multilayer stacked memory chip is performed to obtain an anomaly monitoring report of the chip.

2. The method for monitoring packaging anomalies of multilayer stacked memory chips as described in claim 1, characterized in that, Based on the impedance magnitude and the phase angle, packaging anomaly monitoring is performed on the multilayer stacked memory chip to obtain an anomaly monitoring report, including: A reference parameter table is constructed for the packaging of the multi-layer stacked memory chip, and the reference parameter table includes reference impedance magnitude and reference phase angle; Based on the impedance amplitude and the phase angle, and in conjunction with the reference parameter table, the parameter deviation of the multilayer stacked memory chip during packaging is calculated. Based on the parameter deviation, calculate the comprehensive anomaly index of the multilayer stacked memory chip during packaging; Based on the aforementioned anomaly comprehensive index, analyze the packaging anomaly state during the packaging of the multi-layer stacked memory chip; An anomaly monitoring report for multi-layer stacked memory chips is constructed using the aforementioned packaging anomaly status.

3. The method for monitoring packaging anomalies in multilayer stacked memory chips as described in claim 2, characterized in that, Based on the aforementioned anomaly comprehensive index, the packaging anomaly state during the packaging of the multi-layer stacked memory chip is analyzed, including: The anomaly comprehensive index is used to analyze the anomaly level of the multi-layer stacked memory chip; Based on the anomaly level, typical failure mode characteristics of the multi-layer stacked memory chip are identified; By utilizing the characteristics of the typical failure modes, the abnormal packaging state during the packaging of the multi-layer stacked memory chip is determined.

4. The method for monitoring packaging anomalies of multi-layer stacked memory chips as described in claim 1, characterized in that, Based on the measurement data from the electrical characteristic measurements, the impedance magnitude and phase angle of the chip are determined, including: Using the measurement data, the response signal of the chip during electrical characteristic measurements is identified; Perform a Fast Fourier Transform on the response signal to obtain the electrical response spectrum; The real and imaginary parts of the current and voltage of the chip at various test frequency points are identified using the electrical response spectrum. The impedance amplitude of the chip is calculated based on the real part and the imaginary part. The phase angle of the chip is determined based on the ratio between the real part and the imaginary part.

5. The method for monitoring packaging anomalies of multilayer stacked memory chips as described in claim 1, characterized in that, Using the hot-press bonding temperature and the bonding pressure value, the packaging process stress index of the chip is determined, including: The packaging structure material parameters of the chip are queried, and a thermo-mechanical coupling model of the chip is constructed using the packaging structure material parameters; After using the thermo-press bonding temperature and the bonding pressure value as the boundary conditions of the thermo-mechanical coupling model, the instantaneous thermal stress and mechanical stress of the chip are calculated using the thermo-mechanical coupling model. Based on the instantaneous thermal stress and the mechanical stress, the cumulative stress value of the chip is calculated; Based on the accumulated stress value, the packaging process stress index of the chip is determined.

6. The method for monitoring packaging anomalies of multilayer stacked memory chips as described in claim 5, characterized in that, The calculation of the cumulative stress value of the chip based on the instantaneous thermal stress and the mechanical stress includes: The instantaneous thermal stress and the mechanical stress are transformed by stress tensor to obtain the instantaneous thermal stress tensor and the mechanical stress tensor; The instantaneous thermal stress tensor and the mechanical stress tensor are tensor synthesized to obtain the instantaneous equivalent stress; The cumulative stress value of the chip is calculated using the instantaneous equivalent stress.

7. The method for monitoring packaging anomalies of multilayer stacked memory chips as described in claim 1, characterized in that, Based on the packaging process deviation coefficient and the historical packaging failure information, a monitoring cycle table for the chip is constructed, including: Based on the historical packaging failure information, the historical failure rate corresponding to the packaging process deviation coefficient in different numerical ranges is calculated. Using the historical failure rate, a risk level mapping table for the chip is constructed; Based on the risk level mapping table and the packaging process deviation coefficient, the real-time risk level of different packaging structures of the chip is determined; Based on the real-time risk level, the monitoring frequency and monitoring area of ​​the chip under different packaging structures are constructed. Based on the monitoring frequency and the monitoring area, a monitoring cycle table for the chip is constructed.

8. The method for monitoring packaging anomalies of multilayer stacked memory chips as described in claim 1, characterized in that, Using the packaging process stress index and the cumulative time of the multi-process steps, the packaging process deviation coefficient of the chip is analyzed, including: Obtain the standard process stress range and standard process duration of the chip; The stress deviation of the chip is calculated using the packaging process stress index and the standard process stress range. The chip's time deviation is calculated using the standard process time and the cumulative time of the multiple processes. The stress deviation and the duration deviation are used as the packaging process deviation coefficients of the chip.

9. The method for monitoring packaging anomalies of multilayer stacked memory chips as described in claim 1, characterized in that, Based on the monitoring periodicity, the electrical characteristics of the through-silicon via (TSV) structure of the chip are measured, including: Identify the current monitoring frequency and key monitoring area set for the chip from the monitoring cycle table; Based on the monitoring frequency and the key monitoring area, configure the signal frequency and scanning path for the electrical testing equipment corresponding to the chip; Based on the signal frequency and the scanning path, the electrical characteristics of the through-silicon via (TSV) structure of the chip are measured using the electrical testing equipment.

10. A packaging anomaly monitoring system for multilayer stacked memory chips, characterized in that, The system includes: The packaging stress analysis module is used to collect the hot-press bonding temperature and bonding pressure values ​​of the chip in real time during the packaging process of multi-layer stacked memory chips, and to determine the packaging process stress index of the chip using the hot-press bonding temperature and the bonding pressure values. The monitoring cycle table construction module is used to query the cumulative duration of multiple processes and historical packaging failure information of the multi-layer stacked memory chip, analyze the packaging process deviation coefficient of the chip using the packaging process stress index and the cumulative duration of multiple processes, and construct the monitoring cycle table of the chip based on the packaging process deviation coefficient and the historical packaging failure information. An electrical performance measurement module is used to measure the electrical characteristics of the through-silicon via structure of the chip based on the monitoring periodic table, and to determine the impedance amplitude and phase angle of the chip based on the measurement data of the electrical characteristics measurement. An anomaly monitoring module is used to perform packaging anomaly monitoring on the multilayer stacked memory chip based on the impedance amplitude and the phase angle, and to obtain an anomaly monitoring report for the chip.

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