Architecture search method for quantum neural network, electronic device, chip, storage medium
Patent Information
- Application Number
- CN202610214453.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-13
- Publication Date
- 2026-06-05
AI Technical Summary
Existing quantum neural network architecture search methods suffer from poor task adaptability, insufficient multimodal support, and inadequate consideration of real hardware noise, resulting in low search efficiency and performance degradation.
An architecture search method based on reinforcement learning or evolutionary algorithms is adopted, which combines quantum gradient descent and hardware noise model to dynamically adjust quantum gate type and network structure, introduce quantum measurement error compensation mechanism, and optimize quantum neural network architecture.
A quantum neural network architecture search that automatically adapts to multi-task and multi-modal data was achieved, improving the stability and performance of the model in real hardware environments, reducing network complexity, and increasing search efficiency.
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Abstract
Description
Technical Field
[0001] This application relates to the technical fields of quantum computing, machine learning and artificial intelligence, and in particular to an architecture search method, electronic device, chip and storage medium for quantum neural networks. Background Technology
[0002] The combination of quantum computing and artificial intelligence is a cutting-edge research direction. Quantum neural networks, as the core carrier, rely heavily on their architectural design, including quantum gate type, number of layers, and qubit interconnection method. Traditionally, the architecture of Quantized Neural Networks (QNNs) has largely relied on manual design based on expert experience, a cumbersome process that struggles to achieve optimal results. Specifically, existing technologies suffer from the following technical shortcomings: Poor task adaptability: Its search strategy is relatively fixed, and the architecture lacks generalization ability and adaptability when facing different tasks such as image classification, speech recognition, and time series analysis. It often requires a lot of searching or design for each task. Insufficient multimodal support: It is mainly optimized for the quantum encoding of image data and lacks a flexible adaptation mechanism for the characteristics of other modal data such as text and speech. Insufficient consideration of real hardware noise: The search process is mostly carried out in ideal or low-noise simulators, without fully considering the noise such as decoherence and gate errors in real quantum hardware. This leads to a significant performance degradation of the searched architecture on real devices. Limited search efficiency and scalability: It relies on the specific encoding method of quantum chromosomes. When the architecture space is large, the search efficiency may be low, and the ability to dynamically adjust the macroscopic structure such as network depth and width is limited.
[0003] Therefore, there is an urgent need for a method that can automatically and efficiently search for the optimal quantum neural network architecture that is adaptable to multiple tasks and modes and is robust to quantum hardware noise. Summary of the Invention
[0004] This application provides a method, apparatus, electronic device, chip, storage medium, and program product for quantum neural network architecture search, which can automatically generate high-performance, low-complexity, and noise-resistant QNN architectures for a given task, thereby overcoming the technical problems of existing technologies such as strong reliance on manual design, ignoring hardware noise, and low search efficiency.
[0005] The technical solution of this application embodiment is implemented as follows: This application provides an architecture search method for quantum neural networks, the method comprising: In response to receiving a quantum artificial intelligence task type, a corresponding task objective function is constructed based on the task type; the task objective function is used to characterize the performance index of the quantum neural network under the task. Configure an optional set of quantum gates; the optional set of quantum gates includes at least two different types of single-qubit gates or two-qubit gates, and configure a parameterized representation for each candidate quantum gate; Based on reinforcement learning strategies or evolutionary algorithms, multiple candidate quantum neural network architectures are iteratively generated in a search space consisting of the number of qubits, the number of network layers, and the type and order of quantum gates used in each layer. The parameters of the candidate quantum neural network architecture are trained using the quantum gradient descent method or the quantum natural gradient descent method. A pre-set hardware noise model is introduced during the training process to simulate the decoherence AND gate operation error in real quantum devices. During the inference stage, a quantum measurement error compensation mechanism is applied to the measurement results to correct the output deviation caused by readout errors. Based on the output results after noise modeling and error compensation, the performance score of the candidate quantum neural network architecture under the objective function of the task is calculated; according to the performance score and complexity constraints of each candidate quantum neural network architecture, the candidate architecture set is pruned and optimized, and the architecture that meets the preset performance threshold and has a complexity lower than the upper limit is retained as the optimal quantum neural network architecture output.
[0006] In some implementations, the task type includes one or more of image classification, speech recognition, time series prediction, or quantum reinforcement learning, and the objective function of the task accordingly includes classification accuracy, speech transcription WER metric, prediction mean square error, or cumulative reward value.
[0007] In some implementations, the set of optional quantum gates includes one or more of the Pauli-X gate, Pauli-Y gate, Hadamard gate, quantum circuit controlled reverse gate (CNOT) gate, and RZ(θ) rotation gate, wherein the parameter θ of the parameterized quantum gate participates in the optimization as a learnable variable during the architecture search process.
[0008] In some implementations, the reinforcement learning policy includes a policy network π(a|s), where state s represents the current number of network layers and qubit occupancy, and action a includes adding a new layer, selecting a specific quantum gate type, and adjusting the number of qubits; the policy network is updated by maximizing the expected performance score.
[0009] In some implementations, the hardware noise model includes an amplitude-damped channel, a phase-damped channel, or a universal Pauli noise channel, used to apply noise operators to the density matrix evolution of the quantum circuit during the training simulation phase.
[0010] In some implementations, the quantum measurement error compensation mechanism is based on a pre-calibrated confusion matrix M, which post-processes the original measurement frequency vector p to obtain a corrected probability distribution. =M- ¹p, where the element M_{ij} of M represents the probability that the true state is j and is misread as i.
[0011] In some implementations, the complexity constraint Determined by the following formula: ; in, As a candidate quantum neural network architecture, For the number of qubits, The total number of subgates, For the number of network layers, This represents the total number of trainable parameters. Preset weight coefficients; pruning operations remove branches that satisfy... Or an architecture with a performance score below the threshold; This is the preset upper limit threshold for architectural complexity.
[0012] The architecture search device for quantum neural networks provided in this application includes: A construction unit is configured to, in response to receiving a quantum artificial intelligence task type, construct a corresponding task objective function based on the task type; the task objective function is used to characterize the performance index of the quantum neural network under the task. A configuration unit is used to configure an optional set of quantum gates; the optional set of quantum gates includes at least two different types of single-qubit gates or two-qubit gates, and a parameterized representation is configured for each candidate quantum gate; The generation unit is used to iteratively generate multiple candidate quantum neural network architectures based on reinforcement learning strategies or evolutionary algorithms in a search space consisting of the number of qubits, the number of network layers, and the type and order of quantum gates used in each layer. The training unit is used to train the parameters of the candidate quantum neural network architecture using quantum gradient descent or quantum natural gradient descent. A preset hardware noise model is introduced during the training process to simulate the decoherence AND gate operation error in real quantum devices. During the inference stage, a quantum measurement error compensation mechanism is applied to the measurement results to correct the output deviation caused by readout errors. An optimized output unit is used to calculate the performance score of candidate quantum neural network architectures under the objective function of the task based on the output results after noise modeling and error compensation. According to the performance score and complexity constraints of each candidate quantum neural network architecture, the candidate architecture set is pruned and optimized, and the architectures that meet the preset performance threshold and whose complexity is lower than the upper limit are retained as the optimal quantum neural network architecture output.
[0013] The electronic device provided in this application includes a processor and a memory. The memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute the above-described architecture search method for quantum neural networks.
[0014] The chip provided in this application includes a processor for calling and running a computer program from a memory, causing a device equipped with the chip to execute the above-described architecture search method for quantum neural networks.
[0015] The computer-readable storage medium provided in this application embodiment is used to store a computer program that causes a computer to execute the above-described architecture search method for quantum neural networks.
[0016] The computer program product provided in this application includes computer program instructions that cause a computer to execute the above-described architecture search method for quantum neural networks.
[0017] The embodiments of this application have the following beneficial effects: By dynamically adjusting the objective function and architecture search strategy, it can automatically adapt to various quantum AI tasks such as image classification, speech recognition, and time series analysis without extensive architecture redesign, thus improving its scalability; it provides flexible architecture search paths and quantum gate combination schemes for different types of data, effectively processing multimodal data such as images, text, speech, and time series, expanding the application scenarios of quantum neural networks; by introducing hardware noise model constraints and quantum error correction methods, the pruning process prioritizes the preservation of noise-resistant structures, improving the stability and reliability of the model in real quantum hardware environments; a quantum measurement error compensation mechanism is designed, using historical data modeling and linear compensation to correct parameter updates, ensuring the accuracy of quantum measurement data and improving model performance; by adopting flexible quantum gate combinations and layer selection methods, combined with reinforcement learning / evolutionary algorithms and pruning techniques, the network complexity is significantly reduced, the architecture search and inference efficiency is improved, and the parallel advantages of quantum computing are fully utilized. Attached Figure Description
[0018] Figure 1 This is a flowchart illustrating the architecture search method for quantum neural networks provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating the implementation process of the architecture search method for quantum neural networks provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structural composition of the architecture search device for quantum neural networks provided in an embodiment of this application; Figure 4 This is a schematic structural diagram of an electronic device provided in an embodiment of this application; Figure 5 This is a schematic structural diagram of the chip according to an embodiment of this application. Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of the embodiments of this application.
[0020] Figure 1 This is a flowchart illustrating the architecture search method for quantum neural networks provided in an embodiment of this application, as shown below. Figure 1 As shown, the architecture search method for quantum neural networks in this application embodiment specifically includes the following processing steps: Step 101: In response to receiving the quantum artificial intelligence task type, construct the corresponding task objective function based on the task type.
[0021] In this embodiment, the task objective function is used to characterize the performance index of the quantum neural network under the task. The aforementioned task types include one or more of image classification, speech recognition, time series prediction, or quantum reinforcement learning. Correspondingly, the task objective function includes classification accuracy, word error rate (WER), prediction mean square error, or cumulative reward value.
[0022] Users can input the task type via API or graphical interface, such as "MNIST handwritten digit classification". The processing system automatically selects the corresponding objective function based on the task type: for image / text classification tasks, the objective function is to maximize the validation set accuracy; for speech recognition tasks, the objective function is to minimize the word error rate (WER); for time series prediction, the objective function is to minimize the mean squared error (MSE); and for quantum reinforcement learning, the objective function is to maximize the cumulative discounted reward.
[0023] Step 102: Configure the optional set of quantum gates.
[0024] The optional quantum gate set in this application includes at least two different types of single-qubit gates or two-qubit gates, and a parameterized representation is configured for each candidate quantum gate. Specifically, the optional quantum gate set includes one or more of the following: Pauli-X gate, Pauli-Y gate, Hadamard gate, controlled-NOT gate (CNOT) gate, and phase-transformation RZ(θ) rotation gate, wherein the parameter θ of the parameterized quantum gate participates in the optimization as a learnable variable during the architecture search process.
[0025] This application embodiment pre-configures a set of selectable quantum gates. ,in, (Hadamard Gate) , It is a fixed single-bit gate; For parametric revolving doors, These are learnable parameters; , (Cirac-Zoller) is a two-qubit entanglement gate architecture. Each layer of the architecture consists of several gate operation modules, each specifying the qubit index and gate type to be used. As one implementation, the maximum allowed number of layers is defined as 5, and the maximum number of qubits used is 4. The action space for architecture search includes adding a gate from the set of quantum gates to a specific layer and a specific qubit.
[0026] Step 103: Based on reinforcement learning strategies or evolutionary algorithms, multiple candidate quantum neural network architectures are iteratively generated in a search space consisting of the number of qubits, the number of network layers, and the type and order of quantum gates used in each layer.
[0027] In this embodiment of the application, the reinforcement learning strategy includes a policy network π(a|s), where the state s represents the number of network layers and the qubit occupancy status, and the action a includes adding a new layer, selecting a specific quantum gate type, and adjusting the number of qubits; the policy network is updated by maximizing the expected performance score.
[0028] This application employs one of two optional search strategies to iteratively generate multiple candidate quantum neural network architectures: Reinforcement learning strategy: state Number of layers currently constructed Used qubit set ; action Select new door type Target bits Whether to terminate; Policy Network This is a two-layer Long Short-Term Memory (LSTM) network, updated using the REINFORCE algorithm, with the reward being the architecture performance score. The core of the REINFORCE algorithm lies in directly optimizing the policy parameters using gradient ascent, with the goal of maximizing the expected reward of the policy. in: It is a strategy The parameter represents the state. Select action The probability of. It is a discount factor used to balance immediate rewards with future rewards. In time step The reward obtained. The algorithm samples multiple trajectories (episodes) and calculates the cumulative reward for each trajectory. The reward is then used as an unbiased estimate to update the policy parameters.
[0029] Evolutionary algorithm strategy: The initial population contains 20 random architectures; mutation operations include: replacing a gate, adding or removing layers, and changing the number of qubits; crossover operations swap parts of the layer structure of two parents; the top-10 individuals in each generation are retained to enter the next generation.
[0030] Step 104: Train the parameters of the candidate quantum neural network architecture using quantum gradient descent or quantum natural gradient descent; introduce a preset hardware noise model during the training process to simulate the decoherence AND gate operation error in real quantum devices; apply a quantum measurement error compensation mechanism to the measurement results during the inference stage to correct the output deviation caused by readout errors.
[0031] In this embodiment, the hardware noise model includes an amplitude-damped channel, a phase-damped channel, or a universal Pauli noise channel, which is used to apply noise operators to the density matrix evolution of the quantum circuit during the training simulation phase.
[0032] For each candidate architecture Performing a noisy assessment includes the following processing steps: Optimize parameters using Quantum Natural Gradient Descent (QNG) : ; in, For the quantum Fisher information matrix, For learning rate, For about The gradient operator is used for the loss function. Regarding parameter vectors The gradient vector is composed of the partial derivatives. θ Ltask is the loss gradient.
[0033] In each quantum circuit simulation, a noise channel is inserted after each quantum gate: After a single-bit gate: Amplitude damping ( Phase damping ( ); After the two-bit gate: additional Pauli-X / Y / Z errors are added, each with a probability of 0.005; Noise propagation is simulated using density matrix simulation.
[0034] Step 105: Based on the output results after noise modeling and error compensation, calculate the performance score of the candidate quantum neural network architecture under the task objective function; according to the performance score and complexity constraints of each candidate quantum neural network architecture, perform pruning optimization on the candidate architecture set, and retain the architecture that meets the preset performance threshold and has a complexity lower than the upper limit as the optimal quantum neural network architecture output.
[0035] In this embodiment of the application, complexity constraints Determined by the following formula: ; in, As a candidate quantum neural network architecture, The number of qubits The total number of subgates, For network layers, This represents the total number of trainable parameters. Preset weight coefficients; pruning operations remove branches that satisfy... Or an architecture with a performance score below the threshold; This is the preset upper limit threshold for architectural complexity.
[0036] During the inference phase, 1000 measurements are performed to obtain the original frequency vector. The confusion matrix was obtained in advance through calibration experiments. ,in .
[0037] Calculate the corrected distribution : ; This is the original measurement frequency vector. The inverse of the confusion matrix; if If singular, then use pseudo-inverse. Or Tikhonov regularization.
[0038] Will Input the task objective function to obtain the score. .
[0039] Calculate the overall complexity constraints for each architecture: ; As an example, the default weight settings are: This is to reflect the fact that qubits are the most expensive.
[0040] set up (The upper limit of a typical NISQ device with 6 qubits, 50 gates, 10 layers, and 20 parameters).
[0041] Perform the following pruning operations: like If so, then remove; like If the accuracy rate is less than 60%, then remove it.
[0042] The remaining architecture is retained for the next round of search or used as the final output.
[0043] The following specific examples further illustrate the essence of the technical solutions in the embodiments of this application.
[0044] Figure 2 This is a schematic diagram illustrating the implementation flow of the architecture search method for quantum neural networks provided in this application embodiment, as shown below. Figure 2 As shown, the technical solution of this application embodiment designs the optimal quantum neural network architecture for different quantum artificial intelligence tasks. Different tasks have different requirements for quantum neural networks, such as quantum gate type, number of quantum layers, and number of qubits. Through a search algorithm, the most suitable quantum neural network architecture for a specific task can be automatically generated, thereby improving the performance and training efficiency of quantum AI models and solving the problems of time-consuming and inefficient manual architecture design in the prior art. This method, through effective search and optimization of quantum neural network architectures, is applicable to a variety of quantum AI tasks, including but not limited to quantum classification, quantum regression, and quantum reinforcement learning.
[0045] like Figure 2 As shown, it includes the following processing steps: Step 201: Model the quantum AI problem given by the user.
[0046] Step 202: Quantum gate selection and representation.
[0047] Step 203: Quantum gate architecture search.
[0048] Step 204: Architecture search evaluation.
[0049] Step 205: Architecture optimization and pruning.
[0050] The specific steps are described below: First, the user's requirement is to use a quantum AI model to construct a task objective function based on a given quantum AI task. ,in This represents the set of parameters of a quantum neural network. For different tasks, the objective function can be expressed as classification accuracy, regression error, or the reward value from reinforcement learning. The objective function has the following form: ; in, Represents the quantum neural network architecture, This represents a set of possible quantum network architectures.
[0051] To adapt to different quantum AI tasks, various quantum gates need to be set in the quantum neural network architecture, such as 、 、 Y、 etc. Through a set of discrete variables To represent the choice of quantum gate, where Each quantum gate is represented by a parameter matrix, such as... The matrix form is as follows: ; Architecture search will explore different combinations of quantum gates used in each layer.
[0052] Search for the optimal architecture based on reinforcement learning or evolutionary algorithms. Let... Indicates the current state of the architecture. The action to be performed (such as selecting a quantum gate or adding a layer to a network) is represented by a policy. Alternatively, a genetic algorithm can be used to determine the next action and update the architecture. The result of each search is stored as a candidate architecture, and its performance score is calculated using the following formula. :
[0053] The process iterates until the optimal architecture that meets the task performance requirements is found.
[0054] For each architecture found A quantum neural network was constructed and trained, with the parameters of the quantum neural network updated using quantum gradient descent (QGD) during the training process. The update formula for quantum gradient descent is: ; in, For learning rate, This is the gradient relative to the parameters of the quantum neural network. For networks with a large number of qubits, Natural Gradient Descent (QNG) is used for optimization to accelerate training. The loss function of the computational architecture is also discussed. Used to evaluate the architecture obtained from the search.
[0055] After obtaining multiple candidate architectures through an architecture search algorithm, architecture pruning techniques are applied to remove redundant quantum gates, excessively numerous layers, or redundant qubits. The pruned architecture is shown below. The following conditions must be met: ; in, Indicates the complexity of the architecture. This is a preset performance threshold. After pruning, the architecture performance is retrained and evaluated to ensure it meets the task requirements.
[0056] Taking a quantum neural network suitable for quantum classification tasks as an example, the performance of the quantum neural network is optimized using the architecture search algorithm involved in the embodiments of this application. Assume the task is to perform binary classification on a quantum dataset, and the goal is to maximize the classification accuracy. The specific process is as follows: First, the problem is modeled as an optimization problem, with the goal of finding the optimal quantum neural network architecture. To maximize classification accuracy. Assume... Given architecture Classification accuracy These are network parameters.
[0057] The problem model is defined as follows:
[0058] in, The target of architecture search is to cover the network's architecture, the choice of quantum gates, and the number of qubits.
[0059] Define the set of quantum gates that can be selected in the network, assuming that there are and Gates. Each quantum gate is represented as follows: ; ; ; By combining these quantum gates, it is possible to construct quantum neural networks with different architectures.
[0060] Architecture search employs a reinforcement learning strategy to select quantum gates, the number of layers, and the number of qubits. Each search step involves selecting the type and number of quantum gates for a given layer and designing the architecture of the next layer based on the output of the previous layer.
[0061] Let the current network state be The strategy selects the quantum gate and number of the current layer as the action. The strategy iteration formula is: ; By continuously searching different architectures, the classification accuracy of each architecture is calculated. : ; here, In the architecture The performance of the trained quantum neural network.
[0062] For each found architecture, the network parameters are updated using quantum gradient descent. To minimize the loss function The loss function could be cross-entropy loss. For binary classification tasks, the cross-entropy loss function is: ; Using the quantum-available gradient descent algorithm, the formula for updating the parameters is: ; in, The total number of training samples, For the first The true label of each sample For the model to the first The probability that a sample is predicted to be of the positive class. It's the learning rate. It is the gradient of the loss function.
[0063] After identifying multiple candidate architectures, architecture pruning techniques are applied to reduce network complexity. Pruning removes redundant quantum gates and unnecessary quantum layers while maintaining classification accuracy within an acceptable range.
[0064] Optimize architectural complexity using the following formula. : ; Architectural complexity Typically related to the number of qubits Quantum gate quantity Number of floors The number of parameters of a quantum gate One way to quantify complexity is to assign weights to each factor and use these weights to calculate the total complexity. The general formula for complexity can be expressed as: ; , , These are the weights of each factor, reflecting each factor's contribution to complexity. After pruning, the network is retrained and evaluated to ensure its performance meets task requirements.
[0065] Figure 3 This is a schematic diagram of the structural composition of the architecture search device for quantum neural networks provided in the embodiments of this application, as shown below. Figure 3 As shown, the architecture search device for quantum neural networks in this application embodiment includes: Construction unit 30 is configured to, in response to receiving a quantum artificial intelligence task type, construct a corresponding task objective function based on the task type; the task objective function is used to characterize the performance index of the quantum neural network under the task. Configuration unit 31 is used to configure an optional set of quantum gates; the optional set of quantum gates includes at least two different types of single-qubit gates or two-qubit gates, and configures a parameterized representation for each candidate quantum gate; The generation unit 32 is used to iteratively generate multiple candidate quantum neural network architectures in a search space consisting of the number of qubits, the number of network layers, and the type and order of quantum gates used in each layer, based on reinforcement learning strategies or evolutionary algorithms. Training unit 33 is used to train the parameters of candidate quantum neural network architecture using quantum gradient descent or quantum natural gradient descent. During the training process, a preset hardware noise model is introduced to simulate the decoherence AND gate operation error in real quantum devices. During the inference stage, a quantum measurement error compensation mechanism is applied to the measurement results to correct the output deviation caused by readout errors. The optimized output unit 34 is used to calculate the performance score of the candidate quantum neural network architecture under the objective function of the task based on the output results after noise modeling and error compensation; according to the performance score and complexity constraints of each candidate quantum neural network architecture, the candidate architecture set is pruned and optimized, and the architecture that meets the preset performance threshold and has a complexity lower than the upper limit is retained as the optimal quantum neural network architecture output.
[0066] In some implementations, the task type includes one or more of image classification, speech recognition, time series prediction, or quantum reinforcement learning, and the objective function of the task accordingly includes classification accuracy, speech transcription WER metric, prediction mean square error, or cumulative reward value.
[0067] In some implementations, the set of optional quantum gates includes one or more of the Pauli-X gate, Pauli-Y gate, Hadamard gate, quantum circuit controlled reverse gate (CNOT) gate, and RZ(θ) rotation gate, wherein the parameter θ of the parameterized quantum gate participates in the optimization as a learnable variable during the architecture search process.
[0068] In some implementations, the reinforcement learning policy includes a policy network π(a|s), where state s represents the current number of network layers and qubit occupancy, and action a includes adding a new layer, selecting a specific quantum gate type, and adjusting the number of qubits; the policy network is updated by maximizing the expected performance score.
[0069] In some implementations, the hardware noise model includes an amplitude-damped channel, a phase-damped channel, or a universal Pauli noise channel, used to apply noise operators to the density matrix evolution of the quantum circuit during the training simulation phase.
[0070] In some implementations, the quantum measurement error compensation mechanism is based on a pre-calibrated confusion matrix M, which post-processes the original measurement frequency vector p to obtain a corrected probability distribution. =M - ¹p, where the element M_{ij} of M represents the probability that the true state is j and is misread as i.
[0071] In some implementations, the complexity constraint Determined by the following formula: ; in, As a candidate quantum neural network architecture, For the number of qubits, The total number of subgates, For the number of network layers, This represents the total number of trainable parameters. Preset weight coefficients; pruning operations remove branches that satisfy... Or an architecture with a performance score below the threshold; This is the preset upper limit threshold for architectural complexity.
[0072] In an exemplary embodiment, each processing module in the architecture search device for quantum neural networks of this application embodiment may be implemented by one or more central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components.
[0073] Regarding the apparatus in the above embodiments, the specific manner in which each module and unit performs its operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.
[0074] Figure 4 This is a schematic structural diagram of an electronic device 400 provided in an embodiment of this application. The electronic device may be a personal computer or a server. Figure 4 The illustrated electronic device 400 includes a processor 410, which can call and run computer programs from memory to implement the methods in the embodiments of this application.
[0075] Optionally, such as Figure 4 As shown, the electronic device 400 may further include a memory 420. The processor 410 can retrieve and run computer programs from the memory 420 to implement the methods described in the embodiments of this application.
[0076] The memory 420 can be a separate device independent of the processor 410, or it can be integrated into the processor 410.
[0077] Optionally, such as Figure 4 As shown, the electronic device 400 may also include a transceiver 430, which the processor 410 can control to communicate with other devices. Specifically, it can send information or data to other devices or receive information or data sent by other devices.
[0078] The transceiver 430 may include a transmitter and a receiver. The transceiver 430 may further include an antenna, and the number of antennas may be one or more.
[0079] The electronic device 400 can implement the corresponding processes of the various methods in the embodiments of this application, which will not be described in detail here for the sake of brevity. That is to say, the electronic device in the embodiments of this application can be implemented as a server or as a client. For the sake of simplicity, they will not be presented separately. The main difference lies in the different methods corresponding to the programs they run, while their hardware structures are exactly the same.
[0080] Figure 5 This is a schematic structural diagram of the chip according to an embodiment of this application. Figure 5 The chip 500 shown includes a processor 510, which can call and run computer programs from memory to implement the methods in the embodiments of this application.
[0081] Optionally, such as Figure 5 As shown, chip 500 may further include memory 520. Processor 510 can retrieve and run computer programs from memory 520 to implement the methods described in this embodiment.
[0082] The memory 520 can be a separate device independent of the processor 510, or it can be integrated into the processor 510.
[0083] Optionally, the chip 500 may also include an input interface 530. The processor 510 can control the input interface 530 to communicate with other devices or chips; specifically, it can acquire information or data sent by other devices or chips.
[0084] Optionally, the chip 500 may also include an output interface 540. The processor 510 can control the output interface 540 to communicate with other devices or chips, specifically, to output information or data to other devices or chips.
[0085] The chip can implement the corresponding processes of the various methods in the embodiments of this application, which will not be described in detail here for the sake of brevity.
[0086] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.
[0087] It should be understood that the processor in the embodiments of this application may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. The functionality of a chip can be implemented using different processing methods depending on the program running in its memory.
[0088] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.
[0089] It should be understood that the above-described memory is exemplary and not a limiting description. For example, the memory in the embodiments of this application may also be static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DR RAM), etc. That is to say, the memory in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.
[0090] This application also provides a computer-readable storage medium for storing a computer program. This computer program causes a computer to execute the corresponding processes implemented by the various methods of this application embodiment; for brevity, these will not be elaborated upon here.
[0091] This application also provides a computer program product, including computer program instructions. These computer program instructions cause a computer to execute the corresponding processes implemented by the various methods of this application embodiment; for brevity, they will not be described in detail here.
[0092] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0093] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0094] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0095] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0096] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0097] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0098] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A method for architecture search in quantum neural networks, characterized in that, The method includes: In response to receiving a quantum artificial intelligence task type, a corresponding task objective function is constructed based on the task type; the task objective function is used to characterize the performance index of the quantum neural network under the task. Configure an optional set of quantum gates; the optional set of quantum gates includes at least two different types of single-qubit gates or two-qubit gates, and configure a parameterized representation for each candidate quantum gate; Based on reinforcement learning strategies or evolutionary algorithms, multiple candidate quantum neural network architectures are iteratively generated in a search space consisting of the number of qubits, the number of network layers, and the type and order of quantum gates used in each layer. The parameters of the candidate quantum neural network architecture are trained using the quantum gradient descent method or the quantum natural gradient descent method. A pre-set hardware noise model is introduced during the training process to simulate the decoherence AND gate operation error in real quantum devices. During the inference stage, a quantum measurement error compensation mechanism is applied to the measurement results to correct the output deviation caused by readout errors. Based on the output results after noise modeling and error compensation, the performance score of the candidate quantum neural network architecture under the objective function of the task is calculated; according to the performance score and complexity constraints of each candidate quantum neural network architecture, the candidate architecture set is pruned and optimized, and the architecture that meets the preset performance threshold and has a complexity lower than the upper limit is retained as the optimal quantum neural network architecture output.
2. The method according to claim 1, characterized in that, The task type includes one or more of image classification, speech recognition, time series prediction, or quantum reinforcement learning, and the objective function of the task accordingly includes classification accuracy, speech transcription WER index, prediction mean square error, or cumulative reward value.
3. The method according to claim 1, characterized in that, The set of optional quantum gates includes one or more of the following: Pauli-X gate, Pauli-Y gate, Hadamard gate, quantum circuit controlled reverse gate (CNOT) gate, and RZ(θ) rotating gate. The parameter θ of the parameterized quantum gate participates in the optimization as a learnable variable during the architecture search process.
4. The method according to claim 1, characterized in that, The reinforcement learning strategy includes a policy network π(a|s), where state s represents the current number of network layers and qubit occupancy, and action a includes adding a new layer, selecting a specific quantum gate type, and adjusting the number of qubits; the policy network is updated by maximizing the expected performance score.
5. The method according to claim 1, characterized in that, The hardware noise model includes an amplitude-damped channel, a phase-damped channel, or a general Pauli noise channel, which is used to apply noise operators to the density matrix evolution of the quantum circuit during the training and simulation phase.
6. The method according to claim 1, characterized in that, The quantum measurement error compensation mechanism is based on a pre-calibrated confusion matrix M. It performs post-processing on the original measurement frequency vector p to obtain the corrected probability distribution. =M - ¹p, where the element M_{ij} of M represents the probability that the true state is j and is misread as i.
7. The method according to claim 1, characterized in that, The complexity constraints Determined by the following formula: ； in, As a candidate quantum neural network architecture, The number of qubits The total number of subgates, For network layers, This represents the total number of trainable parameters. Preset weight coefficients; pruning operations remove branches that satisfy... Or an architecture with a performance score below the threshold; This is the preset upper limit threshold for architectural complexity.
8. An electronic device, characterized in that, include: A processor and a memory for storing a computer program, the processor for calling and running the computer program stored in the memory to perform the architecture search method for a quantum neural network as described in any one of claims 1 to 7.
9. A chip, comprising: A processor for retrieving and running a computer program from memory, causing a device with the chip mounted to perform the architecture search method for a quantum neural network as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, Used to store a computer program that causes a computer to perform the architecture search method for quantum neural networks as described in any one of claims 1 to 7.