Wafer map detection method, detection device and computer readable storage medium

Abstract

The wafer map detection method, detection device and computer readable storage medium of the present disclosure comprise: obtaining an original wafer map to be detected with multiple chip maps and corresponding chip quality information; obtaining multiple non-overlapping map edge parts of each offset wafer map to be detected by offsetting the original wafer map to be detected in multiple directions evenly divided according to a circumferential angle by at least one chip pitch; obtaining chip unqualified statistical information of each map edge part, and determining whether the chip unqualified statistical information of each map edge part meets a preset abnormal condition to obtain at least one abnormal map edge part whose chip unqualified statistical information meets the preset abnormal condition; and determining whether the original wafer map to be detected is offset based on the distribution asymmetry judgment of at least one abnormal map edge part on the circumferential angle. The present disclosure does not depend on the identification of chips and is beneficial to improve the wafer map offset detection accuracy.

Description

Technical Field

[0001] This disclosure relates to the field of wafer map inspection technology, and in particular to wafer map inspection methods, inspection devices and computer-readable storage media. Background Technology

[0002] In the semiconductor manufacturing process, wafer testing is a critical step in ensuring chip quality. During testing, the testing machine performs electrical tests on each chip on the wafer according to preset coordinates, and records the test classification code (Bin value) that indicates whether the chip is qualified or unqualified on the wafer map. The wafer map contains the coordinate location information of each chip and its corresponding test classification code. Subsequently, the wafer packaging plant can use this wafer map to screen good chips, sending qualified chips to the packaging process and rejecting unqualified chips.

[0003] However, in actual testing, due to mechanical positioning errors, vacuum adsorption deviations, or misalignment of the probe cards on the testing machine with multiple probes, the coordinate mapping between the physical wafer and the probe cards of the testing machine may shift. When the coordinate mapping shifts, the chip coordinate positions recorded in the wafer map are misaligned with the chip coordinate positions on the physical wafer. This causes subsequent packaging plants to use an incorrect wafer map (i.e., an offset wafer map) for good product screening, potentially misclassifying defective products as good and allowing them to enter subsequent processes, or misjudging good products as defective and discarding them, resulting in serious quality risks and cost losses.

[0004] In related technologies, the main methods for detecting whether a wafer map has shifted include the following:

[0005] The first method involves pre-setting a marker chip (Mark chip) or a bare chip on the wafer, and then comparing the physical marker position with the marker position on the wafer map to determine if there has been a misalignment. However, this method relies on reserving marker positions during the wafer design phase, and most wafer products do not have such markers, limiting its applicability.

[0006] The second method calculates the yield of the map's edge regions and compares whether the yield of the map edge areas exceeds a preset range to determine the offset. Although this method does not rely on the marker chip, it cannot distinguish between wafer map offset and edge anomalies caused by process defects by judging solely by yield. For wafers with inherently low yields or unevenly distributed edge defects, it is prone to misjudgment.

[0007] Therefore, there is an urgent need for a detection method that does not rely on an identification chip and is conducive to improving the accuracy of wafer map offset detection. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this disclosure is to provide a wafer map detection method, detection device and computer-readable storage medium that do not rely on the identification chip and are conducive to improving the accuracy of wafer map offset detection.

[0009] This disclosure provides a wafer map inspection method, comprising the following inspection process: acquiring an original wafer map to be tested having multiple chip maps and corresponding chip quality information; the chip quality information including qualified or unqualified; acquiring at least one abnormal map edge portion that simulates offsetting the original wafer map to be tested along multiple directions evenly divided by circumferential angles by a preset length to obtain chip unqualified statistical information that meets preset abnormal conditions; and determining whether the original wafer map to be tested has been offset based on the asymmetry of the distribution of at least one of the abnormal map edge portions at the circumferential angles.

[0010] According to some embodiments provided in this disclosure, the detection process further includes: determining that the wafer corresponding to the original wafer map to be tested has processing defects based on the symmetrical distribution of multiple map edge portions at the circumferential corners.

[0011] According to some embodiments provided in this disclosure, the preset abnormal condition is implemented as follows: the proportion of defective chips in the edge portion of the map is greater than a preset threshold.

[0012] According to some embodiments provided in this disclosure, the preset threshold is the optimal threshold, which is determined by the following steps: obtaining a sample set, which includes multiple offset wafer map samples, multiple non-offset wafer map samples without processing defects, and multiple wafer map samples with processing defects; obtaining the offset detection results of the sample set under each alternative threshold; determining the detection performance corresponding to each threshold based on the comparison between the offset detection results and the actual situation of the sample set; and determining the threshold with the optimal detection performance as the preset threshold.

[0013] According to some embodiments provided in this disclosure, when the detection performance is optimal, the harmonic mean score of the recall and precision of the sample set detection is the highest.

[0014] According to some embodiments provided in this disclosure, chips with reserved marks in the wafer map to be tested are not included in the statistics of the offset and the non-compliance statistics.

[0015] According to some embodiments provided in this disclosure, the method further includes: acquiring a test map having one or more original test wafer maps; segmenting the test map along at least one segmentation direction using at least one image segmentation algorithm to segment out independent original test wafer maps for detection.

[0016] According to some embodiments provided in this disclosure, the graph segmentation algorithm is multiple, including: a first graph segmentation algorithm for segmenting the original wafer map to be tested from the one or more grid-stitched patterns along a first segmentation direction; and a second graph segmentation algorithm for segmenting the original wafer map to be tested from the one or more grid-stitched patterns along a second segmentation direction intersecting the first segmentation direction; and / or

[0017] Before the segmentation, the wafer map data is preprocessed, including numerical format normalization and dictionary structuring.

[0018] This disclosure also provides a wafer map inspection apparatus, comprising: a processor and a memory; the memory storing program instructions; the processor being configured to run the program instructions to execute the wafer map inspection method as described in any of the above embodiments.

[0019] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the wafer map detection method described in any of the preceding claims.

[0020] Beneficial effects:

[0021] (1) The wafer map detection method, detection device and computer-readable storage medium disclosed herein do not rely on the identification chip and are conducive to improving the accuracy of wafer map offset detection.

[0022] (2) The wafer map detection method, detection device and computer-readable storage medium disclosed herein can effectively distinguish between wafer map offset and wafer processing defects, and avoid misjudging processing defects as offset.

[0023] (3) The wafer map detection method, detection device and computer-readable storage medium disclosed herein can support multiple map layout modes (single map, vertical multiple maps and horizontal side by side multiple maps), without the need for manual specification of the wafer map range, and have strong applicability. Attached Figure Description

[0024] Figure 1 This is a schematic flowchart of a wafer map detection method according to an embodiment of the present disclosure.

[0025] Figure 2 This is a schematic diagram of the process for obtaining the original map of the wafer under test according to an embodiment of this disclosure.

[0026] Figure 3 It is a schematic diagram of a wafer map containing two horizontally side-by-side grid patterns.

[0027] Figure 4 This is a schematic diagram illustrating the processing results of the gap voting detection algorithm on the wafer map data.

[0028] Figure 5 This is a schematic diagram comparing the map of the wafer under test after it has been shifted to the right with the original map of the wafer under test.

[0029] Figure 6 This is a schematic diagram of the threshold optimization process according to an embodiment of the present disclosure.

[0030] Figure 7 This is a schematic diagram of a wafer map inspection device according to an embodiment of the present disclosure.

[0031] Figure label:

[0032] Wafer map inspection device 100; bus 101; processor 102; memory 103; display 104. Detailed Implementation

[0033] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the information disclosed herein. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this disclosure can be modified or changed according to different viewpoints and application modules without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be combined with each other.

[0034] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement it. This disclosure may be embodied in many different forms and is not limited to the embodiments described herein.

[0035] In this disclosure, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic represented in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in any one or a group of embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples represented in this disclosure, as well as the features of those different embodiments or examples.

[0036] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this disclosure, "a set" means two or more, unless otherwise explicitly specified.

[0037] For the purpose of clarity, devices unrelated to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0038] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0039] While the terms first, second, etc., are used in some examples herein to refer to various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, module, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, modules, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0040] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the scope of this disclosure. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0041] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the message of the present disclosure, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0042] In related technologies, the main methods for detecting whether a wafer map has shifted include the following:

[0043] The first method involves pre-setting a marker chip (Mark chip) or a bare chip on the wafer, and then comparing the physical marker position with the marker position on the wafer map to determine if there has been a misalignment. However, this method relies on reserving marker positions during the wafer design phase, and most wafer products do not have such markers, limiting its applicability.

[0044] The second method calculates the yield of the map's edge regions and compares whether the yield of the map edge areas exceeds a preset range to determine the offset. Although this method does not rely on the marker chip, it cannot distinguish between wafer map offset and edge anomalies caused by process defects by judging solely by yield. For wafers with inherently low yields or unevenly distributed edge defects, it is prone to misjudgment.

[0045] In view of this, the present disclosure provides a detection method that does not rely on an identification chip and is beneficial to improving the accuracy of wafer map offset detection.

[0046] Figure 1 This is a schematic flowchart of the wafer map detection method according to an embodiment of this disclosure. (See attached diagram.) Figure 1 The wafer map detection method of this disclosure includes the following detection process:

[0047] S10: Obtain an original wafer map under test containing multiple chip diagrams and corresponding chip quality information; the chip quality information includes whether it is qualified or unqualified. That is, the original wafer map under test contains a chip diagram and chip quality information for each chip on the corresponding wafer. Specifically, the chip quality information is represented by a test classification code, i.e., a Bin value. Optionally, the Bin value can be represented by a universal hard Bin value (HBin) code. For example, an HBin value of 1 (HBin1) indicates that the chip quality is qualified, and HBin values ​​from 2 to 5 indicate various unqualified conditions of the chip quality. For example, an HBin value of 2 (HBin2) indicates that the chip is malfunctioning, an HBin value of 3 (HBin3) indicates that the chip parameters are faulty (voltage / current / timing deviation), an HBin value of 4 (HBin4) indicates that the chip is open-circuited, short-circuited, or structurally damaged, and an HBin value of 5 (HBin5) indicates that the chip has leakage current, etc. The Bin value can also be a four-digit soft Bin value (SBin) code defined by each packaging plant. For example, an SBin value of 1xxx.0 (i.e., S1xxx.0) represents a mainstream good product, an SBin value of 2xxx.0 (i.e., S2xxx.0) represents a short circuit defect, an SBin value of 3xxx.0 (i.e., S3xxx.0) represents a leakage defect, and an SBin value of 4xxx.0 (i.e., S4xxx.0) represents a functional defect. An SBin value of 6xxx (e.g., 6511.0) represents a downgraded substandard product. The Bin value can also be a combination of hard Bin value and soft Bin value, used to characterize the chip's quality status.

[0048] Figure 2 This is a schematic diagram of the process for obtaining the original map of the wafer under test. (See attached document.) Figure 2 Obtaining the original map of the wafer to be tested includes the following steps:

[0049] (1) Obtain wafer map data with one or more grid stitched graphics; wherein, the multiple cells contained in the grid stitched graphics correspond one-to-one with multiple chips of the wafer. Specifically, the obtained wafer map data exists in a grid table (Excel table), the grid table has one or more grid stitched graphics consistent with the shape of the wafer, wherein, the multiple cells contained in each grid stitched graphics correspond one-to-one with multiple chips of a wafer, and each cell has chip quality data (bin value and possible M mark value, # mark value) of the corresponding chip, a background color matching the chip quality data, and a row number and column number matching the coordinate position of the corresponding chip.

[0050] (2) The wafer map data is processed by at least one image segmentation algorithm to segment an independent grid pattern from the one or more grid stitching patterns along at least one segmentation direction, so as to serve as the original wafer map to be tested.

[0051] Optionally, the graph segmentation algorithm may be multiple, including a first graph segmentation algorithm and a second graph segmentation algorithm. The first graph segmentation algorithm is used to segment the original wafer map to be tested along a first segmentation direction. The second graph segmentation algorithm is used to segment the original wafer map to be tested along a second segmentation direction intersecting the first segmentation direction.

[0052] As an example, the first image segmentation algorithm is a column gap voting detection algorithm. Specifically, the wafer map data includes a schematic diagram of two horizontally side-by-side grid stitched graphics, as shown below. Figure 3 As shown in the diagram, the processing result of the column gap voting detection algorithm on the wafer map data is illustrated in the figure below. Figure 4 As shown, see reference Figure 3 and Figure 4 When processing the wafer map data, the column gap voting detection algorithm can analyze the column distribution of each row of cells in the grid table. For column positions without data in each row, it votes as "gap" and counts the gap voting rate of each column position (the proportion of rows judged as gaps to the total number of rows). When the gap voting rate of consecutive columns exceeds 40% and the gap width is not less than 2 columns, the region is segmented at the midpoint of the gap, thereby separating a grid stitched pattern from multiple horizontally side by side as the original wafer map to be tested.

[0053] As an example, the second image segmentation algorithm is a flood fill algorithm. A flood fill algorithm based on four-neighbor connectivity is used to identify connected regions, and the identification of a mesh patchwork pattern as a wafer map is determined based on whether the connected regions satisfy the circular feature condition of the wafer. Specifically, the circular feature condition is that the size of the connected region satisfies an aspect ratio > 0.5 and a fill rate between 0.4 and 0.95; if satisfied, the identified mesh patchwork pattern is determined to be a wafer map. Furthermore, for multiple vertically arranged wafer maps, since vertically adjacent mesh patchwork patterns are not connected, they are not included in the connected regions. Therefore, the flood fill algorithm can separate an independent mesh patchwork pattern from multiple vertically arranged mesh patchwork patterns to serve as the original wafer map to be tested. Simultaneously, when the flood fill algorithm is insensitive to the identification of multiple horizontally arranged mesh patchwork patterns, the column gap voting detection algorithm ensures that the original wafer map to be tested can also be separated from multiple horizontally arranged mesh patchwork patterns. Therefore, the graph segmentation algorithm based on the flood filling algorithm and the column gap voting detection algorithm can support multiple original map layout modes (single map, vertically parallel multiple maps, horizontally parallel multiple maps, or multiple maps in rows and columns), and can perform offset detection on multiple maps in both single map and multiple map modes. It does not require manual specification of the original map range and has strong applicability.

[0054] Optionally, before the segmentation, the wafer map data undergoes numerical format standardization and dictionary structuring to form dictionary-structured data that can be directly and accurately processed by the subsequent graph segmentation algorithm. This helps the subsequent graph segmentation algorithm to quickly segment without numerical format interference, and in the above process, the entire wafer map data is preloaded at once, avoiding repeated access and improving processing efficiency.

[0055] Optionally, the numerical format standardization process includes the following steps: traversing all cells of the grid mosaic graphic and performing numerical type standardization processing on each cell to uniformly convert the floating-point data values ​​contained in all cells into integer strings, for example, converting the Sbin value floating-point data 6511.0 into "6511".

[0056] Optionally, the dictionary structuring process includes the following steps: extracting the background color (by parsing the indexed color and RGB color of Excel) and font color of each cell to construct a unified dictionary-structured data based on the cells: {(row number, column number):(Bin value string, background color, font color)}.

[0057] S20: The simulation offsets the wafer map under test along multiple directions evenly divided by the circumference angle by a preset length to obtain multiple map edge portions of the wafer map under test that do not overlap with the original wafer map under test after each offset; wherein, the preset length is at least one chip pitch.

[0058] Therefore, after the original wafer map to be tested is offset in one direction by at least one chip pitch, the offset wafer map to be tested is compared with the original wafer map to be tested. Figure 5 This is a schematic diagram comparing the offset wafer map A" (shifted to the right) with the original wafer map A. (See attached diagram.) Figure 5 In the original test wafer map A, most of the chips are overlapped and the chips in the left edge area are exposed. Therefore, by comparison, the edge portion of the map at least one chip distance can be obtained.

[0059] Therefore, after the original wafer map to be tested is offset in multiple directions distributed along the circumference, multiple map edge portions of the original wafer map to be tested (or the offset wafer map to be tested) can be obtained along the circumference.

[0060] Optionally, the preset length is preferably one chip pitch. Thus, the map edge portion determined by offsetting and comparing to one chip pitch width can satisfy the requirement of determining the map edge portion of the original wafer under test, and requires less processing in subsequent calculations and statistics, thus improving processing efficiency. It is understood that the preset length in this disclosure includes, but is not limited to, this, and may also be two chip pitches, three chip pitches, etc., and can be adjusted adaptively.

[0061] As an example, taking four directions—upward, downward, leftward, and rightward—divided equally by the circumference angle, the simulation shifts the original wafer map to be tested by one chip spacing in each of the four directions. This yields the wafer maps after each shift. The simulation also identifies the non-overlapping portions of the original wafer map with each shifted wafer map, i.e., the exposed portions of the original wafer map relative to each shifted wafer map. This results in the lower edge, upper edge, right edge, and left edge of the original wafer map. Specifically, when the simulation shifts the wafer map upward, downward, leftward, and rightward, the coordinates (row number, column number) of all chips corresponding to the wafer map are transformed into row number minus 1, row number plus 1, column number minus 1, and column number plus 1, thereby achieving the shift of the wafer map by one chip spacing in each direction. Meanwhile, for the original wafer map under test, the coordinate set of all chips it contains is S_orig, and the coordinate set of all chips in the offset wafer map under test is S_shift. For each offset direction, the difference set D = S_orig - S_shift is calculated to obtain the set of chips that exist only in the original wafer map under test but not in the offset wafer map under test at the map edge, thus determining the map edge.

[0062] S30: Obtain chip defect statistics for each of the map edge portions, and determine whether the chip defect statistics for each of the map edge portions meet preset abnormal conditions, so as to obtain at least one abnormal map edge portion where the chip defect statistics meet the preset abnormal conditions. That is, statistically analyze the defective chip status of each of the map edge portions, and determine whether the offset and the determined map edges are abnormal based on whether the statistically analyzed defective chip status meets the preset abnormal conditions.

[0063] Specifically, the chip defect statistics can be determined by the proportion of chips belonging to a preset set of defective test classification codes in the edge region of the map. This preset set of defective test classification codes includes one bin value or a combination of bin values ​​used to characterize chip defection. In some examples, when the preset set of defective test classification codes only includes Hbin2, the proportion of chips with a bin value of 2 in the edge region of the map is counted. In other examples, when the preset set of defective test classification codes only includes Hbin2 and Hbin3, the proportion of first-category defective chips with a bin value of 2 and second-category defective chips with a bin value of 3 is counted. The total number of first-category and second-category defective chips is calculated, and the proportion of chips belonging to the Hbin2 and Hbin3 classification code sets is determined based on the ratio of this total number to the total number of chips contained in the edge region of the map.

[0064] Optionally, the preset abnormal condition is implemented as follows: the proportion of defective chips in the edge area of ​​the map is greater than a preset threshold. Specifically, when the preset set of defective test classification codes only includes Hbin2, the preset threshold can be 80%. It is also understood that when statistically analyzing the chip defect statistics, the preset threshold can be adjusted to different values ​​depending on the preset set of defective test classification codes.

[0065] In summary, to determine whether a map edge is an abnormal map edge, the following steps are taken: first, the number of all chips 'a' in the map edge is counted; then, the number of chips 'b' belonging to a preset set of unqualified Bin values ​​is counted, thereby determining the number of unqualified chips 'b' in the map edge; then, based on the number of all chips 'a' and the number of unqualified chips 'b' in the map edge, the proportion 'r' = b / a is determined; finally, based on whether the proportion 'r' is greater than a preset threshold, it is determined whether each map edge is abnormal.

[0066] S40: Based on the asymmetry of the distribution of at least one of the abnormal map edge portions at the circumferential corner, determine the offset detection result of whether the original wafer map to be tested has been offset.

[0067] Understandably, when a probe card with multiple probes makes electrical contact with the chips on a wafer to detect them, if the probe card is aligned with the wafer coordinates, the probes will land on each chip on the wafer to electrically test the quality of the chip, resulting in a normal wafer map. However, if there is a misalignment between the probe card and the wafer, some probes will land on blank areas outside the wafer when probing the wafer edge, resulting in a "hole-punch" phenomenon. The test data obtained from these blank areas form the edge portion of the offset wafer map, and when there is a hole-punch, the probe's chip quality test result is unqualified. Therefore, the edge portion of the offset wafer map will be abnormal, showing a higher proportion of unqualified chips (actually blank areas outside the wafer). Furthermore, given the unidirectional nature of the offset movement, the offset cannot occur in both opposite directions. For example, a probe card probe can only deflect downwards or upwards from the physical wafer; it cannot deflect both downwards and upwards simultaneously. Therefore, offset cannot cause both edges of the two relatively arranged maps in the wafer map to be abnormal. Thus, for the wafer map under test, only one map edge is abnormal, or multiple map edges are abnormal but all are asymmetrical, indicating an offset between the physical wafer and the probe card. Therefore, based on the asymmetrical distribution of at least one of the abnormal map edges at the circumferential corner, it is determined that the original wafer map under test has been offset; otherwise, the original wafer map under test has not been offset.

[0068] Specifically, for multiple map edge portions of the statistical information on unqualified chips, the determination of the original wafer map offset is as follows:

[0069] If there is only one abnormal map edge that meets the preset abnormal conditions, and this abnormal map edge cannot be symmetrically distributed on the circumference corner, thus satisfying the asymmetric distribution relationship, then the original wafer map to be tested will be shifted.

[0070] If there are two or more abnormal map edge portions that meet the preset abnormality conditions, and these two or more abnormal map edge portions are asymmetrically distributed, satisfying the distribution asymmetry requirement, then the original wafer map under test has shifted. Conversely, if the two or more abnormal map edge portions are symmetrically distributed, not satisfying the distribution asymmetry requirement, then the original wafer map under test has not shifted.

[0071] Therefore, based on the above steps, it is possible to determine whether the original wafer map under test has shifted. Compared with determining whether the wafer map has shifted by statistically analyzing the defective chips at the overall edge of the wafer map, this disclosure avoids the misjudgment of attributing the abnormalities of two relative map edges in the overall edge to wafer map shift, thus improving the accuracy of wafer shift detection.

[0072] Optionally, the wafer map detection method further includes: determining that the original wafer map to be tested is not offset and has no processing defects based on the absence of the abnormal map edge portions; and determining that the wafer corresponding to the original wafer map to be tested has processing defects based on the symmetrical distribution of multiple abnormal map edge portions at the circumferential corners. Therefore, this disclosure can detect the presence of processing defects in wafers, avoiding misjudging processing defects as wafer offsets.

[0073] As an example, let's consider offsetting the original wafer map under test by one chip spacing in each of the four directions: upward, downward, leftward, and rightward. This offset would expose the lower, upper, right, and left edges of the original wafer map relative to the offset wafer map. We would then determine whether the percentage of defective chips in each of these four edges exceeds 80%. Based on this percentage of defective chips at the four map edges, the offset of the original wafer map under test can be determined as follows:

[0074] If the proportion of defective chips in the four edge areas of the map does not exceed 80%, it is determined that the original test wafer map has not shifted and has no processing defects.

[0075] If the proportion of defective chips in the edge portion of the map exposed only in one direction exceeds 80%, then the original test wafer map is determined to have shifted in that direction. For example, if the proportion of defective chips in the upper edge portion of the test wafer map exposed only in the downward shift exceeds 80%, then the original test wafer map is determined to have shifted downward, meaning that during testing, the physical wafer is shifted downward relative to the probe card.

[0076] When the proportion of defective chips in both exposed map edge portions exceeding 80% in two directional offsets, and the two map edge portions are asymmetrical, it is determined that the original test wafer map has shifted along the midway between the two directions (e.g., the tilt direction between the x-axis and y-axis). Specifically, the two asymmetrical map edge portions can be the lower edge and right edge, the lower edge and left edge, the upper edge and right edge, or the upper edge and left edge.

[0077] When the proportion of defective chips in the two map edge portions exposed by two directional offsets both exceed 80%, and the two map edge portions are symmetrical, it is determined that the wafer corresponding to the original test wafer map has a processing defect.

[0078] If the proportion of defective chips in more than three or more map edge portions exposed by offset in three or more directions exceeds 80%, it is determined that the wafer corresponding to the original test wafer map has a processing defect.

[0079] Therefore, this disclosure can also detect wafer processing defects and wafer map integrity, making the detection more comprehensive.

[0080] Figure 6 This is a schematic diagram illustrating the threshold optimization process according to an embodiment of this disclosure. See also... Figure 6 The preset threshold is determined through the following steps:

[0081] (1) Obtain a sample set, which includes multiple offset wafer map samples, multiple non-offset wafer map samples without processing defects, and multiple wafer map samples with processing defects. For example, the sample set contains approximately 50 to 100 samples, and the ratio of the multiple offset wafer map samples, the multiple non-offset wafer map samples without processing defects, and the multiple wafer map samples with processing defects can be 1:1:1. It is understood that the number of samples is not limited to this and can be adjusted adaptively.

[0082] (2) Obtain the offset detection results of the sample set under each candidate threshold. Specifically, perform offset detection on the sample set multiple times using multiple candidate thresholds to obtain the offset detection results of the sample set under each candidate threshold. As an example, the multiple candidate thresholds can be obtained by equally dividing a preset threshold range, for example, equally dividing the range of 70% to 90%, and selecting 70%, 75%, 80%, 85%, and 90% as candidate thresholds respectively.

[0083] (3) Based on the comparison between the offset detection results and the actual situation of the sample set, determine the detection performance corresponding to each threshold.

[0084] (4) Determine the threshold with optimal detection performance as the preset threshold.

[0085] As an example, the sample set is detected five times at five alternative thresholds of 70%, 75%, 80%, 85%, and 90%. Based on a comparison of the offset detection results of the sample set in the five tests with the true situation of the sample set, the precision and recall rates at the five alternative thresholds are calculated. The harmonic mean index (F1 score) of precision-recall at the five alternative thresholds is then determined, and the threshold with the highest harmonic mean index is selected as the preset threshold. Specifically, after detection at all five alternative thresholds of 70%, 75%, 80%, 85%, and 90%, the F1 score of the detection process is highest when the threshold is 80%. Therefore, 80% is selected as the threshold for comparing the proportion of detections in this disclosed detection process.

[0086] It is understood that recall is used to characterize the complete detection capability of the target defect, while precision is used to characterize the reliability of the detection results. Both can comprehensively evaluate the detection effect from two different dimensions: missed detections and false detections. This disclosure selects the threshold corresponding to the maximum value of the harmonic mean of precision and recall as the preset threshold, which is the optimal threshold. The optimal threshold helps to avoid missed detections and false detections, and ensures the completeness and accuracy of the detection.

[0087] Optionally, chips with reserved marks in the wafer map are not included in the offset and the statistics of the non-conforming information are not included. Specifically, chips with reserved marks are known qualified chips / known non-conforming chips designated by the user, and the marks include at least one of the M mark and the # mark.

[0088] The simulations and statistics in this disclosure aim to determine the proportion of defective chips in the map edge region due to the offset of the physical wafer relative to the probe card. Including chips with reserved marks (especially when the chips with reserved marks are known to be defective) in the offset and statistics can introduce errors and interference, increase the computational and statistical workload, and affect efficiency. Therefore, excluding chips with reserved marks from the offset simulation and statistics helps to ensure the efficiency and accuracy of identifying abnormal map edges.

[0089] Specifically, taking a test map with an original test wafer map as an example, the test map is stored in a grid table. The grid table contains a colored grid pattern formed by stitching together 18444 cells, matching the shape of the wafer. When the graph segmentation algorithm segments and identifies whether the grid pattern is circular, 1443 cells with the "M" label participate in the graph segmentation algorithm's operation, contributing to the segmentation and identification of the original test wafer map. However, in the subsequent offset, only 17001 cells actually participate in the offset coordinate calculation. For example, let the coordinate set of the 17001 chips be denoted as S_orig, and the offset coordinate set of the 17001 chips be S_shift. The difference D = S_orig - S_shift is calculated to obtain the set of 54 edge chips corresponding to the edge region of the map.

[0090] Figure 7 This is a schematic diagram of a wafer mapping inspection apparatus according to an embodiment of the present disclosure. See also... Figure 7 The wafer map detection device 100 includes a bus 101, a processor 102, and a memory 103. The processor 102 and the memory 103 can communicate with each other via the bus 101. The memory 103 can store program instructions. The processor 102 implements the steps of the wafer map detection method in the previous embodiment by running the program instructions in the memory 103.

[0091] In some embodiments, bus 101 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, although only one thick line is used in the figure, this does not indicate that there is only one bus or one type of bus.

[0092] In some embodiments, processor 102 may be implemented as a central processing unit (CPU), microprocessor unit (MCU), system on chip (System on Chip), or field-programmable array (FPGA). Memory 103 may include volatile memory for temporary data storage during program execution, such as random access memory (RAM).

[0093] The memory 103 may also include non-volatile memory for data storage, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state disk (SSD).

[0094] Optionally, the wafer map inspection device 100 further includes a display 104. The display 104 is connected to the processor 102 and is used to display the inspection results processed by the processor 102.

[0095] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the wafer map detection method as described in any of the above examples. That is, the method steps in the above embodiments are implemented as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and subsequently stored in a local recording medium, downloaded via a network. Thus, the method represented herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA).

[0096] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the protection scope of this disclosure.

Claims

1. A method for detecting wafer maps, characterized in that, Includes the following steps: Obtain the original map of the wafer under test, which contains multiple chip images and corresponding chip quality information; The chip quality information includes whether it is qualified or unqualified; The simulation involves offsetting the original wafer map under test along multiple directions evenly divided by circumference by a preset length to obtain multiple map edge portions that do not overlap with the original wafer map under test after each offset; wherein, the preset length is at least one chip pitch. Obtain chip defect statistics for each of the map edge portions, and determine whether the chip defect statistics for each of the map edge portions meet preset anomaly conditions, so as to obtain at least one abnormal map edge portion where the chip defect statistics meet the preset anomaly conditions; and The offset detection result determines whether the original wafer map under test has shifted, based on the asymmetry of the distribution of at least one of the abnormal map edge portions at the circumferential corner.

2. The wafer map detection method according to claim 1, characterized in that, The detection process also includes: Based on the symmetrical distribution of multiple map edge portions at the circumference corners, it is determined that the wafer corresponding to the original test wafer map has processing defects.

3. The wafer map detection method according to claim 1, characterized in that, The preset abnormal condition is implemented as follows: the proportion of unqualified chips in the edge part of the map is greater than a preset threshold.

4. The wafer map detection method according to claim 3, characterized in that, The preset threshold is determined through the following steps: Obtain a sample set, which includes multiple offset wafer map samples, multiple non-offset wafer map samples without processing defects, and multiple wafer map samples with processing defects; The offset detection results of the sample set under each candidate threshold condition are obtained respectively; Based on the comparison between the offset detection results and the actual situation of the sample set, the detection performance corresponding to each threshold is determined; as well as The threshold that yields the best detection performance is determined as the preset threshold.

5. The wafer map detection method according to claim 4, characterized in that, When the detection performance is optimal, the harmonic mean score of the recall and precision of the sample set detection is the highest.

6. The wafer map detection method according to claim 1, characterized in that, Chips with reserved marks in the wafer map are not included in the statistics of offset and non-compliance information.

7. The wafer map detection method according to claim 1, characterized in that, Also includes: Acquire wafer map data having one or more grid stitched patterns; wherein, each of the grid stitched patterns contains multiple cells that correspond one-to-one with multiple chips of a wafer; The wafer map data is processed by at least one image segmentation algorithm to segment an independent grid pattern from one or more grid stitched patterns along at least one segmentation direction, which serves as the original wafer map to be tested.

8. The wafer map detection method according to claim 7, characterized in that, The graph segmentation algorithm comprises multiple algorithms, including: a first graph segmentation algorithm for segmenting the original wafer map to be tested from the one or more grid-stitched graphics along a first segmentation direction; and a second graph segmentation algorithm for segmenting the original wafer map to be tested from the one or more grid-stitched graphics along a second segmentation direction intersecting the first segmentation direction; and / or Before the segmentation, the wafer map data is preprocessed, including numerical format normalization and dictionary structuring.

9. A wafer map inspection device, characterized in that, include: Processor and memory; The memory stores program instructions; The processor is configured to run the program instructions to perform the wafer map detection method as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the wafer map detection method according to any one of claims 1 to 8.

Images