PCB CT image segmentation method and system based on element geometric feature enhancement and SAM model fine tuning

Abstract

The present application relates to the technical field of computer vision, and particularly relates to a PCB CT image segmentation method and system based on element geometric feature enhancement and SAM model fine-tuning, which inputs a to-be-segmented printed circuit board CT image into an image segmentation model, and uses the image segmentation model to predict and output an element segmentation mask in the printed circuit board CT image, wherein the image segmentation model comprises a pre-trained PCB adapter and a fine-tuned SAM model, and the SAM model comprises an image encoder, a prompt encoder and a lightweight mask decoder, and the PCB adapter comprises a feature extractor, an adaptive feature fusion gate unit and an output unit. On the basis of maintaining the original architecture of the SAM, a multi-direction PCB feature extractor is introduced, and the contribution degree of each feature is dynamically adjusted through the adaptive feature fusion gate, so that the global semantics and the local structure are effectively fused, the segmentation accuracy of each element such as a wire, a via and a pad is significantly improved, and excellent performance is achieved on difficult samples such as dense wiring and small structures.

Description

Technical Field

[0001] This invention relates to the field of computer vision technology, and in particular to a PCB CT image segmentation method and system based on element geometric feature enhancement and SAM model fine-tuning. Background Technology

[0002] As PCB manufacturing processes evolve towards higher precision, higher integration, and greater complexity, their production scale and application numbers continue to climb. This poses a serious challenge to traditional methods of PCB inspection and repair, highlighting the importance of non-destructive testing (NDT) based on computed tomography (CT). PCB functionality relies on the precise connections of elements such as conductors, vias, and pads; therefore, accurately extracting these elements is a core aspect of NDT. CT, as a NDT technique, can reconstruct the internal three-dimensional model of the PCB without damaging its structure, providing support for the inspection of critical elements. However, traditional NDT methods often focus on extracting shallow information such as color and texture, which is prone to missed or false detections when dealing with small, densely distributed elements, failing to meet practical needs.

[0003] In recent years, deep learning has demonstrated significant advantages in image segmentation tasks by mining high-level semantic information. Existing PCB element segmentation methods can be mainly divided into three categories: methods based on traditional image processing, methods based on deep learning, and methods based on attention mechanisms. Methods based on traditional image processing, such as edge detection and morphological operations, are computationally efficient but sensitive to noise and have poor adaptability; methods based on deep learning, such as U-Net and Mask R-CNN, can automatically learn features but require a large amount of labeled data; methods based on attention mechanisms, such as Vision Transformer, can capture long-range dependencies but have high computational complexity. However, these models often rely on large amounts of high-quality labeled data. Therefore, the "pre-training + fine-tuning" paradigm is widely adopted. This involves learning general features through self-supervised pre-training and then fine-tuning with a small amount of labeled data to achieve knowledge transfer, greatly alleviating the model's dependence on high-quality labeled data. However, these models are usually trained on closed datasets with similar data features, and their performance degrades significantly when applied to open environments with significantly different circuit structures and layouts. To improve generalization ability, researchers have begun to focus on large-scale segmentation models such as SAM, which possess powerful feature extraction and zero-shot transfer capabilities thanks to large-scale pre-training.

[0004] SAM achieves powerful zero-shot generalization through large-scale pre-training, but its general design leads to significant shortcomings in segmenting PCB-specific structures: First, SAM lacks specialized optimization for PCB-specific structures (such as slender conductors, circular vias, and square pads), making it difficult to effectively extract their geometric features; second, pre-trained SAM has limited perceptual ability when processing small or dense structures in PCB images; furthermore, existing adapter methods typically employ simple feature addition or concatenation, failing to fully consider the geometric characteristics of different PCB structures, resulting in insufficient feature fusion. Specifically, conductors have slender structural characteristics, requiring directional convolutional kernels to enhance their continuity representation; vias are circularly distributed, necessitating multi-scale circular feature extraction to capture their radial structure; pads are square structures with varying sizes in the image, requiring multi-scale convolution to extract their feature information. Existing methods generally use convolutional kernels of fixed shapes, lacking targeted modeling for these diverse geometric structures, thus limiting the model's segmentation performance on complex PCB images. Therefore, designing a segmentation model that can be optimized for specific PCB structures while maintaining the strong generalization ability of the SAM model is of great significance for improving the accuracy and efficiency of automatic PCB inspection. Summary of the Invention

[0005] To address the challenges of segmenting complex PCB images, this invention provides a PCB CT image segmentation method and system based on enhanced geometric features and fine-tuning of the SAM model. By optimizing the feature extraction and fusion of specific structures such as conductors, vias, and pads in printed circuit board (PCB) images, the accuracy and efficiency of automatic PCB inspection are improved.

[0006] According to the design scheme provided by this invention, on the one hand, a PCB CT image segmentation method based on element geometric feature enhancement and SAM model fine-tuning is provided, comprising:

[0007] Acquire CT images of the printed circuit board to be segmented;

[0008] A CT image of a printed circuit board (PCB) to be segmented is input into an image segmentation model. The image segmentation model predicts and outputs a segmentation mask for components in the PCB CT image. The image segmentation model includes a pre-trained PCB adapter and a fine-tuned SAM model. The SAM model includes: an image encoder for encoding the PCB image into image feature vectors, a cue encoder for converting cue content into cue vectors, and a lightweight mask decoder for fusing image features and cue vectors to predict and output a segmentation mask. The PCB adapter includes: a feature extractor for extracting features of each component of the PCB circuit through parallel branches, an adaptive feature fusion gating unit for adjusting the feature weights of each parallel branch to obtain enhanced features of each component, and an output unit for weighted fusion of the image feature vector from the image encoder and the enhanced features of each component to output image features.

[0009] As a PCB CT image segmentation method based on element geometric feature enhancement and SAM model fine-tuning of the present invention, the feature extractor further includes: a wire feature extractor for extracting printed circuit board wire features, a via feature extractor for extracting printed circuit board via features, and a pad feature extractor for extracting printed circuit board pad features. The wire feature extractor enhances the extracted wire features using a channel attention mechanism, the via feature extractor enhances the extracted via features using a spatial attention mechanism, and the pad feature extractor enhances the extracted pad features using both channel attention and spatial attention mechanisms.

[0010] As a PCB CT image segmentation method based on feature geometric enhancement and SAM model fine-tuning of the present invention, the conductor feature extractor further employs horizontal convolution branches, vertical convolution branches, and diagonal convolution branches to capture horizontal conductor features, vertical conductor features, and diagonal conductor features of the printed circuit board in parallel; the via feature extractor employs convolution branches of different scales to extract via features of different sizes; and the pad feature extractor employs convolution branches of different sizes to extract multi-scale pad features.

[0011] As a PCB CT image segmentation method based on element geometric feature enhancement and SAM model fine-tuning of the present invention, each feature extractor further includes the following steps when extracting corresponding component features: using a center clipping strategy to align the size of each branch feature, stitching the aligned features along the channel dimension, and fusing and dimensionally transforming the stitched features using two layers of convolution to obtain a component feature map with uniform size.

[0012] As a PCB CT image segmentation method based on element geometric feature enhancement and SAM model fine-tuning of the present invention, the adaptive feature fusion gating unit further utilizes a feature selector to dynamically generate the weights of the features of each component branch of the printed circuit board to obtain the enhanced features of each component. The feature selector consists of a fully connected layer and a Softmax function, which uses the fully connected layer to perform global average pooling on the image features output by the image encoder to obtain the global features at the channel level of the printed circuit board. Based on the global features, two layers of convolution and Softmax are then used to obtain the feature weights of each component branch.

[0013] As a PCB CT image segmentation method based on element geometric feature enhancement and SAM model fine-tuning of the present invention, the output unit further includes weighted fusion of the image feature vector of the image encoder with the features of each parallel branch and outputting the image features, and also includes:

[0014] During weighted fusion, a learnable scalar is used to globally adjust the contribution magnitude of each parallel branch. The learnable scalar is the feature weight corresponding to the segmentation element learned during model training.

[0015] As a PCB CT image segmentation method based on feature geometric enhancement and SAM model fine-tuning of the present invention, the image segmentation model training process further includes:

[0016] Obtain a PCB sample dataset, wherein each PCB image in the dataset contains annotation information for each component;

[0017] A combined optimization loss function for model training is constructed based on Focal Loss and Dice Loss;

[0018] The image segmentation model is trained using a combination of optimized loss functions and PCB sample datasets to segment the components in PCB images.

[0019] Furthermore, this invention also provides a PCB CT image segmentation system based on element geometric feature enhancement and SAM model fine-tuning, comprising: an image acquisition module and an image segmentation module, wherein,

[0020] Image acquisition module, used to acquire CT images of the printed circuit board to be segmented;

[0021] An image segmentation module is used to input a CT image of a printed circuit board (PCB) to be segmented into an image segmentation model. The image segmentation model predicts and outputs a segmentation mask for components in the PCB CT image. The image segmentation model includes a pre-trained PCB adapter and a fine-tuned SAM model. The SAM model includes: an image encoder for encoding the PCB image into image feature vectors, a cue encoder for converting cue content into cue vectors, and a lightweight mask decoder for fusing image features and cue vectors to predict and output a segmentation mask. The PCB adapter includes: a feature extractor for extracting features of each component of the PCB circuit through parallel branches, an adaptive feature fusion gating unit for adjusting the feature weights of each parallel branch to obtain enhanced features of each component, and an output unit for weighted fusion of the image feature vector from the image encoder and the enhanced features of each component to output image features.

[0022] The beneficial effects of this invention are:

[0023] This invention employs multi-directional feature extractors to optimize the feature representation of conductors, vias, and pads. The conductor feature extractor captures slender structures using directional convolutional kernels, the via feature extractor extracts radial features using multi-scale circular convolutional kernels, and the pad feature extractor detects corners and edges using square convolutional kernels. Each extractor is equipped with a dedicated attention mechanism to further enhance key features. Through an adaptive feature gating switch, the system dynamically adjusts the contribution of the three PCB features, achieving a balance between global semantic alignment and local structural enhancement. Further experimental results demonstrate that the proposed MPFE-SAM scheme significantly outperforms the original SAM model and existing dedicated segmentation methods on PCB image segmentation tasks, particularly showing a significant improvement in segmentation accuracy for small conductors, circular vias, and square pads. The performance advantage is further extended on difficult samples (such as dense wiring and micro-vias), verifying the robustness and sensitivity of this method in PCB-specific structure segmentation. By successfully integrating PCB geometric prior knowledge into a general segmentation framework, it significantly improves the segmentation accuracy for PCB-specific structures while maintaining the strong generalization ability of SAM, providing a new technical approach for industrial visual inspection. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the PCB CT image segmentation process based on feature geometric enhancement and SAM model fine-tuning in the embodiment.

[0025] Figure 2 This is a schematic diagram of the adapter architecture based on the SAM fine-tuning model in the embodiment;

[0026] Figure 3 This is a schematic diagram of the wire feature extractor structure in the embodiment;

[0027] Figure 4 This is a schematic diagram of the via feature extractor structure in the embodiment;

[0028] Figure 5 This is a schematic diagram of the pad feature extractor structure in the embodiment. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer and more understandable, the invention will be further described in detail below with reference to the accompanying drawings and technical solutions.

[0030] To address the issue of insufficient sensitivity of existing general segmentation models for specific PCB structures, this invention provides an embodiment, see [link to embodiment]. Figure 1 As shown, a PCB CT image segmentation method based on feature geometric enhancement and SAM model fine-tuning is provided, comprising:

[0031] S101. Obtain CT images of the printed circuit board to be segmented;

[0032] S102. Input the CT image of the printed circuit board to be segmented into the image segmentation model, and use the image segmentation model to predict and output the component segmentation mask in the CT image of the printed circuit board. The image segmentation model includes a pre-trained PCB adapter and a fine-tuned SAM model. The SAM model includes: an image encoder for encoding the printed circuit board image into image feature vectors, a cue encoder for converting cue content into cue vectors, and a lightweight mask decoder for fusing image features and cue vectors and predicting the output segmentation mask. The PCB adapter includes: a feature extractor for extracting features of each component of the printed circuit board through parallel branches, an adaptive feature fusion gating unit for adjusting the feature weights of each parallel branch to obtain the enhanced features of each component, and an output unit for weighted fusion of the image feature vector of the image encoder and the enhanced features of each component and outputting the image features.

[0033] Specifically, the feature extractor may include: a wire feature extractor for extracting printed circuit board wire features, a via feature extractor for extracting printed circuit board via features, and a pad feature extractor for extracting printed circuit board pad features. The wire feature extractor enhances the extracted wire features using a channel attention mechanism, the via feature extractor enhances the extracted via features using a spatial attention mechanism, and the pad feature extractor enhances the extracted pad features using both channel attention and spatial attention mechanisms.

[0034] like Figure 2The PCB CT image segmentation model (Multi-Branch Geometric Feature Enhancement SAM, MBFE-SAM) architecture shown is based on the original SAM architecture. It introduces three targeted feature extractors to extract corresponding feature characteristics of conductors, vias, and pads, while maintaining the original SAM architecture. It achieves synergistic enhancement of multiple types of PCB features through an adaptive feature selection mechanism. It uses a multi-directional PCB feature extractor (MDFE) and an adaptive feature fusion gating unit (AFFGU) to achieve accurate segmentation of conductors, vias, and pads in PCB images.

[0035] The conductor feature extractor uses horizontal, vertical, and diagonal convolution branches to capture horizontal, vertical, and diagonal conductor features of the printed circuit board in parallel; the via feature extractor uses convolution branches of different scales to extract via features of different sizes; and the pad feature extractor uses convolution branches of different sizes to extract multi-scale pad features.

[0036] like Figure 3 As shown, for wire feature extraction, three parallel convolutional branches are used:

[0037] The horizontal convolution branch uses a 1×7 convolution kernel to specifically capture horizontal wire features, and its mathematical expression is:

[0038]

[0039] in This represents a two-dimensional convolution operation with a kernel size of 1×7. Indicates grouping normalization, This represents the modified linear unit activation function.

[0040] The vertical convolution branch uses a 7×1 convolution kernel to specifically capture vertical wire features, and its mathematical expression is: The diagonal convolution branch uses a 3×3 convolution kernel to capture the features of the diagonal wires. Its mathematical expression is:

[0041]

[0042] like Figure 4As shown, for via feature extraction, three parallel branches are also used, employing convolutional kernels of different scales to extract features of vias of different sizes. However, circular optimized convolutional kernels are used. Unlike ordinary convolutional kernels, circular convolutions are constrained by masks to only respond to features at distances not exceeding a certain distance from the center. The pixels are naturally more sensitive to circular and radial features, while suppressing corner noise, making the features fit circular structures such as vias better.

[0043] The convolutional branch uses a 5×5 convolution kernel to extract circular radial features, and its mathematical expression is:

[0044]

[0045] The convolution branch uses a 7×7 convolution kernel, and its mathematical expression is:

[0046]

[0047] The convolution branch uses a 3×3 convolution kernel to detect circular boundaries; its mathematical expression is:

[0048]

[0049] like Figure 5 As shown, for pad feature extraction, convolution kernels of different sizes are used to extract multi-scale features, covering pads of different sizes:

[0050] The convolution branch uses a 4×4 convolution kernel specifically to extract square features, and its mathematical expression is:

[0051]

[0052] The convolutional branch uses a 6×6 convolutional kernel to capture multi-scale square features, and its mathematical expression is:

[0053]

[0054] The convolution branch uses a 3×3 convolution kernel, and its mathematical expression is:

[0055]

[0056] Different branches have inconsistent output sizes due to differences in convolution kernel size and padding. A center-clipping strategy is used to achieve size alignment. First, the minimum size of all feature maps is calculated:

[0057]

[0058]

[0059]

[0060] in The original feature map of the m-th branch. This is the feature map after aligning the m-th branch. and These are the original height and original width of the feature map output by the m-th feature extraction branch.

[0061] The aligned feature maps are stitched together along the channel dimension:

[0062]

[0063] After concatenation, the features are fused and their dimensions are transformed using two convolutional layers. The first layer uses a 1×1 convolution to reduce the number of channels from 192 to 128, and the second layer uses a 3×3 convolution to increase the number of channels from 128 to 256. Specifically, the first layer uses a 1×1 convolution for channel compression.

[0064]

[0065] The second layer uses 3×3 convolutions to increase the number of channels and further fuse them:

[0066]

[0067] Specialized attention mechanisms are employed based on the characteristics of different PCB structures. The conductor feature extractor uses channel attention, and its calculation process is as follows:

[0068] First, channel-level global information is obtained through global average pooling, where GAP represents global average pooling:

[0069]

[0070] Then, channel attention weights are generated using two 1×1 convolutions and a sigmoid function:

[0071]

[0072] Ultimately, features are enhanced through element-wise multiplication:

[0073]

[0074] The via feature extractor uses spatial attention to generate a spatial weight map through 1×1 convolution and sigmoid:

[0075]

[0076]

[0077] The pad feature extractor uses dual attention, applying both channel and spatial attention simultaneously:

[0078]

[0079] The Adaptive Feature Fusion Gating Unit (AFFG) dynamically generates the weights of the branch features of each component on the printed circuit board using a feature selector to obtain the enhanced features of each component. The feature selector consists of a fully connected layer and a Softmax function. The fully connected layer performs global average pooling on the image features output by the image encoder to obtain the global features at the channel level of the printed circuit board. Based on the global features, two layers of convolution and Softmax are then used to obtain the feature weights of each component branch.

[0080] Furthermore, during weighted fusion, a learnable scalar is used to globally adjust the contribution magnitude of each parallel branch. The learnable scalar is the feature weight corresponding to the segmentation element learned during model training.

[0081] The enhanced PCB features are fused with the original SAM features. First, the original feature map is obtained from the SAM image encoder. B represents batch size, C represents number of channels, and H and W represent width and height, respectively.

[0082] Three enhanced features were obtained , , The size of each feature is In order to be able to Fusion first projects these features onto a graph with... Same channel dimension Using 1×1 convolution:

[0083]

[0084]

[0085] Because size alignment ensures consistent spatial dimensions, therefore and No additional adjustments are needed. Next, the weights of the three PCB features are dynamically calculated using a feature selector. The feature selector is based on... The global information is used to generate weights. Specifically, firstly, the weights are generated based on... Perform global average pooling (GAP) to obtain channel-level global features:

[0086]

[0087] Then, weights are selected by generating features through two layers of 1×1 convolution and Softmax:

[0088] in, It is a three-element vector, representing the weights of the features of wires, vias, and pads, and the sum of the weights is 1.

[0089] The feature selector automatically calculates the weights of conductors, vias, and pads in the current segmentation task. These weights are dynamically generated and reflect the importance of different PCB structures to the final segmentation result.

[0090] Finally, these weighted PCB features are added and fused with the original SAM features. A set of learnable scalar parameters is introduced during fusion to globally adjust the contribution of each branch. This design allows the model to automatically learn to increase the weight of corresponding features based on the elements to be segmented (e.g., segmenting only wires) during training, achieving a "gating" effect; and when processing complex images, it can intelligently balance the contributions of multiple features. The process of fusing enhanced PCB features and original SAM features through learnable parameters can be represented as follows:

[0091]

[0092] in, , , For learnable scalars, , , This represents the selector weight.

[0093] The actual mechanism of the gating switch is to adaptively calculate weights through a feature selector, thereby dynamically adjusting the contribution of each feature branch. During training, since each image is segmented for only one feature (wire, via, or pad), the model learns to assign higher weights to the corresponding features, achieving a gating-like effect. However, during inference, the model automatically calculates weights based on the input image, requiring no manual intervention.

[0094] Finally, the enhanced fused features are input into the mask decoder of the SAM for segmentation prediction, generating the final accurate segmentation mask.

[0095] The image segmentation model training process can be designed to include:

[0096] Obtain a PCB sample dataset, wherein each PCB image in the dataset contains annotation information for each component;

[0097] A combined optimization loss function for model training is constructed based on Focal Loss and Dice Loss;

[0098] The image segmentation model is trained using a combination of optimized loss functions and PCB sample datasets to segment the components in PCB images.

[0099] The model is trained using the Adam optimizer, and the initial learning rate can be set to... Cosine annealing learning rate scheduling is employed. Due to class imbalance in the PCB image and the large proportion of background in the entire image, a combination of Focal Loss and Dice Loss can be used for optimization. The total loss function can be expressed as:

[0100]

[0101] The dataset contains 7098 PCB CT images, each with complete annotations for conductors, vias, and pads. The training strategy involves randomly selecting one feature from each image for segmentation, and using this feature to determine which feature extraction module the gating switch points to. After sufficient training, the model can achieve high-precision segmentation of conductors, vias, and pads in PCB images.

[0102] This solution, while maintaining the original SAM architecture, introduces a multi-directional PCB feature extractor. Dedicated convolutional kernels and attention mechanisms are designed for conductors, vias, and pads to enhance feature extraction capabilities for specific PCB geometries. Furthermore, an adaptive feature fusion gateway dynamically adjusts the contribution of each structural feature, achieving effective fusion of global semantics and local structure. Experimental results show that this solution significantly improves the segmentation accuracy of conductors, vias, and pads in PCB image segmentation tasks, especially performing exceptionally well on challenging samples with dense wiring and minute structures. It exhibits good robustness and generalization ability, making it suitable for industrial visual inspection scenarios.

[0103] Furthermore, based on the above method, this embodiment of the invention also provides a PCB CT image segmentation system based on feature geometric enhancement and SAM model fine-tuning, comprising: an image acquisition module and an image segmentation module, wherein,

[0104] Image acquisition module, used to acquire CT images of the printed circuit board to be segmented;

[0105] An image segmentation module is used to input a CT image of a printed circuit board (PCB) to be segmented into an image segmentation model. The image segmentation model predicts and outputs a segmentation mask for components in the PCB CT image. The image segmentation model includes a pre-trained PCB adapter and a fine-tuned SAM model. The SAM model includes: an image encoder for encoding the PCB image into image feature vectors, a cue encoder for converting cue content into cue vectors, and a lightweight mask decoder for fusing image features and cue vectors to predict and output a segmentation mask. The PCB adapter includes: a feature extractor for extracting features of each component of the PCB circuit through parallel branches, an adaptive feature fusion gating unit for adjusting the feature weights of each parallel branch to obtain enhanced features of each component, and an output unit for weighted fusion of the image feature vector from the image encoder and the enhanced features of each component to output image features.

[0106] Unless otherwise specifically stated, the relative steps, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of the invention.

[0107] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0108] The units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations are not considered to be beyond the scope of this invention.

[0109] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This invention is not limited to any particular combination of hardware and software.

[0110] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A PCB CT image segmentation method based on feature geometric enhancement and SAM model fine-tuning, characterized in that, Include: Acquire CT images of the printed circuit board to be segmented; A CT image of a printed circuit board (PCB) to be segmented is input into an image segmentation model. The image segmentation model predicts and outputs a segmentation mask for components in the PCB CT image. The image segmentation model includes a pre-trained PCB adapter and a fine-tuned SAM model. The SAM model includes: an image encoder for encoding the PCB image into image feature vectors, a cue encoder for converting cue content into cue vectors, and a lightweight mask decoder for fusing image features and cue vectors to predict and output a segmentation mask. The PCB adapter includes: a feature extractor for extracting features of each component of the PCB circuit through parallel branches, an adaptive feature fusion gating unit for adjusting the feature weights of each parallel branch to obtain enhanced features of each component, and an output unit for weighted fusion of the image feature vector from the image encoder and the enhanced features of each component to output image features.

2. The PCB CT image segmentation method based on feature geometric enhancement and SAM model fine-tuning according to claim 1, characterized in that, The feature extractor includes: a wire feature extractor for extracting wire features of a printed circuit board, a via feature extractor for extracting via features of a printed circuit board, and a pad feature extractor for extracting pad features of a printed circuit board. The wire feature extractor enhances the extracted wire features using a channel attention mechanism, the via feature extractor enhances the extracted via features using a spatial attention mechanism, and the pad feature extractor enhances the extracted pad features using both channel attention and spatial attention mechanisms.

3. The PCB CT image segmentation method based on feature geometric enhancement and SAM model fine-tuning according to claim 2, characterized in that, The conductor feature extractor uses horizontal convolution branches, vertical convolution branches, and diagonal convolution branches to capture horizontal conductor features, vertical conductor features, and diagonal conductor features of the printed circuit board in parallel; the via feature extractor uses convolution branches of different scales to extract via features of different sizes; and the pad feature extractor uses convolution branches of different sizes to extract multi-scale pad features.

4. The PCB CT image segmentation method based on feature geometric enhancement and SAM model fine-tuning according to claim 3, characterized in that, Each feature extractor, when extracting the corresponding component features, also includes: using a center-clipping strategy to align the size of each branch feature, stitching the aligned features along the channel dimension, and using two layers of convolution to fuse and transform the dimensions of the stitched features to obtain a component feature map with uniform size.

5. The PCB CT image segmentation method based on feature geometric enhancement and SAM model fine-tuning according to claim 1, characterized in that, The adaptive feature fusion gating unit uses a feature selector to dynamically generate weights for the branch features of each component on the printed circuit board in order to obtain the enhanced features of each component. The feature selector consists of a fully connected layer and a Softmax function, which uses the fully connected layer to perform global average pooling on the image features output by the image encoder to obtain the global features at the channel level of the printed circuit board. Based on global features, two layers of convolution and Softmax are used to obtain the feature weights of each component branch.

6. The PCB CT image segmentation method based on feature geometric enhancement and SAM model fine-tuning according to claim 1 or 5, characterized in that, The output unit weighted and fused the image feature vectors from the image encoder with the features from each parallel branch, and outputs the image features. It also includes: During weighted fusion, a learnable scalar is used to globally adjust the contribution magnitude of each parallel branch. The learnable scalar is the feature weight corresponding to the segmentation element learned during model training.

7. The PCB CT image segmentation method based on feature geometric enhancement and SAM model fine-tuning according to claim 1, characterized in that, The image segmentation model training process includes: Obtain a PCB sample dataset, wherein each PCB image in the dataset contains annotation information for each component; A combined optimization loss function for model training is constructed based on Focal Loss and Dice Loss; The image segmentation model is trained using a combination of optimized loss functions and PCB sample datasets to segment the components in PCB images.

8. A PCB CT image segmentation system based on feature geometric enhancement and SAM model fine-tuning, characterized in that, It includes: an image acquisition module and an image segmentation module, wherein, Image acquisition module, used to acquire CT images of the printed circuit board to be segmented; An image segmentation module is used to input a CT image of a printed circuit board (PCB) to be segmented into an image segmentation model. The image segmentation model predicts and outputs a segmentation mask for components in the PCB CT image. The image segmentation model includes a pre-trained PCB adapter and a fine-tuned SAM model. The SAM model includes: an image encoder for encoding the PCB image into image feature vectors, a cue encoder for converting cue content into cue vectors, and a lightweight mask decoder for fusing image features and cue vectors to predict and output a segmentation mask. The PCB adapter includes: a feature extractor for extracting features of each component of the PCB circuit through parallel branches, an adaptive feature fusion gating unit for adjusting the feature weights of each parallel branch to obtain enhanced features of each component, and an output unit for weighted fusion of the image feature vector from the image encoder and the enhanced features of each component to output image features.

9. An electronic device, characterized in that, include: At least one processor, and a memory coupled to said at least one processor; The memory stores a computer program that can be executed by the at least one processor to implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, enables the implementation of the method as described in any one of claims 1 to 7.

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