Defect detection method, system, device, and readable storage medium

Abstract

The application provides a defect detection method, system, device and readable storage medium. The method comprises the following steps: acquiring a panoramic image of a wafer to be detected and a real-time load state of each special computing node; decomposing the panoramic image into a plurality of image subblocks, and generating a corresponding detection subtask for each image subblock; distributing the detection subtask to the corresponding special computing node based on the real-time load state of each special computing node, and receiving a defect detection result generated by the special computing node for the image subblock defect detection; and fusing all the defect detection results to generate a defect distribution map. Compared with the prior art, the application breaks through the computing power and memory bottleneck of the traditional single-machine centralized architecture, and realizes effective sharing of the computing load. At the same time, the single-point failure risk is fundamentally reduced. The application is suitable for scenes with extremely high requirements for continuous and stable production in semiconductor manufacturing, and effectively avoids the production interruption loss caused by the shutdown of the detection equipment.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and specifically relates to a defect detection method, system, device, and readable storage medium. Background Technology

[0002] Defect detection on bare semiconductor wafers is a critical step in the chip manufacturing process, and its accuracy and efficiency directly affect the yield and reliability of the final product. As the feature size of integrated circuits continues to shrink, the requirements for detecting defects on the wafer surface are becoming increasingly stringent.

[0003] Currently, mainstream equipment in the semiconductor defect detection field generally adopts a centralized computing architecture, where a single high-performance industrial computer handles all core processing tasks. However, with the continuous improvement of detection accuracy requirements, image resolution, and acquisition rates, the inherent defects of the aforementioned centralized computing architecture are becoming increasingly apparent. The processing power of a single industrial computer's central processing unit (CPU) and graphics processing unit (GPU) has a physical limit. When simultaneously processing high-definition image data streams and running large-scale artificial intelligence models, computing resources can easily reach saturation, leading to data processing delays and becoming a bottleneck restricting the improvement of detection speed. Real-time caching of high-resolution images, data exchange between multiple tasks, and loading of artificial intelligence models all consume a large amount of memory. The limited memory capacity of a single machine may lead to data congestion or frequent input / output exchanges, which not only affects speed but may also cause a decrease in detection accuracy due to data loss.

[0004] Furthermore, the entire testing process is highly dependent on the stable operation of a single industrial control computer. Any hardware or software failure in this industrial control computer may cause the entire testing machine to stop, seriously affecting the continuity and efficiency of the production line. Summary of the Invention

[0005] The purpose of this invention is to provide a defect detection method, system, device, and readable storage medium that can improve detection efficiency.

[0006] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0007] In a first aspect, the present invention provides a defect detection method applied to semiconductor bare wafers, comprising: acquiring a panoramic image of the wafer to be inspected and the real-time load status of each dedicated computing node; decomposing the panoramic image into multiple image sub-blocks and generating a corresponding detection sub-task for each image sub-block; allocating the detection sub-task to the corresponding dedicated computing node based on the real-time load status of each dedicated computing node, and receiving the defect detection results generated by the dedicated computing node for defect detection of the image sub-blocks; and fusing all defect detection results to generate a defect distribution map.

[0008] In one or more embodiments of the present invention, the step of decomposing the panoramic image into multiple image sub-blocks includes: determining the block granularity of the panoramic image based on the total resolution of the panoramic image and the number of dedicated computing nodes; dividing the panoramic image into multiple image sub-blocks based on the block granularity; wherein, if there are pixels in the image sub-blocks that exceed the effective area of ​​the wafer, the positions of the pixels that exceed the effective area of ​​the wafer are filled with zero values.

[0009] In one or more embodiments of the present invention, the method further includes: establishing a wafer physical coordinate system and an image pixel coordinate system based on the positioning data of the motion platform and the pixel coordinates of the image acquisition card; determining the mapping relationship between the coordinate points in the wafer physical coordinate system and the image pixel coordinate system; and determining the effective area for image acquisition in the image pixel coordinate system based on the specifications of the wafer to be inspected and the mapping relationship, and removing invalid background areas at the wafer edge.

[0010] In one or more embodiments of the present invention, the detection subtask is allocated to the corresponding dedicated computing node based on the real-time load status of each dedicated computing node, including: determining a corresponding detection task package for each detection subtask, wherein the detection task package includes image sub-block pixel data and image sub-block spatial index; calculating the load score of each dedicated computing node based on the real-time load status of each dedicated computing node, and allocating the detection task package corresponding to the detection subtask to the dedicated computing node based on the load score of each dedicated computing node.

[0011] In one or more embodiments of the present invention, the method further includes: monitoring the heartbeat status of each of the dedicated computing nodes; when the first dedicated computing node malfunctions, reassigning the detection subtasks that have been assigned to the first dedicated computing node but have not been processed to other normal dedicated computing nodes; wherein the malfunction conditions include: not receiving a heartbeat signal from the first dedicated computing node within a preset first time threshold, or not receiving a processing result from the first dedicated computing node for the assigned task within a preset second time threshold.

[0012] In one or more embodiments of the present invention, a dedicated computing node performs defect detection on an assigned detection subtask, including: the dedicated computing node executes a first detection process based on image processing and a second detection process based on a deep learning model on the detection subtask, wherein the first detection process and the second detection process are executed in parallel.

[0013] In one or more embodiments of the present invention, the step of fusing all defect detection results to generate a defect distribution map includes: receiving defect detection results sent from each of the dedicated computing nodes; sorting and stitching the defect detection results based on the spatial index in the defect detection results; matching and merging duplicate defects appearing at the intersection of image sub-blocks based on the coordinates, size, shape and confidence of the defects, and removing duplicate records; and locating the merged defect information to the wafer physical coordinate system to generate a defect distribution map.

[0014] Secondly, the present invention provides a defect detection system, applying the aforementioned defect detection method, comprising: an acquisition module for acquiring a panoramic image of the wafer to be inspected and the real-time load status of each dedicated computing node; a decomposition module for decomposing the panoramic image into multiple image sub-blocks and generating a corresponding detection sub-task for each image sub-block; a detection module for allocating the detection sub-task to the corresponding dedicated computing node based on the real-time load status of each dedicated computing node, and receiving the defect detection results generated by the dedicated computing node for defect detection of the image sub-blocks; and a fusion module for fusing all defect detection results to generate a defect distribution map.

[0015] Thirdly, the present invention provides an electronic device comprising: at least one processor; and a memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform the defect detection method.

[0016] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the defect detection method described above.

[0017] Compared with existing technologies, the defect detection method provided by this invention breaks through the computing power and memory bottlenecks of traditional single-machine centralized architectures by constructing a distributed architecture of multi-industrial control computers (ICCs) co-computing, thus achieving effective distribution of computing load. Compared with the sequential processing mode of a single ICC, this invention significantly shortens the detection cycle of a single wafer. Under the same hardware configuration, the detection speed can be increased approximately linearly with the increase of the number of dedicated ICCs, effectively meeting the high-throughput detection requirements of semiconductor manufacturing.

[0018] Meanwhile, the distributed architecture adopted in this invention fundamentally reduces the risk of single-point failures. The main industrial control computer monitors the operating status of each dedicated industrial control computer in real time through heartbeat keep-alive, status reporting, and timeout judgment mechanisms. When any node malfunctions, the system can automatically isolate that node from the computing resource pool and reassign its unfinished detection subtasks to other normal nodes, achieving fault self-healing and seamless switching. This fault-tolerant mechanism significantly extends the system's mean time between failures (MTBF), making it particularly suitable for semiconductor manufacturing scenarios with extremely high requirements for continuous and stable production, effectively avoiding production interruptions caused by downtime of testing equipment. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of a defect detection method in one embodiment of the present invention;

[0021] Figure 2 This is a structural block diagram of a defect detection system according to another embodiment of the present invention;

[0022] Figure 3 This is a structural block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0024] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0025] Existing technical solutions for defect detection typically rely on a single high-performance industrial control computer (ICSC) to handle all core processing tasks. This includes controlling a high-resolution camera for image acquisition, preprocessing and extracting features from 2D image data, running a deep learning model for defect identification and classification, controlling a precision motion platform for synchronous wafer transfer, and integrating all detection results to generate a defect distribution map. However, due to the physical limitations of the CPU and GPU of a single ICCC, memory constraints leading to data congestion or frequent input / output exchanges, and the high dependence of the entire detection process on the stable operation of a single ICCC, this technical solution inevitably faces reliability risks such as computational bottlenecks hindering efficiency improvement, memory bottlenecks causing data delays or loss, and single-point failures causing system-wide downtime.

[0026] The inventors of this invention discovered that existing improvement solutions mostly focus on the front-end imaging stage, but have consistently failed to address the fundamental architectural bottleneck of back-end data processing, thus failing to effectively resolve the core contradiction between the rapid growth of front-end sensor data acquisition capabilities and the limited data processing capabilities of back-end single machines. Based on this, the inventors propose a novel technical approach: abandoning the traditional architecture of centralized processing by a single industrial control computer, instead constructing a distributed collaborative computing system with a main industrial control computer as the scheduling hub and multiple dedicated computing nodes processing in parallel; by adaptively decomposing the high-resolution image of the entire wafer into multiple image sub-blocks with balanced granularity, and using a dynamic load balancing algorithm to allocate sub-tasks to the nodes with the lowest load in real time, each node executes a dual-process detection workflow of traditional image processing and deep learning in parallel, and finally, the structured results are accurately fused according to spatial coordinates to generate a defect distribution map, thereby fundamentally breaking through the single-machine computing power and memory bottlenecks at the system architecture level, and effectively improving detection speed and system reliability.

[0027] Please refer to Figure 1 The diagram shown is a flowchart illustrating defect detection in one embodiment of the present invention. The defect detection method specifically includes the following steps:

[0028] S101: Acquire a panoramic image of the wafer to be inspected and the real-time load status of each dedicated computing node;

[0029] It should be noted that, under the defect detection architecture of this invention, the dedicated computing node may include, but is not limited to, a combination of one or more hardware forms such as a dedicated industrial control computer, an embedded industrial control board, a GPU server, and an edge computing node. This invention does not impose any restrictions on this.

[0030] In one implementation, a dedicated industrial control computer is used as the aforementioned dedicated computing node. After the testing process starts, the main industrial control computer first performs initialization operations to acquire a panoramic image of the wafer to be tested and the real-time load status of each dedicated industrial control computer, providing a data basis for subsequent task decomposition and dynamic allocation.

[0031] Specifically, the main control industrial computer communicates with a high-resolution line scan camera via a high-speed image acquisition card, controlling the camera to scan and image the wafer under inspection. During the imaging process, the main control industrial computer simultaneously receives positioning data from a high-precision motion platform to acquire the wafer's position information in physical space. After acquisition, the main control industrial computer obtains a high-definition grayscale or color image covering the entire wafer, containing the entire inspection area on the wafer surface. The image resolution depends on the camera parameters and the scanning step size.

[0032] Meanwhile, the main control industrial computer establishes communication connections with each dedicated industrial computer via a high-speed internal network and performs load status acquisition operations. Specifically, the main control industrial computer sends status query commands to each dedicated industrial computer. Upon receiving the commands, each dedicated industrial computer collects multi-dimensional load indicators of its node in real time and encapsulates them into status messages, returning them to the main control industrial computer. The multi-dimensional load indicators mentioned in this invention include, but are not limited to: CPU utilization, GPU utilization, memory usage, current task queue length, and average task processing latency. The main control industrial computer receives and parses the status messages returned by each dedicated industrial computer, constructing a resource status table containing load information for all online nodes. This table records the unique identifier of each node, the current values ​​of each load indicator, and whether the node is valid.

[0033] It should be noted that the acquisition of panoramic images and the collection of load status can be performed in parallel or in a time-sharing manner, and the execution order of the two does not affect the normal progress of subsequent steps. Preferably, the main industrial control computer synchronously polls the load status of each dedicated industrial control computer during the image acquisition process to reduce the overall process waiting time.

[0034] S102: Decompose the panoramic image into multiple image sub-blocks, and generate a corresponding detection sub-task for each image sub-block;

[0035] It should be noted that, in order to improve the predictability of load calculation and simplify the scheduling logic of the main control unit, in this embodiment of the invention, the panoramic image can be decomposed into image sub-blocks with balanced granularity, that is, each image sub-block to be processed has the same or similar amount of data.

[0036] In one implementation, the panoramic image is decomposed into multiple image sub-blocks. First, the granularity of the panoramic image can be determined based on the total resolution of the panoramic image and the number of dedicated computing nodes.

[0037] For example, adaptive calculation can be performed based on the following formula:

[0038]

[0039] in, The side length (in pixels) of a single image sub-block is rounded to an integer to ensure that the blocks are well-organized. This refers to the total pixel resolution of a high-definition image of the entire wafer. This represents the number of dedicated industrial control computer nodes currently online. This is a rounding function that ensures all image pixels are covered.

[0040] Under this adaptive logic, when the number of online nodes When increasing, the granularity of the sub-blocks The computational cost of a single subtask is reduced, while the parallelism is increased; when the number of nodes... When reduced, sub-block granularity Increase the number of subtasks to avoid increased scheduling overhead caused by an excessive number of subtasks, and achieve dynamic matching of "number of nodes - granularity of subtasks - computational load".

[0041] Furthermore, after determining the segmentation granularity, for the main part of the wafer image, i.e., the area located within the effective region and capable of being covered by complete square sub-blocks, the main control industrial computer... The pixel size is divided into several regular square sub-blocks. The number of pixels and the amount of data in each regular sub-block are completely consistent, achieving absolute balance in computational load. For irregular edge regions of the wafer image, i.e., arc-shaped regions caused by the mismatch between the circular boundary of the wafer and the rectangular grid, the main control computer uses the minimum bounding rectangle method to crop the edge image sub-blocks, and fills the part of the edge image sub-block that exceeds the effective area of ​​the wafer with zero-value pixels, so that the size of the edge image sub-block is consistent with that of the regular square sub-blocks.

[0042] In one embodiment, for image blocks generated corresponding to irregular regions, the main industrial control computer can mark the effective region range in the task header information of the sub-block, so that the dedicated industrial control computer that performs subsequent detection only performs defect detection on the effective region and avoids invalid calculations on the filled zero pixels.

[0043] Understandably, in conventional implementation scenarios, the physical coordinate system of the wafer usually deviates from the pixel coordinate system of the generated panoramic image. To facilitate subsequent image stitching and defect location determination, and to better avoid invalid calculations, in one implementation, before image segmentation, the defect detection method of the present invention may further include: establishing a wafer physical coordinate system and an image pixel coordinate system based on the positioning data of the motion platform and the pixel coordinates of the image acquisition card; determining the mapping relationship between the coordinate points in the wafer physical coordinate system and the image pixel coordinate system; and determining the effective area for image acquisition in the image pixel coordinate system based on the specifications of the wafer to be inspected and the mapping relationship, and removing invalid background areas at the wafer edges.

[0044] In this implementation, a Cartesian coordinate system can be established with the wafer center as the origin to ensure that the spatial position of subsequent blocks accurately corresponds to the actual inspection area of ​​the wafer, avoiding blind spots or duplicate inspections. With the determined block granularity, the main control computer can use a Cartesian orthogonal grid to uniformly divide the effective image area of ​​the wafer using the aforementioned block implementation method.

[0045] It should be noted that after image segmentation, the main industrial control computer generates an independent detection sub-task package for each image sub-block. Each detection sub-task package may contain one or more of the following: pixel data of the image sub-block, spatial index information, detection parameters, and scheduling identifier.

[0046] Specifically, the spatial index data may include the row and column coordinates of the image sub-block in the panoramic image, the wafer physical location coordinates of the pixels within the sub-block obtained based on the coordinate system mapping relationship, and a label indicating whether the sub-block is an edge sub-block; the detection parameters may include the algorithm expected to be used by the dedicated computing node to process the current image sub-block, such as an image processing algorithm or a deep learning model, algorithm parameter configuration, and task priority; the scheduling identifier may include a unique identifier for the subtask, a timestamp, and a task status identifier.

[0047] S103: Based on the real-time load status of each dedicated computing node, the detection subtask is assigned to the corresponding dedicated computing node, and the defect detection result generated by the dedicated computing node for the defect detection of image sub-blocks is received;

[0048] In one implementation, the allocation of the detection subtasks can be performed by performing task package allocation operations based on the load scores of each dedicated computing node. Specifically, the main industrial control computer can maintain a queue of tasks to be allocated, which contains detection task packages that have been packaged but not yet distributed. For each detection task package in the queue, the node with the highest load score is selected as the target node from the currently active dedicated computing nodes. If multiple nodes have the same load score, a round-robin or random selection method can be further used.

[0049] Since the allocation of subtasks is only directed to dedicated computing nodes in a valid state, in an exemplary embodiment of the present invention, the main industrial control computer can be used as the system monitoring center to monitor the status of all dedicated industrial control computer nodes in real time through heartbeat keep-alive, active status reporting, and timeout judgment, and to determine the validity of the dedicated computing nodes.

[0050] Specifically, each dedicated industrial control computer sends a heartbeat message to the main control computer at a fixed interval, containing the node ID, operating status, and load information; simultaneously, it proactively reports any data error detected on any node to the main industrial control computer. If no heartbeat signal is received from the first dedicated computing node within a preset first time threshold, or if no processing result for the assigned task is received from the first dedicated computing node within a preset second time threshold, the corresponding dedicated computing node is marked as abnormal.

[0051] The main industrial control computer preferably uses a point-to-point targeted transmission method to send the detection task package to the selected target node via a high-speed internal network. After the task is sent, the main industrial control computer updates the status of the task package to "sent" and increases the task queue length count of the target node in the resource status table accordingly to reflect the change in node load.

[0052] The load score can be calculated based on the real-time load status of each of the dedicated computing nodes. For example, in an exemplary embodiment, the dedicated computing nodes... The various load metrics are as follows: CPU utilization Memory usage GPU utilization Task queue length Average task processing latency Maximum length of task queue Maximum average processing time for tasks The load score can be expressed as:

[0053]

[0054] in, The weighting coefficients for each indicator satisfy the following conditions: ; This is a preset threshold for the task queue length. When the actual queue length exceeds this threshold, this item takes a value of 0. This is a preset average processing latency threshold for tasks. When the actual latency exceeds this threshold, this item is set to 0.

[0055] For dedicated computing nodes, in this embodiment of the invention, they can be configured with various image processing strategies that can be processed in parallel to adaptively process the distributed image sub-blocks. For example, the dedicated computing node can execute a first detection process based on image processing and a second detection process based on a deep learning model on the detection subtask, with the first and second detection processes executed in parallel. The detection results are then fed back to the main industrial control computer.

[0056] In one implementation, to reduce the amount of data transmitted back and decrease network load, only a small volume of structured data can be transmitted back after the image sub-blocks have been processed on a dedicated computing node. This structured data may include, but is not limited to, defect categories, the coordinates of the defects in various coordinate systems, sub-block labels, and timestamps.

[0057] It should be noted that, to ensure the real-time performance and accuracy of the load score, the main industrial control computer continuously updates the load status of each dedicated computing node during task allocation. Specifically, the main industrial control computer re-collects the load data of each node and recalculates the load score in each scheduling cycle to ensure that subsequent task allocation is based on the latest node status.

[0058] When a dedicated computing node completes its detection task and returns the results, the main industrial control computer synchronously updates the task queue length of that node in the resource status table, decrementing it by 1 to reflect the reduction in node load. This feedback mechanism enables the load score to dynamically reflect the real-time processing capacity of the node, forming a closed-loop control and further improving the accuracy and efficiency of load balancing.

[0059] S104: Merge all defect detection results to generate a defect distribution map.

[0060] In one implementation, to avoid blocking the scheduling process, the main industrial control computer can adopt a multi-threaded parallel processing approach, simultaneously receiving defect detection results from multiple dedicated computing nodes. Each result receiving thread independently processes the data stream of one node, avoiding the network latency of a single node from affecting the result reception of other nodes.

[0061] As mentioned earlier, the defect detection results fed back from the dedicated computing node include the defect category, the coordinates of the defect in each coordinate system, the sub-block number, and the timestamp. Based on this, the row and column coordinates of the sub-blocks and the relative coordinates of the defects within the sub-blocks are extracted from the defect detection results. According to the pre-established coordinate system mapping parameters, the relative coordinates of the defects within the sub-blocks can be converted into absolute coordinates in the global coordinate system of the wafer image, forming a complete spatial distribution view of defects.

[0062] It should be noted that, due to the grid-based segmentation strategy, adjacent sub-blocks may have slight overlap at their boundaries, or the same defect may be detected simultaneously by two adjacent sub-blocks if it happens to be located near a block boundary, resulting in duplicate reporting of the same defect. To address this issue, the present invention proposes the following implementation method:

[0063] In this implementation, the main controller can determine whether multiple defects are the same defect based on a combination of one or more of the following conditions. These conditions include, but are not limited to: whether the Euclidean distance between two defects is less than a preset distance threshold; whether the difference in the size parameters of the two defects is within a preset range; and whether the confidence scores of both defects are higher than a preset threshold.

[0064] For candidate pairs identified as duplicate defects, the main industrial control computer performs merging and deduplication operations. Specifically, in one implementation, a weighted average method can be used to calculate the fused defect coordinates. The weights can be determined based on the confidence scores of the two defects, with higher confidence scores carrying greater weights; or the defect coordinates with higher confidence scores can be directly selected as the final coordinates; the maximum value or weighted average of the two defect sizes is taken as the fused size; the confidence score of the fused defect is taken as the maximum value or weighted average of the two defect confidence scores; a unique identifier is assigned to the fused defect, and duplicate defect records are deleted.

[0065] After stitching, deduplication, and precise location of all defect information, the main industrial control computer generates the final defect distribution map. This map graphically presents the spatial distribution of defects across the entire wafer. Specifically, the main industrial control computer uses the wafer image as a base map and draws markers at the coordinate positions corresponding to the defects. Different defect categories can be distinguished using different colors or shapes of markers. The defect distribution map can be output in a two-dimensional image format or overlaid on the wafer physical layout diagram, allowing operators to intuitively understand the spatial distribution characteristics of defects.

[0066] Please refer to Figure 2 As shown, based on the same inventive concept as the aforementioned defect detection method, one embodiment of the present invention provides a defect detection system 200, including: an acquisition module 201, a decomposition module 202, a detection module 203, and a fusion module 204.

[0067] It should be noted that the defect detection method of this embodiment can be applied to the defect detection system 200 of this embodiment. The defect detection system 200 can be configured on a terminal. The terminal may include, but is not limited to, a PC (Personal Computer), a PDA (Tablet PC), a smartphone, a smart wearable device, etc.

[0068] Specifically, the acquisition module 201 is used to acquire a panoramic image of the wafer to be inspected and the real-time load status of each dedicated computing node; the decomposition module 202 is used to decompose the panoramic image into multiple image sub-blocks and generate a corresponding detection sub-task for each image sub-block; the detection module 203 is used to allocate the detection sub-task to the corresponding dedicated computing node based on the real-time load status of each dedicated computing node, and receive the defect detection results generated by the dedicated computing node for defect detection of the image sub-blocks; the fusion module 204 is used to fuse all defect detection results to generate a defect distribution map.

[0069] Please refer to Figure 3 As shown, embodiments of the present invention also provide an electronic device 300, which includes at least one processor 301, a memory 302 (e.g., non-volatile memory), a main memory 303, and a communication interface 304, and the at least one processor 301, memory 302, main memory 303, and communication interface 304 are connected together via an internal bus 305. At least one processor 301 is used to invoke at least one program instruction stored or encoded in the memory 302, so that the at least one processor 301 performs various operations and functions of the defect detection methods described in the various embodiments of this specification.

[0070] In the embodiments of this specification, the electronic device 300 may include, but is not limited to: personal computer, server computer, workstation, desktop computer, laptop computer, notebook computer, mobile electronic device, smartphone, tablet computer, cellular phone, personal digital assistant (PDA), handheld device, messaging device, wearable electronic device, consumer electronic device, etc.

[0071] This invention also provides a computer-readable medium carrying computer-executable instructions. When executed by a processor, these instructions can be used to implement various operations and functions of the defect detection methods described in the various embodiments of this specification.

[0072] The computer-readable medium in this invention can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0073] In this invention, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. This propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0074] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0075] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, systems, and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0076] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

[0077] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0078] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A defect detection method applied to semiconductor bare wafers, characterized in that, include: Acquire panoramic images of the wafer to be inspected and the real-time load status of each dedicated computing node; The panoramic image is decomposed into multiple image sub-blocks, and a corresponding detection sub-task is generated for each image sub-block; Based on the real-time load status of each dedicated computing node, the detection subtask is assigned to the corresponding dedicated computing node, and the defect detection results generated by the dedicated computing node for image sub-block defect detection are received. All defect detection results are merged to generate a defect distribution map.

2. The defect detection method according to claim 1, characterized in that, The step of decomposing the panoramic image into multiple image sub-blocks includes: The granularity of the panoramic image is determined based on the total resolution of the panoramic image and the number of dedicated computing nodes. Based on the block granularity, the panoramic image is divided into multiple image sub-blocks; wherein, if there are pixels in the image sub-blocks that exceed the effective area of ​​the wafer, the positions of the pixels that exceed the effective area of ​​the wafer are filled with zero values.

3. The defect detection method according to claim 2, characterized in that, The method further includes: Based on the positioning data of the motion platform and the pixel coordinates of the image acquisition card, a wafer physical coordinate system and an image pixel coordinate system are established. Determine the mapping relationship between the coordinate points in the wafer physical coordinate system and the image pixel coordinate system; Based on the specifications of the wafer to be inspected and the mapping relationship, the effective area for image acquisition is determined in the image pixel coordinate system, and the invalid background area at the edge of the wafer is removed.

4. The defect detection method according to claim 1, characterized in that, Based on the real-time load status of each dedicated computing node, the detection subtask is assigned to the corresponding dedicated computing node, including: A corresponding detection task package is determined for each of the detection subtasks, and the detection task package includes image sub-block pixel data and image sub-block spatial index; Based on the real-time load status of each dedicated computing node, a load score for each dedicated computing node is calculated, and the detection task package corresponding to the detection subtask is allocated to the dedicated computing node based on the load score of each dedicated computing node.

5. The defect detection method according to claim 1, characterized in that, The method further includes: Monitor the heartbeat status of each of the dedicated computing nodes; When the first dedicated computing node malfunctions, the detection subtasks that have been assigned to the first dedicated computing node but have not been processed will be reassigned to other normal dedicated computing nodes. The abnormal conditions include: not receiving a heartbeat signal from the first dedicated computing node within a preset first time threshold, or not receiving the processing result of the first dedicated computing node for the assigned task within a preset second time threshold.

6. The defect detection method according to claim 1, characterized in that, Dedicated computing nodes perform defect detection on assigned detection subtasks, including: A dedicated computing node performs a first detection process based on image processing and a second detection process based on a deep learning model on the detection subtask, with the first detection process and the second detection process being executed in parallel.

7. The defect detection method according to claim 1, characterized in that, The process of fusing all defect detection results to generate a defect distribution map includes: Receive defect detection results sent from each of the dedicated computing nodes, and sort and concatenate the defect detection results based on the spatial index in the defect detection results; For duplicate defects appearing at the boundaries of image sub-blocks, matching and merging are performed based on the coordinates, size, shape, and confidence level of the defects to remove duplicate records; The merged defect information is located in the wafer physical coordinate system to generate a defect distribution map.

8. A defect detection system, employing the defect detection method as described in any one of claims 1-7, characterized in that, include: The acquisition module is used to acquire panoramic images of the wafer to be inspected and the real-time load status of each dedicated computing node; The decomposition module is used to decompose the panoramic image into multiple image sub-blocks and generate a corresponding detection sub-task for each image sub-block; The detection module is used to allocate the detection subtasks to the corresponding dedicated computing nodes based on the real-time load status of each dedicated computing node, and to receive the defect detection results generated by the dedicated computing nodes for defect detection of image sub-blocks. The fusion module is used to merge all defect detection results to generate a defect distribution map.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory that stores instructions that, when executed by the at least one processor, cause the at least one processor to perform the defect detection method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the defect detection method according to any one of claims 1-7.

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