Semiconductor memory device

Abstract

The semiconductor storage device of the embodiment includes a storage area including a plurality of storage units, and a first circuit that calculates an error rate of a storage unit in which an error is detected, and performs recovery processing on the storage unit when the error rate is lower than a first value and higher than a second value.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on March 8, 2019, with application number 201910177108.0 and title "Semiconductor Memory Device".

[0003] [Related Applications]

[0004] This application claims priority to Japanese Patent Application No. 2018-218538 (filed on November 21, 2018). This application incorporates the entire contents of that basic application by reference. Technical Field

[0005] The implementation relates to a semiconductor memory device. Background Technology

[0006] MRAM (Magnetic Random Access Memory) is a storage device that uses magnetic elements with a magnetoresistive effect to store information. It is attracting attention as a next-generation storage device characterized by high speed, large capacity, and non-volatility. Furthermore, MRAM is being researched and developed as a replacement for volatile memories such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). In this context, it is ideal to make MRAM operate with the same specifications as DRAM and SRAM to control development costs and facilitate a smooth replacement. Summary of the Invention

[0007] The implementation provides a high-quality semiconductor memory device.

[0008] The semiconductor memory device according to the embodiment includes: a memory region having a plurality of memory cells; and a first circuit that calculates the error rate of the memory cells that have detected errors, and performs recovery processing on the memory cells when the error rate is lower than a first value and higher than a second value. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating the memory system of an implementation method.

[0010] Figure 2 This is a diagram showing a group of memory systems in an implementation scheme.

[0011] Figure 3It is a graph showing the relationship between the number of write operations and BER (Bit Error Ratio).

[0012] Figure 4 This is a graph showing the relationship between the membrane's charging-related cycles (number of write operations) and BER.

[0013] Figure 5 This is a flowchart illustrating the recovery process of the memory system in an implementation method. Detailed Implementation

[0014] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In this description, common parts will be marked with common reference numerals in all the drawings.

[0015] <1> Implementation Method

[0016] <1-1> Memory System

[0017] First, the memory system of the implementation method will be described. For example... Figure 1 As shown, the memory system includes a semiconductor memory device 1 and a host (or memory controller) 2. In this embodiment, the semiconductor memory device 1 is, for example, a spin-transfer-torque magnetoresistive random access memory (STT-MRAM).

[0018] like Figure 1 As shown, the semiconductor memory device 1 includes a memory core 11 and peripheral circuitry 12.

[0019] Storage core 11 has multiple storage units for data storage.

[0020] Peripheral circuitry 12 performs data writing and reading operations on the memory core 11. Peripheral circuitry 12 includes solder pads for receiving instructions, addresses, and data. Each solder pad has multiple solder pads. Peripheral circuitry 12 is connected to the host computer 2 via the solder pads and control signal lines CNT. Furthermore, peripheral circuitry 12 is connected to the host computer 2 via the solder pads and instruction / address lines CA<n:0>. Additionally, peripheral circuitry 12 is connected to the host computer 2 via the solder pads and data lines DQ<m:0>. n and m are natural numbers.

[0021] The control signal line CNT is used for transmitting and receiving control signals. Control signals include the clock signal CK / CKb, the clock enable signal CKE, and the chip select signal CS. The instruction / address lines CA<n:0> are used for transmitting and receiving instructions and addresses. DQ<m:0> are used for data transmission and reception between semiconductor memory device 1 and host 2.

[0022] In addition, the control signal line CNT, the instruction / address line CA<n:0>, and the data line DQ<m:0> can be either wiring that includes the pin or the pin itself.

[0023] <1-2> Semiconductor memory devices

[0024] use Figure 1 The semiconductor memory device 1 will be described.

[0025] <1-2-1> Storage Core

[0026] The memory core 11 of the semiconductor memory device 1 will be described. The memory core 11 includes a memory region 20, a row decoder 21, and a column decoder 22. The memory region 20 has (j+1) groups BK0 to BKj, where j is a natural number. For example, these groups BK0 to BKj can be used independently. In addition, when not distinguishing between groups BK0 to BKj, they are simply referred to as group BK.

[0027] The row decoder 21 decodes, for example, the group address BA<x:0> and the row address R<y:0>, wherein the group address BA<x:0> selects one of the groups BK0 to BKj, and the row address R<y:0> is used to select the row within the selected group.

[0028] The column decoder 22 decodes, for example, the column address C<z:0>, which is used to select a column within the storage area 20.

[0029] <1-2-2> Peripheral Circuits

[0030] The peripheral circuitry 12 of the semiconductor memory device 1 will be described. For example... Figure 1 As shown, the peripheral circuit 12 includes a first data latch circuit 23, a control circuit 24, an instruction latch circuit 25, an address latch circuit 26, an ECC (Error Correcting Code) circuit 27, a MUX (Multiplexer) 28, a delay circuit 29, a gate circuit 30, a second data latch circuit 31, and a comparator 32.

[0031] The first data latch circuit 23 temporarily stores input data received from the host 2 via the data line DQ<m:0>, or output data read from the selected group. Input data is written into the storage unit of the selected group.

[0032] The control circuit 24 controls the operation of the semiconductor memory device 1 based on the clock enable signal CKE, the chip select signal CS, and the instruction CMD from the host 2.

[0033] The instruction latch circuit 25 receives instructions CMD from the host 2 via the instruction / address lines CA<n:0> and temporarily stores these instructions CMD. The instructions CMD are then sent to the control circuit 24 and the ECC circuit 27.

[0034] Address latch circuit 26 receives address ADD. Address latch circuit 26 sends the group address and row address R<y:0> from address ADD to row decoder 21, and sends the column address C<z:0> to column decoder 22.

[0035] When writing data, the ECC circuit 27 generates a parity bit (error correction code) for the data to be written to the first data latch circuit 23 and appends the parity bit to the data to be written. The data with the parity bit appended is written into the memory cell array.

[0036] Furthermore, during data read operations, the ECC circuit 27 performs error correction processing on the data output from the memory cell array to the first data latch circuit 23. The ECC circuit 27 checks for errors in the data from the memory cell array using parity bit error correction processing. If a data error is detected, the ECC circuit 27 corrects the detected error. Alternatively, the ECC circuit 27 can also be located within the memory area 20 (group BK).

[0037] Furthermore, when the ECC circuit 27 determines that an error exists, it outputs an error detection signal DET at a "H (High)" level. Conversely, when the ECC circuit 27 determines that no error exists, it outputs an error detection signal DET at a "L (Low)" level.

[0038] The delay circuit 29 delays the address used when reading data, thus adjusting the timing.

[0039] MUX circuit 28 combines the data from ECC circuit 27 with the address obtained via delay circuit 29. This address corresponds to the address where the data was read.

[0040] When the gate circuit 30 receives the error detection signal DET at the "H" level from the ECC circuit, it will use the data and address combined by the MUX circuit 28 to transmit it to the second data latch circuit.

[0041] The second data latch circuit 31 stores the address and data of the failed bit. Furthermore, the second data latch circuit 31 stores the number of recovery processes N and the error rate (also denoted as BER (Bit Error Rate)) P as counter values. Additionally, recovery processing refers to the action of writing a random value to a memory cell. Furthermore, the error rate refers to the error occurrence rate of each memory cell.

[0042] Comparator 32 stores a threshold related to the number of recovery processes N or the error rate P, and compares it with the number of recovery processes or the error rate stored in the second data latch circuit 31.

[0043] Group BK (<1-2-3>)

[0044] Next, use Figure 2 The group BK of storage area 20 is described below. Group BK includes a read amplifier / write driver (SA / WD) 20b, a page buffer 20c, and a storage cell array 20a.

[0045] The read amplifier / write driver 20b is configured in the bit line direction of the memory cell array 20a. The read amplifier / write driver 20b includes a read amplifier and a write driver. The read amplifier reads the data stored in the memory cell MC by detecting the current flowing in the memory cell MC, which is connected to the bit line BL and the select word line WL. The write driver writes data by responding to the current flowing in the memory cell MC, which is connected to the bit line BL and the select word line WL. Furthermore, the read amplifier / write driver 20b controls the bit line BL and the source line SL based on control signals from the control circuit 24. Data transmission and reception between the read amplifier / write driver 20b and the data line DQ are performed via the data latch circuit 23.

[0046] Page buffer 20c temporarily holds data read from memory cell array 20a or data written to host 2. Data writing to memory cell array 20a is performed in multiple memory cell transistor units (page units). Thus, a unit written to memory cell array 20a at one time is called a "page". Furthermore, in this embodiment, page buffer 20c is provided in each group BK and has a storage capacity capable of temporarily storing data for all pages of group BK.

[0047] When writing data to the memory cell array 20a, the host 2 sends the page address indicating the write destination, the write data, and the write command to the semiconductor memory device 1. The control circuit 24 stores the write data received from the host 2 into the page buffer 20c and writes the write data in the page buffer 20c to the memory cell MC specified in the page address.

[0048] Furthermore, when reading data from the memory cell array 20a, the host 2 sends the page address indicating the read destination along with a read command to the semiconductor memory device 1. The control circuit 24 reads data from the memory cell MC specified in the page address to the page buffer 20c.

[0049] The memory cell array 20a is composed of multiple memory cells MC arranged in a matrix. The memory cell array 20a includes multiple word lines WL0~WLi-1, multiple bit lines BL0~BLj-1, and multiple source lines SL0~SLj-1. A row of the memory cell array 20a is connected via a word line WL, and a column of the memory cell array 20a is connected via a pair of lines consisting of a bit line BL and a source line SL.

[0050] The memory cell MC includes a magnetoresistive element (MTJ) 40 and a selection transistor 41. The selection transistor 41 is, for example, an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0051] One end of the MTJ element 40 is connected to the bit line BL, and the other end is connected to the drain (source) of the select transistor 41. The gate of the select transistor 41 is connected to the word line WL, and the source (drain) is connected to the source line SL.

[0052] Furthermore, the configuration of group BK is just one example; group BK may also have other configurations.

[0053] <1-3> bit fault

[0054] From the perspective of endurance (rewrite lifetime), bit faults in MRAM are as follows: Figure 3 As shown, they are mainly divided into three types: "hard breakdown," "soft error," and "membrane charging." Figure 3 The diagram shows the relationship between the number of loops (the number of write operations) and the BER.

[0055] "Hard breakdown" refers to an irreversible bit fault that occurs when the membrane inside the memory cell is damaged beyond a certain number of cycles (e.g., 1e7 times), resulting in an error rate of 1.

[0056] "Soft error" refers to a bit fault with a fixed error rate relative to the loop (e.g., 0.01).

[0057] "Membrane charging" refers to, for example, Figure 4 As shown, even with an increase in the error rate, reversible bit faults can recover (reduce) the error rate by applying additional stress (Y cycles) to the memory cell or ignoring them. The error rate of "membrane charging" is, for example, higher than 0.01 and lower than 1.

[0058] The charging of the membrane tends to occur at a stage earlier than hard breakdown (e.g., X times < 1e7). Therefore, the chip's durability is speed-limited by this charging phenomenon of the membrane.

[0059] Therefore, in this embodiment, a process to promote recovery is actively implemented for the storage cells that cause the membrane to charge.

[0060] <1-4> Actions

[0061] Next, use Figure 5 The recovery process of the memory system in this embodiment will be explained.

[0062] [S101]

[0063] After the host 2 sends a read request to the semiconductor storage device 1, the address of the object to be read is stored in the address latch circuit 26. For example, the read is performed in page units.

[0064] [S102]

[0065] The address stored in the address latch circuit 26 is transmitted to the row decoder 21, column decoder 22, and delay circuit 29. The control circuit 24 reads data from the storage area 20 based on the address stored in the address latch circuit 26.

[0066] [S103]

[0067] The data read from storage area 20 (read data) is transmitted to ECC circuit 27. ECC circuit 27 determines whether there are any errors in the read data.

[0068] If the ECC circuit 27 determines that the read data is error-free (S103, No), it outputs an "L" level error detection signal DET and the read data. The gate circuit 30 receives the "L" level error detection signal DET, thereby preventing the data from the MUX circuit 28 from being transmitted to the second data latch circuit 31. Furthermore, the read data is stored in the first data latch circuit 23.

[0069] [S104]

[0070] When the ECC circuit 27 determines that there is an error in the read data (S103, Yes), it outputs an error detection signal DET at the "H" level and corrects the error in the read data. When correcting the error in the read data, the ECC circuit 27 transmits the corrected read data to the first data latch circuit 23 and the MUX circuit 28.

[0071] [S105]

[0072] The MUX circuit 28 combines the corrected read data with the address used in reading the read data supplied via the delay circuit 29. Furthermore, the MUX circuit 28 supplies the corrected read data and address to the gate circuit 30.

[0073] The gate circuit 30 receives the error detection signal DET at the "H" level, thereby supplying the corrected read data and address to the second data latch circuit 31.

[0074] Therefore, the correlated corrected read data and address are stored in the second data latch circuit 31.

[0075] [S106]

[0076] The control circuit 24 determines whether the semiconductor storage device 1 is at a point in time when there are no read or write commands for the storage area 20.

[0077] [S107]

[0078] When the control circuit 24 determines that the semiconductor memory device 1 is inactive (S106, Yes), it performs multiple (e.g., 100) write and read operations on the address stored in the second data latch circuit 31.

[0079] Specifically, an address with an error is written to, and the written address is read out, with ECC circuit 27 used to determine if an error exists. Control circuit 24 calculates the error rate P associated with that address by repeating this action multiple times. Furthermore, after calculating the error rate P, control circuit 24 stores the error rate P in the second data latch circuit 31.

[0080] [S108]

[0081] Comparator 32 determines whether the error rate P stored in the second data latch circuit 31 is less than the first threshold stored in comparator 32. Specifically, comparator 32 determines whether the error rate P is less than 1. If comparator 32 determines that the error rate P is 1 (S108, No), it determines that the corresponding memory cell has experienced a "hard breakdown" and ends this operation. The reason is that, as mentioned above, after a "hard breakdown" occurs, the memory cell will not recover.

[0082] [S109]

[0083] If the comparator 32 determines that the error rate P is less than 1 (S108, Yes), it determines whether the error rate P stored in the second data latch circuit 31 is greater than the second threshold stored in the comparator 32. Specifically, the comparator 32 determines whether the error rate P is higher than 0.01. If the comparator 32 determines that the error rate P is less than 0.01 (S109, No), it determines that the corresponding memory cell has been recovered and ends this operation.

[0084] [S110]

[0085] If the error rate P is determined to be higher than 0.01 (S109, Yes), the control circuit 24 transfers the address for recovery processing from the second data latch circuit 31 to the address latch circuit 26. Based on this address, random write processing (recovery processing) is performed on the erroneous memory cell. This recovery processing typically involves approximately 1e3 to 1e6 write operations. This number can be appropriately varied. Furthermore, the memory cells containing the read address, i.e., the memory cell where the error occurred, are the targets of the recovery processing.

[0086] In addition, after the recovery process, the control circuit 24 stores the number of recovery processes N into the second data latch circuit 31.

[0087] [S111]

[0088] After the recovery process, comparator 32 determines whether the number of recovery processes N is less than the third threshold stored in comparator 32. If the number of recovery processes N exceeds the third threshold (S110, No), comparator 32 terminates the operation. If the number of recovery processes N is less than the third threshold (S110, Yes), comparator 32 repeats S106.

[0089] <1-5> Effects

[0090] According to the described embodiment, a storage area (second data latch circuit) is set up to store failure information (address, data). Referring to this information, when the memory is disabled, the faulty bit is actively written to, thereby recovering from the fault. The charging of the membrane has a higher error rate compared to soft errors but a lower error rate compared to hard breakdowns. Therefore, memory cells that fail during reading are detected using ECC or similar methods, and writing and reading are repeatedly performed. For example, when the error rate P is 0.01 < P < 1, it is considered membrane charging, and recovery processing is repeatedly performed on the faulty bit (additional writing at 1e3 to 1e6 cycle levels) until P decreases to P < 0.01. Furthermore, the recovery process ends when recovery is determined (P < 0.01), when the process completely fails (P = 1), or when the total number of recovery processing times N exceeds the upper limit (N > 10^7 cycles).

[0091] <2> Examples of variations, etc.

[0092] Furthermore, in the described embodiment, the recovery process targets multiple memory cells, including the read unit, i.e., the memory cell that experienced the error. In other words, recovery processing is also performed on memory cells that did not experience errors. However, it is also possible to perform recovery processing only on the memory cells that experienced errors.

[0093] Specifically, when the ECC circuit 27 detects an error, it generates a bit masking signal. This bit masking signal only allows writing to the memory cell in the error correction unit where the error has occurred. This bit masking signal is used to prevent writing to the target memory cell. The act of not writing to the memory cell is expressed as "masking," etc.

[0094] After error correction, ECC circuit 27 supplies bit masking signal and corrected data to MUX circuit 28.

[0095] The MUX circuit 28, in the same manner as described in the embodiment, merges the corrected data with the address associated with the corrected data, and further merges the bit masking signal. Furthermore, the MUX circuit 28 supplies the corrected readout data, address, and bit masking signal to the gate circuit 30.

[0096] The gate circuit 30 receives the error detection signal DET at the "H" level, thereby supplying the corrected read data, address and bit masking signal to the second data latch circuit 31.

[0097] Thus, the correlated corrected readout data, address, and bit masking signal are stored in the second data latch circuit 31.

[0098] Furthermore, during recovery processing, the control circuit 24 can prevent recovery processing of memory cells for which no errors were detected by using a bit masking signal.

[0099] Therefore, it is possible to suppress excessive write stress on memory cells where errors are not detected.

[0100] The configuration of the group shown in the various embodiments is an example and can be modified in various ways. For example, the memory cell array can also be constructed as follows: a two-terminal switching element with switching function is used instead of the three-terminal selection transistor to select a memory cell by means of a group of one bit line BL and one word line WL.

[0101] The standard for the semiconductor memory device used in the implementation can be the JEDEC memory standard such as LPDDR (Low Power Double Data Rate) and DDR (Double Data Rate), or it can be a memory not based on a specific standard.

[0102] In the various embodiments described above, MRAM using magnetoresistive elements has been used as an example of a semiconductor memory device, but it is not limited to this. It can be applied to various semiconductor memory devices, not limited to volatile memory and non-volatile memory. In addition, it can also be applied to resistive change memory of the same type as MRAM, such as ReRAM (Resistive Random Access Memory) and PCRAM (Phase-Change Random Access Memory).

[0103] The embodiments of the present invention have been described above, but the present invention is not limited to the described embodiments, and various changes can be made without departing from its spirit. Moreover, the described embodiments include inventions at various stages, and various inventions can be obtained by appropriately combining the disclosed constituent elements. For example, even if some constituent elements are deleted from the disclosed constituent elements, as long as a specific effect is obtained, it can be obtained as an invention.

[0104] [Explanation of Symbols]

[0105] 1 Semiconductor memory device

[0106] 2 hosts

[0107] 11 storage cores

[0108] 12 Peripheral Circuits

[0109] 20 storage areas

[0110] 20a memory cell array

[0111] 20b Read Amplifier / Write Driver

[0112] 20c buffer

[0113] 21-line decoder

[0114] 22-column decoder

[0115] 23 Data latch circuit

[0116] 24 control circuits

[0117] 25 Instruction Latch Circuit

[0118] 26-address latch circuit

[0119] 27ECC circuit

[0120] 28MUX circuit

[0121] 29 Delay Circuits

[0122] 30 gate circuit

[0123] 31 Data latch circuit

[0124] 32 comparator

[0125] 40MTJ components

[0126] 41 Select Transistor

Claims

1. A semiconductor memory device comprising: Multiple storage units; and The first circuit is configured as follows: Data is read from a subset of the storage units. Determine whether the data read from the subset contains errors. If the subset contains errors, calculate the bit error rate of the subset, and If the calculated bit error rate is less than the first threshold but greater than the second threshold, the subset is restored. The first circuit includes an error correction code circuit configured to determine whether the data read from the subset contains an error. The error correction code circuit is configured to generate a bit masking signal, through which the subset performs recovery processing only on the specific memory cells where errors were detected.

2. The semiconductor memory device according to claim 1, wherein, The first circuit calculates the bit error rate by repeatedly writing data to and reading data from the subset.

3. The semiconductor memory device according to claim 1, wherein, The first circuit is configured such that when the calculated bit error rate is greater than the first threshold, the recovery process is not performed on the subset.

4. The semiconductor memory device according to claim 1, wherein, The first circuit is configured such that when the calculated bit error rate is less than or equal to the second threshold, the recovery process is not performed on the subset.

5. The semiconductor memory device according to claim 1, wherein, The first circuit includes a comparator that stores the first threshold and the second threshold.

6. The semiconductor memory device according to claim 1, wherein, The recovery process includes repeatedly writing random data into the subset.

7. The semiconductor memory device according to claim 6, wherein, The number of times random data is repeatedly written to the subset is limited to a predetermined upper limit.

8. The semiconductor memory device according to claim 1, wherein, The subset is: the page units of the plurality of storage units.

9. The semiconductor memory device according to claim 1, wherein, The plurality of storage units are: magnetoresistive random access memory units.

10. The semiconductor memory device according to claim 1, wherein, The first circuit is configured to perform the recovery process during the idle state of the semiconductor memory device.

11. A semiconductor memory device comprising: Multiple storage units; The peripheral circuitry, including the error correction code circuitry and the comparator, is configured as follows: Data is read from a subset of the storage units. The output of the error correction code circuit is used to detect whether the data read from the subset contains errors. When the subset contains errors, the bit error rate of the subset is calculated by repeatedly writing and reading data from the subset and checking the total number of invalid bits in the subset after each write. When the comparator indicates that the calculated bit error rate is greater than or equal to a first threshold stored in the comparator, a hard breakdown defect is determined to have occurred. When the comparator indicates that the calculated bit error rate is less than the first threshold but greater than the second threshold stored in the comparator, the subset is restored by means of: repeatedly writing random data into the subset, up to a predetermined upper limit for repeated writing.

12. The semiconductor memory device according to claim 11, wherein, The peripheral circuitry is configured to calculate the bit error rate and perform the recovery process during the idle state of the semiconductor memory device.

13. The semiconductor memory device according to claim 11, wherein, The error correction code circuit is configured to generate a bit masking signal, through which the subset performs recovery processing only on the specific memory cells where errors were detected.

14. The semiconductor memory device of claim 11, wherein, The subset is: the page units of the plurality of storage units.

15. A method for operating a semiconductor memory device having a plurality of memory cells, the method comprising: Data is read from a subset of the plurality of storage units; The error correction circuit outputs a method to detect whether the data read from the subset contains errors. When the subset contains errors, the bit error rate of the subset is calculated by repeatedly writing and reading data into the subset and detecting the total number of invalid bits in the subset after each write. When the calculated bit error rate is greater than or equal to the first threshold, it is determined that a hard breakdown has occurred. When the calculated bit error rate is less than the first threshold but greater than the second threshold, the subset is restored. The restoration process includes: repeatedly writing random data into the subset, up to a predetermined upper limit for repeated writing.

16. The method according to claim 15, wherein, The calculation of the bit error rate and the recovery process are controlled to occur during the idle state of the semiconductor memory device.

17. The method of claim 15, further comprising: generating a bit masking signal, wherein the subset performs recovery processing only on specific memory cells for which errors were detected, using the bit masking signal.

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