Memory devices and operations thereof

Abstract

A memory device includes an array of memory cells in a plurality of memory strings and arranged in a plurality of rows of memory cells. The memory device also includes a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform a read operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line, wherein the peripheral circuit is configured to apply a word line voltage on each of the plurality of word lines and determine a highest threshold voltage of the plurality of rows of memory cells based on a change in a word line capacitance load in response to the word line voltage.

Description

[0001] This application is a divisional application of the invention patent application filed on December 14, 2021, with application number 202180004725.6 and title "Memory Device and Operation Thereof". Background Technology

[0002] This disclosure relates to memory devices and their operating methods.

[0003] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed on flash memory, such as reading, programming (writing), and erasing, to change the threshold voltage of each memory cell to a desired level. For NAND flash memory, erase operations can be performed at the block level, and programming or reading operations can be performed at the page level. Summary of the Invention

[0004] In one aspect, a memory device includes an array of memory cells, the memory cells being arranged in multiple memory strings and multiple rows of memory cells. The memory device also includes multiple word lines respectively coupled to the multiple rows of memory cells, and peripheral circuitry coupled to the multiple word lines and configured to perform a read operation on a selected row of memory cells among the multiple rows of memory cells. The selected row of memory cells is coupled to the selected word line, wherein the peripheral circuitry is configured to apply a word line voltage to each of the multiple word lines and determine a highest threshold voltage of the multiple rows of memory cells based on a change in word line capacitive load in response to the word line voltage.

[0005] In another aspect, a system includes a memory device configured to store data. The memory device includes: an array of memory cells arranged in multiple memory strings and multiple rows of memory cells; multiple word lines coupled to the multiple rows of memory cells; and peripheral circuitry coupled to the multiple word lines and configured to perform a read operation on a selected row of memory cells among the multiple rows of memory cells. The selected row of memory cells is coupled to the selected word line. The peripheral circuitry is configured to apply a word line voltage to each of the multiple word lines and determine a highest threshold voltage of the multiple rows of memory cells based on changes in word line capacitive load in response to the word line voltage. The system also includes a memory controller coupled to the memory device and configured to control the memory device.

[0006] In another aspect, a method for operating a memory device includes: an array of memory cells arranged in multiple memory strings and multiple rows of memory cells; and multiple word lines respectively coupled to the multiple rows of memory cells. The method includes performing a read operation on a selected row of memory cells among the multiple rows of memory cells. The selected row of memory cells is coupled to the selected word line. Performing the read operation includes: applying a word line voltage on each of the multiple word lines, and determining a highest threshold voltage of the multiple rows of memory cells based on a change in word line capacitive load in response to the word line voltage. Attached Figure Description

[0007] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0008] Figure 1 The threshold voltage distribution of memory cells in a memory device is shown.

[0009] Figure 2 Timing diagrams of multiple voltages used in read operations in a memory device according to some aspects of this disclosure are shown.

[0010] Figure 3 A block diagram of an exemplary system having a memory device is shown, according to some aspects of this disclosure.

[0011] Figure 4A A diagram of an exemplary memory card having a memory device is shown, according to some aspects of this disclosure.

[0012] Figure 4B A diagram of an exemplary solid-state drive (SSD) having a memory device is shown, according to some aspects of this disclosure.

[0013] Figure 5 A schematic diagram of an exemplary memory device including peripheral circuitry is shown, according to some aspects of this disclosure.

[0014] Figure 6 A side view of a cross section of an exemplary memory cell array including NAND memory strings is shown, according to some aspects of this disclosure.

[0015] Figure 7A A block diagram of an exemplary memory device including a memory cell array and peripheral circuitry is shown, according to some aspects of this disclosure.

[0016] Figure 7BA detailed block diagram of control logic in an exemplary memory device, including a memory cell array and peripheral circuitry, is shown according to some aspects of this disclosure.

[0017] Figure 8A An exemplary voltage generator is shown in accordance with some aspects of this disclosure.

[0018] Figure 8B Exemplary reference signals and word line voltages are shown according to some aspects of this disclosure.

[0019] Figure 8C An exemplary sensing device is shown in accordance with some aspects of this disclosure.

[0020] Figure 9A An exemplary word line capacitive load coupled to a voltage generator according to some aspects of this disclosure is shown.

[0021] Figure 9B The capacitance of a word line capacitive load as a function of word line voltage is shown according to some aspects of this disclosure.

[0022] Figure 10A A flowchart of a method for operating a memory device according to some aspects of this disclosure is shown.

[0023] Figure 10B A flowchart illustrating detailed operations performed by a memory device according to some aspects of this disclosure is shown.

[0024] The contents of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0025] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other, and in a manner not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0026] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a” or “described” can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0027] In some memory devices, such as 3D NAND flash memory devices, memory cells are formed by the intersection of word lines and semiconductor channels. A memory cell can be programmed to have multiple states (e.g., threshold voltages) and thus can store multiple bits of data per cell. In triple-level cell (TLC) flash memory devices, memory cells can be programmed to include eight threshold voltages (e.g., L0, L1, ..., L7) to store 3 bits of data; and in quad-level cell (QLC) flash memory devices, memory cells can be programmed to include sixteen threshold voltages (e.g., L0, L1, ..., L15) to store 4 bits of data. During a read operation in a 3D NAND flash memory device, all word lines need to be ramped up to high word line voltages to fully conduct the semiconductor channel. The critical voltage for the read operation is the highest threshold voltage used to program the memory cell. For example, for TLC and QLC flash memory devices, the highest threshold voltage could be the L7 threshold voltage and the L15 threshold voltage, respectively. When the word line voltage reaches the maximum threshold voltage, certain operations can be performed based on the time it takes for the word line voltage to reach the maximum threshold voltage and / or the value of the maximum threshold voltage. The maximum threshold voltage can be a critical transition point during the ramp-up process, and is therefore highly desirable for read operations performed on 3D NAND memory devices.

[0028] This transition point can be used to trigger other array operations. For example, the timing of when the word line voltage reaches the highest threshold voltage is crucial. As the word line voltage increases, the select gates of the semiconductor channels, such as the source select gate (e.g., bottom-select gate or BSG) and drain select gate (top-select gate or TSG), are also turned on to allow all semiconductor channels to undergo a "reset," such as a clearing process to remove unwanted carriers from the semiconductor channels to avoid hot carrier injection (HCI). After the word line voltage reaches the highest threshold voltage, the non-selected select gates can then be turned off. Power consumption can be reduced, and the semiconductor channels can be tuned for data access during read operations. During a read operation, a high voltage is applied to the non-selected word line, for example, a pass voltage (Vpass) determined based on the highest threshold voltage. Vpass is typically determined (e.g., optimized) by adding an overdrive voltage to the highest threshold voltage. An optimized Vpass can reduce read interference during read operations. Furthermore, memory cells can lose charge over time. This phenomenon is also known as retention charge loss. Threshold voltage distributions (especially higher threshold voltage distributions) can be shifted downwards over time, for example, towards lower voltage distributions. Retention information can be obtained based on the highest threshold voltage of the memory cell. For example, the shift of the highest threshold voltage can be used to adjust the read reference voltage used for reading data. This helps reduce read errors during read operations.

[0029] Typically, the highest threshold voltage of a memory cell is measured after the memory device is manufactured, and other voltages and timings are designed based on the measurement results. However, the measured value of the highest threshold voltage lacks accuracy for at least the following reasons. For example, the driver used to drive the word line may cause a voltage drop in the word line voltage. This voltage drop can vary based on design and factors such as processing, voltage, and temperature. Therefore, the Vpass applied to a non-selected word line may not be accurate enough to reduce interference during read operations. Furthermore, when a read reference voltage is applied between adjacent threshold voltages to read data from a memory cell, the shift in the threshold voltage distribution may require changing / adjusting the read reference voltage from its manufacturer's value so that the read reference voltage has sufficient margin with respect to adjacent threshold voltages for accurate read operations. That is, a read reference voltage set at the manufacturer's location may be prone to read errors if not adjusted over time during use.

[0030] Figure 1The diagram illustrates the threshold voltage distribution in a memory device (e.g., a 3D NAND flash memory device) at two different times. The x-axis represents the threshold voltage values, and the y-axis represents the cell distribution. As an example, distribution 102 represents the threshold voltage distribution of a TLC or QLC memory cell at time t1, and distribution 104 represents the threshold voltage distribution of a TLC or QLC memory cell at time t2. Time t1 represents the earlier time. t1 This represents the minimum threshold voltage for an erase operation, such as L0 for TLC and QLC memory cells. tn This represents the highest threshold voltage, for example, L7 in a TLC memory cell and L15 in a QLC memory cell. Time t2 can be a time after t1, and the interval between time t2 and t1 is greater than 0, for example, several hours, a week, a month, several months, etc. At time t1, the respective read reference voltage V located between adjacent threshold voltage distributions is... R1 and V R2 Apply to the selected word line to perform a read operation. For example... Figure 1 As shown, compared to time t1, the threshold voltage distribution 104 shifts to a lower voltage distribution and becomes wider at time t2. Consequently, the reference voltage V is read... t1 and V t2 There may not be sufficient margin for adjacent threshold voltages, and the read reference voltage V is used. t1 and V t2 Read operations may be susceptible to read errors.

[0031] Figure 2 A timing diagram illustrating multiple voltages used in a read operation of a memory device according to this disclosure is shown. The memory device may include a 3D NAND flash memory device. Specifically, time T1 to time T2 can be considered as the initialization or reset time period of the read operation. During this time period, the channel structure undergoes a reset or initialization process, and certain voltages begin to ramp up and reach their respective initialization values. Time T2 to time T3 can be considered as a fine-tunable delay time period. At time T2, the initialization / reset process is complete, and the voltage begins to change and approaches the value for reading data from the memory cell. At time T3, the voltage reaches the value used for reading data. Starting from time T3, data is read from the memory cell formed by the channel structure. Figure 2As shown, during a read operation, the voltage applied to the bit line (“BL”) and source line (“ACS”) is low to turn off the bit line and source line. The voltage on the select gates in the memory block (e.g., selected drain select gate (“DSG(sel)”), non-selected drain select gate corresponding to the selected bottom select gate (“DSG(unsel)”), non-selected drain select gate corresponding to the non-selected source select gate (“DSG(unsel)”), selected source select gate (“SSG(sel)”), and non-selected source select gate (“SSG(unsel)”)) begins to increase from a low value to a high value (e.g., the on-state voltage value). Between time T1 and T2, the voltage applied to the aforementioned select gates reaches the corresponding high value and remains high for a period of time for initialization / reset of the channel structure.

[0032] The word line voltage, i.e., the voltage applied to the word line, the selected word line (“WL(sel)”), and the unselected word line (“WL(unsel)”), also increases from a lower value at time T1 and reaches a higher value V1 at time T2. The value of V1 can be equal to or higher than the highest threshold voltage of the memory cell. At time T2, the voltages on DSG(unsel) in the selected SSG, DSG(unsel) in the unselected SSG, and SSG(unsel) begin to decrease, reaching a low value (e.g., the shutdown voltage value) by time T3, while the voltages on DSG(sel) and SSG(sel) remain high (e.g., the turn-on voltage value) for the remainder of the read operation. At time T2, the channel structure is turned on and reset / initialized from ACS and BL. Starting from time T2, the voltage on WL(sel) begins to decrease to a low value (e.g., the shutdown voltage value), while the voltage on WL(unsel) increases to a higher value V2 by time T3. V2 is also referred to as the Vpass voltage. The voltage of V2 applied to WL (unsel) is maintained during the remaining read operations.

[0033] In some memory devices, the value of V1 is measured after the memory device is manufactured. V1, equal to or sufficiently close to the highest threshold voltage of the memory cell, is used to determine time T2, for example, when certain select gates are turned off. For instance, when the word line voltage reaches V1, certain select gates are turned off. Simultaneously, the value of V1 is also used to determine the value V2. For example, V2 is typically determined by adding an overdrive value ΔV to V1. Because V1 is a value measured after manufacturing and does not represent a shift in the threshold voltage distribution within the memory cell over time, some parameters determined based on V1 (such as the time when certain select gates are turned off, the value of V2, and one or more read reference voltages) may be inaccurate. A more accurate determination of the highest threshold voltage is desired.

[0034] To address one or more of the aforementioned problems, this disclosure provides a memory device and method for obtaining a highest threshold voltage of a memory cell at a desired time. The method may include an automatic detection scheme, wherein the highest threshold voltage can be obtained in real time, or it can be obtained at a desired time and stored for the next read operation. The time at which the word line voltage reaches the highest threshold voltage and the value of the highest threshold voltage can be more accurate. Therefore, the value of the highest threshold voltage and the time at which the word line voltage reaches the highest threshold voltage can be used to determine other parameters (e.g., the time for turning off certain select gates, the value of Vpass, and the value of the read reference voltage), which can also be more accurate. Read operations performed in the memory device are less susceptible to interference and errors.

[0035] According to this disclosure, when the word line voltage increases, the word line capacitive load formed by the word line and channel structure can be equivalent to a variable capacitor. When the word line voltage reaches the highest threshold voltage, the capacitance reaches its maximum value, i.e., the maximum capacitance. The capacitance of the word line capacitive load can remain constant or decrease further after reaching the maximum capacitance. By detecting the capacitance change of the word line capacitive load, the time when the word line voltage reaches the highest threshold voltage and the value of the highest threshold voltage can be obtained in real time.

[0036] To automatically detect capacitance changes in the word line capacitive load, a voltage generator pumps the output word line voltage. The voltage generator includes a comparator circuit that allows the voltage generator to gradually increase the word line voltage until a maximum threshold voltage is reached, for example, the maximum capacitance of the word line capacitive load. A sensing device is used to detect the capacitance change in the word line capacitive load at each step. The control logic of the memory device is used to compare the capacitance changes at two adjacent values ​​of the word line voltage. When a maximum capacitance change is detected, the maximum capacitance is detected. Therefore, the word line voltage corresponding to the maximum capacitance is determined as the maximum threshold voltage. Then, the control logic controls other operations based on the time it takes for the word line voltage to reach the maximum threshold voltage and the value of the maximum threshold voltage.

[0037] In some embodiments, the sensing device includes a counter. The counter is coupled to a voltage generator and has a flag signal input indicating the pumping time of the voltage generator at each step. The counter's output includes multiple values, each indicating the pumping time of the voltage generator at the corresponding step. Because the pumping time of each step is associated with the capacitance charged to the word line capacitive load during the corresponding step, the counter's output represents the capacitance change of the word line capacitive load at each step. In some embodiments, the counter includes an AND gate coupled to multiple flip-flops. In other embodiments, the memory device includes a sensing device configured to detect the current flowing from the voltage generator to the word line capacitive load. Control logic may determine a maximum threshold voltage based on the current.

[0038] Figure 3 A block diagram of an exemplary system 300 having a memory device according to some aspects of this disclosure is shown. System 300 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 3 As shown, system 300 may include host 308 and memory system 302, the memory system 302 having one or more memory devices 304 and memory controller 306. Host 308 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). Host 308 may be configured to send data to or receive data from memory device 304.

[0039] Memory device 304 can be any memory device disclosed herein. As detailed below, memory device 304, such as a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device), can automatically obtain the highest threshold voltage of the memory cell at a desired time and determine other operations based on the timing and value of the threshold voltage. In some embodiments, memory device 304 obtains the highest threshold voltage of the memory cell as part of each read operation. In some embodiments, memory device 304 obtains the highest threshold voltage of the memory cell and stores that highest threshold voltage for subsequent read operations.

[0040] According to some embodiments, a memory controller 306 is coupled to a memory device 304 and a host 308 and is configured to control the memory device 304. The memory controller 306 can manage data stored in the memory device 304 and communicate with the host 308. In some embodiments, the memory controller 306 is designed to operate in low-duty-cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 306 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multi-media cards (eMMCs), which serve as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 306 can be configured to control the operation of the memory device 304, such as read, erase, and program operations. The memory controller 306 can also be configured to manage various functions relating to data stored or to be stored in the memory device 304, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 306 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory device 304. The memory controller 306 can also perform any other suitable functions, such as formatting the memory device 304. The memory controller 306 can communicate with external devices (e.g., host 308) according to specific communication protocols.For example, the memory controller 306 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, PCI (Peripheral Component Interconnection), PCI-E, ATA (Advanced Technology Attachment), Serial ATA, Parallel ATA, SCSI (Small Computer Small Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), and Firewire.

[0041] The memory controller 306 and one or more memory devices 304 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 302 can be implemented and packaged into different types of end electronic products. Figure 4A In one example shown, the memory controller 306 and a single memory device 304 can be integrated into the memory card 402. The memory card 402 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 402 may also include features for connecting the memory card 402 to a host computer (e.g., ...). Figure 3 The host 308 in the memory card connector 404 is coupled to the host 308. In such a way... Figure 4B In another example shown, the memory controller 306 and multiple memory devices 304 can be integrated into the SSD 406. The SSD 406 may also include components for connecting the SSD 406 to a host computer (e.g., ...). Figure 3 The SSD connector 408 is coupled to the host 308 in the memory card 402. In some embodiments, the storage capacity and / or operating speed of the SSD 406 is greater than that of the memory card 402.

[0042] Figure 5 A schematic circuit diagram of an exemplary memory device 500, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 500 may be... Figure 3 An example of memory device 304 is shown. Memory device 500 may include a memory cell array 501 and peripheral circuitry 502 coupled to the memory cell array 501. The memory cell array 501 may be a NAND flash memory cell array, wherein memory cells 506 are provided in the form of an array of NAND memory strings 508, each NAND memory string 508 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 508 includes a plurality of memory cells 506 coupled in series and stacked vertically. Each memory cell 506 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 506. Each memory cell 506 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0043] In some implementations, each memory cell 506 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 506 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0044] like Figure 5As shown, each NAND memory string 508 may include a source-select gate (SSG) 510 at its source end and a drain-select gate (DSG) 512 at its drain end. The SSG 510 and DSG 512 can be configured to initiate selected NAND memory strings 508 (columns of the array) during read and program operations. In some embodiments, the SSG 510 is also referred to as a BSG, and the DSG 512 is also referred to as a TSG. In some embodiments, the sources of the NAND memory strings 508 in the same block 504 are coupled via the same source line (SL) 514 (e.g., a common SL). That is, according to some embodiments, all NAND memory strings 508 in the same block 504 have an array common source (ASC). According to some embodiments, the DSG 512 of each NAND memory string 508 is coupled to a corresponding bit line 516, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 508 is configured to be selected or unselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 512) or a deselection voltage (e.g., 0V) to the corresponding DSG 512 via one or more DSG lines 513 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 510) or a deselection voltage (e.g., 0V) to the corresponding SSG 510 via one or more SSG lines 515.

[0045] like Figure 5 As shown, NAND memory strings 508 can be organized into multiple blocks 504, each block 504 may have, for example, a common source line 514 coupled to the ACS. In some embodiments, each block 504 is a basic data unit for erase operations, i.e., all memory cells 506 on the same block 504 are erased simultaneously. In some embodiments, each word line 518 is coupled to a page 520 of memory cells 506, a page being a basic data unit for programming and reading operations. Memory cells 506 of adjacent NAND memory strings 508 can be coupled via word lines 518, which select which row of memory cells 506 is affected by read and programming operations. The size of a page 520, in bits, can be related to the number of NAND memory strings 508 coupled by word lines 518 in a block 504. Each word line 518 may include multiple control gates (gate electrodes) at each memory cell 506 in the corresponding page 520 and gate lines coupling the control gates.

[0046] During a read operation, data stored on page 520 can be accessed. (Return to reference) Figure 2 When a read operation begins, bit lines 516 and source lines 514 in block 504 are biased at a low voltage (e.g., ground (GND)), and the voltages on all select gates (e.g., SSG 510 and DSG 512) and word lines (e.g., word line 518) in block 504 begin to ramp up. After the voltage on the select gates reaches its corresponding high voltage, the voltage is maintained for a period of time for channel reset / initialization. When the voltage on the word lines reaches the highest threshold voltage of memory cell 506, the voltage on the unselected select gates may begin to decrease to a low voltage, the voltage on the selected select gates (e.g., the select gate for selecting page 520) remains at its corresponding high voltage, the voltage on the selected word lines (e.g., word line 518 coupled to page 520) begins to decrease to a low voltage, and the voltage on the unselected word lines continues to increase to Vpass. After the voltage on the unselected word lines reaches Vpass, page 520 is opened, and the data stored in page 520 can be accessed. In some implementations, a threshold voltage of memory cell 506 is compared with a read reference voltage to determine the stored data. In some implementations, peripheral circuitry 502 detects when the voltage on word line 518 reaches the highest threshold voltage and changes the voltage on the selection gate (e.g., non-selected SSG 510 and DSG 512). Peripheral circuitry 502 also determines the values ​​of Vpass and the read reference voltage based on the value of the highest threshold voltage. Bits in the flash memory cell are read by changing the voltages on the rows and columns of the memory cell and then evaluating the results. In a page read operation, data stored in page 520 is moved from memory cell array 501 into an output data register.

[0047] Figure 6 A side view of a cross-section of an exemplary memory cell array 501 including NAND memory strings 508, according to some aspects of this disclosure, is shown. Figure 6 As shown, the NAND memory string 508 may extend vertically through the memory stack 604 above the substrate 602. The substrate 602 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0048] The memory stack 604 may include staggered gate conductive layers 606 and gate-to-gate dielectric layers 608. The number of pairs of gate conductive layers 606 and gate-to-gate dielectric layers 608 in the memory stack 604 determines the number of memory cells 506 in the memory cell array 501. The gate conductive layers 606 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 606 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 606 includes a doped polysilicon layer. Each gate conductive layer 606 may include a control gate surrounding the memory cell 506 and may extend laterally as a DSG line 513 at the top of the memory stack 604, an SSG line 515 at the bottom of the memory stack 604, or a word line 518 between DSG lines 513 and SSG lines 515.

[0049] like Figure 6 As shown, the NAND memory string 508 includes a channel structure 612 extending vertically through the memory stack 604. In some embodiments, the channel structure 612 includes channel holes filled with one or more semiconductor materials (e.g., as semiconductor channel 620) and one or more dielectric materials (e.g., as memory film 618). In some embodiments, the semiconductor channel 620 includes silicon, such as polysilicon. In some embodiments, the memory film 618 is a composite dielectric layer including a tunneling layer 626, a storage layer 624 (also referred to as a "charge trap / storage layer"), and a barrier layer 622. The channel structure 612 may have a cylindrical shape (e.g., columnar). According to some embodiments, the semiconductor channel 620, tunneling layer 626, storage layer 624, and barrier layer 622 are arranged radially from the center of the column toward the outer surface in this order. The tunneling layer 626 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 624 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 622 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 618 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0050] like Figure 6As shown, according to some embodiments, a well 614 (e.g., a p-well and / or an n-well) is formed in a substrate 602, and the source terminal of the NAND memory string 508 is in contact with the well 614. For example, a source line 514 may be coupled to the well 614 to apply an erase voltage to the well 614 (i.e., the source of the NAND memory string 508) during an erase operation. In some embodiments, the NAND memory string 508 also includes a channel plug 616 at the drain terminal of the NAND memory string 508. It should be understood that, although Figure 6 Additional components that may form the memory cell array 501, but not shown in the diagram, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0051] Return to reference Figure 5 Peripheral circuitry 502 can be coupled to memory cell array 501 via bit line 516, word line 518, source line 514, SSG line 515, and DSG line 513. Peripheral circuitry 502 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 501 by applying voltage and / or current signals to each target memory cell 506 via bit line 516, word line 518, source line 514, SSG line 515, and DSG line 513, and by sensing voltage and / or current signals from each target memory cell 506. Peripheral circuitry 502 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 7A The diagram illustrates some exemplary peripheral circuitry, including a page buffer / sensor amplifier 704, a column decoder / bit line driver 706, a row decoder / word line driver 708, a voltage generator 710, control logic 712, a register 714, an interface 716, a data bus 718, and a sensing device 720. It should be understood that in some examples, additional peripheral circuitry may also be included. Figure 7A Additional peripheral circuitry not shown.

[0052] Page buffer / sensor amplifier 704 can be configured to read data from memory cell array 501 and program (write) data to memory cell array 501 according to control signals from control logic 712. In one example, page buffer / sensor amplifier 704 can store one page of programming data (write data) in one page 520 to be programmed into memory cell array 501. In another example, page buffer / sensor amplifier 704 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 506 coupled to selected word line 518. In yet another example, page buffer / sensor amplifier 704 can also sense a low-power signal from bit line 516 representing a data bit stored in memory cell 506 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 706 can be configured to be controlled by control logic 712 and select one or more NAND memory strings 508 by applying a bit line voltage generated from voltage generator 710.

[0053] The row decoder / word line driver 708 can be configured to be controlled by control logic 712 and select / deselect block 504 and select / deselect word line 518 of block 504 in memory cell array 501. The row decoder / word line driver 708 can also be configured to drive word line 518 using word line voltages generated from voltage generator 710. In some embodiments, the row decoder / word line driver 708 can also select / deselect and drive SSG line 515 and DSG line 513. As described in detail below, the row decoder / word line driver 708 is configured to perform an erase operation on memory cell 506 coupled to (one or more) selected word lines 518. Voltage generator 710 can be configured to be controlled by control logic 712 and generate word line voltages (e.g., read reference voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 501.

[0054] As part of peripheral circuitry 502, control logic 712 can be coupled to other peripheral circuitry described above and configured to control the operation of those peripheral circuitry. Register 714 can be coupled to control logic 712 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuitry. Interface 716 can be coupled to control logic 712 and serves as a control buffer to buffer and relay control commands received from the host (not shown) and status information received from the host. Interface 716 can also be coupled to column decoder / bitline driver 706 via data bus 718 and serves as a data input / output (I / O) interface and data buffer, buffering and relaying data to and from memory cell array 501.

[0055] Figure 7B A detailed block diagram of exemplary control logic 712 coupled to host 308, sensing device 720, line decoder / word line driver 708 and voltage generator 710 according to some aspects of this disclosure is shown. Figure 8A An exemplary voltage generator is shown in accordance with some aspects of this disclosure. Figure 8B Reference signals and word line voltages are shown according to some aspects of this disclosure. Figure 8C An exemplary sensing device is shown in accordance with some aspects of this disclosure. Figure 9A The word line capacitor load coupled to the voltage generator is shown in some aspects according to this disclosure. Figure 9B The capacitance of a word line capacitive load as a function of word line voltage is shown according to some aspects of this disclosure. For ease of explanation, it is described together. Figure 2 , Figure 5 , Figure 7B , Figures 8A-8C , Figure 9A and Figure 9B .

[0056] The control logic 712 may include a reference voltage determination module 701, a word line voltage determination module 703, a capacitor comparison module 705, and a subsequent operation control module 707. Each module includes corresponding software and hardware for performing the corresponding function. (Return to Reference) Figure 2 At the start of a read operation (e.g., at time T1), the word line voltage (i.e., the voltage applied to all word lines) begins to increase from a low voltage. (See reference) Figure 5 and Figure 7BControl logic 712 can control the increase of the word line voltage applied to word line 518 in block 504. In some embodiments, reference voltage determination module 701 and word line voltage determination module 703 are each electrically coupled to voltage generator 710. Reference voltage determination module 701 and word line voltage determination module 703 can be electrically coupled together so that signals / commands can be transmitted between them. One or both modules of reference voltage determination module 701 and word line voltage determination module 703 can be electrically coupled to host 308 to receive commands, such as read operation commands. In some embodiments, at time T1, control logic 712 can also control row decoder / word line driver 708 and / or column decoder / bit line driver 706 to start applying / increasing voltage on select gate lines 513 and 515, bit line 516, source line 514, etc., and return to reference. Figure 2 .

[0057] The voltage generator 710, coupled to the reference voltage determination module 701 and the word line voltage determination module 703, can be electrically coupled to the line decoder / word line driver 708 and the sensing device 720. The reference voltage determination module 701 and the word line voltage determination module 703 can control the voltage generator 710 to output the word line voltage applied to the word line 518 by the line decoder / word line driver 708. Figure 8A An exemplary voltage generator is shown, which includes a word line voltage (V) WL The pumping device 802 (“PUMP”) outputs a clock signal (“CLK”) and a flag signal (“FLAG”). The pumping device 802 can include any suitable charge pump, such as a direct current to direct current converter (DC-DC converter), which uses capacitors for energy charge storage to increase or decrease the voltage. The output of the pumping device 802 is electrically coupled to a comparator circuit, which includes resistors Rt and Rb, a transistor, and a comparator 804. Figure 8A As shown, resistor Rt is coupled to the output of pumping device 802, resistor Rb is coupled in series with resistor Rt at its first end, and transistor is coupled to resistor Rb at its second end. In some embodiments, resistors Rt and Rb are two separate resistors, each with a constant resistance. In some embodiments, resistors Rt and Rb are two parts of a variable resistor, and the value of each of Rt and Rb can be changed. An enable signal (“EN”) can be applied to the gate electrode of the transistor to turn the comparator circuit on and off.

[0058] Comparator 804 may include any logic circuitry that compares the magnitudes of two voltages to determine which one has a larger magnitude. For example, the comparator may include an operational amplifier (Pp-Amp) with high gain. The first input of comparator 804 is coupled to the first terminal of resistor Rb, such that the word line voltage V... WL A portion of the input is fed into comparator 804. For ease of description, the first input of comparator 804 is referred to as the word line voltage portion Vfb, and the word line voltage portion Vfb is related to the word line voltage V. WL The value is proportional. The word line voltage section Vfb can change proportionally with the word line voltage V. WL The second input to comparator 804 is the reference signal Vref_ramp, determined by the reference voltage determination module 701. The output (flag signal) of comparator 804 can be equal to the difference between the second input and the first input, for example, (Vref_ramp - Vfb). That is, when the voltage of the reference signal Vref_ramp is higher than the voltage of the word line voltage portion Vfb, the flag signal is equal to 1; and when the voltage of the reference signal Vref_ramp is equal to the voltage of the word line voltage portion Vfb, the flag signal is equal to 0.

[0059] like Figure 8A As shown, the flag signal is coupled to the input of the pumping device 802 as a feedback signal. When the flag signal is equal to 1, the pumping device 802 turns on and outputs a word line voltage V. WL In some embodiments, the pumping device 802 maintains an increased word line voltage V during pumping. WL The value of the flag signal. When the flag signal is equal to 0, the pumping device 802 shuts down and stops outputting the word line voltage V. WL In some implementations, when the flag signal is equal to 0, the pumping device 802 stops increasing the word line voltage V. WL The value of the flag signal reflects the time it takes for the pumping device 802 to start before the word line voltage portion Vfb reaches the voltage value of the reference signal Vref_ramp.

[0060] Upon receiving a read operation command, the reference voltage determination module 701 can control the voltage generator 710 to generate a reference signal Vref_ramp with a step voltage. Under the step voltage, the word line voltage determination module 703 controls the pumping device 802 to continue increasing the word line voltage V. WL The value is maintained until the word line voltage portion Vfb reaches a step voltage. Then, the flag signal outputs "0", and the pumping device 802 stops increasing / outputting the word line voltage V. WLThen, the reference voltage determination module 701 can control the voltage generator 710 to generate a higher step voltage. Because the word line voltage portion Vfb is lower than the higher step voltage, the comparator circuit generates a flag signal equal to 1, and the pumping device 802 can begin increasing the word line voltage Vfb. WL This continues until the word line voltage section Vfb reaches a higher step voltage.

[0061] Figure 8B Exemplary reference signal Vref_ramp and exemplary word line voltage V are shown in three consecutive time periods P1, P2 and P3 according to some embodiments of this disclosure. WL It should be noted that the voltage and time period values ​​are for illustrative purposes only and not proportional. Additionally, the word line voltage V... WL It can be increased relative to time using any suitable curve / line, and Figure 8B Only the word line voltage V is shown. WL The trend. For ease of explanation, the word line voltage V... WL It is shown as increasing linearly as a function of time.

[0062] Controlled by the reference voltage determination module 701, the voltage generator 710 can generate multiple step voltages as reference signals Vref_ramp, each step voltage representing a constant voltage within a corresponding time period. For example, ... Figure 8B As shown, the reference signal Vref_ramp can be generated from V at the beginning of time period P1. S1 Increase to V S2 At the start of time period P2, from V S2 Increase to V S3 And from V at the start of time period P3. S3 Increase to V S4 Each step voltage is higher than the previous step voltage, for example, V. S1 <V S2 <V S3 <V S4 Time periods P1, P2, and P3 can have the same duration or different durations. The length of each time period (e.g., P1, P2, and P3) can be determined by the duration for which the pumping device 802 is turned on under the corresponding step voltage. Word line voltage V WL It is possible to start from V at the end of time period P1. WL1 Increase to V WL2 At the end of time period P2, from V WL2 Increase to V WL3 And from V at the end of time period P3. WL3 Increase to V WL4 .

[0063] As mentioned earlier, before the start of time period P1, the word line voltage V WL equals V WL1 The word line voltage Vfb is equal to the step voltage V. S1 The flag signal is equal to 0, and the pumping device 802 stops increasing the word line voltage V. WL The reference voltage determination module 701 can sense the operation of the pumping device 802 and control the voltage generator 710 to generate a voltage higher than the step voltage V. S1 step voltage V S2 That is, at the beginning of time period P1, the step voltage V S2 The voltage is greater than the word line voltage Vfb, and the comparator 804 outputs a flag signal equal to 1. The pumping device 802 can start pumping and increase the word line voltage Vfb during time period P1. WL The word line voltage Vfb varies with the word line voltage V. WL And continue to increase until the step voltage V is reached. S2 And word line voltage V WL Reaching V WL2 Then, comparator 804 can output a flag signal equal to 0, and pumping device 802 can stop increasing or output word line voltage V. WL Then, time period P1 ends. The reference voltage determination module 701 can sense the operation of the pumping device 802 and control the voltage generator 710 to generate a step voltage V, which serves as the second input to the comparison circuit. S3 Pumping equipment 802 can increase the line voltage V. WL Until the word line voltage section Vfb reaches V S3 And word line voltage V WL V is reached at the end of time period P2. WL3 The reference voltage determination module 701 can sense the operation of the pumping device 802 and control the voltage generator 710 to generate a step voltage V, which serves as the second input to the comparison circuit. S4 Similarly, pumping device 802 can increase the word line voltage V. WL Until the word line voltage section Vfb reaches V S4 And word line voltage V WL V is reached at the end of time period P3. WL4 For each time period, the reference voltage determination module 701 and the word line voltage determination module 703 can control the voltage generator 710 to repeat the above operation until V... WL The highest threshold voltage of memory cell 506 is reached.

[0064] refer to Figure 9A When the word line voltage V WLWhen the increment is maintained, word line 518 and memory cell 506 can be equivalent to word line capacitive load 902 with variable capacitance. When word line voltage V WL As the capacitance increases, the capacitance of the word line capacitive load 902 can continue to increase. This can be achieved when the threshold voltage is lower than the word line voltage V. WL The increase in the value of the reference signal Vref_ramp and the number of memory cells coupled to the corresponding portion of the channel structure 612 with the word line 518 is caused by the increase in the number of memory cells coupled to the word line 518. This occurs when the reference signal Vref_ramp reaches a higher step voltage in each time period (e.g., P1, P2, and P3). WL The increase and charging of the variable capacitor can continue (e.g., the flag signal equals 1) until the pumping device 802 stops increasing the word line voltage V. WL (For example, the flag signal is equal to 0). Therefore, at each step voltage of the reference signal Vref_ramp, the time for the word line capacitive load 902 to be charged is equal to the time for the flag signal to be equal to 1 before becoming 0. That is, the time for the flag signal to be 1 at each step voltage of the reference signal Vref_ramp can reflect the capacitance change of the word line capacitive load 902, that is, the capacitance charged to the word line capacitive load 902. Figure 9B The capacitance of word line capacitive load 902 ("WL CAP (Nf)") is shown as a function of word line voltage ("WL voltage (V)"). Figure 9B As shown, the capacitance can continue to increase until the word line voltage V WL The highest threshold voltage of memory cell 506 is reached. Then, the capacitance can stop increasing or begin decreasing. In some embodiments, the highest threshold voltage can be obtained before detection. Figure 9B The functions shown are, for example, used as a reference for comparison. For example, the functions may be measured and stored in a memory device (e.g., 304) and / or a memory controller (e.g., 306).

[0065] Return to reference Figure 7B Sensing device 720 can be electrically coupled to voltage generator 710 to obtain the capacitance change of word line capacitive load 902 based on a flag signal. Sensing device 720 can generate values ​​reflecting the time during which the flag signal is equal to 1 at each step voltage of the reference signal Vref_ramp. For example, during each time period (e.g., P1, P2, and P3) of the corresponding step voltage, the flag signal is equal to 1 until the word line voltage portion Vfb reaches the corresponding step voltage at the end of the corresponding time period. The flag signal is equal to 0 between two adjacent time periods (e.g., between time periods P1 and P2, and between P2 and P3, etc.). The output of sensing device 720 can include a value representing the flag signal at each step voltage (e.g., Vref_ramp). S2 V S3 and V S4The value of the time period equal to 1. In some embodiments, the output of the sensing device 720 may include each of the corresponding time periods (e.g., P1, P2, and P3) and indicate the value of the capacitance charged into the word line capacitive load 902 during the corresponding time period.

[0066] Figure 8C An exemplary sensing device 720 according to some embodiments of the present disclosure is shown. The sensing device 720 may include a counter having a first input of a clock signal (“CLK”) and a second input of a flag signal (“FLAG”). The output of the sensing device 720 may include a plurality of binary numbers, such as Q0Q1Q2Q3. When the flag signal is equal to 1, the counter continues to count the clock signal, and the output continues to increase until the flag signal becomes 0. When the flag signal is 0, the counter stops counting, and the output reflects the time when the flag signal was equal to 1. In some embodiments, the counter stops counting between two adjacent time periods (e.g., between P1 and P2 and between P2 and P3), and outputs a value corresponding to the most recent time period. In some embodiments, a reset signal (not shown) is coupled to the counter to reset the output to 0 after each time period. Thus, the output of the counter includes values ​​each reflecting the time when the flag signal was equal to 1 before becoming 0. In some embodiments, the output of the counter includes values ​​each reflecting the time of the respective time periods (e.g., P1, P2, and P3). In some embodiments, the counter includes an AND gate 806 coupled to a plurality of flip-flops 808 (e.g., latches). The input is coupled to the counter via an AND gate 806, and each of the flip-flops in the flip-flops 808 outputs a digital value. In various embodiments, the number of flip-flops 808 can vary. In some embodiments, the sensing device 720 can output multiple values ​​C1, C2, C3, ..., each associated with the duration (e.g., the length of the corresponding time period) for a flag signal to be equal to 1. As described above, the values ​​C1, C2, C3, ... can each be associated with the capacitance change of the word line capacitive load 902 under the corresponding step voltage (i.e., the capacitance charged to the word line capacitive load 902).

[0067] Return to reference Figure 7A The sensing device 720 can be electrically coupled to the capacitance comparison module 705 of the control logic 712. The sensing device 720 can transmit its output (e.g., values ​​C1, C2, C3, ...) to the capacitance comparison module 705 after each corresponding time period. The capacitance comparison module 705 can receive the output of the sensing device 720 and compare the difference between two adjacent values ​​(e.g., (C1, C2, C3, ...)). n+1 -C nThe value of n (where n is 1, 2, 3, etc.) is used. Based on the comparison results, the capacitance comparison module 705 can determine the time when the maximum capacitance of the word line capacitor load 902 is reached and the value of the highest threshold voltage of the memory unit 506. For example, when the capacitance of the word line capacitor load 902 is close to its maximum value, (C... n+1 -C n The capacitor reaches its maximum value. The capacitor comparison module 705 can then determine when (C) reaches its maximum value. n+1 -C n The word line voltage V reaches its maximum value. WL The highest threshold voltage of memory cell 506 has been reached, and corresponding to C n+1 The step voltage is the highest threshold voltage. In the example, value C1 can represent the output of sensing device 720 during time period P1, value C2 can represent the output of sensing device 720 during time period P2, and value C3 can represent the output of sensing device 720 during time period P3. Capacitor comparison module 705 can determine the value of (C2-C1) after receiving value C2, and determine the value of (C3-C2) after receiving C3. If (C3-C2) is equal to or less than (C2-C1), then capacitor comparison module 705 can determine the word line voltage V. WL At the end of time period P2, the highest threshold voltage of memory cell 506 is reached, and the value of the highest threshold voltage is equal to or sufficiently close to V. WL3 .

[0068] The capacitor comparator module 705 can also be electrically coupled to the reference voltage determination module 701. In some embodiments, when the word line voltage V... WL When the highest threshold voltage of memory cell 506 is reached, capacitor comparison module 705 notifies reference voltage determination module 701, and reference voltage determination module 701 controls voltage generator 710 to stop increasing the value of the step voltage in reference signal Vref_ramp. In some embodiments, when a command for a read operation is received, reference voltage determination module 701 notifies capacitor comparison module 705 so that capacitor comparison module 705 can initialize to perform a comparison.

[0069] The subsequent operation control module 707 can be electrically coupled to the capacitor comparator module 705, which is electrically coupled to the line decoder / word line driver 708 and the voltage generator 710. In some embodiments, when the word line voltage V... WL When the highest threshold voltage of memory cell 506 is reached, capacitor comparison module 705 notifies subsequent operation control module 707, which can then return to the reference based on the time when the highest threshold was reached (e.g., at time T2). Figure 2 The value of the highest threshold voltage and / or the value of the reference voltage will trigger other operations. For example, return to the reference. Figure 2When the word line voltage V WL When the highest threshold voltage of memory cell 506 is reached, the subsequent operation control module 707 can control the row decoder / word line driver 708 to apply a shutdown voltage (e.g., a low voltage) on the unselected DSG, unselected SSG, and selected word lines. The subsequent operation control module 707 can also determine a read reference voltage and Vpass based on the value of the highest threshold voltage of memory cell 506. For example, the subsequent operation control module 707 can compare the detected highest threshold voltage with the highest threshold voltage stored in memory device 304 prior to detection. In some embodiments, if the highest threshold voltage has shifted to a lower voltage, the subsequent operation control module 707 can determine that one or more read reference voltages each have a lower voltage value. The subsequent operation control module 707 can refer to an overdrive value corresponding to the value of the highest threshold voltage (e.g., ... Figure 2 The value of Vpass is determined by a lookup table of ΔV in the table, or by performing real-time calculations to determine the overdrive value. In some implementations, the subsequent operation control module 707 controls the voltage generator 710 to generate the determined read reference voltage and Vpass, and controls the line decoder / word line driver 708 to apply the corresponding voltage on the corresponding word line.

[0070] It should be noted that in various embodiments, additional or optional, a suitable number of voltage generators 710 may also be monitored to detect the highest threshold voltage of memory cell 506 at a desired time (e.g., in real-time or at a desired time). For example, sensing device 720 may be configured to output a value reflecting a change in the current output by voltage generator 710. In some embodiments, when word line voltage V WL When the voltage reaches or approaches the maximum threshold voltage, the current of the voltage generator 710 reaches its maximum value for a period of time.

[0071] Figure 10A A flowchart of a method 1000 for operating a memory device according to some aspects of this disclosure is shown. The memory device can be any suitable memory device disclosed herein, such as memory device 304. Method 1000 can be implemented by peripheral circuitry 502 (e.g., control logic 712, voltage generator 710, line decoder / word line driver 708, and sensing device 720). It should be understood that the operations shown in method 1000 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 10A The different execution orders shown.

[0072] refer to Figure 10AMethod 1000 begins with operation 1002, in which a word line voltage is applied to each of the multiple word lines. At the start of the read operation, control logic controls a voltage generator to generate word line voltages and controls the line decoder / word line driver to apply word line voltages to all word lines. The control logic may also control the voltage generator to increase the word line voltages by following a reference signal with multiple step voltages.

[0073] Method 1000 proceeds to operation 1004, where the highest threshold voltage of a plurality of memory cells coupled to the word line is determined based on changes in the word line capacitive load in response to the word line voltage. In response to an increase in the word line voltage, control logic obtains the capacitance change of the word line capacitive load formed by the memory cells and the word line from a sensing device. Based on the capacitance change, the control logic can determine the time at which the maximum capacitance of the word line capacitive load is reached. Therefore, the control logic can determine the word line voltage at the time when the maximum capacitance is reached as the highest threshold voltage of the memory cell. Figure 10B The document shows a detailed description of operations 1002 and 1004.

[0074] Method 1000 proceeds to operation 1006, where multiple subsequent operations are performed based on one or more of the time when the word line voltage reaches the highest threshold voltage and the value of the highest threshold voltage. The control logic can begin performing other operations from the time the highest threshold voltage is reached. For example, at the time the highest threshold voltage is reached, the control logic can control the voltage generator to generate a low voltage and control the line decoder / word line driver to apply a low voltage to the unselected select gate. The control logic can also calculate Vpass to be applied to the unselected word line based on the value to be applied to the selected word line and the read reference voltage. The control logic can then control the voltage generator to continue increasing the word line voltage on the unselected word line until Vpass is reached.

[0075] Figure 10B A flowchart of a method 1001 for operating a memory device according to some aspects of this disclosure is shown. Method 1001 includes... Figure 10A and Figure 10B The detailed operation of operation 1004 in method 1001 can be implemented by peripheral circuitry 502 (e.g., control logic 712, voltage generator 710, line decoder / word line driver 708, and sensing device 720). It should be understood that the operations shown in method 1001 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 10B The different execution orders are shown. For ease of explanation, Figure 10B The operation during time period Pn is shown, and the word line voltage changes from V. n Increase to V n+1.

[0076] refer to Figure 10B Method 1001 begins with operation 1003, where the reference signal increases by a step size at the beginning of time period Pn. The word line voltage is equal to V at the beginning of time period Pn. n The control logic determines the step size and increments the reference signal voltage by that step size. The reference signal can be an input to the voltage generator's comparator circuit and is compared with the word line voltage portion. The word line voltage portion is a portion of the word line voltage output by the voltage generator's pumping device. When the word line voltage portion is lower than the reference signal, the comparator circuit outputs a flag signal of 1, and when the word line voltage portion equals the reference signal, the comparator circuit outputs a flag signal of 0. The flag signal is also an input to the pumping device.

[0077] Method 1001 proceeds to operation 1005, where the word line voltage is increased to reach the current reference voltage. When the flag signal is 1, the control logic can control the pumping device to maintain the increased word line voltage value. When the word line voltage partially equals the current reference signal (e.g., the current step voltage), the flag signal equals 0, and the pumping device stops increasing the word line voltage value. At the end of time period Pn, the word line voltage decreases from V... n Increase to V n+1 .

[0078] Method 1001 proceeds to operation 1007, where the current capacitance of the word line capacitive load is determined after the word line voltage reaches the current reference signal. The sensing device can output a value C indicating the time when the indicator flag signal is 1. n+1 This value is associated with the capacitance change of the word line capacitive load during the time period Pn, or with the capacitance charged to the word line capacitive load during the time period Pn.

[0079] Method 1001 proceeds to operation 1009, where the difference between the current capacitance change and the previous capacitance change is determined. The control logic can obtain this value and acquire the value C. n+1 AND value C n The difference between them, value C n+1 Sum C n This is generated by the sensing device in the time period Pn-1 immediately preceding the time period Pn. For example, the control logic can determine (C n+1 -C n The value of ).

[0080] Method 1001 proceeds to operation 1011, where it is determined whether the difference obtained in operation 1009 has decreased compared to the previous difference. The control logic can compare (C... n+1 -C n ) and (C n -C n-1 The value of ) and determine (C)n+1 -C n Is it less than or equal to (C)? n -C n-1 ), where C n-1 Generated by the sensing device during time period Pn-2 and obtained by the control logic at the end of time period Pn-2. If (C n+1 -C n ) less than or equal to (C n -C n-1 If (C) is reached, the control logic determines that the word line capacitance load has reached its maximum capacitance. Then, the control signal can determine the time when the maximum capacitance of the word line capacitance load is reached, and the word line voltage at the time of reaching the maximum capacitance is determined as the highest threshold voltage of the memory cell. Method 1001 proceeds to operation 1006. If (C) n+1 -C n ) greater than (C n -C n-1 If the word line capacitor load has not yet reached the maximum capacitance, then the control logic determines that method 1001 proceeds to operation 1003.

[0081] Embodiments of this disclosure provide a memory device. The memory device includes a memory cell array, with memory cells arranged in multiple memory strings and multiple memory cell rows. The memory device also includes multiple word lines respectively coupled to the multiple memory cell rows, and peripheral circuitry coupled to the multiple word lines and configured to perform a read operation on a selected memory cell row among the multiple memory cell rows. The selected memory cell row is coupled to the selected word line, wherein the peripheral circuitry is configured to apply a word line voltage to each of the multiple word lines and determine a highest threshold voltage of the multiple memory cell rows based on changes in word line capacitive load in response to the word line voltage.

[0082] In some implementations, the word line capacitive load includes a variable capacitor, and determining the highest threshold voltage of the plurality of memory cell rows includes determining the maximum capacitance of the variable capacitor and determining the highest threshold voltage based on the maximum capacitance.

[0083] In some implementations, the peripheral circuitry includes control logic configured to perform at least one of the following: determining the time when a maximum threshold voltage is reached, determining a pass voltage applied to a non-selected word line among multiple word lines during a read operation based on the maximum threshold voltage, or determining a read reference voltage applied to a selected word line based on the maximum threshold voltage.

[0084] In some implementations, the peripheral circuitry also includes a driver configured to perform at least one of the following operations based on control logic: applying a turn-off voltage to an SG transistor coupled to a non-selected memory string among a plurality of memory strings at a time when a maximum threshold voltage is reached; applying a pass voltage to a non-selected word line among a plurality of word lines during a read operation; or applying a read reference voltage to a selected word line.

[0085] In some embodiments, the peripheral circuitry further includes a voltage generator configured to output word line voltages, control logic configured to control the voltage generator, and a driver configured to apply word line voltages to a plurality of memory cell rows. The control logic controls the voltage generator to increase the word line voltages from a first voltage value to a second voltage value, and from the second voltage value to a third voltage value. The driver applies word line voltages to the plurality of word lines.

[0086] In some embodiments, the control logic is further configured to obtain a first value associated with a first capacitance charged to the word line capacitive load between a first voltage value and a second voltage value, and a second value associated with a second capacitance charged to the word line capacitive load between a second voltage value and a third voltage value. The control logic is also configured to determine the difference between the first value and the second value. The control logic is further configured to determine the capacitance of the word line capacitive load as the maximum capacitance of the word line capacitive load in response to the difference reaching its maximum value.

[0087] In some implementations, the control logic is also configured to determine the third voltage value as the highest threshold voltage of the plurality of memory cell rows.

[0088] In some implementations, the peripheral circuitry also includes a sensing device coupled to the voltage generator and control logic. The sensing device is configured to generate a first value associated with a first capacitor and a second value associated with a second capacitor.

[0089] In some implementations, the voltage generator further includes a comparator circuit having a flag signal output coupled to the input of the voltage generator. In response to the flag signal being 1, the voltage generator continues to increase the word line voltage. In response to the flag signal being 0, the voltage generator stops increasing the word line voltage.

[0090] In some implementations, the flag signal is equal to 1 in the first time period and the second time period, respectively. In some implementations, the flag signal is equal to 0 between the first time period and the second time period.

[0091] In some implementations, the sensing device includes a counter that counts time periods in response to a flag being 1 and generates values ​​corresponding to the time periods, such that a first time period corresponds to a first value and a second time period corresponds to a second value.

[0092] In some implementations, the sensing device outputs a first value at the end of a first time period and a second value at the end of a second time period.

[0093] In some implementations, the sensing device includes an input and multiple triggers. The input includes a flag signal. Each trigger generates a digital output from the sensing device.

[0094] In some implementations, the comparator circuit includes a first input of a voltage portion proportional to the word line voltage and a second input of a reference signal coupled to control logic, wherein a flag signal is the difference between the voltage portion and the reference signal. The control logic is configured to apply a first step voltage to the second input of the comparator. The first step voltage is equal to a second voltage. The control logic is also configured to obtain a first value from a sensing device. The control logic is further configured to apply a second step voltage to the second input of the comparator in response to the flag signal changing from 1 to 0, the second step voltage being equal to a third voltage and greater than the first step voltage. The control logic is also configured to obtain a second value from a sensing device.

[0095] In some embodiments, the plurality of memory cells include at least one of a plurality of TLCs or a plurality of QLCs. In some embodiments, the highest threshold voltage of the plurality of memory cell rows includes at least one of the highest threshold voltages in the TLCs or one of the highest threshold voltages in the QLCs.

[0096] In some implementations, multiple memory cells are located within a 3D NAND memory device.

[0097] Embodiments of this disclosure provide a system. The system includes a memory device configured to store data. The memory device includes: a memory cell array, memory cells arranged in a plurality of memory strings and in a plurality of memory cell rows; a plurality of word lines coupled to the plurality of memory cell rows; and peripheral circuitry coupled to the plurality of word lines and configured to perform a read operation on a selected memory cell row among the plurality of memory cell rows. The selected memory cell row is coupled to the selected word line. The peripheral circuitry is configured to apply a word line voltage on each of the plurality of word lines and determine a highest threshold voltage of the plurality of memory cell rows based on a change in word line capacitive load in response to the word line voltage. The system also includes a memory controller coupled to the memory device and configured to control the memory device.

[0098] In some implementations, the word line capacitive load includes a variable capacitor. In some implementations, determining the highest threshold voltage across the plurality of memory cell rows includes determining the maximum capacitance of the variable capacitor and determining the highest threshold voltage based on the maximum capacitance.

[0099] In some implementations, the peripheral circuitry includes control logic configured to perform at least one of the following: determining the time when a maximum threshold voltage is reached, determining a Vpass voltage applied to a non-selected word line among multiple word lines during a read operation based on the maximum threshold voltage, or determining a read reference voltage applied to a selected word line based on the maximum threshold voltage.

[0100] In some implementations, the peripheral circuitry also includes a driver configured to perform at least one of the following operations based on control logic: applying a turn-off voltage to an SG transistor coupled to a non-selected memory string among a plurality of memory strings at a time when a maximum threshold voltage is reached; applying a Vpass voltage to a non-selected word line among a plurality of word lines during a read operation; or applying a read reference voltage to a selected word line.

[0101] In some embodiments, the peripheral circuitry further includes a voltage generator configured to output word line voltages, control logic configured to control the voltage generator, and a driver configured to apply word line voltages to a plurality of memory cell rows. The control logic controls the voltage generator to increase the word line voltages from a first voltage value to a second voltage value, and from the second voltage value to a third voltage value. The driver applies word line voltages to the plurality of word lines.

[0102] In some embodiments, the control logic is further configured to obtain a first value associated with a first capacitance charged to the word line capacitive load between a first voltage value and a second voltage value, and a second value associated with a second capacitance charged to the word line capacitive load between a second voltage value and a third voltage value. In some embodiments, the control logic is further configured to determine the difference between the first value and the second value. In some embodiments, the control logic is further configured to determine the capacitance of the word line capacitive load as the maximum capacitance of the word line capacitive load in response to the difference reaching its maximum value.

[0103] In some implementations, the control logic is also configured to determine the third voltage value as the highest threshold voltage of the plurality of memory cell rows.

[0104] In some implementations, the peripheral circuitry also includes a sensing device coupled to the voltage generator and control logic. The sensing device is configured to generate a first value associated with a first capacitor and a second value associated with a second capacitor.

[0105] In some implementations, the voltage generator further includes a comparator circuit having a flag signal output coupled to the input of the voltage generator. In response to the flag signal being 1, the voltage generator continues to increase the word line voltage. In response to the flag signal being 0, the voltage generator stops increasing the word line voltage.

[0106] In some implementations, the flag signal is equal to 1 in the first time period and the second time period, respectively. In some implementations, the flag signal is equal to 0 between the first time period and the second time period.

[0107] In some implementations, the sensing device includes a counter that counts time periods in response to a flag being 1 and generates values ​​corresponding to the time periods, such that a first time period corresponds to a first value and a second time period corresponds to a second value.

[0108] In some implementations, the sensing device outputs a first value at the end of a first time period and a second value at the end of a second time period.

[0109] In some implementations, the sensing device includes an input and multiple triggers. The input includes a flag signal. Each trigger generates a digital output from the sensing device.

[0110] In some embodiments, the comparator circuit includes a first input of a voltage portion proportional to the word line voltage and a second input of a reference signal coupled to control logic, wherein a flag signal is the difference between the voltage portion and the reference signal. The control logic is configured to apply a first step voltage to the second input of the comparator. The first step voltage is equal to a second voltage. The control logic is also configured to obtain a first value from a sensing device. The control logic is further configured to apply a second step voltage to the second input of the comparator in response to the flag signal changing from 1 to 0, the second step voltage being equal to a third voltage and greater than the first step voltage. In some embodiments, the control logic is also configured to obtain a second value from a sensing device.

[0111] In some embodiments, the plurality of memory cells include at least one of a plurality of TLCs or a plurality of QLCs. In some embodiments, the highest threshold voltage of the plurality of memory cell rows includes at least one of the highest threshold voltages in the TLCs or one of the highest threshold voltages in the QLCs.

[0112] In some implementations, the memory device is a 3D NAND memory device.

[0113] Embodiments of this disclosure also provide a method for operating a memory device. The memory device includes: a memory cell array, memory cells arranged in a plurality of memory strings and in a plurality of memory cell rows; and a plurality of word lines respectively coupled to the plurality of memory cell rows. The method includes performing a read operation on a selected memory cell row among the plurality of memory cell rows. The selected memory cell row is coupled to the selected word line. Performing the read operation includes: applying a word line voltage on each of the plurality of word lines, and determining a highest threshold voltage of the plurality of memory cell rows based on a change in word line capacitive load in response to the word line voltage.

[0114] In some implementations, the word line capacitive load includes a variable capacitor. In some implementations, determining the highest threshold voltage across the plurality of memory cell rows includes determining the maximum capacitance of the variable capacitor and determining the highest threshold voltage based on the maximum capacitance.

[0115] In some implementations, the method further includes determining the time when the highest threshold voltage is reached, determining the Vpass voltage applied to a non-selected word line among multiple word lines during a read operation based on the highest threshold voltage, or determining a read reference voltage applied to a selected word line based on the highest threshold voltage.

[0116] In some implementations, the method further includes performing at least one of the following: applying a turn-off voltage to an SG transistor coupled to a non-selected memory string in a plurality of memory strings at a time when a maximum threshold voltage is reached, applying a pass voltage to a non-selected word line in a plurality of word lines during a read operation, or applying a read reference voltage to a selected word line.

[0117] In some embodiments, the method further includes increasing the word line voltage from a first voltage value to a second voltage value, and from the second voltage value to a third voltage value. The method also includes applying word line voltages to multiple word lines.

[0118] In some embodiments, the method further includes obtaining a first value associated with a first capacitance charged to the word line capacitive load between a first voltage value and a second voltage value, and a second value associated with a second capacitance charged to the word line capacitive load between a second voltage value and a third voltage value. The method may also include determining a difference between the first value and the second value. The method may further include determining the capacitance of the word line capacitive load as the maximum capacitance of the word line capacitive load in response to the difference reaching its maximum value.

[0119] In some implementations, the method further includes determining a third voltage value as the highest threshold voltage of a plurality of memory cell rows.

[0120] In some implementations, the method further includes generating a first value associated with a first capacitor and generating a second value associated with a second capacitor.

[0121] In some embodiments, the method further includes generating a flag signal. The flag signal is coupled to an input of a voltage generator. In some embodiments, the method further includes increasing the word line voltage in response to the flag signal being equal to 1; and stopping the increase of the word line voltage in response to the flag signal being equal to 0.

[0122] In some implementations, the flag signal is equal to 1 in the first time period and the second time period, respectively. In some implementations, the flag signal is equal to 0 between the first time period and the second time period.

[0123] In some embodiments, the method further includes obtaining a voltage portion proportional to the word line voltage and increasing the word line voltage during a first time period by comparing the voltage portion with a first step voltage. The first step voltage is equal to a second voltage. In some embodiments, the method further includes counting the length of the first time period to obtain a first value. In some embodiments, the method further includes increasing the word line voltage during a second time period in response to a flag signal changing from 1 to 0 by comparing the voltage portion with a second step voltage. The second step voltage is equal to a third voltage and greater than the first step voltage. In some embodiments, the method further includes counting the length of the second time period to obtain a second value.

[0124] In some embodiments, the plurality of memory cells include at least one of a plurality of TLCs or a plurality of QLCs. In some embodiments, the highest threshold voltage of the plurality of memory cell rows includes at least one of the highest threshold voltages in the TLCs or one of the highest threshold voltages in the QLCs.

[0125] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0126] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A circuit comprising: A voltage generator includes a first output terminal and a second output terminal, the first output terminal being configured to output a word line voltage, and the second output terminal being configured to output a flag signal indicating the relationship between the word line voltage and a reference signal; as well as A sensing device, the sensing device including a first input terminal and a third output terminal, the first input terminal being coupled to a second output terminal of the voltage generator, and the third output terminal being configured to output a value corresponding to the capacitance change of the word line capacitive load according to the flag signal.

2. The circuit according to claim 1, wherein, The voltage generator is configured to increase the word line voltage from a first voltage value to a second voltage value, and from the second voltage value to a third voltage value.

3. The circuit according to claim 2, wherein, The sensing device is configured to generate a first value and a second value, the first value being associated with a first capacitor that charges the word line capacitive load between the first voltage value and the second voltage value, and the second value being associated with a second capacitor that charges the word line capacitive load between the second voltage value and the third voltage value.

4. The circuit according to claim 3, wherein, The voltage generator includes a comparator circuit and a pumping device. The output terminal of the comparator circuit serves as the second output terminal of the voltage generator, and the output terminal of the pumping device serves as the first output terminal of the voltage generator. One input terminal of the comparator circuit is coupled to the first output terminal of the voltage generator, and the other input terminal of the comparator circuit is input with the reference signal. in, In response to the flag signal being equal to 1, the pumping device continues to increase the word line voltage; and In response to the flag signal being equal to 0, the pumping device stops increasing the word line voltage.

5. The circuit according to claim 4, wherein, The sensing device includes a counter coupled to the second output of the voltage generator, the counter counting time periods in response to the flag signal being 1.

6. The circuit according to claim 5, wherein, The third output terminal of the sensing device outputs the first value at the end of the time period during which the word line voltage increases from the first voltage value to the second voltage value; and The third output terminal of the sensing device outputs the second value at the end of the time period in which the word line voltage increases from the second voltage value to the third voltage value.

7. The circuit according to claim 4, wherein, The sensing device includes multiple triggers, which generate numbers corresponding to the values ​​output by the third output terminal.

8. The circuit according to claim 1, wherein, Both the voltage generator and the sensing device are input with a clock signal.

9. A memory device, comprising: Memory cell array, wherein the memory cells are in multiple memory strings and arranged in multiple memory cell rows. ； Multiple word lines are coupled to the multiple rows of memory cells, respectively; as well as Peripheral circuitry, coupled to the plurality of word lines and including: A voltage generator includes a first output terminal and a second output terminal, the first output terminal being configured to output a word line voltage, and the second output terminal being configured to output a flag signal indicating the relationship between the word line voltage and a reference signal; as well as A sensing device, the sensing device including a first input terminal and a third output terminal, the first input terminal being coupled to a second output terminal of the voltage generator, and the third output terminal being configured to output a value corresponding to the capacitance change of the word line capacitive load according to the flag signal.

10. The memory device according to claim 9, wherein, The voltage generator includes a pumping device, the output terminal of which serves as the first output terminal of the voltage generator; and The peripheral circuitry also includes control logic coupled to the pumping device, the control logic being configured to control the pumping device to increase the word line voltage from a first voltage value to a second voltage value, and from the second voltage value to a third voltage value.

11. The memory device according to claim 10, wherein, The voltage generator further includes a comparator circuit, the output of which serves as the second output of the voltage generator, one input of which is coupled to the first output of the voltage generator, and the other input of which is input with the reference signal. in, In response to the flag signal being equal to 1, the pumping device continues to increase the word line voltage; and In response to the flag signal being equal to 0, the pumping device stops increasing the word line voltage.

12. The memory device according to claim 11, wherein, The control logic is also configured to control the voltage generator to generate the reference signal with a step voltage, and to control the pumping device to continue increasing the word line voltage until the flag signal equals 0.

13. The memory device according to claim 11, wherein, The control logic is coupled to the third output of the sensing device and configured to acquire the difference between two adjacent values ​​received from the third output of the sensing device.

14. The memory device according to claim 13, wherein, The sensing device includes a counter coupled to the second output of the voltage generator, the counter counting time periods in response to the flag signal being 1.

15. The memory device according to claim 14, wherein, The third output terminal of the sensing device outputs a first value at the end of the time period during which the word line voltage increases from the first voltage value to the second voltage value; and The third output terminal of the sensing device outputs a second value at the end of the time period during which the word line voltage increases from the second voltage value to the third voltage value.

16. The memory device according to claim 13, wherein, The control logic is also configured as follows: In response to a second difference being less than or equal to a first difference obtained before the second difference, it is determined that the word line voltage has reached the highest threshold voltage of the memory cell; as well as Other operations are initiated based on the time it takes for the highest threshold voltage or the word line voltage to reach the highest threshold voltage of the memory cell.

17. A system comprising: Memory devices, including: A memory cell array, wherein the memory cells are in multiple memory strings and arranged in multiple memory cell rows; Multiple word lines are coupled to the multiple rows of memory cells, respectively; and Peripheral circuitry, coupled to the plurality of word lines and configured to perform a read operation on a selected memory cell row among the plurality of memory cell rows, the selected memory cell row being coupled to a selected word line, wherein the peripheral circuitry is configured to include: A voltage generator, comprising a first output terminal and a second output terminal, the first output terminal being configured to output a word line voltage, and the second output terminal being configured to output a flag signal indicating the relationship between the word line voltage and a reference signal; and A sensing device, comprising a first input terminal and a third output terminal, the first input terminal being coupled to a second output terminal of the voltage generator, the third output terminal being configured to output a value corresponding to a capacitance change of a word line capacitive load based on the flag signal; and A memory controller is coupled to the memory device and configured to control the memory device.

18. The system according to claim 17, wherein, The voltage generator includes a pumping device, the output terminal of which serves as the first output terminal of the voltage generator; and The peripheral circuitry also includes control logic coupled to the pumping device, the control logic being configured to control the pumping device to increase the word line voltage from a first voltage value to a second voltage value, and from the second voltage value to a third voltage value.

19. The system according to claim 18, wherein, The voltage generator further includes a comparator circuit, the output of which serves as the second output of the voltage generator, one input of which is coupled to the first output of the voltage generator, and the other input of which is input with the reference signal. in, In response to the flag signal being equal to 1, the pumping device continues to increase the word line voltage; and In response to the flag signal being equal to 0, the pumping device stops increasing the word line voltage.

20. The system according to claim 19, wherein, The control logic is also configured to control the voltage generator to generate the reference signal with a step voltage, and to control the pumping device to continue increasing the word line voltage until the flag signal equals 0.

21. The system according to claim 19, wherein, The control logic is coupled to the third output of the sensing device and configured to acquire the difference between two adjacent values ​​received from the third output of the sensing device.

22. The system according to claim 21, wherein, The sensing device includes a counter coupled to the second output of the voltage generator, the counter counting time periods in response to the flag signal being 1.

23. The system according to claim 22, wherein, The third output terminal of the sensing device outputs a first value at the end of the time period during which the word line voltage increases from the first voltage value to the second voltage value; and The third output terminal of the sensing device outputs a second value at the end of the time period during which the word line voltage increases from the second voltage value to the third voltage value.

24. The system according to claim 21, wherein, The control logic is also configured as follows: In response to a second difference being less than or equal to a first difference obtained before the second difference, it is determined that the word line voltage has reached the highest threshold voltage of the memory cell; as well as Other operations are initiated based on the time it takes for the highest threshold voltage or the word line voltage to reach the highest threshold voltage of the memory cell.

25. A method for operating a memory device, the memory device comprising: A memory cell array, wherein the memory cells are in multiple memory strings and arranged in multiple memory cell rows; And multiple word lines, respectively coupled to the multiple rows of memory cells, the method includes: Increase the word line voltage applied to one of the plurality of word lines; Detect the word line voltage; and Determine whether the word line voltage reaches the highest threshold voltage of the memory cell coupled to the word line.

26. The method according to claim 25, wherein, Increasing the word line voltage includes: The word line voltage is increased from a first voltage value to a second voltage value, and from the second voltage value to a third voltage value.

27. The method according to claim 26, wherein, Detecting the word line voltage includes: Obtain a first value and a second value, wherein the first value is associated with a first capacitor charged to the word line capacitive load between the first voltage value and the second voltage value, and the second value is associated with a second capacitor charged to the word line capacitive load between the second voltage value and the third voltage value; and Determine the difference between the first value and the second value.

28. The method according to claim 27, wherein, Determining whether the word line voltage reaches the highest threshold voltage of the memory cell coupled to the word line includes: In response to the difference reaching its maximum value, it is determined that the word line voltage has reached the highest threshold voltage of the memory cell coupled to the word line.

29. The method according to claim 25, wherein, The method further includes performing at least one of the following: When the word line voltage reaches the highest threshold voltage, a turn-off voltage is applied to the select gate (SG) transistor of the non-selected memory string coupled to the plurality of memory strings; During a read operation, the pass voltage is applied to the non-selected word line among the plurality of word lines; or A read reference voltage is applied to a selected word line among the plurality of word lines.

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