Motor driver system and active-standby switching method

Abstract

The application discloses a motor driver system and a master-backup switching method. The system comprises a first driver and a second driver which are redundant to each other; the first driver is a master, and the second driver is a backup; each driver comprises an FPGA and a communication module; the first FPGA controls the first communication module to send a master signal and receive a backup signal; when the first driver fails, the first communication module is controlled to send a backup signal; the second FPGA controls the second communication module to send a backup signal and receive a master signal; when the second communication module receives a backup signal, the second communication module is controlled to send a master signal; the first communication module comprises a first serial communication module, and the second communication module comprises a second serial communication module; or the first communication module comprises a first parallel communication module, and the second communication module comprises a second parallel communication module. The system can realize master-backup switching of the motor driver through the FPGA, and has simple hardware design, low cost and high real-time performance.

Description

Technical Field

[0001] This application relates to the field of automation control technology, specifically to a motor driver system and a method for switching between primary and backup systems. Background Technology

[0002] A drive can make motors, loads, and other equipment operate stably according to instructions based on control signals. To improve reliability, the control system of a drive generally adopts a redundant design, that is, a backup drive is set up in addition to the primary drive. When the primary drive fails, the control system switches to the backup drive to drive the equipment, thereby ensuring the stable operation of the equipment and avoiding equipment downtime.

[0003] Related technologies use a central processing unit (CPU) to achieve driver switching between primary and backup systems. However, CPUs are expensive, and their circuitry is complex, resulting in high hardware costs and design difficulties. Furthermore, because CPUs process data serially, they are unsuitable for applications with high real-time requirements. Summary of the Invention

[0004] In view of this, this application provides a motor driver system and a master-slave switching method, which can realize the master-slave switching of the motor driver through a field-programmable gate array. The hardware design is simple, the cost is low and the real-time performance is high.

[0005] To solve the above problems, the technical solution provided in this application is as follows:

[0006] In a first aspect of this application, a motor drive system is provided, comprising: a first drive and a second drive that are redundant with each other; the first drive is a main drive and the second drive is a standby drive; the main drive is in an operating state and the standby drive is in a standby state.

[0007] The first driver includes a first field-programmable gate array (FPGA) and a first communication module, and the second driver includes a second FPGA and a second communication module.

[0008] The first FPGA is used to control the first communication module to send host signals to the second communication module and receive standby signals from the second communication module; when the first driver fails, it controls the first communication module to send standby signals to the second communication module.

[0009] The second FPGA is used to control the second communication module to send a standby signal to the first communication module and to receive a master signal from the first communication module; when the second communication module receives the standby signal from the first communication module, it controls the second communication module to send a master signal to the first communication module.

[0010] The first communication module includes a first serial communication module, and the second communication module includes a second serial communication module; or, the first communication module includes a first parallel communication module, and the second communication module includes a second parallel communication module.

[0011] In one possible implementation, the first communication module includes a first serial communication module, and the second communication module includes a second serial communication module.

[0012] The second FPGA is also used to control the second serial communication module to send a host signal to the first serial communication module when the second serial communication module does not receive a standby signal from the first serial communication module after a time threshold.

[0013] The first FPGA is also used to control the first serial communication module to send the motor angle of the first driver to the second serial communication module, and to control the first serial communication module to receive the host signal from the second serial communication module; when the first serial communication module receives the host signal from the second serial communication module, it controls the first serial communication module to send the standby signal to the second serial communication module; the host signal and the standby signal are different status signals.

[0014] In one possible implementation, the first communication module includes a first parallel communication module, and the second communication module includes a second parallel communication module. The first parallel communication module and the second parallel communication module are implemented through an optical coupler.

[0015] The second FPGA is also used to control the second parallel communication module to send a host signal to the first parallel communication module when the second parallel communication module does not receive a host signal from the first parallel communication module.

[0016] The first FPGA is also used to control the first parallel communication module to send a standby signal to the second parallel communication module when the first parallel communication module receives a host signal from the second parallel communication module; the host signal and the standby signal are different heartbeat signals.

[0017] In one possible implementation, the first communication module further includes a first serial communication module, which is used to send the motor angle of the first driver to the second serial communication module.

[0018] Before the first FPGA controls the first parallel communication module to send the standby signal to the second parallel communication module, the method further includes: the first serial communication module receiving the motor angle from the second serial communication module; the second communication module further includes a second serial communication module, which is used to send the motor angle of the second driver to the first serial communication module.

[0019] Before the second FPGA controls the second parallel communication module to send a host signal to the first parallel communication module, it further includes: the second serial communication module not receiving a motor angle from the first serial communication module; the second FPGA is also used to control the second parallel communication module to send a standby signal to the first parallel communication module when the second parallel communication module does not receive a host signal from the first parallel communication module and the second serial communication module receives a motor angle from the first serial communication module.

[0020] In one possible implementation, before the first driver becomes the master, the first FPGA is also used to control the first driver to enter an initial state and send a master signal to the second driver after the first driver is initialized and ready.

[0021] Before the second driver becomes a standby device, the second FPGA is also used to control the second driver to enter the initial state and to receive host signals from the first driver after the second driver is initialized and ready.

[0022] In a second aspect of this application, a method for switching between primary and backup motor drivers is provided. The method is applied to a motor driver system, which includes a first driver and a second driver that are redundant with each other. The first driver is the primary driver, and the second driver is the backup driver. The primary driver is in a working state, and the backup driver is in a standby state. The first driver includes a first field-programmable gate array (FPGA) and a first communication module, and the second driver includes a second FPGA and a second communication module. The first communication module includes a first serial communication module, and the second communication module includes a second serial communication module; or, the first communication module includes a first parallel communication module, and the second communication module includes a second parallel communication module.

[0023] The method includes:

[0024] The system controls the first communication module to send a master signal to the second communication module and receive a standby signal from the second communication module; when the first driver fails, the system controls the first communication module to send a standby signal to the second communication module.

[0025] The second communication module is controlled to send a standby signal to the first communication module and receive a host signal from the first communication module; when the second communication module receives the standby signal from the first communication module, the second communication module is controlled to send a host signal to the first communication module.

[0026] One possible implementation of the method further includes:

[0027] When the second serial communication module does not receive a standby signal from the first communication module after a time threshold, the second serial communication module is controlled to send a master signal to the first communication module.

[0028] The system controls the first serial communication module to send the motor angle of the first driver to the second serial communication module, and controls the first serial communication module to receive the host signal from the second serial communication module; when the first serial communication module receives the host signal from the second serial communication module, the system controls the first serial communication module to send the standby signal to the second serial communication module.

[0029] The first communication module includes a first serial communication module, and the second communication module includes a second serial communication module; the master signal and the standby signal are different status signals.

[0030] One possible implementation of the method further includes:

[0031] When the second parallel communication module does not receive a standby signal from the first parallel communication module, it controls the second parallel communication module to send a master signal to the first parallel communication module.

[0032] When the first parallel communication module receives a host signal from the second parallel communication module, it controls the first parallel communication module to send a standby signal to the second parallel communication module.

[0033] The primary and backup signals are different heartbeat signals;

[0034] The first communication module includes a first parallel communication module, and the second communication module includes a second parallel communication module. The first parallel communication module and the second parallel communication module are implemented through an optical coupler.

[0035] One possible implementation of the method further includes:

[0036] Before the first parallel communication module sends the standby signal to the second parallel communication module, the method further includes: the first serial communication module receiving the motor angle from the second serial communication module; the first communication module also includes a first serial communication module, which is used to send the motor angle of the first driver to the second serial communication module.

[0037] The second serial communication module is used to send the motor angle of the second driver to the first serial communication module; the second communication module also includes a second serial communication module.

[0038] Before the second parallel communication module sends a host signal to the first parallel communication module, the process also includes: the second serial communication module does not receive the motor angle from the first serial communication module;

[0039] When the second parallel communication module does not receive a host signal from the first parallel communication module, and the second serial communication module receives a motor angle from the first serial communication module, the second parallel communication module is controlled to send a standby signal to the first parallel communication module.

[0040] Send the motor angle of the first driver to the second serial communication module; send the motor angle of the second driver to the first serial communication module.

[0041] In one possible implementation, before the first drive becomes the host, the method further includes: controlling the first drive to enter an initial state, and sending a host signal to the second drive after the first drive is initialized and ready;

[0042] Before the second drive becomes a standby unit, the method further includes: controlling the second drive to enter an initial state, and receiving a host signal from the first drive after the second drive is initialized and ready.

[0043] The motor drive system provided in this application includes a redundant first driver and a second driver, with the first driver serving as the primary and the second driver as the backup. The first driver includes a first FPGA and a first communication module, while the second driver includes a second FPGA and a second communication module. When the first driver fails, the first FPGA controls the first communication module to send a backup signal to the second communication module, causing the first driver to become the new backup. The second FPGA, based on the backup signal received by the second communication module, controls the second communication module to send a primary signal to the first communication module, causing the second driver to become the new primary, thus enabling the motor drive system to complete the primary / backup switchover under fault conditions. This motor drive system achieves primary / backup switchover through FPGA, resulting in a simple hardware design, low hardware cost, and high flexibility, as the communication module can include either a serial communication module or a parallel communication module. Attached Figure Description

[0044] Figure 1 A schematic diagram of a first type of motor driver system provided in the embodiments of this application;

[0045] Figure 2 This is a schematic diagram of a second type of motor drive system provided in an embodiment of this application;

[0046] Figure 3 This is a schematic diagram of the state switching of a first type of first driver provided in an embodiment of this application;

[0047] Figure 4 This is a schematic diagram of the state switching of a first type of second driver provided in an embodiment of this application;

[0048] Figure 5 A schematic diagram of a third type of motor drive system provided in the embodiments of this application;

[0049] Figure 6 This is a schematic diagram illustrating the state switching of a second type of first driver provided in an embodiment of this application;

[0050] Figure 7This is a schematic diagram of the state switching of a second type of second driver provided in an embodiment of this application;

[0051] Figure 8 This is a schematic diagram of a fourth type of motor drive system provided in the embodiments of this application;

[0052] Figure 9 This is a schematic diagram illustrating the state switching of the third type of first driver provided in an embodiment of this application;

[0053] Figure 10 This is a schematic diagram illustrating the state switching of a third type of second driver provided in an embodiment of this application;

[0054] Figure 11 This is a schematic diagram of the first initial state switching provided in the embodiments of this application;

[0055] Figure 12 This is a schematic diagram of a second initial state switching provided in an embodiment of this application;

[0056] Figure 13 This is a schematic diagram of a third initial state switching provided in an embodiment of this application;

[0057] Figure 14 This is a flowchart of a primary / backup switching method provided in an embodiment of this application. Detailed Implementation

[0058] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0059] See Figure 1 The figure is a schematic diagram of the first type of motor drive system provided in the embodiments of this application.

[0060] The motor drive system provided in this application includes a first driver 10 and a second driver 20 that are redundant with each other. The first driver 10 is the master, that is, the first driver 10 is in working state; the second driver 20 is the standby, that is, the second driver 20 is in standby state.

[0061] The first driver 10 includes a first field-programmable gate array (FPGA) 101 and a first communication module 102, and the second driver 20 includes a second FPGA 201 and a second communication module 202.

[0062] The first FPGA 101 is used to control the first communication module 102 to send a host signal to the second communication module 202 and receive a standby signal from the second communication module 202; when the first driver 10 fails, it controls the first communication module 102 to send a standby signal to the second communication module 202.

[0063] The second FPGA 201 is used to control the second communication module 202 to send a standby signal to the first communication module 102 and to receive a host signal from the first communication module 102; when the second communication module 202 receives the standby signal from the first communication module 102, it controls the second communication module 202 to send a host signal to the first communication module 102.

[0064] Specifically, when the first driver 10 is in normal operating condition, the second driver 20 is in standby condition. The first FPGA 101 is used to control the first communication module 102 to send host signals to the second communication module 202 and to receive standby signals from the second communication module 202; the second FPGA 201 is used to control the second communication module 202 to send standby signals to the first communication module 102 and to receive host signals from the first communication module 102.

[0065] When the first driver 10 fails, the first driver 10 cannot continue to perform normal driving functions. The first FPGA 101 is used to control the first communication module 102 to send a standby signal to the second communication module 202, thereby actively controlling the first driver 10 to be downgraded from the host to the new standby, that is, the first driver 10 is downgraded from the working state to the standby state.

[0066] When the second communication module 202 receives a standby signal from the first communication module 102, the second FPGA 201 controls the second communication module 202 to send a master signal to the first communication module 102, thereby upgrading the second driver from standby to the new master, that is, upgrading the second driver 20 from standby state to working state, and the second driver 20 performs the driving function. After the second driver 20 is upgraded to the new master, the second FPGA 201 is also used to control the second communication module 202 to receive the standby signal from the first communication module 102.

[0067] It should be understood that at this time, the first FPGA 101 is also used to control the first communication module 102 to receive host signals from the second communication module 202.

[0068] The first communication module 102 includes a first serial communication module, and the second communication module 202 includes a second serial communication module; or, the first communication module 102 includes a first parallel communication module, and the second communication module 202 includes a second parallel communication module.

[0069] The motor driver system provided in this application includes a redundant first driver and a second driver, with the first driver serving as the primary and the second driver as the backup. The first driver includes a first FPGA and a first communication module, while the second driver includes a second FPGA and a second communication module. When the first driver fails, the first FPGA controls the first communication module to send a backup signal to the second communication module, causing the first driver to become the new backup. The second FPGA, based on the backup signal received by the second communication module, controls the second communication module to send a primary signal to the first communication module, causing the second driver to become the new primary, thus enabling the motor driver system to complete the primary / backup switchover under fault conditions. This motor driver system achieves primary / backup switchover through FPGA, resulting in simple hardware design, low hardware cost, and high flexibility, as the communication module can include either a serial communication module or a parallel communication module.

[0070] In one possible implementation, the first communication module includes a first serial communication module, and the second communication module includes a second serial communication module.

[0071] See Figure 2 The figure is a schematic diagram of a second type of motor drive system provided in an embodiment of this application.

[0072] Figure 2 and Figure 1 The difference is that, Figure 2 In this configuration, the first communication module includes a first serial communication module 103, and the second communication module includes a second serial communication module 203. Specifically, the first serial communication module 103 includes a first serial transmitting module 1031 and a first serial receiving module 1032; the second serial communication module 203 includes a second serial transmitting module 2031 and a second serial receiving module 2032.

[0073] The second FPGA 201 is also used to control the second serial transmitting module 2031 to send a host signal to the first serial receiving module 1032 when the second serial receiving module 2032 does not receive a standby signal from the first serial transmitting module 1031 after a time threshold.

[0074] The first FPGA 101 is used to control the first serial transmitting module 1031 to send the motor angle of the first driver 10 to the second serial receiving module 2032. The first FPGA 101 is also used to control the first serial receiving module 1032 to receive the host signal from the second serial transmitting module 2031; when the first serial receiving module 1032 receives the host signal from the second serial transmitting module 2031, it controls the first serial transmitting module 1031 to send a standby signal to the second serial receiving module 2032.

[0075] The master signal and the standby signal are different status signals. This application does not specifically limit the type of status signal. In one possible implementation, the status signal may include a state defined by 0 and 1 encoding. For example, in the embodiments of this application, the master signal may be 011 and the standby signal may be 001.

[0076] Specifically, the first FPGA 101 is used to control the first serial transmitting module 1031 to send the motor angle of the first driver 10 to the second serial receiving module 2032. The second FPGA 201 is used to control the second driver 20 to update the starting rotation angle of its own motor according to the motor angle of the first driver 10, so that the motor angle of the second driver 20 is synchronized with the motor angle of the first driver 10, which facilitates seamless switching between the first driver 10 and the second driver 20.

[0077] When the second serial receiving module 2032 fails to receive a host signal from the first serial transmitting module 1031 after a time threshold, it indicates that the first driver 10 may have experienced a power outage or communication interruption. To ensure that the motor continues to drive normally, the second FPGA 201 controls the second driver 20 to become the new host, and the second FPGA 201 controls the second serial transmitting module 2031 to send a host signal to the first serial receiving module 1032.

[0078] When the first serial receiving module 1032 receives the host signal from the second serial transmitting module 2031, in order to ensure that only one motor driver is in working state, the first FPGA 101 controls the first driver 10 to be downgraded to a new standby machine, that is, the first serial transmitting module 1031 sends a standby machine signal to the second serial receiving module 2032.

[0079] This application does not specifically limit the structure of the first serial communication module and the second serial communication module. In one possible implementation, the first serial transmitting module, the first serial receiving module, the second serial transmitting module, and the second serial receiving module can be implemented using transceiver chips. For example, in this application embodiment, the above-mentioned serial communication module can be implemented using an RS485 transceiver chip or an RS422 transceiver chip.

[0080] To enable those skilled in the art to better understand the control logic of the first FPGA and the second FPGA, the switching logic described above will be further explained below with reference to the accompanying drawings.

[0081] See Figure 3 This figure is a schematic diagram of the state switching of the first type of first driver provided in the embodiment of this application.

[0082] Figure 3In the initial state, the first driver is in operation. When the first driver fails, the first FPGA controls the first serial communication module to send a standby status signal, the first driver degrades from the master to the new standby, and the first serial communication module sends a standby status signal. Alternatively, when the first serial communication module receives the master status signal, the first FPGA controls the first driver to degrade from the master to the new standby, and the first serial communication module sends a standby status signal.

[0083] In one possible implementation, when the first driver is operating normally and the first serial communication module does not receive a host status signal, the first driver continues to act as the host.

[0084] See Figure 4 This figure is a schematic diagram of the state switching of the first type of second driver provided in the embodiment of this application.

[0085] Figure 4 In the initial state, the second driver is in hot standby mode, meaning it is ready to go. If the second driver does not receive a master status signal after a time threshold, the second FPGA controls the second serial communication module to send a master status signal, and the second driver is promoted from standby to the new master. Alternatively, when the second serial communication module receives the standby status signal, the second FPGA controls the second driver to be promoted from standby to the new master, and the second serial communication module sends a master status signal.

[0086] In one possible implementation, the second driver continues to act as a standby device when it receives a master status signal within a time threshold, or when the second serial communication module does not receive a standby status signal.

[0087] It should be understood that when the second driver 20 is upgraded to the new host, the second FPGA 201 is also used to control the second serial transmitting module 2031 to send the motor angle of the second driver 20 to the first serial receiving module 1032.

[0088] This application does not specifically limit the value of the time threshold. One possible implementation is that the time threshold can be selected in conjunction with the transmission time of the master signal or the standby signal. For example, the time threshold can be the sum of the transmission time of the master signal, the transmission time of the standby signal, and the signal transmission time. For instance, if the transmission time of the master signal, the transmission time of the standby signal, and the signal transmission time are all T, then the time threshold can be 3T.

[0089] The motor driver system provided in this application embodiment includes a first communication module that may include a first serial communication module, and a second communication module that may include a second serial communication module. A first FPGA can control the first serial communication module to send the motor angle of the first driver to the second serial communication module, thereby ensuring that the motor angle of the second driver is consistent with that of the first driver, facilitating seamless switching between primary and backup. When the second serial communication module does not receive a master signal from the first serial communication module after a time threshold, the second FPGA can control the second driver to become the new master and control the second serial communication module to send a master signal to the first serial communication module. This ensures that even if the first driver experiences power failure or communication failure, the second driver remains operational, guaranteeing the reliability of the motor driver system. When the first serial communication module receives a master signal from the second serial communication module, the first FPGA controls the first driver to become the new backup, ensuring that only one driver is operational in the motor driver system, thus guaranteeing the safety of the motor driver system.

[0090] In one possible implementation, the first communication module includes a first parallel communication module, and the second communication module includes a second parallel communication module. The first parallel communication module and the second parallel communication module are implemented through an optical coupler.

[0091] See Figure 5 This figure is a schematic diagram of a third type of motor drive system provided in an embodiment of this application.

[0092] Figure 5 and Figure 1 The difference is that, Figure 5 In the first communication module, there is a first parallel communication module 104, and the second communication module includes a second parallel communication module 204.

[0093] The first parallel communication module 104 includes a first optical coupler Q1, a second optical coupler Q2, a third optical coupler Q3, and a fourth optical coupler Q4; the second parallel communication module 204 includes a fifth optical coupler Q5, a sixth optical coupler Q6, a seventh optical coupler Q7, and an eighth optical coupler Q8.

[0094] The first input terminal of the first optocoupler Q1 is connected to the first power supply DC1 through the first resistor R1. The second input terminal of the first optocoupler Q1 is connected to the first FPGA101. The first output terminal of the first optocoupler Q1 is connected to the first input terminal of the seventh optocoupler Q7. The second output terminal of the first optocoupler Q1 is connected to the first input terminal of the second optocoupler Q2. The first optocoupler Q1 is used to send host signals.

[0095] The second input terminal of the second optocoupler Q2 is connected to the second input terminal of the seventh optocoupler Q7. The first output terminal of the second optocoupler Q2 is connected to the first power supply DC1 through the second resistor R2. The second output terminal of the second optocoupler Q2 is used to read back the host signal. The second optocoupler Q2 is used to confirm that the host signal was successfully sent.

[0096] The first input terminal of the seventh optocoupler Q7 is connected to the second power supply DC2 through the third resistor R3, the first output terminal of the seventh optocoupler Q7 is connected to the first power supply DC1 through the fourth resistor R4, the first output terminal of the seventh optocoupler Q7 is connected to the second FPGA201, and the second input terminal and the second output terminal of the seventh optocoupler Q7 are connected to the reference ground.

[0097] The first input terminal of the seventh optocoupler Q7 is connected to the first input terminal of the eighth optocoupler Q8 through the fifth resistor R5 and the first diode D1. The first output terminal of the eighth optocoupler Q8 is connected to the first power supply DC1 through the sixth resistor R6. The first output terminal of the eighth optocoupler Q8 is connected to the second FPGA201. The second input terminal and the second output terminal of the eighth optocoupler Q8 are connected to the reference ground.

[0098] This application does not specifically limit the voltage of the first power supply and the second power supply. In one possible implementation, for example, in the embodiments of this application, the voltage of the first power supply can be 2.5V and the voltage of the second power supply can be 24V.

[0099] The second optocoupler Q2 is used to read back the output signal of the first optocoupler Q1 to confirm that the output function of the first parallel communication module 104 is normal. The output signals of the seventh optocoupler Q7 and the eighth optocoupler Q8 are mutually exclusive to confirm that the input function of the second parallel communication module 204 is normal. Specifically, when the output of the first optocoupler Q1 is high, the output of the second optocoupler Q2 is high, the output of the seventh optocoupler Q7 is low, and the output of the eighth optocoupler Q8 is high; when the output of the first optocoupler Q1 is low, the output of the second optocoupler Q2 is low, the output of the seventh optocoupler Q7 is high, and the output of the eighth optocoupler Q8 is low, thus confirming that the output function of the first parallel communication module 104 and the input function of the second parallel communication module 204 are normal.

[0100] The connection relationship between the third optocoupler Q3, the fourth optocoupler Q4, the fifth optocoupler Q5 and the sixth optocoupler Q6 is similar to the connection relationship between the first optocoupler Q1, the second optocoupler Q2, the seventh optocoupler Q7 and the eighth optocoupler Q8, and will not be repeated here.

[0101] The sixth optocoupler Q6 is used to read back the output signal of the fifth optocoupler Q5 to confirm that the output function of the second parallel communication module 204 is normal. The output signals of the third optocoupler Q3 and the fourth optocoupler Q4 are mutually exclusive to confirm that the input function of the first parallel communication module 104 is normal. Specifically, when the output of the fifth optocoupler Q5 is high, the output of the sixth optocoupler Q6 is high, the output of the third optocoupler Q3 is low, and the output of the fourth optocoupler Q4 is high; when the output of the fifth optocoupler Q5 is low, the output of the sixth optocoupler Q6 is low, the output of the third optocoupler Q3 is high, and the output of the fourth optocoupler Q4 is low. This confirms that the output function of the second parallel communication module 204 and the input function of the first parallel communication module 104 are normal.

[0102] This application does not specifically limit the model of the optocoupler; the optocoupler can be selected based on the actual operating conditions. In one possible implementation, when the motor speed of the driver is relatively high or the master / slave switching time is short, a high-speed optocoupler, such as the FOD060L model, can be selected; when the motor speed of the driver is relatively low or the master / slave switching time is long, a low-speed optocoupler, such as the MOCD213 model, can be selected.

[0103] The second FPGA 201 is also used to control the second parallel communication module 204 to send a host signal to the first parallel communication module 104 when the second parallel communication module 204 does not receive a standby signal from the first parallel communication module 104.

[0104] The first FPGA 101 is also used to control the first parallel communication module 104 to send a standby signal to the second parallel communication module 204 when the first parallel communication module 104 receives a host signal from the second parallel communication module 204.

[0105] Specifically, when the second parallel communication module 204 does not receive a standby signal from the first parallel communication module 104, it indicates that the first driver 10 may have experienced a power failure or communication interruption. To ensure that the motor can still be driven normally, the second FPGA 201 is used to control the second driver 20 to become the new master, and the second FPGA 201 controls the second parallel communication module 204 to send a master signal to the first parallel communication module 104.

[0106] When the first parallel communication module 104 receives a host signal from the second parallel communication module 204, in order to ensure that only one motor driver is in working state, the first FPGA 101 controls the first driver 10 to be downgraded to a new standby machine, that is, the first parallel communication module 104 sends a standby machine signal to the second parallel communication module 204.

[0107] In this embodiment, the master signal and the standby signal are different heartbeat signals. This application does not specifically limit the frequency of the heartbeat signals; one possible implementation is that the frequency of the heartbeat signals can be 1 kHz, meaning the length of each heartbeat signal is 1 ms. For example, in this embodiment, the parameters of the master signal and the standby signal can be as shown in the table below.

[0108] High level (µs) High level lower limit (µs) High level limit (µs) High-level pulse count (25ns per pulse) High-level lower limit pulse count (25ns per pulse) High-level upper limit pulse count (25ns per pulse) host signal 700 500 900 28000 20000 36000 standby signal 300 100 500 12000 4000 20000

[0109] In the table above, the master signal includes a 700µs high level and a 300µs low level, while the standby signal includes a 300µs high level and a 700µs low level. To reduce the impact of external signal interference and improve fault tolerance, signals with a high level length between 500µs and 900µs can be considered master signals, and signals with a high level length between 100µs and 500µs can be considered standby signals. The high level of the heartbeat signal consists of multiple pulses, with a single pulse length of 25ns. Therefore, the high level of the master signal corresponds to 28,000 pulses, and signals with 20,000 to 36,000 high-level pulses are considered master signals. The high level of the standby signal corresponds to 12,000 pulses, and signals with 4,000 to 20,000 high-level pulses are considered standby signals.

[0110] Figure 5 The third optocoupler Q3, the fourth optocoupler Q4, the seventh optocoupler Q7, and the eighth optocoupler Q8 can be used to detect whether the high level of the input signal is within the upper and lower limits. When the signal received by the parallel communication module is higher than the upper limit of the high level of the host signal or lower than the lower limit of the high level of the backup signal, it indicates that the signal is not the required host signal or backup signal, and the corresponding FPGA will issue an alarm.

[0111] Figure 5 The second optocoupler Q2 and the sixth optocoupler Q6 in the module can be used to detect whether the high level of the transmitted signal is within the upper and lower limits. For parallel communication modules that need to transmit master signals, if the transmitted signal is lower than the lower limit of the master signal's high level or higher than the upper limit of the master signal's high level, it indicates that the signal is not the required master signal, and the corresponding FPGA will issue an alarm. Similarly, for parallel communication modules that need to transmit backup signals, if the transmitted signal is lower than the lower limit of the backup signal's high level or higher than the upper limit of the backup signal's high level, it indicates that the signal is not the required backup signal, and the corresponding FPGA will issue an alarm.

[0112] See Figure 6 This figure is a schematic diagram of the state switching of the second type of first driver provided in the embodiment of this application.

[0113] Figure 6 and Figure 3The difference lies in that the master signal is specifically the master heartbeat signal, and the standby signal is specifically the standby heartbeat signal.

[0114] In one possible implementation, when the first driver is operating normally and the first parallel communication module does not receive a host status signal, the first driver continues to act as the host.

[0115] See Figure 7 This figure is a schematic diagram of the state switching of the second type of second driver provided in the embodiment of this application.

[0116] Because parallel communication has higher real-time performance than serial communication, Figure 7 and Figure 4 The difference is that when the second driver does not receive the host signal, the second FPGA controls the second driver to become the new host from the backup, and the second parallel communication module sends the host signal.

[0117] In one possible implementation, when the second parallel communication module does not receive a standby status signal, the second driver continues to act as a standby device.

[0118] The motor driver system provided in this application embodiment includes a first communication module that may include a first parallel communication module, and a second communication module that may include a second parallel communication module. It features high communication speed and high system real-time performance. The first and second parallel communication modules can be implemented using optocouplers, allowing for selection of the optocoupler type based on operating conditions, thus offering high flexibility. The operating status of the parallel communication modules can be determined based on the output of different optocouplers. Furthermore, the system can monitor the master and backup signals in real time by observing the hardware status, providing timely alarms when signals exceed upper or lower limits, demonstrating self-diagnostic capabilities. When the second driver does not receive a master signal, the second FPGA controls the second driver to become the new master from the backup, resulting in simple and easy-to-implement control logic.

[0119] In one possible implementation, the first communication module further includes a first serial communication module, and the second communication module further includes a second serial communication module. The first serial communication module is used to send the motor angle of the first driver to the second serial communication module, and the second serial communication module is used to send the motor angle of the second driver to the first serial communication module.

[0120] See Figure 8 This figure is a schematic diagram of the fourth type of motor drive system provided in the embodiments of this application.

[0121] Figure 8 and Figure 5 The difference is that the first communication module 102 also includes a first serial communication module 103, and the second communication module 202 also includes a second serial communication module 203.

[0122] When the first driver 10 is the master, the first serial communication module 103 is used to send the motor angle of the first driver 10 to the second serial communication module 203 so that the motor angle of the second driver 20 is synchronized with the first driver 10.

[0123] Before the first FPGA 101 controls the first parallel communication module 104 to send a standby signal to the second parallel communication module, the method further includes: the first serial communication module 103 receiving a signal from the second serial communication module 203.

[0124] Since the motor angle transmitted by the serial communication module is sent from the master to the standby machine, the current status of the master and standby machines can be reconfirmed based on the transmission direction of the motor angle.

[0125] Specifically, after the first parallel communication module 104 receives the host signal from the second parallel communication module 204, the first FPGA is also used to determine whether the first serial receiving module 1032 has received the motor angle from the second serial transmitting module 2031. When the first serial receiving module 1032 receives the motor angle from the second serial transmitting module 2031, it can be confirmed that the second driver 20 is the host. At this time, the first FPGA 101 controls the first parallel communication module 104 to send a standby signal to the second parallel communication module 204.

[0126] See Figure 9 This figure is a schematic diagram of the state switching of the third type of first driver provided in the embodiments of this application.

[0127] Figure 9 and Figure 6 The difference is that after the first parallel communication module receives the host signal from the second parallel communication module, and when the first serial communication module receives the motor angle from the second serial communication module, it controls the first driver to be downgraded from the host to the new standby.

[0128] In one possible implementation, when the first parallel communication module does not receive a host signal from the second parallel communication module, or when the first parallel communication module receives a host signal from the second parallel communication module and the first serial communication module does not receive a motor angle from the second serial communication module, the first driver continues to act as the host.

[0129] Similarly, the second communication module 202 also includes a second serial communication module 203. When the second driver 20 is the master, the second serial communication module 203 is used to send the motor angle of the second driver 20 to the first serial communication module 103 so that the motor angle of the first driver 10 is synchronized with the second driver 20.

[0130] Before the second FPGA 201 controls the second parallel communication module 204 to send a host signal to the first parallel communication module 104, it also includes the following: the second serial communication module 203 does not receive a signal from the first serial communication module 103.

[0131] When the second serial receiving module 2032 does not receive the motor angle from the first serial transmitting module 1031, the second driver 20 can be confirmed as the master. At this time, the second FPGA 201 controls the second parallel communication module 204 to send a standby signal to the first parallel communication module 104.

[0132] The second FPGA 201 is also used to control the second parallel communication module 204 to send a standby signal to the first parallel communication module 104 when the host of the second parallel communication module 204 does not receive a host signal from the first parallel communication module 104 and the second serial communication module 203 receives a motor angle from the first serial communication module 103.

[0133] Specifically, when the second serial receiving module 2032 receives the motor angle from the first serial transmitting module 1031, it indicates that the first driver 10 is the master at this time. The fact that the second parallel communication module 204, as the master, does not receive the master signal from the first parallel communication module 104 may be due to external interference affecting the parallel communication. The second FPGA 201 confirms that the second driver 20 is still the standby machine and controls the second parallel communication module 204 to send a standby signal to the first parallel communication module 104.

[0134] See Figure 10 This figure is a schematic diagram of the state switching of the third type of second driver provided in the embodiments of this application.

[0135] Figure 10 and Figure 7 The difference is that when the second parallel communication module does not receive the host signal, and when the second serial communication module receives the motor angle, the second driver remains in standby mode, and the second FPGA controls the second parallel communication module to send the standby signal; when the second serial communication module does not receive the motor angle, the second FPGA controls the second driver to become the new host from the standby mode, and the second parallel communication module sends the host signal.

[0136] In one possible implementation, when the second parallel communication module receives a host signal, the second driver continues to act as a backup.

[0137] The motor driver system provided in this application embodiment includes a first communication module that may include a first parallel communication module and a first serial communication module, and a second communication module that may include a second parallel communication module and a second serial communication module. The serial communication module corresponding to the driver in master mode can send the motor angle, facilitating seamless master-slave switching. After the parallel communication module receives the master signal, it performs a secondary confirmation of whether the serial communication module has received the motor angle, which improves the anti-interference capability of the motor driver system and enhances its reliability.

[0138] In one possible implementation, before the first driver becomes the master, the first FPGA is further configured to control the first driver to enter an initial state and send a master signal to the second driver after the first driver is initialized and ready. Before the second driver becomes the standby, the second FPGA is further configured to control the second driver to enter an initial state and receive a master signal from the first driver after the second driver is initialized and ready.

[0139] Since the master / slave allocation is not completed in the initial state, a "master contention" process is required, whereby the driver competes for the master status by sending a master signal. To help those skilled in the art better understand the master and slave status allocation logic, further explanation is provided below with reference to the accompanying drawings.

[0140] See Figure 11 This figure is a schematic diagram of the first initial state switching provided in the embodiment of this application.

[0141] Figure 11 In this configuration, the first communication module includes a first serial communication module, and the second communication module includes a second serial communication module.

[0142] After the first driver is initialized and ready, if the first serial communication module does not receive a master signal from the second serial communication module, the first FPGA controls the first serial communication module to send a master signal to the second serial communication module. When the first serial communication module receives a standby signal from the second serial communication module, it confirms that the first driver is the master; when the first serial communication module does not receive a standby signal from the second serial communication module, the first FPGA controls the first serial communication module to continue sending a master signal to the second serial communication module, and confirms that the first driver is the master after a time threshold.

[0143] After the second driver is initialized and ready, when the second serial communication module receives a host signal from the first serial communication module, the second FPGA confirms that the second driver is a standby device.

[0144] See Figure 12 This figure is a schematic diagram of the second initial state switching provided in the embodiment of this application.

[0145] Figure 12 In this configuration, the first communication module includes a first parallel communication module, and the second communication module includes a second parallel communication module.

[0146] After the first driver is initialized and ready, if the first parallel communication module does not receive a host signal from the second parallel communication module, the first FPGA confirms that the first driver is the host and controls the first parallel communication module to send a host signal to the second parallel communication module.

[0147] After the second driver is initialized and ready, the second parallel communication module receives the host signal from the first parallel communication module, and then the second FPGA confirms that the second driver is the standby device.

[0148] See Figure 13 This figure is a schematic diagram of the third initial state switching provided in the embodiment of this application.

[0149] Figure 13 In this system, the first communication module includes a first serial communication module and a first parallel communication module, and the second communication module includes a second serial communication module and a second parallel communication module.

[0150] After the first driver is initialized and ready, if the first parallel communication module does not receive a host signal from the second parallel communication module and the first serial communication module does not receive a motor angle from the second serial communication module, then the first FPGA confirms that the first driver is the host and controls the first parallel communication module to send a host signal to the second parallel communication module.

[0151] After the second driver is initialized and ready, if the second parallel communication module receives a master signal from the first parallel communication module, the second FPGA confirms that the second driver is a standby device and controls the second parallel communication module to send a standby signal to the first parallel communication module. Alternatively, if the second parallel communication module does not receive a master signal from the first parallel communication module, but the second serial communication module receives a motor angle from the first serial communication module, the second FPGA confirms that the second driver is a standby device and controls the second parallel communication module to send a standby signal to the first parallel communication module.

[0152] In one possible implementation, when the first driver initialization is not ready, the first FPGA is also used to control the first driver to reinitialize; when the second driver initialization is not ready, the second FPGA is also used to control the second driver to reinitialize.

[0153] The motor driver system provided in this application embodiment first initializes and sends a host signal to become the host state, which can realize the reasonable allocation of host state and standby state in the initialization state.

[0154] Based on the motor driver system provided in the above embodiments, this application also provides a master-slave switching method for the motor driver. The master-slave switching method provided in this application is applied to the motor driver system provided in the above embodiments. The motor driver system includes a first driver and a second driver that are redundant with each other; the first driver is the master, and the second driver is the standby; the master is in a working state, and the standby is in a standby state; the first driver includes a first field-programmable gate array (FPGA) and a first communication module, and the second driver includes a second FPGA and a second communication module; the first communication module includes a first serial communication module, and the second communication module includes a second serial communication module; or, the first communication module includes a first parallel communication module, and the second communication module includes a second parallel communication module.

[0155] See Figure 14 The figure is a flowchart of a primary / backup switching method provided in an embodiment of this application.

[0156] The method includes:

[0157] S141: Control the first communication module to send a host signal to the second communication module and receive a standby signal from the second communication module; when the first driver fails, control the first communication module to send a standby signal to the second communication module.

[0158] For example, the first FPGA controls the first communication module to send a host signal to the second communication module and receive a standby signal from the second communication module; when the first driver fails, it controls the first communication module to send a standby signal to the second communication module.

[0159] S142: Control the second communication module to send a standby signal to the first communication module and receive a host signal from the first communication module; when the second communication module receives the standby signal from the first communication module, control the second communication module to send a host signal to the first communication module.

[0160] For example, the second FPGA controls the first communication module to send a host signal to the second communication module and receive a standby signal from the second communication module; when the first driver fails, it controls the first communication module to send a standby signal to the second communication module.

[0161] In the above methods, S141 and S142 are not executed in any particular order.

[0162] The primary / backup switching method provided in this application embodiment, when the first driver fails, controls the first communication module to send a backup signal to the second communication module, thereby controlling the first driver to become the new backup; according to the backup signal received by the second communication module, controls the second communication module to send a backup signal to the first communication module, thereby controlling the second driver to become the new primary driver, so that the motor driver system completes the primary / backup switching under fault conditions.

[0163] One possible implementation of the method further includes:

[0164] When the second serial communication module does not receive a standby signal from the first communication module after a time threshold, the second serial communication module is controlled to send a master signal to the first communication module.

[0165] The system controls the first serial communication module to send the motor angle of the first driver to the second serial communication module, and controls the first serial communication module to receive the host signal from the second serial communication module; when the first serial communication module receives the host signal from the second serial communication module, the system controls the first serial communication module to send the standby signal to the second serial communication module.

[0166] The first communication module includes a first serial communication module, and the second communication module includes a second serial communication module; the master signal and the standby signal are different status signals.

[0167] One possible implementation of the method further includes:

[0168] When the second parallel communication module does not receive a standby signal from the first parallel communication module, it controls the second parallel communication module to send a master signal to the first parallel communication module.

[0169] When the first parallel communication module receives a host signal from the second parallel communication module, it controls the first parallel communication module to send a standby signal to the second parallel communication module.

[0170] The master signal and the standby signal are different heartbeat signals; the first communication module includes a first parallel communication module, and the second communication module includes a second parallel communication module. The first parallel communication module and the second parallel communication module are implemented through an optocoupler.

[0171] One possible implementation of the method further includes:

[0172] Before the first parallel communication module sends the standby signal to the second parallel communication module, the method further includes: the first serial communication module receiving the motor angle from the second serial communication module; the first communication module also includes a first serial communication module, which is used to send the motor angle of the first driver to the second serial communication module.

[0173] The second serial communication module is used to send the motor angle of the second driver to the first serial communication module; the second communication module also includes a second serial communication module.

[0174] Before the second parallel communication module sends a host signal to the first parallel communication module, the process also includes: the second serial communication module does not receive the motor angle from the first serial communication module;

[0175] When the second parallel communication module does not receive a host signal from the first parallel communication module, and the second serial communication module receives a motor angle from the first serial communication module, the second parallel communication module is controlled to send a standby signal to the first parallel communication module.

[0176] Send the motor angle of the first driver to the second serial communication module; send the motor angle of the second driver to the first serial communication module.

[0177] In one possible implementation, before the first drive becomes the host, the method further includes: controlling the first drive to enter an initial state, and sending a host signal to the second drive after the first drive is initialized and ready;

[0178] Before the second drive becomes a standby unit, the method further includes: controlling the second drive to enter an initial state, and receiving a host signal from the first drive after the second drive is initialized and ready.

[0179] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0180] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A motor driver system, characterized in that, include: The first and second drivers are redundant with each other; The first drive is the primary drive, and the second drive is the backup drive; The host machine is in working state, and the standby machine is in standby state; The first driver includes a first field-programmable gate array (FPGA) and a first communication module, and the second driver includes a second FPGA and a second communication module; The first FPGA is used to control the first communication module to send a host signal to the second communication module and to receive a standby signal from the second communication module. When the first driver fails, the first communication module is controlled to send the backup signal to the second communication module; The second FPGA is used to control the second communication module to send the backup signal to the first communication module and to receive the host signal from the first communication module; When the second communication module receives the standby signal from the first communication module, it controls the second communication module to send the host signal to the first communication module; The first communication module includes a first serial communication module, and the second communication module includes a second serial communication module; or, the first communication module includes a first parallel communication module, and the second communication module includes a second parallel communication module.

2. The system according to claim 1, characterized in that, The first communication module includes a first serial communication module, and the second communication module includes a second serial communication module; The second FPGA is further configured to control the second serial communication module to send the host signal to the first serial communication module when the second serial communication module does not receive the host signal or the standby signal from the first serial communication module after a time threshold. The first FPGA is further configured to control the first serial communication module to send the motor angle of the first driver to the second serial communication module, and control the first serial communication module to receive the host signal from the second serial communication module; when the first serial communication module receives the host signal from the second serial communication module, control the first serial communication module to send the standby signal to the second serial communication module; the host signal and the standby signal are different status signals.

3. The system according to claim 1, characterized in that, The first communication module includes a first parallel communication module, and the second communication module includes a second parallel communication module. The first parallel communication module and the second parallel communication module are implemented through an optical coupler. The second FPGA is further configured to control the second parallel communication module to send the host signal to the first parallel communication module when the second parallel communication module does not receive the host signal from the first parallel communication module; The first FPGA is further configured to control the first parallel communication module to send the standby signal to the second parallel communication module when the first parallel communication module receives the host signal from the second parallel communication module; the host signal and the standby signal are different heartbeat signals.

4. The system according to claim 3, characterized in that, The first communication module further includes the first serial communication module, which is used to send the motor angle of the first driver to the second serial communication module. Before the first FPGA controls the first parallel communication module to send the standby signal to the second parallel communication module, the method further includes: the first serial communication module receiving the motor angle from the second serial communication module; The second communication module further includes a second serial communication module, which is used to send the motor angle of the second driver to the first serial communication module; Before the second FPGA controls the second parallel communication module to send the host signal to the first parallel communication module, the method further includes: the second serial communication module does not receive the motor angle from the first serial communication module; The second FPGA is further configured to control the second parallel communication module to send the standby signal to the first parallel communication module when the second parallel communication module does not receive the host signal from the first parallel communication module and the second serial communication module receives the motor angle from the first serial communication module.

5. The system according to any one of claims 1 to 4, characterized in that, Before the first driver becomes the host, the first FPGA is also used to control the first driver to enter the initial state and send the host signal to the second driver after the first driver is initialized and ready. Before the second driver becomes a standby device, the second FPGA is also used to control the second driver to enter an initial state and to receive the host signal from the first driver after the second driver is initialized and ready.

6. A method for master / slave switching of a motor driver, characterized in that, The method is applied to a motor drive system, which includes a first driver and a second driver that are redundant with each other; the first driver is the master driver and the second driver is the standby driver; the master driver is in a working state and the standby driver is in a standby state; the first driver includes a first field-programmable gate array (FPGA) and a first communication module, and the second driver includes a second FPGA and a second communication module; the first communication module includes a first serial communication module and the second communication module includes a second serial communication module. Alternatively, the first communication module may include a first parallel communication module, and the second communication module may include a second parallel communication module; The method includes: The system controls the first communication module to send a host signal to the second communication module and receive a standby signal from the second communication module; when the first driver fails, the system controls the first communication module to send the standby signal to the second communication module. The second communication module is controlled to send the standby signal to the first communication module and receive the host signal from the first communication module; when the second communication module receives the standby signal from the first communication module, the second communication module is controlled to send the host signal to the first communication module.

7. The method according to claim 6, characterized in that, The method also includes: When the second serial communication module does not receive the standby signal from the first communication module after a time threshold, the second serial communication module is controlled to send the host signal to the first communication module. The system controls the first serial communication module to send the motor angle of the first driver to the second serial communication module, and controls the first serial communication module to receive the host signal from the second serial communication module; when the first serial communication module receives the host signal from the second serial communication module, the system controls the first serial communication module to send the standby signal to the second serial communication module. The first communication module includes the first serial communication module, and the second communication module includes the second serial communication module; the host signal and the standby signal are different status signals.

8. The method according to claim 6, characterized in that, The method also includes: When the second parallel communication module does not receive the backup signal from the first parallel communication module, the second parallel communication module is controlled to send the master signal to the first parallel communication module. When the first parallel communication module receives the host signal from the second parallel communication module, it controls the first parallel communication module to send the standby signal to the second parallel communication module. The host signal and the standby signal are different heartbeat signals; The first communication module includes a first parallel communication module, and the second communication module includes a second parallel communication module. The first parallel communication module and the second parallel communication module are implemented through an optical coupler.

9. The method according to claim 8, characterized in that, The method also includes: Before the first parallel communication module sends the standby signal to the second parallel communication module, the method further includes: the first serial communication module receiving the motor angle from the second serial communication module; the first communication module further includes the first serial communication module, which is used to send the motor angle of the first driver to the second serial communication module. The second serial communication module is used to send the motor angle of the second driver to the first serial communication module; the second communication module also includes the second serial communication module. Before the second parallel communication module sends the host signal to the first parallel communication module, the method further includes: the second serial communication module does not receive the motor angle from the first serial communication module; When the second parallel communication module does not receive the host signal from the first parallel communication module and the second serial communication module receives the motor angle from the first serial communication module, the second parallel communication module is controlled to send the standby signal to the first parallel communication module. Send the motor angle of the first driver to the second serial communication module; send the motor angle of the second driver to the first serial communication module.

10. The method according to any one of claims 6 to 9, characterized in that, Before the first driver is the host, the method further includes: controlling the first driver to enter an initial state, and sending the host signal to the second driver after the first driver is initialized and ready; Before the second driver is a standby device, the method further includes: controlling the second driver to enter an initial state, and receiving the host signal from the first driver after the second driver is initialized and ready.

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