High precision automatic gain control feedback regulation method and system

Abstract

The application relates to a high-precision automatic gain control feedback adjustment method and system, which comprises the following steps: calculating a real-time power deviation value of an input signal; taking the power deviation value as an index to query a lookup table to obtain a coarse gain adjustment factor; using state monitoring logic to dynamically switch a filtering strategy according to the state of the deviation value to perform nonlinear smoothing processing on the coarse gain to output a fine gain adjustment factor; and using a multiplier to perform closed-loop gain compensation. The application replaces hardware division operation by table mapping, and uses three-state control logic including locking, rapid suppression and smooth recovery to reduce hardware resource consumption, consider noise suppression in a steady state and rapid response in a transient state, and realize high-precision gain locking.

Description

Technical Field

[0001] This application relates to the field of radar detection, and in particular to a high-precision automatic gain control feedback adjustment method and system. Background Technology

[0002] In modern digital communication, radar detection, and industrial measurement signal processing systems, automatic gain control (AGC) plays a fundamental role in maintaining the stability of the received signal amplitude. With the continuous increase in signal processing bandwidth and system integration, hardware processing platforms such as field-programmable gate arrays (FPGAs) place higher demands on the efficiency of logic resource allocation. In traditional AGC algorithm implementations, to accurately calculate the required gain adjustment, designers typically use a mathematical model based on real-time division, i.e., calculating the ratio of the target power to the current detected power using a hardware divider. While this direct calculation method theoretically yields continuous and accurate gain control words, it faces challenges in terms of hardware resource consumption in practical engineering deployments. Hardware division logic is a highly complex arithmetic unit in digital circuit implementations, requiring not only a large amount of digital signal processing slices or general-purpose logic resources, but also often becoming a bottleneck restricting the increase of system clock frequency due to its long pipeline delay, increasing the difficulty of timing convergence.

[0003] To avoid the resource overhead of hardware dividers, existing technologies often use lookup tables as an alternative. This method stores pre-calculated gain values ​​in memory and directly retrieves the gain factor using the power deviation value as an address index, thus transforming complex division operations into simple memory read operations. However, traditional direct lookup table schemes present an irreconcilable contradiction between storage capacity and control precision. To achieve high-precision, smooth adjustment, the depth and bit width of the lookup table must be significantly increased, leading to a substantial rise in on-chip memory consumption. Conversely, if the size of the lookup table is limited to control storage costs, the gain factor output from the lookup table will exhibit a distinct stepped discrete characteristic. This discontinuous gain transition introduces quantization noise during signal amplitude adjustment, causing a step effect in the output signal envelope, thereby degrading the signal-to-noise ratio or affecting the decision accuracy of subsequent demodulation circuits.

[0004] Furthermore, when faced with dynamically changing input signals, a simple static lookup table mechanism lacks the ability to smooth the time domain of the gain adjustment process. When the coarse gain factor output by the lookup table is directly applied to the signal, it is prone to causing abrupt amplitude changes at the moment of gain switching. Summary of the Invention

[0005] In order to eliminate the quantization error caused by the lookup table method in resource-constrained embedded systems without relying on hardware dividers and without consuming a large amount of storage resources, and to transform discrete coarse gains into continuous fine gains in order to achieve high-precision and low-latency closed-loop control, this application provides a high-precision automatic gain control feedback adjustment method and system.

[0006] Firstly, this application provides a high-precision automatic gain control feedback adjustment method, which adopts the following technical solution: A high-precision automatic gain control feedback adjustment method includes the following steps: S1. Receive the input signal, calculate the real-time power value of the input signal, compare the real-time power value with the preset target power threshold, and generate a power deviation value representing the difference between the real-time power value and the target power threshold; S2. Using the power deviation value as the index address, query the pre-configured lookup table and directly read the coarse gain adjustment factor corresponding to the power deviation value from the lookup table. The lookup table stores pre-calculated gain mapping data. S3. Input the power deviation value into the status monitoring logic, dynamically adjust the filtering strategy according to the absolute value and positive / negative sign of the power deviation value, perform nonlinear smoothing on the coarse gain adjustment factor, and output the fine gain adjustment factor. S4. Use a multiplier to multiply the fine gain adjustment factor with the input signal, and output the amplitude-adjusted input signal.

[0007] By adopting the above technical solution, the power detection and deviation acquisition step quantizes the difference between the real-time signal power in the analog domain and the target threshold into an address index in the digital domain. The lookup table mapping module uses this index to directly retrieve the preset gain data from the memory, transforming the resource-intensive real-time division operation into a low-latency logical addressing operation. This eliminates the dependence of the feedback loop on hardware divider resources and shortens the operation cycle.

[0008] The adaptive state filtering step dynamically reconstructs the filter's transfer function and response characteristics based on the physical amplitude and sign characteristics of the power deviation. When the deviation is within a small range, the system employs a high-damping smoothing strategy to physically block high-frequency quantization noise from disturbing the gain control word and suppressing digital jitter in steady state. When the deviation deviates significantly or the polarity reverses, the system automatically switches to a fast response path to reduce the inertial delay of the filtering stage and ensure rapid tracking and locking of sudden signal amplitudes.

[0009] The nonlinear smoothing logic constructs a continuous transition trajectory between discrete lookup table outputs, filling the numerical gaps caused by the lookup table quantization interval through numerical operations in the time domain. This processing method eliminates the gain step phenomenon caused by direct lookup, enabling the fine gain adjustment factor of the output to approach the ideal gain value with an accuracy exceeding the physical resolution of the lookup table. Thus, lossless adjustment and high-precision convergence of the output signal envelope are achieved while maintaining low storage overhead.

[0010] Optionally, step S3 includes the following sub-steps: S31. Receive power deviation values, compare the absolute value of the power deviation value with a preset dead zone threshold and a preset ultra-fast response threshold respectively, and determine the current operating state of the system based on the comparison results; wherein, the operating state includes a locked state, an ultra-fast suppression state, and a smooth recovery state, the locked state is the state when the absolute value of the power deviation value is less than the preset dead zone threshold; the ultra-fast suppression state is the state when the power deviation value is positive and the absolute value of the power deviation value is greater than the preset ultra-fast response threshold; the smooth recovery state is any state other than the locked state and the ultra-fast suppression state; S32. When the working state determined in step S31 is the locked state, freeze the output of the adaptive state filtering step, forcibly keep the fine gain adjustment factor output at the previous moment unchanged, and use the fine gain adjustment factor output at the previous moment as the fine gain adjustment factor output at the current moment. S33. When the working state determined in S31 is the extreme speed suppression state, the state monitoring logic is controlled to enter the minimum delay response mode, the coarse gain adjustment factor is processed using the first shift parameter, and the processed value is output as the fine gain adjustment factor at the current moment. S34. When the working state determined in S31 is the smooth recovery state, the state monitoring logic is controlled to enter the smoothing filtering mode, and the coarse gain adjustment factor is processed using the second shift parameter, and the smoothed value is output as the fine gain adjustment factor at the current moment.

[0011] By employing the above technical solutions, the adaptive state filtering step divides the continuous power deviation domain into discrete logic control intervals using dead-zone thresholds and ultra-fast response thresholds, constructing a segmented response mechanism based on the physical magnitude of the deviation value. The locked-state logic physically cuts off the error data update path when the absolute value of the deviation falls into the dead zone, forcing the output to maintain the gain state of the previous moment. This blocks the transmission of small-amplitude quantization noise or background noise to the gain control word, eliminating digital jitter caused by noise disturbances in steady state. The ultra-fast suppression state logic bypasses the high-inertia filtering channel for large-amplitude positive deviations, directly using a low-delay path to output a gain attenuation signal, ensuring the system can instantly respond to high-energy burst signals and preventing overload clipping in the subsequent analog-to-digital conversion circuit. The smooth recovery state logic takes over signal fluctuations of normal amplitude, enabling a smoothing filtering mode to shape gain changes, ensuring the linearity and integrity of the signal envelope in non-burst states.

[0012] Optionally, in steps S33 and S34, the state monitoring logic performs shift operation logic based on dynamic coefficients, the steps of which include: S341. Receive the coarse gain adjustment factor at the current time and obtain the fine gain adjustment factor output at the previous time, and calculate the numerical difference between the coarse gain adjustment factor at the current time and the fine gain adjustment factor output at the previous time. S342. Select the corresponding number of shift bits according to the determined working state, and perform a right shift operation on the numerical difference to obtain the shifted increment value; S343. Add the shifted increment value to the fine gain adjustment factor output at the previous time step to obtain the fine gain adjustment factor at the current time step.

[0013] By employing the above technical solution, the shift operation logic utilizes the numerical difference calculation stage to obtain the instantaneous jump variable of the current coarse gain relative to the historical state, and then digitally attenuates this jump variable through a right shift operation. The right shift operation is equivalent in hardware to introducing a configurable damping coefficient, transforming a large step signal into a small incremental step. Subsequent accumulation and update steps integrate these attenuated increments into the historical fine gain, thereby constructing a first-order inertial smoothing system in the time domain. This processing method eliminates the discrete step characteristics of the lookup table output, enabling the final output gain control word to approach the target value in an asymptotically convergent manner. It effectively suppresses signal spectral spread or phase distortion caused by sudden gain changes, and the entire process only occupies adder and shift register resources, avoiding the overhead of hardware multipliers.

[0014] Optionally, in step S342: When the operating status is indicated as the extreme speed suppression state, the number of shift bits is configured as the first shift parameter; When the operating status is indicated as smooth recovery, the number of shift bits is configured as the second shift parameter; wherein the value of the first shift parameter is less than the value of the second shift parameter.

[0015] By employing the above technical solution, the differentiated configuration of the shift bit parameter endows the feedback loop with asymmetric time-domain response characteristics. In the extreme suppression state, a smaller first shift parameter reduces the attenuation of the logarithmic difference in the right shift operation, allowing a larger gain adjustment to be quickly superimposed on the output, physically shortening the loop's integration time constant and achieving millisecond-level interception of overload signals. In the smooth recovery state, a larger second shift parameter significantly increases the attenuation of the logarithmic difference, extending the loop's integration time constant, resulting in a slow, gradual increase in gain during the recovery process. This asymmetric mechanism, while ensuring system safety, avoids the rapid amplification of background noise during the signal recovery phase due to excessively rapid gain changes, thus preventing the perceived breathing effect or drastic fluctuations in the signal-to-noise ratio in the data link.

[0016] Optionally, step S34 may also include step S344, which is executed in parallel with steps S342 and S343: When performing the right shift operation in step S342, the low-order data portion that was truncated due to the shift operation is extracted and temporarily stored as a residual value; In the next calculation cycle, the temporarily stored residual value is superimposed with the numerical difference calculated in step S341 in the next calculation cycle, and the combined value after superposition is used as the operand to perform the right shift operation in step S342.

[0017] By employing the aforementioned technical solution, the residual cyclic compensation step physically extracts the low-order data stream that is truncated and discarded during the right shift operation, transforming the precision information inevitably lost in a single digital operation into a temporarily stored energy residual, which is then fed back and superimposed onto the input data stream of the next calculation cycle. This cross-clock-cycle error feedback mechanism allows minute power deviations, which would otherwise be insufficient to trigger a single shift change, to accumulate over time until their accumulated value exceeds the minimum resolution threshold of the digital system, thereby driving gain updates. This technique, while maintaining the hardware register bit width unchanged, eliminates the steady-state error caused by integer operation truncation through a time-for-precision strategy, achieving sub-pixel-level fine-tuning of the gain control word beyond physical bit precision.

[0018] Optionally, the first shift parameter and the second shift parameter are variable parameters that are dynamically mapped based on real-time power values. The dynamic mapping logic follows these rules: When the real-time power value is in the preset low power range, increase the values ​​of the first shift parameter and the second shift parameter to reduce the rate of change of the fine gain adjustment factor. When the real-time power value is in the preset high power range, the values ​​of the first shift parameter and the second shift parameter are reduced to increase the rate of change of the fine gain adjustment factor.

[0019] By employing the above technical solution, the dynamic parameter mapping logic directly modulates the integral time constant of the feedback loop using the absolute power physical quantity of the real-time signal, constructing a damping characteristic that adaptively changes with the signal energy environment. In the preset low-power range, increasing the shift parameter physically attenuates the gain adjustment step rate, effectively shrinking the control loop's bandwidth. This utilizes the large inertia characteristic to suppress the system's over-response to background noise or weak interference, preventing noise pumping or breathing effects in low signal-to-noise ratio environments. In the preset high-power range, decreasing the shift parameter physically releases the gain adjustment response speed, effectively expanding the control loop's bandwidth. This ensures the system can track transient changes in high-energy signals with extremely low phase delay, preventing amplitude overload or waveform clipping distortion in subsequent circuits due to response lag.

[0020] Secondly, this application provides a high-precision automatic gain control feedback adjustment system, which adopts the following technical solution: A high-precision automatic gain control feedback adjustment system includes: The power detection module is configured to receive input signals, calculate real-time power values, and output a power deviation value representing the difference between the real-time power value and a preset target power threshold. The lookup table mapping module has a pre-configured lookup table built in. The lookup table mapping module is configured to use the received power deviation value as the address index and output a coarse gain adjustment factor corresponding to the power deviation value. The status monitoring and filtering module is configured to receive power deviation values ​​and coarse gain adjustment factors, dynamically switch filtering parameters according to the status of the power deviation values, and output fine gain adjustment factors. The gain execution module is configured to multiply the fine gain adjustment factor by the input signal and output the amplitude-adjusted input signal.

[0021] By adopting the above technical solution, the power detection module quantizes the difference between the real-time energy of the analog domain input signal and a preset threshold into a digital domain power deviation value. The lookup table mapping module uses this deviation value as a physical address index to directly retrieve gain data from memory, transforming the complex real-time division operation into a low-latency logic addressing operation. This eliminates the impact of feedback loops on hardware divider resources and shortens the computation cycle. The state monitoring and filtering module dynamically reconstructs the filtering parameters based on the physical characteristics of the deviation value, constructing a continuous transition trajectory between discrete lookup table outputs. This shapes the coarse gain factor into a high-precision control word. The gain execution module uses a hardware multiplier to complete the closed-loop adjustment of the signal amplitude, ensuring that the output signal envelope achieves high linearity convergence with low resource consumption.

[0022] Optional, the condition monitoring and filtering module includes: The dual-window comparison unit is configured to compare the power deviation value with a preset dead zone threshold and a preset extreme speed response threshold respectively, and generate a status control signal indicating the current system operating status. The dynamic coefficient shift register is configured to adjust the number of shift bits according to the state control signal generated by the dual-window comparison unit, and to perform asymmetric filtering response processing on the coarse gain adjustment factor.

[0023] By employing the above technical solution, the dual-window comparison unit divides the continuous power deviation domain into discrete logic control intervals using dead-zone thresholds and ultra-fast response thresholds, generating deterministic state control signals. The dynamic coefficient shift register unit modulates the shift depth of the digital filter in real time based on this control signal, constructing variable damping characteristics by changing the bit width of the right shift operation. This configuration physically enables dynamic switching of the feedback loop damping coefficient, constructing an asymmetric filtering response mechanism, thereby decoupling the system's noise suppression requirements in steady state from its rapid tracking requirements in transient states at the hardware structure level.

[0024] Optionally, the dynamic coefficient shift register is configured to execute the following logic: When the status control signal indicates the ultra-fast response state, the shift bit number is configured as the first shift parameter; When the state control signal indicates a smooth recovery state, the shift number is configured as the second shift parameter; wherein the first shift parameter is smaller than the second shift parameter.

[0025] In summary, this application includes at least one of the following beneficial technical effects: 1. By quantizing the difference between the real-time signal power in the analog domain and the target threshold into an address index in the digital domain, and using this index to directly retrieve preset gain data from memory, the resource-intensive real-time division operation is transformed into a low-latency logic addressing operation. This eliminates the dependence of the feedback loop on hardware divider resources and shortens the operation cycle, enabling the system to achieve fast gain locking of high-frequency signals with limited FPGA logic resources.

[0026] 2. By constructing a three-state control logic that includes a locked state, a high-speed suppression state, and a smooth recovery state, the noise suppression requirements of the system in steady state and the fast tracking requirements in transient state are decoupled at the physical level. Dead-zone logic is used to cut off the feedback path of small noise to eliminate steady-state digital jitter, and bypass logic is used to release inertial constraints to prevent waveform clipping when the signal is overloaded. This solves the technical problem that a single linear control law cannot take into account both steady-state accuracy and dynamic protection characteristics.

[0027] 3. By capturing the truncated low-bit residual data in the shift operation and feeding it back to the input stream of the next clock cycle, the cumulative effect of the time dimension is used to compensate for the quantization loss of a single integer operation. This allows the feedback loop to achieve sub-pixel level adjustment accuracy beyond physical resolution without increasing the hardware register bit width, ensuring that the output signal envelope achieves smooth convergence with high linearity under low storage overhead. Attached Figure Description

[0028] Figure 1 A flowchart illustrating a high-precision automatic gain control feedback adjustment method in one embodiment of the present invention is shown. Detailed Implementation

[0029] The present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the scope of the application.

[0030] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the inventive concept. As part of this specification, some of the accompanying drawings of this disclosure are block diagrams illustrating structures and devices to avoid complicating the disclosed principles. For clarity, not all features of the actual embodiment need to be described. Furthermore, the language used in this disclosure has been primarily chosen for readability and instructional purposes and may not have been chosen to define or limit the subject matter of the invention, thus requiring the necessary claims to determine such inventive subject matter. References to “an embodiment” or “an embodiment” in this disclosure mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment, and multiple references to “an embodiment” or “an embodiment” should not be construed as necessarily referring to the same embodiment.

[0031] Unless explicitly defined, the terms “a,” “an,” and “the” are not intended to refer to a singular entity, but rather to include a general category whose specific examples can be used for illustration. Therefore, the use of the terms “a” or “an” can mean any number of at least one, including “a,” “one or more,” “at least one,” and “one or more.” The term “or” means any of the options and any combination of the options, including all options unless explicitly indicated that the options are mutually exclusive. The phrase “at least one of” when combined with a list of items refers to a single item in the list or any combination of items in the list. The phrase does not require all items listed unless explicitly defined as such.

[0032] This application discloses a high-precision automatic gain control feedback adjustment method, including the following steps S1-S4.

[0033] S1. Receive the input signal, calculate the real-time power value of the input signal, compare the real-time power value with the preset target power threshold, and generate a power deviation value representing the difference between the real-time power value and the target power threshold.

[0034] The input signal typically originates from the digital baseband signal output by the analog-to-digital converter (ADC) at the front end of the RF receiving link, specifically manifested as the in-phase (I-channel) data and quadrature (Q-channel) data after quadrature demodulation. When calculating the real-time power value, the hardware logic uses pipelined multipliers and adders to perform squaring operations on the input I-channel and Q-channel data respectively and then sums them, or employs a modulo approximation algorithm to obtain the real-time power value representing the instantaneous energy of the signal. Simultaneously, the system presets a target power threshold. This target power threshold is typically set based on the full-scale range of the back-end ADC device and reserves appropriate dynamic margin according to the signal's peak-to-average power ratio (PAPR) characteristics to prevent signal peak clipping distortion in subsequent processing stages.

[0035] Based on this, the system compares the calculated real-time power value with a preset target power threshold. Specifically, it uses a subtractor to calculate the difference between the two to generate a power deviation value. The magnitude and sign of this power deviation value indicate that when the power deviation value is positive, it means that the real-time power of the current input signal exceeds the target threshold, the system is in an overload state, and a gain attenuation operation needs to be performed subsequently; when the power deviation value is negative, it means that the real-time power of the current input signal is lower than the target threshold, the system is in an underload state, and a gain amplification operation needs to be performed subsequently.

[0036] For example, assuming the system's preset target power threshold corresponds to a digital quantization value of 2048, and the real-time power value of the input signal after processing by the hardware computing unit is 3072, then the power deviation value output by the subtractor is +1024. This positive value of +1024 directly quantizes the overshoot amplitude of the input signal relative to the optimal operating point and serves as the basic data input for subsequent lookup and adjustment processes.

[0037] S2. Using the power deviation value as the index address, query the pre-configured lookup table and directly read the coarse gain adjustment factor corresponding to the power deviation value from the lookup table. The lookup table stores pre-calculated gain mapping data.

[0038] Specifically, the lookup table is typically instantiated at the physical level as an embedded memory block within a field-programmable gate array (FPGA), such as Block RAM or distributed ROM. The gain mapping data stored therein is not a simple linear ratio, but rather a logarithmic domain gain value represented in fixed-point binary format, pre-calculated based on the system link budget. Since the power deviation value output in step S1 contains positive and negative signs, and the physical memory address space only supports non-negative integers, an address offset mapping mechanism is used during the lookup process. This involves adding a preset address offset to the signed power deviation value, so that zero deviation values ​​correspond to the center address of the lookup table, negative deviation values ​​are mapped to the lower address region, and positive deviation values ​​are mapped to the higher address region.

[0039] This lookup-based mapping mechanism trades memory resources for computation time, avoiding the high-latency and resource-intensive real-time division operations performed in the feedback loop. This ensures that the generation of the gain control signal can be completed within one clock cycle. The resulting coarse gain adjustment factor is limited by the physical depth and address width of the lookup table, exhibiting a discrete, step-like characteristic. This means that continuously varying power deviations will be quantized into a finite number of fixed gain levels at the lookup table output, which is why it is defined as a coarse adjustment factor.

[0040] Following the previous embodiment, assume the system's set address offset is 2048. For the power deviation value calculated in step S1 + 1024, the mapping logic adds it to the offset to obtain the physical address 3072. The system then reads the data stored in address 3072, for example, the hexadecimal value 0xCC. This value is the corresponding coarse gain adjustment factor, representing the initial attenuation ratio required for this overload state.

[0041] S3. Input the power deviation value into the status monitoring logic. Based on the absolute value and sign of the power deviation value, dynamically adjust the filtering strategy, perform nonlinear smoothing on the coarse gain adjustment factor, and output the fine gain adjustment factor.

[0042] Specifically, the absolute value of the power deviation physically characterizes the magnitude of the error in the current signal power deviating from the target threshold, while the positive or negative sign indicates the direction of gain adjustment, i.e., whether signal attenuation or signal amplification is required. Based on these two dimensions, the state monitoring logic changes the time constant or operational coefficients of the filtering stage in real time, constructing a nonlinear smoothing mechanism. Unlike traditional linear filters that use a fixed cutoff frequency or a single response speed, this mechanism can flexibly switch between fast tracking and slow smoothing according to different deviation amplitudes. This processing method eliminates the step-like jump characteristics inherent in the coarse gain adjustment factor due to table lookup discretization, and generates a fine gain adjustment factor that changes continuously and smoothly in the time domain by inserting transition values ​​between adjacent quantized gain values.

[0043] Continuing with the previous embodiments, in response to a large positive deviation of +1024 in the input state, the state monitoring logic identifies that the system is in a significant overload state. Therefore, it dynamically configures the filtering strategy to allow the gain to drop rapidly. The discrete value 0xCC originally obtained by looking up the table is no longer a sudden step signal after nonlinear smoothing, but is transformed into a series of gradually changing numerical sequences with high resolution, thereby smoothly driving the gain execution unit.

[0044] Specifically, S3 includes the following sub-steps S31-S34.

[0045] S31. Receive the power deviation value, compare the absolute value of the power deviation value with a preset dead zone threshold and a preset ultra-fast response threshold respectively, and determine the current operating state of the system based on the comparison results; wherein, the operating state includes a locked state, an ultra-fast suppression state, and a smooth recovery state, the locked state is the state when the absolute value of the power deviation value is less than the preset dead zone threshold; the ultra-fast suppression state is the state when the power deviation value is positive and the absolute value of the power deviation value is greater than the preset ultra-fast response threshold; the smooth recovery state is any state other than the locked state and the ultra-fast suppression state.

[0046] In this process, the preset dead-zone threshold is set based on the system's noise floor level or the allowable steady-state error range, for example, setting it to a range corresponding to 0.5dB. Its physical meaning is to define a "quiet zone" that requires no adjustment, preventing the system from responding to minute quantization noise or thermal noise. The preset ultra-fast response threshold is set based on the full-scale clipping limit of the ADC input, for example, setting it to a range corresponding to 6dB. Its physical meaning is to define a safe boundary for signal energy; exceeding this boundary means the system faces a serious overload risk.

[0047] In terms of hardware logic, this step is implemented through a dual-window comparison mechanism, which uses parallel digital comparators to simultaneously monitor the absolute value and sign direction of the power deviation. This mechanism explicitly maps the physical scenario into three modes: the locked state corresponds to a stable signal maintenance scenario, the rapid suppression state corresponds to a signal overload protection scenario, and the smooth recovery state corresponds to a normal signal fluctuation adjustment scenario.

[0048] Following the previous embodiment, assume the system sets a dead zone threshold of 0.5dB and a rapid response threshold of 6dB. If the calculated power deviation value at the current moment corresponds to +0.2dB, since its absolute value is less than 0.5dB, the system determines that it is currently in a locked state; if the power deviation value corresponds to +8dB, since it is positive and its absolute value is greater than 6dB, the system determines that it is currently in a rapid suppression state; if the power deviation value corresponds to -3dB, since it does not meet either the locked state condition or the rapid suppression state condition, the system determines that it is currently in a smooth recovery state.

[0049] S32. When the working state determined in step S31 is the locked state, freeze the output of the adaptive state filtering step, forcibly keep the fine gain adjustment factor output at the previous moment unchanged, and output the fine gain adjustment factor output at the previous moment as the fine gain adjustment factor at the current moment.

[0050] In the implementation of digital logic circuits, output freezing is typically achieved by either deactivating the write enable signal of the register storing the fine gain adjustment factor or by cutting off the clock input of the logic module using clock gating technology. This mechanism physically cuts off the data update path, thereby ensuring that the output value remains absolutely still in the time domain. The core technological contribution of locked state lies in eliminating digital jitter, that is, preventing the gain control word from repeatedly jumping between adjacent values ​​near the target power threshold due to ADC sampling noise or quantization errors during calculation.

[0051] The purpose of forcibly maintaining the previous value is that the system determines that the current power deviation is within an acceptable error range (e.g., less than 0.5dB). At this point, maintaining the status quo is the optimal solution for system energy efficiency and stability. This not only reduces the power consumption of invalid logic switching, but more importantly, it achieves signal integrity protection in steady state, avoiding the introduction of additional amplitude modulation sidebands or phase noise into the output signal due to frequent and minor gain adjustments, thereby ensuring signal purity.

[0052] For example, suppose the fine gain adjustment factor output by the system at the previous moment was 100 (corresponding to a certain fixed-point value), and the currently detected power deviation is +0.2dB (in the locked-state range). At this time, although the calculation logic may tend to fine-tune according to the deviation of +0.2dB, step S32 will force the deviation to be ignored, so that the fine gain adjustment factor output at the current moment is strictly kept at 100, without any numerical change.

[0053] S33. When the working state determined in S31 is the extreme speed suppression state, the state monitoring logic is controlled to enter the minimum delay response mode, the coarse gain adjustment factor is processed using the first shift parameter, and the processed value is output as the fine gain adjustment factor at the current moment.

[0054] Specifically, when a sharp increase in signal power is detected and exceeds the ultrafast response threshold (e.g., +6dB), the system determines it to be a sudden overload risk and must respond immediately to protect the downstream analog-to-digital converter or power amplifier from breakdown or entering the saturation region. At this point, the status monitoring logic switches to a minimum delay response mode, which bypasses a deeply smoothed filter path in the circuit path and selects a fast signal path with extremely low group delay. By configuring a small first shift parameter (e.g., 0 or 1), the system significantly reduces the attenuation of the error signal, allowing changes in the coarse gain adjustment factor to be transmitted to the output almost losslessly and without delay. This processing mechanism ensures that when faced with large positive deviations, the gain control word can rapidly decrease within several clock cycles, thereby physically cutting off the energy accumulation of the overload signal.

[0055] For example, if the input signal experiences a sudden power deviation of +8dB due to a sudden interference, the system enters a rapid suppression state and applies a first shift parameter with a value of 0. This means that the error signal does not undergo any right-shift attenuation and directly drives the gain adjustment factor to decrease at the maximum step rate, thereby suppressing the signal amplitude back to a safe range within a microsecond timescale.

[0056] S34. When the working state determined in S31 is the smooth recovery state, the state monitoring logic is controlled to enter the smoothing filtering mode, and the coarse gain adjustment factor is processed using the second shift parameter, and the smoothed value is output as the fine gain adjustment factor at the current moment.

[0057] In this state (e.g., power deviation of -3dB), the system primarily faces the challenge of normal signal fluctuations or weak signal recovery. To prevent drastic gain changes from degrading the signal-to-noise ratio or creating a fluctuating breathing effect in the auditory perception, the state monitoring logic employs a smoothing filter mode. This mode incorporates a feedback accumulation loop with significant inertia into the circuit path. By configuring a large second shift parameter (e.g., 4 to 8), the system artificially introduces high damping characteristics. This transforms a step change in the coarse gain adjustment factor into an extremely small incremental step, thereby lengthening the system's response time constant in the time domain.

[0058] Continuing with the previous embodiment, when the signal amplitude slowly decays, resulting in a power deviation of -3dB, the system applies a second shift parameter with a value of 8. At this time, although the coarse gain adjustment factor obtained from the lookup table may indicate that the gain needs to be increased, due to the large shift attenuation, the actual output fine gain adjustment factor will compensate with a very small slope, slowly rising along a smooth curve, thereby achieving flexible control of the signal envelope.

[0059] Specifically, in steps S33 and S34, the state monitoring logic executes a shift operation logic based on dynamic coefficients, and the shift operation logic includes steps S341-S343.

[0060] S341. Receive the coarse gain adjustment factor at the current time and obtain the fine gain adjustment factor output at the previous time, and calculate the numerical difference between the coarse gain adjustment factor at the current time and the fine gain adjustment factor output at the previous time.

[0061] In this step, the coarse gain adjustment factor originates from a lookup table operation, and its value is limited by the address depth of the lookup table, exhibiting a discrete, step-like distribution. The fine gain adjustment factor, on the other hand, is the output after filtering, and its value exhibits a continuous and smooth transition in the time domain, with higher numerical accuracy.

[0062] The physical meaning of calculating the numerical difference between the two lies in quantifying the step size and direction of the adjustment required for the current system gain to reach the target lookup table value. To obtain the output value from the previous time step, the hardware typically uses a set of D flip-flops or registers to latch the calculation result from the previous clock cycle and feed it back to the input of the subtractor. The reason for not directly using the coarse gain factor obtained from the lookup table as the output, but instead constructing this difference-based error feedback loop, is to utilize an incremental adjustment mechanism to decompose large step changes into small steps, thereby achieving a smooth transition in gain. For example, suppose the fine gain adjustment factor latched in the register at the previous time step was 100.5 (fixed-point value), while the coarse gain adjustment factor obtained from the lookup table based on the power deviation at the current time step is 102. The subtractor subtracts the two, calculating a numerical difference of +1.5. This numerical difference indicates that, to approach the target value, the system gain needs to be adjusted in the positive direction by 1.5 units.

[0063] S342. Select the corresponding number of shift bits according to the determined working state to perform a right shift operation on the numerical difference to obtain the shifted increment value.

[0064] In the field of digital signal processing, right shift is mathematically equivalent to dividing a value by 2 raised to the power of N. Compared to using a hardware divider, shift operations have significant advantages in hardware implementations such as FPGAs. They consume almost no logic resources and can be implemented simply by offsetting data bus connections or calling a simple barrel shifter. The shifted increment physically represents the actual adjustment that the system is allowed to add to the output within the current clock cycle. The number of shift bits is positively correlated with the system's filtering time constant: the larger the shift bit, the smaller the increment obtained in a single calculation, the greater the system's inertia, the stronger the suppression of abrupt signals, and the smoother the filtering effect; conversely, the smaller the shift bit, the faster the system response. Continuing with the previous example, assume the calculated numerical difference is 16. If the shift bit corresponding to the current state is 2, then shifting right by 2 bits is equivalent to dividing by 4, resulting in a shifted increment of 4; if the shift bit corresponding to the current state is 4, then shifting right by 4 bits is equivalent to dividing by 16, resulting in a shifted increment of 1. Obviously, different shift bits directly determine the single-step rate of gain adjustment.

[0065] In step S342, the system adopts a differentiated parameter configuration strategy for different operating states. Specifically, when the operating state indicates a high-speed suppression state, the number of shift bits is configured as the first shift parameter; when the operating state indicates a smooth recovery state, the number of shift bits is configured as the second shift parameter. The value of the first shift parameter is set to be strictly less than the value of the second shift parameter.

[0066] This parameter configuration establishes the asymmetric response characteristics necessary for an automatic gain control system. The first shift parameter typically takes a very small value (e.g., 0 or 1), which gives the system a low-damping physical characteristic, allowing the calculated numerical difference to retain its original amplitude as much as possible after the shift operation. This means the gain adjustment factor can respond quickly to changes in the input signal in a near-straight-through manner, enabling rapid tracking of sudden large signals. Conversely, the second shift parameter typically takes a large value (e.g., 4 to 8), which gives the system a high-damping physical characteristic, causing the numerical difference to be greatly attenuated after the shift operation. This means the gain adjustment factor can only be updated in tiny steps, resulting in a slow gain ramp-up.

[0067] In the high-speed suppression state, the system prioritizes protecting the subsequent circuitry from damage caused by overload signals, thus requiring transient response. In the smooth recovery state, however, the system prioritizes the smoothness of the user's listening experience, preventing a breathing effect caused by abrupt gain changes, thus requiring steady-state transition. For example, in the high-speed suppression state, using a shift value K=0 preserves the difference caused by sudden signal changes, resulting in an instantaneous gain reduction. In the smooth recovery state, using a shift value K=8 ensures that even with larger differences, only 1 / 256 of the output difference is allowed as an increment per clock cycle, thus guaranteeing an extremely smooth signal envelope.

[0068] Furthermore, the first shift parameter and the second shift parameter are variable parameters that are dynamically mapped based on real-time power values. The dynamic mapping logic follows these rules: When the real-time power value is in the preset low power range, increase the values ​​of the first shift parameter and the second shift parameter to reduce the rate of change of the fine gain adjustment factor. When the real-time power value is in the preset high power range, the values ​​of the first shift parameter and the second shift parameter are reduced to increase the rate of change of the fine gain adjustment factor.

[0069] By introducing this dynamic mapping mechanism, even with the same power deviation (error), the system's stability requirements differ drastically at different absolute power levels. In the low-power range, the signal-to-noise ratio is poor; if the gain is adjusted too quickly, the background noise can be amplified sharply, leading to significant noise fluctuations in the output signal. Therefore, by increasing the shift parameter, the system physically increases the filter's inertia, implementing slow adjustment to suppress noise amplification. Conversely, in the high-power range, the signal energy is strong, and the circuit faces a high risk of overload; circuit safety becomes the primary consideration. Therefore, by decreasing the shift parameter, the system implements rapid adjustment, ensuring that the gain can quickly adjust back when the signal approaches full scale, preventing overload clipping.

[0070] This mechanism endows the system with the ability to perceive the signal environment, so that the filtering parameters are no longer dead values, but can adapt to the signal strength. Continuing with the previous embodiment, also in a smooth recovery state, if the current real-time power is a weak signal of -80dBm, the system may map a shift number K=10, making the gain adjustment extremely slow to protect the weak signal-to-noise ratio; while if the current real-time power is a strong signal of -10dBm, the system may map a shift number K=4, making the gain adjustment relatively fast to maintain the dynamic range under large signals.

[0071] S343. Add the shifted increment value to the fine gain adjustment factor output at the previous time step to obtain the fine gain adjustment factor at the current time step.

[0072] In this step, the computational logic is mathematically equivalent to constructing a digital integrator. Physically, this means integrating the incremental value representing the rate of gain change over time, thus transforming it into an absolute control quantity representing the real-time gain value. This process utilizes a feedback mechanism to introduce the output state from the previous moment as a calculation benchmark, ensuring the continuity of gain adjustment in the time domain and effectively eliminating abrupt interference common in signal processing. The positive or negative characteristic of the increment directly determines the direction of gain evolution: positive increments drive the fine-grained gain adjustment factor to increase, negative increments drive its value to decrease, while zero increments maintain the current state. This method of accumulating tiny increments breaks the inherent resolution limitations of the lookup table method, achieving a more refined numerical transition than directly reading the lookup table.

[0073] Following the previous embodiment, assume that the fine gain adjustment factor output and latched at the previous moment was 500 (fixed-point value). If the currently calculated shift increment is +2, the adder outputs 502 as the fine gain adjustment factor at the current moment; if the shift increment is -1, the adder outputs 499. This point-by-point accumulation method ensures the smoothness of the output waveform.

[0074] Step S34 also includes step S344, which is executed in parallel with steps S342 and S343: When performing the right shift operation in step S342, the low-order data portion that was truncated due to the shift operation is extracted and temporarily stored as a residual value; In the next calculation cycle, the temporarily stored residual value is superimposed with the numerical difference calculated in step S341 in the next calculation cycle, and the combined value after superposition is used as the operand to perform the right shift operation in step S342.

[0075] This step primarily compensates for the quantization error inevitably caused by right shift operations on integers. Physically, a right shift operation moves the low-order bits of the data out of the register boundary, resulting in the loss of fractional parts less than 1. To prevent this energy from disappearing, the system uses an additional low-width register to store the discarded mantissa, i.e., the residual value. By adding the residual value back to the input in the next calculation cycle, the system utilizes time-domain compensation principles to transfer the precision that cannot be expressed spatially (in terms of bit width) to the time axis for accumulation. This mechanism is similar to the Sigma-Delta modulation principle, where accumulation over multiple cycles eventually triggers a carry-in to a higher bit, thus achieving "sub-pixel-level" adjustment precision that surpasses physical bit-width limitations.

[0076] For example, suppose the shift parameter in the current state is 2, which mathematically corresponds to dividing by 4. If the calculated numerical difference is always 1, under normal logic, the integer result of 1 divided by 4 will always be 0, causing the system to be unresponsive. However, after introducing residual compensation: In the first cycle, the input is 1, shifted right to get 0, the remainder (residual) is 1, and the output increment is 0; in the second cycle, the input numerical difference 1 plus one round of residual 1 equals 2, shifted right to get 0, the remainder is 2, and the output increment is 0; in the third cycle, the input numerical difference 1 plus one round of residual 2 equals 3, shifted right to get 0, the remainder is 3, and the output increment is 0; in the fourth cycle, the input numerical difference 1 plus one round of residual 3 equals 4, shifted right by 2 bits (divided by 4) to get the integer 1, the remainder is 0, and the output increment is 1. Thus, the system achieves effective gain adjustment once every 4 clock cycles, thereby accurately responding to small input deviations.

[0077] S4. Use a multiplier to multiply the fine gain adjustment factor with the input signal, and output the amplitude-adjusted input signal.

[0078] In terms of hardware implementation, this step preferably utilizes dedicated multiplier resources within the FPGA's underlying digital signal processing hard core. Compared to soft-core multipliers or dividers that consume a large number of logic gates, dedicated hardware multipliers offer extremely high processing speed and deterministic pipeline delays, ensuring the timing convergence of the data path and meeting the real-time requirements of high-speed signal processing. During this process, the fine-tuned gain adjustment factor processed in step S3 acts as a smooth envelope control word, performing stepless linear amplitude scaling on the original input signal.

[0079] This operation marks the physical closure of the automatic gain control loop. Changes in the output signal amplitude directly affect the real-time power detection result in step S1 of the next clock cycle, thus altering the power deviation value at the next moment and constructing a complete negative feedback adjustment loop. Thanks to the multiplier (i.e., the fine gain adjustment factor) being a high-precision value smoothed by a nonlinear filtering strategy and corrected by a residual compensation algorithm, the output signal maintains extremely high signal integrity during amplitude adjustment, effectively avoiding zipper noise or phase abrupt changes caused by gain jumps and ensuring waveform purity.

[0080] Following the previous embodiment, assume that the instantaneous amplitude quantization value of the input signal at the current moment is 100mV (corresponding to a certain digital order of magnitude), and the fine gain adjustment factor of the state monitoring logic output is 15.5 (a fixed-point value, for example, expressed in Q4.12 format). After the multiplier performs the operation, the amplitude of the output signal will be precisely adjusted and stabilized at 1550mV, thereby completing the standardized control of the signal's dynamic range.

[0081] This application also discloses a high-precision automatic gain control feedback adjustment system. This system is implemented based on a field-programmable gate array (FPGA) hardware architecture, using Verilog or VHDL hardware description languages ​​to construct each logic module, and cascading the modules through an on-chip high-speed data bus. The system mainly includes a power detection module, a lookup table mapping module, a state monitoring and filtering module, and a gain execution module.

[0082] The power detection module is configured to receive the input signal, calculate the real-time power value, and output a power deviation value representing the difference between the real-time power value and a preset target power threshold. In terms of hardware, this module integrates a pipelined squarer and accumulator circuit for real-time energy integration of the input high-speed digital signal, ensuring that the power calculation throughput matches the input sampling rate. The lookup table mapping module has a pre-configured lookup table built-in. It is configured to receive the power deviation value as an address index and output a coarse gain adjustment factor corresponding to the power deviation value. Physically, this lookup table is typically instantiated as a block memory or distributed read-only memory within the FPGA, pre-loaded with logarithmic domain gain curve data calculated based on system link characteristics.

[0083] The state monitoring and filtering module is configured to receive power deviation values ​​and coarse gain adjustment factors, dynamically switch filtering parameters based on the power deviation value, and output a fine gain adjustment factor. As the core decision-making and control hub of the system, this module logically reconciles the contradiction between the speed of open-loop lookup and the stability of closed-loop smoothness, ensuring that the control word of the output signal can both follow quickly and transition smoothly. The gain execution module is configured to multiply the fine gain adjustment factor by the input signal and output the amplitude-adjusted input signal. This module directly calls the dedicated multiplier hard core in the FPGA's underlying DSP Slice, achieving linear scaling of the signal amplitude without delay.

[0084] Following the aforementioned data flow example, after the input data sampled by the ADC enters the power detection module, a power deviation of +3dB relative to the target value is calculated. This deviation value is transmitted to the lookup table mapping module via the address bus, which indexes and outputs the corresponding coarse gain adjustment factor (e.g., a fixed-point number corresponding to a 0.707 multiplier). This coarse factor then enters the status monitoring and filtering module, where it is optimized into a fine gain adjustment factor (e.g., corresponding to a 0.705 multiplier) through nonlinear filtering. Finally, this fine factor enters the gain execution module, is multiplied by the original input signal, and outputs a waveform with precisely compressed amplitude.

[0085] Furthermore, the state monitoring and filtering module includes a dual-window comparison unit and a dynamic coefficient shift register unit. The dual-window comparison unit is configured to compare the power deviation value with a preset dead-time threshold and a preset ultra-fast response threshold, respectively, to generate a state control signal indicating the current system operating state. In terms of circuit connections, the comparator's signal input terminal is connected to the output port of the power detection module via a bus to receive the power deviation value, while the reference voltage terminal is hardwired to a configuration register storing the dead-time threshold and ultra-fast response threshold, and the comparison result is output in real time through pure combinational logic circuitry. The state control signal adopts a multi-bit binary encoding form, for example, a 2-bit wide binary code: an output of "00" represents a locked state, an output of "01" represents a smooth recovery state, and an output of "10" represents an ultra-fast suppression state.

[0086] The dynamic coefficient shift register unit is configured to adjust the shift bit according to the state control signal generated by the dual-window comparison unit, performing asymmetric filtering response processing on the coarse gain adjustment factor. Internally, this unit mainly contains a variable-bit barrel shifter and a feedback accumulator. In terms of gating logic, the state control signal is connected to the selection control terminal of the multiplexer, and the input channels of the multiplexer are respectively connected to register groups storing different shift parameters (constants). Through this physical connection, the state control signal physically connects the preset constant register and the shifter control terminal, thereby realizing real-time reconfiguration of the hardware circuit structure.

[0087] For example, when the dual-window comparison unit detects that the absolute value of the input deviation is greater than the dead zone threshold and less than the ultra-fast response threshold, it outputs a status code "01". This status code drives the multiplexer of the dynamic coefficient shift register unit to select the corresponding parameter channel, loading the value "8" to the control terminal of the shifter, thereby immediately causing the filter to exhibit high-damping characteristics.

[0088] The dynamic coefficient shift register is configured to execute the following logic: when the state control signal indicates a fast response state, the number of shift bits is configured as a first shift parameter; when the state control signal indicates a smooth recovery state, the number of shift bits is configured as a second shift parameter; wherein the first shift parameter is less than the second shift parameter.

[0089] This state-switching-based hardware configuration effectively solves the problem of limited FPGA resources. The system does not need to instantiate two separate filter modules for ultra-fast response and smooth recovery; instead, it reuses the same barrel shifter and accumulator core. By changing the control signal input to the shifter (the number of shift bits), two distinctly different filter characteristics (a physical change in the low-pass cutoff frequency) can be implemented on a single hardware entity. At the register configuration logic level, the status code serves as the select signal for the multiplexer. In the ultra-fast state, a small constant (e.g., 0) is selected as the input to the shifter, while in the recovery state, a large constant (e.g., 8) is selected, thus achieving complex adaptive control functions with minimal hardware overhead.

[0090] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0091] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A high-precision automatic gain control feedback adjustment method, characterized in that, Includes the following steps: S1. Receive the input signal, calculate the real-time power value of the input signal, compare the real-time power value with the preset target power threshold, and generate a power deviation value representing the difference between the real-time power value and the target power threshold; S2. Using the power deviation value as the index address, query the pre-configured lookup table and directly read the coarse gain adjustment factor corresponding to the power deviation value from the lookup table. The lookup table stores pre-calculated gain mapping data. S3. Input the power deviation value into the status monitoring logic, dynamically adjust the filtering strategy according to the absolute value and positive / negative sign of the power deviation value, perform nonlinear smoothing on the coarse gain adjustment factor, and output the fine gain adjustment factor. S4. Use a multiplier to multiply the fine gain adjustment factor with the input signal, and output the amplitude-adjusted input signal.

2. The high-precision automatic gain control feedback adjustment method according to claim 1, characterized in that, S3 includes the following sub-steps: S31. Receive power deviation values, compare the absolute value of the power deviation value with a preset dead zone threshold and a preset ultra-fast response threshold respectively, and determine the current operating state of the system based on the comparison results; wherein, the operating state includes a locked state, an ultra-fast suppression state, and a smooth recovery state, the locked state is the state when the absolute value of the power deviation value is less than the preset dead zone threshold; the ultra-fast suppression state is the state when the power deviation value is positive and the absolute value of the power deviation value is greater than the preset ultra-fast response threshold; the smooth recovery state is any state other than the locked state and the ultra-fast suppression state; S32. When the working state determined in step S31 is the locked state, freeze the output of the adaptive state filtering step, forcibly keep the fine gain adjustment factor output at the previous moment unchanged, and use the fine gain adjustment factor output at the previous moment as the fine gain adjustment factor output at the current moment. S33. When the working state determined in S31 is the extreme speed suppression state, the state monitoring logic is controlled to enter the minimum delay response mode, the coarse gain adjustment factor is processed using the first shift parameter, and the processed value is output as the fine gain adjustment factor at the current moment. S34. When the working state determined in S31 is the smooth recovery state, the state monitoring logic is controlled to enter the smoothing filtering mode, and the coarse gain adjustment factor is processed using the second shift parameter, and the smoothed value is output as the fine gain adjustment factor at the current moment.

3. The high-precision automatic gain control feedback adjustment method according to claim 2, characterized in that, In steps S33 and S34, the state monitoring logic performs shift operation logic based on dynamic coefficients. The steps of the shift operation logic include: S341. Receive the coarse gain adjustment factor at the current time and obtain the fine gain adjustment factor output at the previous time, and calculate the numerical difference between the coarse gain adjustment factor at the current time and the fine gain adjustment factor output at the previous time. S342. Select the corresponding number of shift bits according to the determined working state, and perform a right shift operation on the numerical difference to obtain the shifted increment value; S343. Add the shifted increment value to the fine gain adjustment factor output at the previous time step to obtain the fine gain adjustment factor at the current time step.

4. The high-precision automatic gain control feedback adjustment method according to claim 3, characterized in that, In step S342: When the operating status is indicated as high-speed suppression, the number of shift bits is configured as the first shift parameter; When the operating status is indicated as smooth recovery, the number of shift bits is configured as the second shift parameter; wherein the value of the first shift parameter is less than the value of the second shift parameter.

5. The high-precision automatic gain control feedback adjustment method according to claim 3, characterized in that, Step S34 also includes step S344, which is executed in parallel with steps S342 and S343: When performing the right shift operation in step S342, the low-order data portion that was truncated due to the shift operation is extracted and temporarily stored as a residual value; In the next calculation cycle, the temporarily stored residual value is superimposed with the numerical difference calculated in step S341 in the next calculation cycle, and the combined value after superposition is used as the operand to perform the right shift operation in step S342.

6. The high-precision automatic gain control feedback adjustment method according to claim 4, characterized in that, The first shift parameter and the second shift parameter are variable parameters that are dynamically mapped based on real-time power values. The dynamic mapping logic follows these rules: When the real-time power value is in the preset low power range, increase the values ​​of the first shift parameter and the second shift parameter to reduce the rate of change of the fine gain adjustment factor. When the real-time power value is in the preset high power range, the values ​​of the first shift parameter and the second shift parameter are reduced to increase the rate of change of the fine gain adjustment factor.

7. A high-precision automatic gain control feedback adjustment system, characterized in that, include: The power detection module is configured to receive input signals, calculate real-time power values, and output a power deviation value representing the difference between the real-time power value and a preset target power threshold. The lookup table mapping module has a pre-configured lookup table built in. The lookup table mapping module is configured to use the received power deviation value as the address index and output a coarse gain adjustment factor corresponding to the power deviation value. The status monitoring and filtering module is configured to receive power deviation values ​​and coarse gain adjustment factors, dynamically switch filtering parameters according to the status of the power deviation values, and output fine gain adjustment factors. The gain execution module is configured to multiply the fine gain adjustment factor by the input signal and output the amplitude-adjusted input signal.

8. The high-precision automatic gain control feedback adjustment system according to claim 7, characterized in that, The condition monitoring and filtering module includes: The dual-window comparison unit is configured to compare the power deviation value with a preset dead zone threshold and a preset extreme speed response threshold respectively, and generate a status control signal indicating the current system operating status. The dynamic coefficient shift register is configured to adjust the number of shift bits according to the state control signal generated by the dual-window comparison unit, and to perform asymmetric filtering response processing on the coarse gain adjustment factor.

9. A high-precision automatic gain control feedback adjustment system according to claim 8, characterized in that, The dynamic coefficient shift register is configured to execute the following logic: When the status control signal indicates the ultra-fast response state, the shift bit number is configured as the first shift parameter; When the state control signal indicates a smooth recovery state, the shift number is configured as the second shift parameter; wherein the first shift parameter is smaller than the second shift parameter.

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