An active gate drive circuit based on variable resistance variable current regulation

Abstract

The application belongs to the technical field of power electronics, and provides an active gate drive circuit based on variable resistance and variable current regulation, which comprises a control unit, an isolated gate drive module, a gate variable resistance module, a gate variable current module, a power loop and a gate voltage feedback module. The application combines discrete resistance switching (coarse adjustment) with linear current source regulation (fine adjustment), realizes fine management of the switching trajectory of a power device, limits the current variation rate by initially connecting a large resistance in the on process, then switches to a low resistance to accelerate conduction, and splits part of the current from the gate through a Wilson current mirror structure to suppress current overshoot, and in the off process, initially discharges rapidly through a low resistance, then switches to a high resistance to increase damping, and injects a compensation current into the gate through a current mirror to suppress voltage ringing.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, and specifically relates to an active gate drive circuit for power semiconductor devices.

[0002] In high-frequency, high-efficiency power electronic systems, the switching performance of power switching devices such as insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs) directly determines the overall system efficiency, electromagnetic interference (EMI) level, and operational reliability. The gate drive circuit, as a crucial component controlling the switching trajectory of power devices, plays a key role in balancing switching speed, switching losses, and voltage / current overshoot / ring.

[0003] In the prior art, in order to optimize the switching transient process, common active gate drive (AGD) schemes mainly include: variable resistor drive structure based on switch array, drive structure based on variable power supply voltage, and drive structure based on current source.

[0004] Among them, the variable resistance active gate drive has been widely used in industry due to its simple topology, low cost, and ease of integration. This method typically uses multiple resistor branches with different resistance values ​​connected in parallel to switch the total gate resistance according to different stages of the switching process, thereby changing the time constant of the gate circuit to adjust the switching speed.

[0005] However, in practical applications, the above-mentioned traditional solutions have obvious limitations: Discreteness and discontinuity in regulation: Traditional variable resistor schemes rely on a limited number of switching transistors and resistor combinations, and their regulation is essentially "hierarchical" or "step-like". This discrete regulation method makes it difficult to achieve smooth and continuous control of the gate current, which can easily lead to sudden current changes or oscillations that would not normally occur at the moment of resistor switching.

[0006] The trade-off between control precision and range: To improve adjustment precision, the number of parallel resistors and switches needs to be significantly increased, resulting in a large circuit size and complex control logic. Conversely, if there are too few resistor ranges, it is difficult to accurately suppress current overshoot and EMI under a wide load range or bus voltage fluctuations.

[0007] The shortcomings of a single control method: Although some studies have attempted to use pure current source drive to achieve continuous regulation, pure current source circuits often face problems such as limited bandwidth, complex circuit structure and high static power consumption when outputting large currents. It is difficult to meet the dual requirements of "transient large current throughput (for fast switching)" and "steady-state small current regulation (for suppressing ringing)".

[0008] Therefore, there is an urgent need for a new gate drive architecture that can combine the advantages of a large dynamic range of resistance regulation with the advantages of high-precision linear control of current regulation to achieve fine management of the switching trajectory of power devices, so as to meet the stringent requirements of high-performance systems such as magnetic levitation bearings for low noise and low loss. Summary of the Invention

[0009] The variable resistor type active gate drive scheme suffers from discrete adjustment and insufficient precision, while the pure current source type drive scheme suffers from circuit complexity and limited dynamic range. This makes it difficult to balance switching speed, current overshoot, and ringing suppression in applications such as magnetic levitation bearing power amplifiers that have stringent requirements for switching transients. This invention provides an active gate drive circuit based on variable resistance and variable current regulation. By combining discrete resistor switching (coarse adjustment) with linear current source regulation (fine adjustment), it achieves fine control of the gate voltage and current of power semiconductor devices, thereby effectively suppressing current overshoot and electromagnetic interference while ensuring switching speed.

[0010] This invention relates to an active gate drive circuit based on variable resistance and variable current regulation. The circuit includes a control unit, an isolated gate drive module, a gate variable resistance module, a gate variable current module, a power circuit of a magnetic levitation bearing power amplifier, and a gate voltage feedback module.

[0011] The control unit includes a first controller and a second controller; the isolated gate drive module includes a first set of isolated drivers and a second set of isolated drivers; the first controller is connected to the first set of isolated drivers; and the second controller is connected to the second set of isolated drivers.

[0012] The first and second isolation drivers are respectively connected to the gate variable resistor module.

[0013] The gate variable resistor module is connected to the gate variable current module and the power circuit of the magnetic levitation bearing power amplifier, respectively.

[0014] The gate voltage feedback module is connected between the power circuit of the magnetic levitation bearing power amplifier and the control unit.

[0015] Compared with the prior art, the present invention has the following significant advantages: This invention achieves high-precision hybrid control combining coarse and fine adjustments: it creatively combines the advantages of a wide dynamic range of variable resistance adjustment with the linear high precision of variable current adjustment. Resistor switching enables rapid adjustment of switching speed, while a transistor current source smoothly suppresses overshoot and ringing.

[0016] Optimized topology: A highly symmetrical push-pull current regulation branch is constructed through a specific transistor array design. Combined with precision resistors and specific types of bipolar transistors (preferably PNP / NPN combination), the linearity and reliability of the drive circuit are ensured over a wide voltage range.

[0017] It improves the electromagnetic compatibility of the magnetic levitation system: it can effectively suppress voltage spikes and oscillations in the magnetic levitation bearing power amplifier during high-current switching, significantly reduce EMI, and ensure long-term stable operation of the system. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the active gate drive circuit structure for variable resistance and variable current regulation provided in an embodiment of this application; Figure 2 This is a schematic diagram of the active gate drive circuit structure for variable resistance and variable current regulation provided in an embodiment of this application. Figure 3 This is a schematic diagram of the active gate drive circuit structure for variable resistance and variable current regulation provided in an embodiment of this application. Figure 4 This is a schematic diagram of the active gate drive circuit structure for variable resistance and variable current regulation provided in an embodiment of this application. Figure 5 The waveform diagram shows the switching process of the active gate driving method for variable resistance and variable current regulation provided in the embodiments of this application. Figure 6 The simulation waveform diagrams show the performance comparison of different driving schemes under the opening process provided in the embodiments of this application; Figure 7 The simulation waveforms show the performance comparison of different driving schemes during the shutdown process provided in the embodiments of this application. Detailed Implementation

[0020] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0021] like Figure 1-4 As shown, the present invention relates to an active gate drive circuit based on variable resistance and variable current regulation. The circuit includes a control unit 1, an isolated gate drive module 2, a gate variable resistance module 3, a gate variable current module 4, a magnetic levitation bearing power amplifier power circuit 5, and a gate voltage feedback module 6.

[0022] The control unit 1 includes a first controller A1 and a second controller A2; the isolated gate drive module 2 includes a first group of isolated drivers (M1, M2, M3) and a second group of isolated drivers (M4, M5, M6); the first controller A1 is connected to the first group of isolated drivers (M1, M2, M3); and the second controller A2 is connected to the second group of isolated drivers (M4, M5, M6).

[0023] The first group of isolation drivers (M1, M2, M3) and the second group of isolation drivers (M4, M5, M6) are respectively connected to the gate variable resistor module 3.

[0024] The gate variable resistor module 3 is connected to the gate variable current module 4 and the power circuit of the magnetic levitation bearing power amplifier 5, respectively.

[0025] The gate voltage feedback module 6 is connected between the power circuit 5 of the magnetic levitation bearing power amplifier and the control unit 1.

[0026] Specifically, such as Figure 2-3 As shown, in the isolated gate drive module 2, the output terminal of the first controller A1 is connected to the input terminal of the first group of isolated drivers (M1, M2, M3); the output terminal of the second controller A2 is connected to the input terminal of the second group of isolated drivers (M4, M5, M6); and the output terminals of the two groups of isolated drivers are connected to the gates of different switching transistors in the gate variable resistor module 3.

[0027] The gate variable resistor module 3 includes: first to eighth switching transistors T1-T8, first to sixth resistors R1-R6, and a first ground terminal GND1 and a second ground terminal GND2; the output terminal of the first isolation driver M1 is connected to the gates of the first and second switching transistors (T1, T2), and the output terminal of the fourth isolation driver M4 is connected to the gates of the fifth and sixth switching transistors T5, T6; the output terminals of the second, third, fifth and sixth isolation drivers (M2, M3, M5, M6) are respectively connected to the gates of the corresponding third, fourth, seventh and eighth switching transistors (T3, T4, T7, T8).

[0028] Specifically, the gate variable resistor module 3 is connected to the power circuit 5 of the magnetic levitation bearing power amplifier. The connection includes a first drive branch and a second drive branch. In the first drive branch, the first switch T1 and the second switch T2 form the main on / off path. The first resistor R1 is connected in parallel across the third switch T3, and the second resistor R2 is connected in parallel across the fourth switch T4. This changes the equivalent drive resistance connected to the gate of T9 by controlling the on / off states of T3 and T4. In the second drive branch, a symmetrical structure is adopted. The fourth resistor R4 is connected in parallel across the seventh switch T7, and the fifth resistor R5 is connected in parallel across the eighth switch T8. This changes the equivalent drive resistance connected to the gate of T10 by controlling the on / off states of T7 and T8.

[0029] In a specific embodiment, the connection relationship of the first driving branch is as follows: the drain of the first switching transistor T1 is connected to the positive terminal of the first power supply VDD1, and the source is connected to the drain of the third switching transistor T3; the first resistor R1 is connected in parallel between the drain and source of the third switching transistor T3; the source of the third switching transistor T3 is connected to the first end of the third resistor R3 and the drain of the fourth switching transistor T4; the second end of the third resistor R3 is connected to the gate of the ninth switching transistor T9; the second resistor R2 is connected in parallel between the drain and source of the fourth switching transistor T4; the source of the fourth switching transistor T4 is connected to the drain of the second switching transistor T2, and the source of the second switching transistor T2 is connected to the negative terminal of the first power supply VDD1 and the first ground terminal GND1.

[0030] The connection relationship of the second driving branch is as follows: the drain of the fifth switch T5 is connected to the positive terminal of the second power supply VDD2, and the source is connected to the drain of the seventh switch T7; the fourth resistor R4 is connected in parallel between the drain and source of the seventh switch T7; the source of the seventh switch T7 is also connected to the second terminal of the sixth resistor R6 and the drain of the eighth switch T8; the first terminal of the sixth resistor R6 is connected to the gate of the tenth switch T10; the fifth resistor R5 is connected in parallel between the drain and source of the eighth switch T8; the source of the eighth switch T8 is connected to the drain of the sixth switch T6, and the source of the sixth switch T6 is connected to the negative terminal of the second power supply VDD2 and the second ground terminal GND2.

[0031] Taking the first drive branch for T9 as an example: the first switch T1 and the second switch T2 serve as the main drive transistors. The first resistor R1 is connected in parallel across the third switch T3, and the second resistor R2 is connected in parallel across the fourth switch T4. When T3 is off, R1 is connected in series with the drive circuit, providing a large resistance; when T3 is on, R1 is short-circuited, and the drive circuit presents a low impedance.

[0032] Similarly, T4, in conjunction with R2, is used for resistance adjustment during the turn-off process. Since the second drive branch structure of T10 is completely symmetrical, T7 / R4 and T8 / R5 are used to achieve a similar variable resistance function. In a preferred embodiment of the invention, resistors R1-R12 are all low-temperature drift precision resistors to ensure the accuracy of time constant switching under different temperature conditions.

[0033] The gate variable current module 4 is a key component for achieving high-precision control in this invention. It works in conjunction with the gate variable resistor module 3 to compensate for the discreteness and insufficient precision inherent in resistance adjustment methods. In this embodiment, the module employs an improved Wilson current mirror structure to ensure high output impedance and stable current following characteristics over a wide voltage range.

[0034] The gate variable current module 4 is connected to the power circuit 5 of the magnetic levitation bearing power amplifier, and the connection relationship includes a first adjustment branch and a second adjustment branch with symmetrical structure.

[0035] like Figure 2-4 As shown, the first regulation branch is used to drive the ninth switch T9. It includes two complementary current regulation structures: On one hand, the first to fourth transistors Q1-Q4 form an improved Wilson current mirror structure, responsible for accurately replicating the reference current generated by the fifth transistor Q5 and injecting it into the gate of T9. The reference current of Q5 can be linearly changed by adjusting the voltage of the external first power supply V1, thereby controlling the magnitude of the drive current injected into the gate of T9. On the other hand, the seventh to tenth transistors Q7-Q10 form another improved Wilson current mirror structure, responsible for accurately replicating the reference current generated by the sixth transistor Q6 and drawing it from the gate of T9. The reference current of Q6 can be changed by adjusting the voltage of the external second power supply V2, thereby controlling the magnitude of the shunt drive current drawn from the gate of T9.

[0036] The second regulation branch is used to drive the tenth switch transistor T10. Its structure is completely symmetrical to the first regulation branch: using the current mirror structure composed of the eleventh to fourteenth transistors Q11-Q14, the reference current set by the third power supply V3 and the fifteenth transistor Q15 is copied and injected into the gate of T10; using the current mirror structure composed of the seventeenth to twentieth transistors Q17-Q20, the reference current set by the fourth power supply V4 and the sixteenth transistor Q16 is copied and extracted from the gate of T10.

[0037] The injection current branch is formed by transistors Q1-Q4 (first to fourth) and transistor Q5 (fifth). Transistors Q1-Q4 form an improved Wilson current mirror. When the voltage of the first power supply V1 is adjusted, the reference current flowing through Q5 changes. This current is accurately replicated by the Wilson current mirror and injected into the gate of T9 through the collector of Q4.

[0038] The sixth to tenth transistors, Q6-Q10, constitute the current-draining branch, and Q7-Q10 form another improved Wilson current mirror. Adjusting the voltage of the second power supply V2 changes the reference current of Q6, thereby controlling the collector of Q8 to draw shunt current from the gate of T9. In a preferred embodiment of the invention, to ensure the matching and response speed of the current mirror, the transistor type is preferably a complementary combination of PNP and NPN transistors.

[0039] The improved Wilson current mirror structure can effectively suppress transistor base current error, provide extremely high output impedance, ensure that the gate drive current strictly follows the adjustment commands of the external power supply V1-V4, and achieve highly linear analog control.

[0040] As a preferred technical solution of the present invention, in order to ensure the linearity of current regulation and response speed, the first to fifth transistors Q1-Q5 and the eleventh to fifteenth transistors Q11-Q15 are all PNP type transistors; the sixth to tenth transistors Q6-Q10 and the sixteenth to twentieth transistors Q16-Q20 are all NPN type transistors.

[0041] In one specific embodiment, the first regulating branch is used to drive the ninth switch T9, and its connection relationship is as follows: the emitter of the first transistor Q1 and the emitter of the second transistor Q2 are connected to the positive terminal of the first main power supply VCC1, and the negative terminal of the first main power supply VCC1 is connected to the third ground terminal GND3; the base of the first transistor Q1, the base of the second transistor Q2, the collector of the second transistor Q2, and the emitter of the fourth transistor Q4 are connected together; the collector of the first transistor Q1 is connected to the emitter of the third transistor Q3; the base and collector of the third transistor Q3, the base of the fourth transistor Q4, and the emitter of the fifth transistor Q5 are connected to the positive terminal of the first power supply V1; the collector of the fourth transistor Q4 is connected to the gate of the ninth switch T9; the negative terminal of the first power supply V1 is connected to the second terminal of the seventh resistor R7, the first terminal of the seventh resistor R7 is connected to the base of the fifth transistor Q5, and the collector of the fifth transistor Q5 is connected to the second terminal of the seventh resistor R7. The sixth transistor Q6 is connected to the fourth ground terminal GND4; the collector of the sixth transistor Q6 is connected to the positive terminal of the second main power supply VCC2, and the negative terminal of the second main power supply VCC2 is connected to the fifth ground terminal GND5; the base of the sixth transistor Q6 is connected to the first terminal of the eighth resistor R8, and the second terminal of the eighth resistor R8 is connected to the positive terminal of the second power supply V2; the negative terminal of the second power supply V2 is connected to the emitter of the sixth transistor Q6, the collector of the seventh transistor Q7, the base of the seventh transistor Q7, and the base of the eighth transistor Q8; the collector of the eighth transistor Q8 is connected to the gate of the ninth switch T9; the emitter of the seventh transistor Q7 is connected to the collector of the ninth transistor Q9; the emitter of the eighth transistor Q8, the base of the ninth transistor Q9, the base of the tenth transistor Q10, and the collector of the tenth transistor Q10 are all connected together; the emitter of the ninth transistor Q9 and the emitter of the tenth transistor Q10 are all connected to the sixth ground terminal GND6.

[0042] The second regulating branch is used to drive the tenth switching transistor T10, and its connection relationship is as follows: the emitter of the eleventh transistor Q11 and the emitter of the twelfth transistor Q12 are connected to the positive terminal of the third main power supply VCC3, and the negative terminal of the third main power supply VCC3 is connected to the seventh ground terminal GND7; the base of the eleventh transistor Q11, the base of the twelfth transistor Q12, the collector of the twelfth transistor Q12, and the emitter of the fourteenth transistor Q14 are connected together; the collector of the eleventh transistor Q11 is connected to... The base and collector of the thirteenth transistor Q13, the base of the fourteenth transistor Q14, and the emitter of the fifteenth transistor Q15 are all connected to the positive terminal of the third power supply V3; the collector of the fourteenth transistor Q14 is connected to the gate of the tenth switch T10; the negative terminal of the third power supply V3 is connected to the second terminal of the ninth resistor R9, the first terminal of the ninth resistor R9 is connected to the base of the fifteenth transistor Q15, and the collector of the fifteenth transistor Q15 is connected to the emitter of the thirteenth transistor Q13; the base and collector of the thirteenth transistor Q13, the base of the fourteenth transistor Q14, and the emitter of the fifteenth transistor Q15 are all connected to the positive terminal of the third power supply V3; the collector of the fourteenth transistor Q14 is connected to the gate of the tenth switch T10; the negative terminal of the third power supply V3 is connected to the second terminal of the ninth resistor R9, the first terminal of the ninth resistor R9 is connected to the base of the fifteenth transistor Q15, and the collector of the fifteenth transistor Q15 is connected to the emitter of the tenth switch T10. The eighth ground terminal is GND8; the collector of the sixteenth transistor Q16 is connected to the positive terminal of the fourth main power supply VCC4, and the negative terminal of the fourth main power supply VCC4 is connected to the ninth ground terminal GND9; the base of the sixteenth transistor Q16 is connected to the first terminal of the tenth resistor R10, and the second terminal of the tenth resistor R10 is connected to the positive terminal of the fourth power supply V4; the negative terminal of the fourth power supply V4 is connected to the emitter of the sixteenth transistor Q16, the collector of the seventeenth transistor Q17, the base of the seventeenth transistor Q17, and the... The base of the eighteenth transistor Q18; the collector of the eighteenth transistor Q18 is connected to the gate of the tenth switch T10; the emitter of the seventeenth transistor Q17 is connected to the collector of the nineteenth transistor Q19; the emitter of the eighteenth transistor Q18, the base of the nineteenth transistor Q19, the base of the twentieth transistor Q20, and the collector of the twentieth transistor Q20 are all connected together; the emitter of the nineteenth transistor Q19 and the emitter of the twentieth transistor Q20 are all connected to the tenth ground terminal GND10.

[0043] Specifically, the gate voltage feedback module 6 is connected between the power circuit 5 of the magnetic levitation bearing power amplifier and the control unit 1, and the connection relationship is as follows: The first input terminals of the first comparator U1 and the second comparator U2 are connected to the gate of the ninth switch T9, and their second input terminals are respectively connected to the first reference voltage terminal Vref1 and the second reference voltage terminal Vref2. Their output terminals are both connected to the first controller A1. The first input terminals of the third comparator U3 and the fourth comparator U4 are connected to the gate of the tenth switch T10, and their second input terminals are respectively connected to the third reference voltage terminal Vref3 and the fourth reference voltage terminal Vref4. Their output terminals are all connected to the second controller A2.

[0044] In one specific embodiment, the first to twelfth resistors R1-R12 are all precision resistors; the first to fifth transistors Q1-Q5 and the eleventh to fifteenth transistors Q11-Q15 are all PNP type transistors; the sixth to tenth transistors Q6-Q10 and the sixteenth to twentieth transistors Q16-Q20 are all NPN type transistors.

[0045] Based on the above hardware structure, this invention also provides a drive circuit control method. This method dynamically adjusts the resistance value and current source magnitude according to the transient characteristics of the switching process. The following explanation uses the switching process of the ninth switch T9 as an example; the control logic of the tenth switch T10 is symmetrical to it.

[0046] The turn-on process of the ninth switch T9 involves the coordinated action of graded resistor adjustment and current fine-tuning, specifically divided into the following stages: The first stage is the turn-on delay and the initial current rise. Control unit 1 controls the third switch T3 to be in the off state. At this time, the first resistor R1 is connected in series with the gate drive circuit. The large gate resistance limits the current change rate di / dt in the initial turn-on stage, thereby preventing current overshoot or oscillation and suppressing excessive electromagnetic interference.

[0047] The second stage is the rapid turn-on stage. The gate voltage feedback module 6 continuously monitors the gate voltage of T9. When the gate voltage rises to the threshold set by the first reference voltage terminal Vref1, the output state of the first comparator U1 changes, for example, from low level to high level. The threshold of the first reference voltage terminal is preferably set near the Miller plateau voltage. Based on this signal, the control unit 1 controls the third switch T3 to turn on, short-circuiting the first resistor R1. At this time, the gate drive circuit impedance decreases, providing a large current drive capability, allowing T9 to quickly enter the turn-on state, thereby significantly reducing switching losses.

[0048] The third stage is the overshoot suppression and current regulation stage. During the above turn-on process, in order to further optimize the waveform, the system executes a preferred current regulation step. Control unit 1 adjusts the output voltage of the second power supply V2. As the voltage of V2 changes, the improved Wilson current mirror structure composed of transistors Q6-Q10 (sixth to tenth) operates in the linear region, causing the collector current of the eighth transistor Q8 to increase. This current directly draws part of the drive current from the gate of T9, smoothly reducing the peak value of the gate drive current without changing the main resistor network configuration, thereby effectively suppressing collector current overshoot and ringing.

[0049] The turn-off process of the ninth switch T9 also adopts a segmented control strategy, as follows: The first stage is the rapid discharge stage. At the initial stage of the turn-off signal, control unit 1 controls the fourth switch T4 to turn on, short-circuiting the second resistor R2. The gate charge of T9 is rapidly discharged through this low-impedance path, thereby significantly shortening the turn-off delay time.

[0050] The second stage is the soft turn-off stage. When the gate voltage feedback module 6 detects that the gate voltage of T9 has dropped to the threshold set by the second reference voltage terminal Vref2, the output state of the second comparator U2 changes. Based on this, the control unit 1 controls the fourth switch T4 to turn off, causing the second resistor R2 to reconnect to the gate drive circuit. The increased gate resistance at this time slows down the voltage change rate dv / dt at the end of the turn-off period, preventing excessive voltage spikes.

[0051] The third stage is the ringing suppression and current regulation stage. If there is a risk of excessive ringing at the end of the turn-off period, control unit 1 initiates the preferred current regulation step: adjusting the output voltage of the first power supply V1. As the voltage of V1 changes, the improved Wilson current mirror structure composed of transistors Q1-Q5 (first to fifth) operates in the linear region, causing the collector of the fourth transistor Q4 to inject compensation current into the gate of T9. This reverse-injected current offsets part of the discharge rate, acting as active damping, thereby reducing voltage oscillations at the turn-off tail.

[0052] In this invention, the drain current waveform control of the MOSFET is achieved by adjusting the gate drive current. Although the MOSFET is a voltage-controlled device in steady state, during transient switching, the establishment of its gate voltage is essentially a charging process of its input parasitic capacitance, which follows the laws of charge conservation and capacitance voltage change.

[0053] Specifically, the turn-on process of a MOSFET includes a current rise phase. During this phase, the MOSFET operates in the saturation region, and its drain current... With gate-source voltage There exists an approximately linear transconductance relationship between them, that is: ; in, For the transconductance of the MOSFET, This is the threshold voltage for activation. The above equation shows that the drain current... The instantaneous amplitude directly follows the gate voltage. It changes with the changes.

[0054] Meanwhile, gate voltage The rate of change depends on the gate drive current. Input capacitor of MOSFET Mainly composed of gate-source capacitance and gate-drain capacitance The charging speed is determined by the capacitor current formula: ; The rate of change of the gate voltage can be derived. Proportional to gate drive current .

[0055] Combining the above two equations, the drain current change rate can be obtained. With gate drive current Direct coupling relationship: ; Based on the above physical model, the drive current injected into the gate of the MOS transistor can be actively controlled or adjusted. The size of the gate voltage can directly control the gate voltage. The rising slope of the drain current is used to precisely control the drain current. The rising slope. Specifically, increasing the gate drive current. This results in a steeper drain current waveform and faster switching speed; it also reduces the gate drive current. This makes the drain current waveform smoother, thereby reducing the rate of change of current. .

[0056] like Figure 5 As shown, Figure 5 The diagram illustrates the waveform timing of the active gate driving method for variable resistance and variable current regulation provided in this application during the switching cycle. From top to bottom, the diagram shows: driving signal V... GATE Gate-source voltage Drain current Drain-source voltage Gate resistance R G and the output current of the variable current module .

[0057] The following detailed explanation uses the switching process of the ninth switch T9 as an example. The switching process of T10 is symmetrical to that of T9.

[0058] Opening process t1-t6: t1-t4: At time t1, the driving signal V GATE The resistance changes from low to high. At this time, the control unit 1 controls the gate variable resistor module 3 to maintain a high resistance value R. big With R1 connected, the larger gate resistance limits the rise rate of the gate current, thereby suppressing the rate of change of current during the initial turn-on phase. .

[0059] Coordinated regulation: As shown in the IQ waveform in the figure, during the period t1-t4, control unit 1 simultaneously regulates the second power supply V2, so that the improved Wilson current mirror composed of Q6-Q10 operates in the linear region, generating an absorption current I. abs This current draws a portion of the charge from the T9 gate, further smoothing the flow. The rising slope of the drain current is used to reduce the drain current. The peak amplitude and oscillation intensity.

[0060] t4-t6: At time t4, when it is detected When the Miller plateau is exceeded or the preset first reference voltage threshold is reached, the control unit 1 issues a command to switch the gate variable resistor module 3 to a low resistance state R. small This means R1 is short-circuited. Simultaneously, the current source composed of Q6-Q10 is turned off, and IQ returns to zero. The purpose of this step is to rapidly increase the gate drive current, causing T9 to quickly pass through the Miller plateau and enter a fully saturated conduction state, thereby shortening the turn-on time and reducing conduction losses.

[0061] Shutdown process t7-t12: t7-t10: At time t7, the driving signal V GATE The resistance changes from high to low. At this time, the control unit 1 controls the gate variable resistor module 3 to switch to a low resistance state R. small This means R2 is short-circuited. During this period, the variable current module is in the off state. The connection of this low-impedance path is intended to accelerate the extraction rate of the gate charge of T9, causing VGS to drop rapidly, thereby shortening the turn-off delay time.

[0062] t10-t12: At time t10, when it is detected When the voltage drops to a preset second reference voltage threshold, the control unit 1 switches the gate variable resistor module 3 back to the high resistance state. big That is, R2 access.

[0063] Coordinated regulation: As shown in the IQ waveform in the figure, during the period t10-t12, control unit 1 adjusts the first power supply V1, so that the improved Wilson current mirror composed of Q1-Q5 operates in the linear region, generating an injected current I. injThis step injects charge into the gate of T9 to counteract the rapid drop in gate voltage, thereby slowing the rise rate dv / dt of the drain-source voltage VDS, reducing the amplitude of the turn-off voltage-current spikes, and suppressing electromagnetic interference.

[0064] To verify the effectiveness of the active gate drive circuit and method based on variable resistance and variable current regulation proposed in this invention, a simulation model was built using LTspice software in this embodiment. The key simulation parameters are configured as follows: the bus voltage VDC is set to 200V, and the load inductance L is set to 1mH.

[0065] Figure 6 The waveforms show a performance comparison between the traditional fixed resistor drive scheme and the variable resistance and current drive scheme of this invention during the turn-on process.

[0066] Simulation results show that if a smaller fixed gate resistor of 15Ω is used to pursue switching speed, the drain current iD will produce severe overshoot and ringing, with a peak value as high as 28.0A. If the resistor is increased to 25Ω to suppress ringing, the peak current overshoot can be reduced to 15.5A, but the conduction time of VDS will be significantly extended from 13ns to 31ns, which significantly increases the turn-on loss.

[0067] In this invention, the gate resistance is kept switching between 15Ω and 25Ω, and the voltage source V2 in the gate variable current module is subjected to a parameter scan range of 0.8V to 0.9V, with a step size of 0.01V. The simulated family of waveforms is as follows... Figure 6 The green waveform shows that the drain current overshoot peak can be precisely controlled between 16.9A and 19.0A, with a corresponding VDS conduction time of only 24.5ns to 27.2ns.

[0068] Compared to traditional solutions, this invention achieves precise suppression of turn-on current spikes without sacrificing too much switching speed through linear adjustment of V2. Further adjustment of the V2 value range enables broader-dimensional dynamic trajectory management.

[0069] Figure 7 The comparison between the two driving schemes during the shutdown process is shown.

[0070] When using a 15Ω fixed resistor, the drain current generates a reverse overshoot and ringing of approximately -5.0A. Switching to a 25Ω resistor can reduce the ringing peak to -3.6A, but the delay time for VDS to reach its peak value is increased from 57ns to 87ns, reducing the system's response frequency.

[0071] This invention introduces a compensation current during the turn-off phase by adjusting the voltage source V1 scanning range from 0.8V to 0.9V. Simulation results show that the drain current delay time is stable between 53ns and 59ns, while the delay time for VDS to reach its peak value fluctuates only between 57ns and 64ns.

[0072] This invention effectively smooths the voltage rise trajectory by injecting current at the end of the turn-off period, thereby improving the oscillation problem of the turn-off transient while maintaining a relatively fast turn-off speed.

[0073] Simulation results demonstrate that this invention successfully resolves the inherent contradiction in traditional drive circuits—the difficulty in simultaneously achieving both switching speed and signal quality overshoot / ringing—through a coordinated control strategy of coarse resistance adjustment and fine current adjustment. This scheme can flexibly find the optimal operating point within a continuous control range based on actual load requirements, validating the correctness and application value of the proposed theory and circuit structure. It is particularly suitable for scenarios such as magnetic bearing power amplifiers, where electromagnetic interference (EMI) and efficiency requirements are stringent.

[0074] The main feature that distinguishes this invention from the prior art is that it constructs a hybrid drive architecture that combines graded resistance regulation with linear current regulation. Although a single variable resistance drive technology has the characteristics of low impedance and strong driving capability, which can meet the needs of fast switching, the resistance value adjustment is discrete and limited by the number of resistor branches. Therefore, it is often difficult to achieve high-precision control when suppressing small current overshoots or voltage oscillations.

[0075] For single variable current drive technology, although the continuous linear adjustment of the drive current can be achieved by utilizing the characteristics of constant current source, in high-current fast switching application scenarios, it is difficult to independently provide the large transient current required for high-speed switching due to the limitations of transistor power capacity and circuit bandwidth.

[0076] This invention resolves the aforementioned technical contradictions through the coordinated operation of the two modules: on the one hand, the gate variable resistor module 3 provides the main gate charging and discharging circuit, and by switching the low-resistance resistor branch, it ensures that the power switch has sufficient switching speed to meet the high-frequency response requirements of the magnetic levitation system; on the other hand, the gate variable current module 4 is used to adjust the transistor in the linear operating region, and by injecting or extracting additional compensation current into the gate, it continuously and minutely corrects the main drive current set by the resistor network.

[0077] This hybrid control strategy effectively combines the high current capability of resistor drive with the high linearity of current drive, achieving precise suppression of current overshoot and electromagnetic interference (EMI) over a wide operating range.

[0078] In summary, this invention achieves optimized control of the switching trajectory of a magnetic levitation bearing power amplifier by switching the resistor value at specific time points to achieve graded adjustment of the driving capability, and by combining the Wilson current mirror to continuously and linearly adjust the gate current in both directions.

[0079] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0080] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0081] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An active gate drive circuit based on variable resistance and variable current regulation, characterized in that, The drive circuit includes a control unit (1), an isolated gate drive module (2), a gate variable resistor module (3), a gate variable current module (4), a magnetic levitation bearing power amplifier power circuit (5), and a gate voltage feedback module (6). The control unit (1) includes a first controller (A1) and a second controller (A2); the isolated gate drive module (2) includes a first set of isolated drivers (M1, M2, M3) and a second set of isolated drivers (M4, M5, M6); the first controller (A1) is connected to the first set of isolated drivers (M1, M2, M3); the second controller (A2) is connected to the second set of isolated drivers (M4, M5, M6); The first group of isolation drivers (M1, M2, M3) and the second group of isolation drivers (M4, M5, M6) are respectively connected to the gate variable resistor module (3); The gate variable resistor module (3) is connected to the gate variable current module (4) and the power circuit (5) of the magnetic levitation bearing power amplifier, respectively; The gate voltage feedback module (6) is connected between the power circuit (5) of the magnetic levitation bearing power amplifier and the control unit (1); The gate variable current module (4) includes a first regulation branch and a second regulation branch with symmetrical structure; the first regulation branch includes two sets of complementary current regulation structures for driving the ninth switch (T9); the first to fourth transistors (Q1-Q4) form a set of improved Wilson current mirror structures, and the seventh to tenth transistors (Q7-Q10) form another set of improved Wilson current mirror structures. The second regulating branch is used to drive the tenth switching transistor (T10), and its structure is completely symmetrical with that of the first regulating branch.

2. In the active gate drive circuit according to claim 1, in the isolated gate drive module (2), the output terminal of the first controller (A1) is connected to the input terminal of the first group of isolated drivers (M1, M2, M3); the output terminal of the second controller (A2) is connected to the input terminal of the second group of isolated drivers (M4, M5, M6); and the output terminals of the two groups of isolated drivers are connected to the gates of different switching transistors in the gate variable resistor module (3).

3. The active gate drive circuit according to claim 1, wherein the gate variable resistor module (3) is connected to the power circuit (5) of the magnetic levitation bearing power amplifier, and the connection relationship includes a first drive branch and a second drive branch. In the first drive branch, the first switch (T1) and the second switch (T2) constitute the main on / off path, the first resistor (R1) is connected in parallel across the third switch (T3), and the second resistor (R2) is connected in parallel across the fourth switch (T4), thereby changing the equivalent drive resistance connected to the gate of the ninth switch (T9) by controlling the on / off state of the third switch (T3) and the fourth switch (T4); in the second drive branch, a symmetrical structure is adopted, the fourth resistor (R4) is connected in parallel across the seventh switch (T7), and the fifth resistor (R5) is connected in parallel across the eighth switch (T8), thereby changing the equivalent drive resistance connected to the gate of the tenth switch (T10) by controlling the on / off state of the seventh switch (T7) and the eighth switch (T8).

4. The active gate driving circuit according to claim 1, wherein the gate variable resistor module (3) comprises: The first to eighth switching transistors (T1-T8), the first to sixth resistors (R1-R6), and the first ground terminal (GND1) and the second ground terminal (GND2) are connected; the output terminal of the first isolation driver (M1) is connected to the gate of the first and second switching transistors (T1, T2), and the output terminal of the fourth isolation driver (M4) is connected to the gate of the fifth and sixth switching transistors (T5, T6); the output terminals of the second, third, fifth and sixth isolation drivers (M2, M3, M5, M6) are respectively connected to the gate of the corresponding third, fourth, seventh and eighth switching transistors (T3, T4, T7, T8).

5. The active gate driving circuit according to claim 3, wherein the connection relationship of the first driving branch is as follows: the drain of the first switching transistor (T1) is connected to the positive terminal of the first power supply (VDD1), and the source is connected to the drain of the third switching transistor (T3); the first resistor (R1) is connected in parallel between the drain and the source of the third switching transistor (T3); the source of the third switching transistor (T3) is connected to the first end of the third resistor (R3) and the drain of the fourth switching transistor (T4); the second end of the third resistor (R3) is connected to the gate of the ninth switching transistor (T9); the second resistor (R2) is connected in parallel between the drain and the source of the fourth switching transistor (T4); the source of the fourth switching transistor (T4) is connected to the drain of the second switching transistor (T2), and the source of the second switching transistor (T2) is connected to the negative terminal of the first power supply (VDD1) and the first ground terminal (GND1).

6. The active gate drive circuit according to claim 3, wherein the connection relationship of the second drive branch is as follows: the drain of the fifth switch (T5) is connected to the positive terminal of the second power supply (VDD2), and the source is connected to the drain of the seventh switch (T7); the fourth resistor (R4) is connected in parallel between the drain and source of the seventh switch (T7); the source of the seventh switch (T7) is also connected to the second terminal of the sixth resistor (R6) and the drain of the eighth switch (T8); the first terminal of the sixth resistor (R6) is connected to the gate of the tenth switch (T10); the fifth resistor (R5) is connected in parallel between the drain and source of the eighth switch (T8); the source of the eighth switch (T8) is connected to the drain of the sixth switch (T6), and the source of the sixth switch (T6) is connected to the negative terminal of the second power supply (VDD2) and the second ground terminal (GND2).

7. The active gate drive circuit according to claim 1, wherein in the first adjustment branch, the first to fourth transistors (Q1-Q4) are responsible for accurately replicating the reference current generated by the fifth transistor (Q5) and injecting it into the gate of the ninth switch (T9); wherein, The reference current of the fifth transistor (Q5) can be linearly changed by adjusting the voltage of the external first power supply (V1), thereby controlling the magnitude of the drive current injected into the gate of the ninth switch (T9).

8. The active gate driving circuit according to claim 1, wherein the first adjustment branch is used to drive the ninth switch (T9), and its connection relationship is as follows: the emitter of the first transistor (Q1) and the emitter of the second transistor (Q2) are connected to the positive terminal of the first main power supply (VCC1), and the negative terminal of the first main power supply (VCC1) is connected to the third ground terminal (GND3); the base of the first transistor (Q1), the base of the second transistor (Q2), the collector of the second transistor (Q2), and the emitter of the fourth transistor (Q4) are connected to the third ground terminal (GND3). The collector of the first transistor (Q1) is connected to the emitter of the third transistor (Q3); the base and collector of the third transistor (Q3), the base of the fourth transistor (Q4), and the emitter of the fifth transistor (Q5) are all connected to the positive terminal of the first power supply (V1); the collector of the fourth transistor (Q4) is connected to the gate of the ninth switch (T9); the negative terminal of the first power supply (V1) is connected to the second terminal of the seventh resistor (R7), the first terminal of the seventh resistor (R7) is connected to the base of the fifth transistor (Q5), and the fifth transistor (Q5... The collector of the sixth transistor (Q6) is connected to the fourth ground terminal (GND4); the collector of the sixth transistor (Q6) is connected to the positive terminal of the second main power supply (VCC2), and the negative terminal of the second main power supply (VCC2) is connected to the fifth ground terminal (GND5); the base of the sixth transistor (Q6) is connected to the first terminal of the eighth resistor (R8), and the second terminal of the eighth resistor (R8) is connected to the positive terminal of the second power supply (V2); the negative terminal of the second power supply (V2) is connected to the emitter of the sixth transistor (Q6), the collector of the seventh transistor (Q7), and the collector of the seventh transistor (Q... 7) The base of the transistor and the base of the eighth transistor (Q8); the collector of the eighth transistor (Q8) is connected to the gate of the ninth switch (T9); the emitter of the seventh transistor (Q7) is connected to the collector of the ninth transistor (Q9); the emitter of the eighth transistor (Q8), the base of the ninth transistor (Q9), the base of the tenth transistor (Q10), and the collector of the tenth transistor (Q10) are connected together; the emitter of the ninth transistor (Q9) and the emitter of the tenth transistor (Q10) are connected together to the sixth ground terminal (GND6).

9. The active gate drive circuit according to claim 1, wherein the gate voltage feedback module (6) is connected between the power circuit (5) of the magnetic levitation bearing power amplifier and the control unit (1), and the connection relationship is as follows: The first input terminals of the first comparator (U1) and the second comparator (U2) are connected to the gate of the ninth switch (T9), and their second input terminals are connected to the first reference voltage terminal (Vref1) and the second reference voltage terminal (Vref2) respectively. Their output terminals are all connected to the first controller (A1). The first input terminals of the third comparator (U3) and the fourth comparator (U4) are connected to the gate of the tenth switch (T10), and their second input terminals are connected to the third reference voltage terminal (Vref3) and the fourth reference voltage terminal (Vref4), respectively. Their output terminals are all connected to the second controller (A2).

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