An input / output port switchable circuit

Abstract

The application relates to the field of data transmission circuits and discloses a circuit with switchable input and output ports, which comprises a first data port and a second data port, an enable control signal generation module, when input data signals exist in the first data port, the level state of the second enable control signal is switched, and the level state of the first enable control signal remains unchanged; when input data signals exist in the second data port, the level state of the first enable control signal is switched, and the level state of the second enable control signal remains unchanged. The enable control signal generation module monitors the signal states of the two data ports in real time, automatically identifies the data input direction, and dynamically switches the corresponding enable control signal, so as to control the transmission direction of the data channel. The intelligent switching of the input and output functions is realized, and the defects of the fixed port function and the insufficient flexibility of the traditional bidirectional transmission circuit are overcome.

Description

Technical Field

[0001] This invention relates to the field of data transmission circuits, specifically to a circuit with switchable input and output ports. Background Technology

[0002] As the integration and functional complexity of electronic devices continue to increase, the methods of data transmission in circuit systems are also becoming increasingly diverse. In applications such as integrated circuits, LED drivers, and electronic product control, signal transmission typically relies on directional connections between input and output ports. These circuits are widely used in various electronic control systems, switching circuits, and related algorithm implementations, placing high demands on system stability, response speed, and configuration flexibility.

[0003] In traditional signal transmission architectures, circuits often employ fixed input / output port configurations, meaning a port can only be used as either an input or output, and the data transmission direction is determined during the hardware design phase. While this fixed approach simplifies circuit design and control logic to some extent, its flexibility is significantly limited in applications requiring dynamic adjustment of data flow or multiplexing of the same port. For example, in operating modes requiring bidirectional device detection, signal feedback, or role switching, fixed ports often necessitate external switching circuits or complex control logic, increasing system complexity and cost. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a circuit with switchable input and output ports, solving the problem that the signal transmission direction is limited by the fixed functional definition of the ports, making it impossible to dynamically switch between input and output functions without changing the hardware connection.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a circuit with switchable input and output ports, comprising: a first data port, DIN, and a second data port, DOUT; an enable control signal generation module, the input terminals of which are electrically connected to the first data port and the second data port respectively, and the output terminals of which output a first enable control signal, DIN_OEA, and a second enable control signal, DOUT_OEA; the enable control signal generation module is configured such that: when an input data signal is present at the first data port, the level state of the second enable control signal switches, while the level state of the first enable control signal remains unchanged; when an input data signal is present at the second data port, the level state of the first enable control signal switches, while the level state of the second enable control signal remains unchanged.

[0006] Preferably, the enable control signal generation module includes: a signal detection submodule, whose input terminals are electrically connected to the first data port and the second data port respectively; and a logic output submodule, whose input terminal is electrically connected to the output terminal of the signal detection submodule, and whose output terminal outputs the first enable control signal and the second enable control signal; the signal detection submodule detects the input data signal of the first data port or the second data port and outputs the detection result, and the logic output submodule selects to control the level state switching of the first enable control signal or the second enable control signal according to the detection result.

[0007] Preferably, it further includes: a data channel switching unit, whose control terminal is electrically connected to the two output terminals of the logic output submodule to receive the first enable control signal and the second enable control signal, and whose two ends of the data path are electrically connected to the first data port and the second data port, respectively; the data channel switching unit configures the first data port as an input state and the second data port as an output state, or configures the first data port as an output state and the second data port as an input state, according to the level state of the first enable control signal and the second enable control signal.

[0008] Preferably, the enable control signal generation module further includes a conflict arbitration submodule, the input of which is electrically connected to the output of the signal detection submodule; when the signal detection submodule detects that the first data port and the second data port have input data signals at the same time, the conflict arbitration submodule outputs an arbitration command to the logic output submodule, and the logic output submodule adjusts the level switching timing of the first enable control signal and the second enable control signal according to the arbitration command.

[0009] Preferably, the signal detection submodule includes a protocol identification submodule, the input terminals of which are electrically connected to the first data port and the second data port respectively, and the output terminal of which is electrically connected to the input terminal of the conflict arbitration submodule. The protocol identification submodule performs protocol type parsing on the input data signal and outputs a protocol type identifier.

[0010] Preferably, the conflict arbitration submodule has a built-in priority configuration table, which pre-stores the correspondence between different protocol types and priority levels; after receiving the protocol type identifier, the conflict arbitration submodule queries the priority configuration table to obtain the corresponding priority level, and generates the arbitration instruction based on the priority level.

[0011] Preferably, the logic output submodule includes a timing parameter adjustment submodule, which establishes a communication connection with the protocol identification submodule; the timing parameter adjustment submodule has built-in timing parameters that correspond one-to-one with different protocol types, and the timing parameter adjustment submodule calls the corresponding timing parameters according to the protocol type identifier output by the protocol identification submodule to adjust the output delay duration of the first enable control signal and / or the second enable control signal.

[0012] Preferably, the data channel switching unit includes an electrical characteristic matching submodule, which establishes a communication connection with the protocol identification submodule; after receiving the protocol type identifier, the electrical characteristic matching submodule configures the structural parameters of the driving circuit corresponding to the first data port or the second data port in the output state.

[0013] Preferably, it further includes a first data buffer unit and a second data buffer unit; the first data buffer unit is connected in series in the signal path between the first data port and the data channel switching unit, and the second data buffer unit is connected in series in the signal path between the second data port and the data channel switching unit; when the conflict arbitration submodule determines that the transmission priority of the first data port or the second data port is lower than that of another port, the first data buffer unit or the second data buffer unit corresponding to that port stores the input data signal.

[0014] Preferably, the conflict arbitration submodule further includes a data feature extraction submodule, the input terminals of which are electrically connected to the first data port and the second data port, respectively; the data feature extraction submodule extracts a priority field of a preset format from the input data signal, and the conflict arbitration submodule combines the priority field with the detection result of the signal detection submodule to generate the arbitration instruction.

[0015] This invention provides a circuit with switchable input and output ports. It has the following advantages:

[0016] 1. This invention uses an enable control signal generation module to monitor the signal status of two data ports in real time, automatically identify the data input direction, and dynamically switch the corresponding enable control signal to control the transmission direction of the data channel. It achieves intelligent switching of input and output functions without external manual intervention or additional switching commands, overcoming the shortcomings of traditional bidirectional transmission circuits with fixed port functions and insufficient flexibility.

[0017] 2. This invention adds a conflict arbitration submodule to the enable control signal generation module, and sets up a protocol identification submodule and a priority configuration table. The circuit can automatically parse multiple transmission protocols such as UART, SPI, and I2C through the protocol identification submodule, and complete the protocol priority determination in combination with the pre-stored priority configuration table to generate targeted arbitration instructions. This prioritizes the data transmission of protocols with high real-time performance and high importance, and avoids data transmission disorder through timing adjustment. This significantly improves the orderliness and reliability of multi-source data transmission at the same time, and meets the needs of concurrent transmission of multiple protocols and multiple data streams in complex application scenarios.

[0018] 3. The present invention can automatically calibrate key parameters such as delay duration, setup time and hold time of enable control signal according to protocol type through timing parameter adjustment submodule, thereby avoiding data transmission errors caused by timing mismatch; the electrical characteristic matching submodule can dynamically adjust electrical parameters such as drive current, output impedance and level amplitude of output port according to protocol requirements, to prevent data signal distortion and attenuation during transmission, so that a single circuit can be compatible with multiple transmission protocols with different timing and electrical characteristic requirements at the same time.

[0019] 4. This invention can extract a dedicated priority field from the data signal through the data feature extraction submodule, forming a dual judgment basis with the protocol priority, making the arbitration result more in line with the priority requirements of actual applications; the first and second data caching units can perform high-speed and orderly temporary storage of low-priority data in the event of a conflict, and then read it out and transmit it in an orderly manner after the high-priority data transmission is completed, completely avoiding the problem of low-priority data loss caused by data conflict. Combined with the first-in-first-out storage mode, it ensures the consistency between the data transmission order and the input order. Attached Figure Description

[0020] Figure 1 This is a block diagram of the overall circuit structure of the present invention;

[0021] Figure 2 This is a sub-block diagram of the internal structure of the enable control signal generation module of the present invention;

[0022] Figure 3 This is a detailed diagram showing the connection between the data channel switching unit and the data buffer unit of the present invention;

[0023] Figure 4 This is a signal timing diagram for a typical application scenario of the present invention. Detailed Implementation

[0024] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Referring to the accompanying drawings, this embodiment of the invention provides a circuit with switchable input and output ports, solving the technical problem of fixed input and output states and insufficient flexibility in traditional bidirectional transmission circuits. This circuit includes two core data ports: a first data port and a second data port, referred to as DIN and DOUT, respectively. These two data ports serve as interfaces for data interaction between the circuit and external devices, used to receive externally input data signals or output data signals to external devices. The input and output functions can be dynamically switched according to actual transmission requirements.

[0026] The circuit includes an enable control signal generation module, which is the core control unit for achieving adaptive port switching. Its input terminals are electrically connected to the first and second data ports, respectively, enabling real-time acquisition of the signal status of both data ports. The output terminal of the enable control signal generation module can output two independent enable control signals: a first enable control signal and a second enable control signal.

[0027] The enabling control signal generation module is specifically configured to adaptively switch the data transmission direction. When an input data signal is received at the first data port (i.e., an external device is transmitting data to the first data port), the enabling control signal generation module detects this signal change in real time. At this point, the module controls the level state of the second enabling control signal to switch, while the level state of the first enabling control signal remains unchanged. This level switching directly affects subsequent data channel control, ensuring that the data input at the first data port can be successfully transmitted to the target end.

[0028] When an input data signal is received at the second data port, i.e., when an external device transmits data to the second data port, the enable control signal generation module will also detect the signal change in real time. At this time, the module will control the level state of the first enable control signal to switch, while the level state of the second enable control signal remains unchanged. Through this differentiated enable control logic, the circuit can automatically identify the data input port and then switch the data transmission direction to achieve adaptive bidirectional data transmission without manual intervention or additional switching control signals.

[0029] Based on the aforementioned adaptive bidirectional data transmission circuit, the signal detection submodule establishes electrical connections between its input terminals and the first and second data ports, respectively, enabling continuous monitoring of the signal status of both data ports and identification of whether an input data signal is connected. The signal detection submodule's detection range covers various common data signal types, capable of identifying input signals of different amplitudes and frequencies. It also possesses strong anti-interference capabilities, effectively distinguishing between valid data signals and external interference signals, avoiding false detections caused by interference. The logic output submodule is the unit for generating and outputting enable control signals. Its input terminal establishes an electrical connection with the output terminal of the signal detection submodule, enabling real-time reception of the detection results transmitted by the signal detection submodule. The logic output submodule's output terminal is divided into two paths, outputting a first enable control signal and a second enable control signal respectively. These two signals are output independently and can be applied to subsequent port control units.

[0030] The signal detection submodule continuously monitors the input status of the first and second data ports. When it detects an input data signal at either port, it immediately outputs the corresponding detection result to the logic output submodule. The detection result is transmitted in the form of an electrical signal, clearly identifying the port with data input. After receiving the detection result, the logic output submodule selects one of the following to control the level state of either the first or second enable control signal according to preset logic rules: If the detection result indicates input at the first data port, the logic output submodule controls the second enable control signal to switch its level state, while the first enable control signal remains unchanged; if the detection result indicates input at the second data port, the logic output submodule controls the first enable control signal to switch its level state, while the second enable control signal remains unchanged, thus achieving adaptive control of the enable signal.

[0031] The aforementioned adaptive bidirectional data transmission circuit also includes a data channel switching unit. The control terminal of this unit employs a dual-input design, establishing electrical connections with the two output terminals of the logic output submodule, enabling it to receive the first and second enable control signals in real time. These two enable control signals serve as control commands for data channel switching, and their level directly determines the operating state of the data channel switching unit and the data transmission direction. The data path of the data channel switching unit adopts a bidirectional design, with its two ends establishing electrical connections with the first and second data ports, forming a complete data transmission path. The data path possesses bidirectional conduction capability, allowing for flexible switching of the data transmission direction according to control commands.

[0032] When the first enable control signal output by the logic output submodule maintains its original level while the second enable control signal undergoes a level switch, the data channel switching unit configures the first data port as an input and the second data port as an output. Data is then input from the first data port, transmitted through the data channel switching unit's path to the second data port, and finally output from the second data port to the external device. Conversely, when the second enable control signal output by the logic output submodule maintains its original level while the first enable control signal undergoes a level switch, the data channel switching unit configures the first data port as an output and the second data port as an input. Data is then input from the second data port, transmitted through the data channel switching unit's path to the first data port, and finally output from the first data port to the external device. Through this configuration, the circuit achieves adaptive switching between input and output ports, meeting the requirements for bidirectional data transmission.

[0033] Considering that in practical applications, there might be situations where both the first and second data ports receive input data signals simultaneously, to avoid data transmission conflicts and ensure data transmission integrity, the aforementioned enable control signal generation module also includes a conflict arbitration submodule. The input of the conflict arbitration submodule is electrically connected to the output of the signal detection submodule, enabling it to receive the detection results transmitted by the signal detection submodule in real time and identify whether two data ports have simultaneous input data signals. The conflict arbitration submodule has built-in dedicated arbitration logic, which can quickly respond to data conflict scenarios, generate reasonable arbitration instructions, and ensure orderly data transmission.

[0034] When the signal detection submodule detects that input data signals exist simultaneously at both the first and second data ports, it immediately transmits the corresponding detection result to the conflict arbitration submodule, indicating that a data conflict is currently occurring. Upon receiving the detection result, the conflict arbitration submodule quickly analyzes the data according to its built-in arbitration logic and outputs an arbitration command, which is transmitted to the logic output submodule in the form of an electrical signal.

[0035] After receiving the arbitration instruction from the conflict arbitration submodule, the logic output submodule will abandon the original single-choice control logic and instead adjust the level switching timing of the first enable control signal and the second enable control signal according to the arbitration instruction.

[0036] The protocol identification submodule is responsible for parsing the protocol type of the input data signal, providing a basis for subsequent arbitration, timing adjustment, and electrical characteristic matching. The submodule employs a dual-input design, establishing electrical connections with both the first and second data ports, enabling real-time acquisition of input data signals from both ports. Whether the first or second data port is the sole input, or both ports are input simultaneously, the submodule can synchronously acquire the data signal and perform protocol parsing. The output of the submodule is electrically connected to the input of the conflict arbitration submodule. Its core function is to parse the protocol type of the input data signal, extract the protocol identification information, and transmit the parsed protocol type identifier to the conflict arbitration submodule as an electrical signal. The protocol identification submodule supports parsing various common data transmission protocols, including but not limited to UART, SPI, and I2C protocols. It can automatically identify the characteristic fields of different protocols, such as start bits, stop bits, and protocol identifier codes, with high parsing accuracy and strong anti-interference capabilities, effectively avoiding protocol parsing errors caused by signal distortion. The protocol identification submodule's parsing process is performed in real time, synchronized with the signal detection submodule's detection process. This ensures that protocol type parsing is completed simultaneously with the detection of input data signals, and the protocol type identifier is quickly output. This protocol type identifier not only provides arbitration evidence for the conflict arbitration submodule but also supports subsequent timing parameter adjustments and electrical characteristic matching, enabling the circuit to adapt to the data transmission requirements of different protocols and improving the circuit's versatility and practicality.

[0037] The priority configuration table pre-stores the correspondence between different protocol types and priority levels. The priority levels can be preset according to the actual application scenario. For example, based on the real-time requirements of data transmission, protocols with high real-time requirements (such as SPI) correspond to high priority levels, while protocols with lower real-time requirements (such as UART) correspond to low priority levels. Alternatively, they can be based on the importance of the data, with important data corresponding to higher protocol priority and ordinary data corresponding to lower protocol priority. The contents of the priority configuration table can be pre-defined in the conflict arbitration submodule or flexibly adjusted according to actual application needs to improve circuit adaptability.

[0038] When the signal detection submodule detects simultaneous input data signals from two data ports, the protocol identification submodule performs protocol parsing on both input data signals, outputs the corresponding protocol type identifiers, and synchronously transmits both protocol type identifiers to the conflict arbitration submodule. Upon receiving the two protocol type identifiers, the conflict arbitration submodule immediately queries the built-in priority configuration table and, based on the pre-stored correspondence in the configuration table, obtains the priority level corresponding to each protocol type. Subsequently, the conflict arbitration submodule compares the two priority levels and generates an arbitration command based on the comparison result. The arbitration command explicitly specifies that the port corresponding to the higher priority protocol should prioritize data transmission, while the port corresponding to the lower priority protocol should postpone transmission. This achieves conflict arbitration based on protocol priority, ensuring that high-priority data can be transmitted in a timely manner to meet real-time requirements.

[0039] The timing parameter adjustment submodule establishes a stable communication connection with the protocol identification submodule. This communication connection uses electrical signal transmission to ensure that the timing parameter adjustment submodule can receive the protocol type identifier output by the protocol identification submodule in real time. The timing parameter adjustment submodule has a built-in timing parameter library, which stores timing parameters corresponding one-to-one with different protocol types. These timing parameters include, but are not limited to, the output delay duration of the enable signal, setup time, and hold time. The timing parameters corresponding to different protocol types are precisely calibrated to meet the data transmission timing requirements of that protocol.

[0040] After parsing the input data signal, the protocol identification submodule transmits the obtained protocol type identifier to the timing parameter adjustment submodule. Upon receiving the protocol type identifier, the timing parameter adjustment submodule immediately queries the internal timing parameter library for the corresponding timing parameter and calls the timing parameter. Subsequently, based on the called timing parameter, the timing parameter adjustment submodule adjusts the timing of one or both of the first and second enable control signals output by the logic output submodule, focusing on adjusting the output delay duration of the enable control signal to ensure that the switching timing of the enable control signal matches the timing requirements of the current transmission protocol. After adjustment, the logic output submodule outputs the adjusted enable control signal to the data channel switching unit to control data channel switching and data transmission, thereby avoiding data transmission errors caused by timing mismatch and improving the reliability of data transmission.

[0041] Different data transmission protocols have varying electrical characteristic requirements for circuits. To ensure stable data transmission for all protocols, the electrical characteristic matching submodule establishes a communication connection with the protocol identification submodule. It can receive the protocol type identifier output by the protocol identification submodule in real time, thereby obtaining the protocol type information for the current data transmission. The electrical characteristic matching submodule has built-in electrical characteristic configuration parameters corresponding to different protocol types. These configuration parameters include, but are not limited to, the drive current magnitude, output impedance, voltage level, rise and fall times of the drive circuit. These parameters are precisely optimized to adapt to the electrical characteristic requirements of the corresponding protocol.

[0042] After the data channel switching unit determines the output port based on the enable control signal, the protocol identification submodule transmits the protocol type identifier of the currently transmitted data to the electrical characteristic matching submodule. Upon receiving the protocol type identifier, the electrical characteristic matching submodule queries the built-in electrical characteristic configuration parameters to obtain the drive circuit configuration parameters corresponding to the protocol type. Subsequently, based on the obtained configuration parameters, the electrical characteristic matching submodule configures the structural parameters of the drive circuit corresponding to the first or second data port in the output state, adjusting parameters such as the drive current and output impedance of the drive circuit to match the electrical characteristics of the output port with the requirements of the current transmission protocol. After configuration, the output port can output data signals according to the matched electrical characteristics, ensuring that the data signal will not be distorted or attenuated during transmission, improving the stability and integrity of data transmission, and expanding the circuit's adaptability range to be compatible with protocols with different electrical characteristic requirements.

[0043] The first data buffer unit and the second data buffer unit work in conjunction with the two data ports and the data channel switching unit to achieve temporary data storage. The first data buffer unit is connected in series in the signal path between the first data port and the data channel switching unit. Its input is electrically connected to the first data port, and its output is electrically connected to one end of the data channel switching unit. It can receive and temporarily store the data signal input from the first data port in real time. The second data buffer unit is also connected in series in the signal path between the second data port and the data channel switching unit. Its input is electrically connected to the second data port, and its output is electrically connected to the other end of the data channel switching unit. It can receive and temporarily store the data signal input from the second data port in real time.

[0044] Both data buffer units employ a high-speed cache design, possessing large storage capacity and fast read / write speeds to meet the temporary storage needs of various protocol data. They also support a first-in-first-out (FIFO) storage method, ensuring that the data transmission order matches the input order. The operating state of the data buffer units is indirectly controlled by the conflict arbitration submodule, whose control logic is as follows: When the conflict arbitration submodule determines that both the first and second data ports have input data signals simultaneously, and determines through arbitration that the transmission priority of one port is lower than the other, the buffer unit corresponding to the lower-priority port immediately activates its storage function, temporarily storing the input data signal from that port. After the higher-priority port completes data transmission, the conflict arbitration submodule issues a control command to activate the corresponding buffer unit, reads the stored data signal, and transmits it to the output port through the data channel switching unit. This prevents the loss of low-priority data due to conflict and ensures that both data streams are transmitted completely.

[0045] The data feature extraction submodule employs a dual-input design, establishing electrical connections with both the first and second data ports. This allows for real-time acquisition of data signals from both ports, enabling synchronous feature extraction regardless of data conflicts. The core function of this submodule is to extract a pre-formatted priority field from the input data signal. This priority field is a pre-defined field in the data signal used to identify data priority; its format can be preset according to the specific application scenario, such as a few binary digits in a data frame or a specific character sequence.

[0046] The data feature extraction submodule possesses strong field recognition capabilities, enabling it to quickly locate and extract priority fields from complex data signals. It also exhibits anti-interference capabilities, effectively preventing field extraction errors caused by signal distortion and noise interference. After extraction, the data feature extraction submodule transmits the extracted priority fields to the core arbitration unit of the conflict arbitration submodule, where they work in conjunction with the protocol type identifier output by the protocol identification submodule and the detection results output by the signal detection submodule.

[0047] When the signal detection submodule detects simultaneous input data signals from two data ports, the data feature extraction submodule extracts the priority fields from both data signals. The protocol identification submodule parses the protocol types of the two data signals and outputs the protocol type identifier. The conflict arbitration submodule receives the priority fields, protocol type identifier, and detection results simultaneously. It first queries the priority configuration table based on the protocol type identifier to obtain the protocol priority, and then combines it with the extracted priority fields to comprehensively determine the priority of the two data signals. If the protocol priorities of the two data signals are different, an arbitration command is generated based on the protocol priority. If the protocol priorities of the two data signals are the same, the priority is determined based on the extracted priority fields, and an arbitration command is generated to control the transmission sequence of the two data signals. In this way, the basis for conflict arbitration is more comprehensive, the arbitration logic is more accurate and flexible, and it can better adapt to the arbitration needs of different application scenarios, further improving the rationality and efficiency of data transmission.

[0048] The present invention also provides the following embodiments:

[0049] Example 1: This example is applicable to scenarios without data transmission conflicts, enabling adaptive bidirectional data transmission between the DIN and DOUT ports. The core components include a first data port DIN and a second data port DOUT enable control signal generation module, and a data channel switching unit.

[0050] The signal detection submodule uses a dual-channel voltage comparator LM311, with its two input terminals electrically connected to the DIN and DOUT ports respectively. The reference voltage is set to 0.8V. When the amplitude of the input data signal exceeds 0.8V, the comparator outputs a high level, indicating the presence of a valid data signal. When the amplitude is below 0.8V, it outputs a low level, indicating the absence of valid data.

[0051] The logic output submodule uses a dual-channel NAND gate 74HC00. Its input is electrically connected to the output of the signal detection submodule. The output outputs DIN_OEA and DOUT_OEA, two enable control signals. The NAND gate is powered by 3.3V and its operating frequency is adapted to a data transmission rate of 0-100MHz.

[0052] The data channel switching unit uses a bidirectional analog switch ADG715, whose control terminal receives DIN_OEA and DOUT_OEA signals respectively. The two ends of the data path are electrically connected to the DIN and DOUT ports respectively. The on-resistance of the analog switch is less than 5Ω, ensuring that there is no significant attenuation in the data signal transmission.

[0053] Work process:

[0054] When an external device inputs a UART protocol data signal to the DIN port, the corresponding comparator of the signal detection submodule outputs a high level. This detection result is transmitted to the logic output submodule, which keeps DIN_OEA at a high level and controls DOUT_OEA to switch from a high level to a low level.

[0055] After receiving the above enable signal, the data channel switching unit configures DIN as the input state and DOUT as the output state. The data signal input from the DIN port is transmitted to the DOUT port through the analog switch path and output to the external receiving device from the DOUT port. At this time, in the timing diagram, the DIN signal precedes DOUT_OEA. When the level switches, the waveforms of the DOUT signal and the DIN signal are consistent, with a delay of no more than 10ns.

[0056] When an external device inputs a UART protocol data signal to the DOUT port, the corresponding comparator of the signal detection submodule outputs a high level, and the logic output submodule keeps DOUT_OEA at a high level and controls DIN_OEA to switch from a high level to a low level.

[0057] The data channel switching unit configures DOUT as an input state and DIN as an output state. The data signal input from the DOUT port is transmitted to the DIN port through the analog switch path and output from the DIN port. In the timing diagram, the DOUT signal appears before the DIN_OEA level switch. The waveforms of the DIN signal and the DOUT signal are consistent, with a delay of no more than 10ns.

[0058] Example 2,

[0059] This embodiment is applicable to conflict scenarios where data is input simultaneously from two ports. Based on Embodiment 1, it adds a conflict arbitration submodule, a first data cache unit, a second data cache unit, a protocol identification submodule, and a data feature extraction submodule.

[0060] The protocol identification submodule uses a field-programmable gate array (FPGA), XC7K325T. Its inputs are electrically connected to the DIN and DOUT ports, respectively. It has built-in feature identification algorithms for UART, SPI, and I2C protocols, and can complete protocol type parsing and output the protocol type identifier within 10ns.

[0061] The conflict arbitration submodule uses the built-in priority configuration table of the STM32F103 microcontroller. The pre-stored SPI protocol priority is 1, UART is 2, I2C is 3, and the smaller the value, the higher the priority. The data feature extraction submodule is integrated into the FPGA and can extract the 3rd to 5th bits of the data frame as the priority field.

[0062] Both the first and second data cache units use static random access memory (SRAM) IS61LV25616 with a storage capacity of 4 Mbit and a read / write speed of 10 ns. They are connected in series between DIN and the data channel switching unit DOUT.

[0063] Work process:

[0064] When an SPI protocol data signal is input to the DIN port and a UART protocol data signal is simultaneously input to the DOUT port, the signal detection submodule detects both valid data signals at the same time and outputs a high-level detection result.

[0065] The protocol identification submodule parses and outputs the SPI protocol identifier and UART protocol identifier for the two signals respectively. The data feature extraction submodule extracts the priority field from the two data streams, both of which have a default value of 010.

[0066] After receiving the protocol identifier and priority field, the conflict arbitration submodule queries the priority configuration table to determine that the SPI protocol has a higher priority than the UART protocol. Since there is no special configuration for the priority field, it generates an arbitration command. The command specifies that the DIN port should prioritize the transmission of DOUT port data for temporary storage.

[0067] According to the arbitration command, the logic output submodule controls DIN_OEA to remain high and DOUT_OEA to switch to low, and at the same time sends a storage command to the second data buffer unit. The data signal input to the DOUT port is stored in the second data buffer unit.

[0068] The data channel switching unit configures DIN as the input state and DOUT as the output state. The SPI protocol data of the DIN port is transmitted to the DOUT port output through the channel. After the transmission is completed, the conflict arbitration submodule sends a read command, and the data stored in the second data buffer unit is read out and transmitted to the DIN port output through the data channel switching unit.

[0069] Example 3,

[0070] This embodiment is applicable to multi-protocol data transmission scenarios. It supports adaptive switching between I2C, SPI, and UART protocols, and optimizes timing parameter adjustment and electrical characteristic matching functions.

[0071] The timing parameter adjustment submodule is integrated into the FPGA and has a built-in timing parameter library that stores the output delay time of the enable signal corresponding to three protocols: 5ns for SPI protocol, 8ns for I2C protocol, and 10ns for UART protocol. The setup time and hold time are preset to 3ns and 2ns, respectively.

[0072] The electrical characteristic matching submodule uses a programmable driver chip, MAX3232, which establishes a communication connection with the protocol identification submodule. It has a built-in electrical characteristic configuration parameter table: SPI protocol corresponds to a drive current of 20mA and an output impedance of 50Ω; I2C protocol corresponds to a drive current of 15mA and an output impedance of 100Ω; and UART protocol corresponds to a drive current of 10mA and an output impedance of 150Ω.

[0073] The data channel switching unit still uses ADG715, and the signal detection submodule and logic output submodule of the enable control signal generation module are consistent with those in Embodiment 1.

[0074] Work process:

[0075] When an external device inputs an I2C protocol data signal to the DI port, the signal detection submodule detects valid data and outputs a high-level detection result. The protocol recognition submodule then parses the data and outputs the I2C protocol identifier.

[0076] The timing parameter adjustment submodule receives the I2C protocol identifier, calls the corresponding timing parameters, and controls the logic output submodule to set the output delay of DOUT_OEA to 8ns to ensure that the enable signal switching timing matches the I2C protocol.

[0077] The electrical characteristic matching submodule receives the I2C protocol identifier, reads the corresponding configuration parameters, controls the MAX3232, and adjusts the drive current of the drive circuit corresponding to the DOUT port to 15mA and the output impedance to 100Ω.

[0078] The logic output submodule controls DIN_OEA to remain high and DOUT_OEA to switch to low. The data channel switching unit configures DIN as an input state and DOUT as an output state. The I2C protocol data of the DIN port is transmitted to the DOUT port through the path and output according to the matched electrical characteristics.

[0079] When an external device inputs an SPI protocol data signal to the DOUT port, the signal detection submodule detects valid data, the protocol identification submodule outputs the SPI protocol identifier, the timing parameter adjustment submodule calls a 5ns delay, the electrical characteristic matching submodule adjusts the DIN port drive circuit to 20mA drive current and 50Ω output impedance, the logic output submodule controls DOUT_OEA to remain high, and DIN_OEA switches to low, and the data is transmitted to the DIN output via DOUT.

[0080] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A circuit with switchable input and output ports, characterized in that, include: The first data port is DIN, and the second data port is DOUT. An enable control signal generation module has its input terminals electrically connected to the first data port and the second data port, respectively, and its output terminals output a first enable control signal (DIN_OEA) and a second enable control signal (DOUT_OEA). The enable control signal generation module is configured such that when an input data signal exists at the first data port, the level state of the second enable control signal switches, while the level state of the first enable control signal remains unchanged. When there is an input data signal at the second data port, the level state of the first enable control signal is switched, while the level state of the second enable control signal remains unchanged.

2. The circuit with switchable input and output ports according to claim 1, characterized in that, The enable control signal generation module includes: a signal detection submodule, whose input terminals are electrically connected to the first data port and the second data port respectively; and a logic output submodule, whose input terminal is electrically connected to the output terminal of the signal detection submodule, and whose output terminal outputs the first enable control signal and the second enable control signal; the signal detection submodule detects the input data signal of the first data port or the second data port and outputs the detection result; and the logic output submodule, based on the detection result, selectively controls the level state switching of the first enable control signal or the second enable control signal.

3. The circuit with switchable input and output ports according to claim 2, characterized in that, Also includes: The data channel switching unit has its control terminal electrically connected to the two output terminals of the logic output submodule to receive the first enable control signal and the second enable control signal, and its two ends of the data path are electrically connected to the first data port and the second data port, respectively. The data channel switching unit configures the first data port as an input state and the second data port as an output state, or configures the first data port as an output state and the second data port as an input state, based on the level states of the first enable control signal and the second enable control signal.

4. The circuit with switchable input and output ports according to claim 3, characterized in that, The enable control signal generation module further includes a conflict arbitration submodule, the input of which is electrically connected to the output of the signal detection submodule; When the signal detection submodule detects that input data signals exist simultaneously at the first data port and the second data port, the conflict arbitration submodule outputs an arbitration command to the logic output submodule, and the logic output submodule adjusts the level switching timing of the first enable control signal and the second enable control signal according to the arbitration command.

5. The circuit with switchable input and output ports according to claim 4, characterized in that, The signal detection submodule includes a protocol identification submodule. The input terminals of the protocol identification submodule are electrically connected to the first data port and the second data port, respectively. The output terminal of the protocol identification submodule is electrically connected to the input terminal of the conflict arbitration submodule. The protocol identification submodule performs protocol type parsing on the input data signal and outputs a protocol type identifier.

6. The circuit with switchable input and output ports according to claim 5, characterized in that, The conflict arbitration submodule has a built-in priority configuration table, which pre-stores the correspondence between different protocol types and priority levels; After receiving the protocol type identifier, the conflict arbitration submodule queries the priority configuration table to obtain the corresponding priority level, and generates the arbitration instruction based on the priority level.

7. The circuit with switchable input and output ports according to claim 5, characterized in that, The logic output submodule includes a timing parameter adjustment submodule, which establishes a communication connection with the protocol identification submodule; The timing parameter adjustment submodule has built-in timing parameters that correspond one-to-one with different protocol types. The timing parameter adjustment submodule calls the corresponding timing parameters according to the protocol type identifier output by the protocol identification submodule, and adjusts the output delay duration of the first enable control signal and / or the second enable control signal.

8. A circuit with switchable input and output ports according to claim 5, characterized in that, The data channel switching unit includes an electrical characteristic matching submodule, which establishes a communication connection with the protocol identification submodule. After receiving the protocol type identifier, the electrical characteristic matching submodule configures the structural parameters of the drive circuit corresponding to the first data port or the second data port in the output state.

9. A circuit with switchable input and output ports according to claim 4, characterized in that, It also includes a first data buffer unit and a second data buffer unit; the first data buffer unit is connected in series in the signal path between the first data port and the data channel switching unit, and the second data buffer unit is connected in series in the signal path between the second data port and the data channel switching unit; when the conflict arbitration submodule determines that the transmission priority of the first data port or the second data port is lower than that of another port, the first data buffer unit or the second data buffer unit corresponding to that port stores the input data signal.

10. A circuit with switchable input and output ports according to claim 9, characterized in that, The conflict arbitration submodule further includes a data feature extraction submodule, the input terminals of which are electrically connected to the first data port and the second data port, respectively; the data feature extraction submodule extracts a priority field of a preset format from the input data signal, and the conflict arbitration submodule combines the priority field with the detection result of the signal detection submodule to generate the arbitration instruction.

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