A TIADC channel mismatch calibration method and system based on a feedforward equalization algorithm

Abstract

The application provides a TIADC channel mismatch calibration method and system based on a feedforward equalization algorithm, relates to the technical field of data transmission, and comprises the following steps: obtaining a first sequence obtained by performing digital-to-analog conversion and downsampling processing on a preset PRBS sequence and a second sequence obtained by performing alignment and downsampling processing on an expected sequence of the preset PRBS sequence; performing correlation operation on the first sequence and the second sequence to obtain a correlation operation result, and adjusting the second sequence to be aligned with the first sequence based on the correlation operation result; the correlation operation result comprises a correlation maximum value and a correlation minimum value for measuring the correlation degree; performing equalization processing on the first sequence by using an FFE algorithm to obtain an error sequence between the first sequence after equalization processing and the second sequence after alignment adjustment, performing bias error calibration and gain error calibration based on an expected value and a standard deviation of the error sequence; and performing time mismatch error calibration based on time errors of channels.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and in particular to a TIADC channel mismatch calibration method and system based on a feedforward equalization algorithm. Background Technology

[0002] In today's era of explosive growth in digital information, the demand for data communication is increasing exponentially. Whether it's the massive data interaction between servers within cloud computing centers, the high-speed data transmission between 5G base stations and the core network, or the ever-growing demand for high-bandwidth services such as high-definition video and virtual reality between data centers and user terminals, all place increasingly stringent requirements on the transmission rate of optical communication systems. As a key component of optical communication systems, optical modules play a crucial role in converting electrical signals to optical signals, and improving their speed is a key factor in meeting the ever-increasing data transmission demands. However, with the continuous increase in optical module speed, unprecedented challenges are being placed on the performance of the various core components within the optical module, among which improving the acquisition rate of the analog-to-digital converter (ADC) is particularly critical. Faced with high acquisition rate requirements, single-chip ADCs are limited by chip manufacturing processes, power consumption, cost, and other factors, making it difficult to directly achieve sampling rates of tens of GSps. Therefore, achieving high-speed acquisition through parallel connection of multiple ADCs and time-interleaved (TI) has become the mainstream solution. The basic principle of TIADC technology is to sample the input signal sequentially by multiple sub-ADCs at certain time intervals, and then recombine these sampling results in time order to achieve equivalent high-speed sampling.

[0003] However, TIADC technology faces numerous challenges in practical applications, with channel mismatch error being one of the most prominent issues. Due to unavoidable manufacturing tolerances and asymmetry in printed circuit board layouts during the production of multiple ADC chips, coupled with the influence of factors such as ambient temperature variations during operation, mismatches can occur between the individual ADCs in terms of sampling time, sampling amplitude, and DC bias. This leads to channel mismatch error, significantly reducing the ADC's resolution and making it impossible to accurately reproduce the detailed information of the input signal, severely impacting the signal transmission quality of the optical communication system. Summary of the Invention

[0004] In view of this, the present invention proposes a TIADC channel mismatch calibration method and system based on a feedforward equalization algorithm.

[0005] The technical solution of this invention is implemented as follows: The first aspect of this invention provides a TIADC channel mismatch calibration method based on a feedforward equalization algorithm, comprising: A first sequence is obtained by converting a preset PRBS sequence to an analog-to-digital converter and downsampling, and a second sequence is obtained by aligning and downsampling the desired sequence of the preset PRBS sequence. A correlation operation is performed on the first sequence and the second sequence to obtain a correlation result, and the second sequence is adjusted to be aligned with the first sequence based on the correlation result; the correlation result includes a maximum correlation value and a minimum correlation value that measure the degree of correlation. The first sequence is equalized using the FFE algorithm to obtain the error sequence between the equalized first sequence and the second sequence after alignment adjustment. Bias error calibration and gain error calibration are performed based on the expected value and standard deviation of the error sequence, respectively. The equalized first sequence is resampled based on the number of channels and the baud rate of the first sequence to determine the time error of each channel. The time error is then used to perform time mismatch error calibration.

[0006] Based on the above technical solutions, preferably, the step of obtaining the first sequence obtained by digital-to-analog conversion and downsampling of the preset PRBS sequence and the second sequence obtained by alignment and downsampling of the desired sequence of the preset PRBS sequence includes: The preset PRBS sequence is converted from digital to analog to obtain an analog sequence; The simulated sequence is input into a multi-channel ADC for downsampling to obtain a first sequence; the first sequence includes multiple sub-sequences corresponding to the number of channels.

[0007] Based on the above technical solutions, preferably, the step of obtaining the first sequence obtained by digital-to-analog conversion and downsampling of the preset PRBS sequence and the second sequence obtained by alignment and downsampling of the desired sequence of the preset PRBS sequence includes: The desired sequence of the preset PRBS sequence is sampled in the digital domain and combined with multi-channel ADC downsampling processing to obtain a second sequence aligned with the sampling rate of each sub-channel; the second sequence includes multiple sub-sequences corresponding to the number of channels.

[0008] Based on the above technical solutions, preferably, adjusting the second sequence to align with the first sequence based on the relevant calculation results includes: If the absolute value of the maximum correlation value is greater than the absolute value of the minimum correlation value, the subsequences in the second sequence are delayed and adjusted based on the first position corresponding to the maximum correlation value. If the absolute value of the maximum correlation value is less than the absolute value of the minimum correlation value, each subsequence in the second sequence is inverted to obtain a reverse sequence, and each subsequence in the reverse sequence is delayed based on the second position corresponding to the minimum correlation value. If the absolute value of the maximum related value is equal to the absolute value of the minimum related value, discard the current first sequence and second sequence.

[0009] Based on the above technical solutions, preferably, the step of using the FFE algorithm to perform equalization processing on the first sequence to obtain the error sequence between the equalized first sequence and the aligned second sequence includes: The first sequence is balanced using the FFE algorithm to obtain the initial error sequence between the first sequence after equalization and the second sequence after alignment adjustment. The FFE coefficients are iteratively optimized using the least mean square algorithm until the initial error sequence is less than a preset threshold, thus obtaining the final error sequence.

[0010] Based on the above technical solutions, preferably, the bias error calibration and gain error calibration are performed based on the expected value and standard deviation of the error sequence, respectively; and the time error of each channel is determined by resampling the first sequence after equalization based on the number of channels and the baud rate of the first sequence, and the time mismatch error is calibrated using the time error, including: The bias value of the bias control register is adjusted according to the expected error sequence until the bias value is less than the first threshold, thus completing the bias error calibration. The gain value of the gain control register is adjusted based on the standard deviation of the error sequence until the gain value is less than the second threshold, thus completing the gain error calibration. The sampling time of the sampling time control register is adjusted based on the time error until the time error is less than the third threshold, thus completing the time mismatch error calibration.

[0011] Based on the above technical solution, preferably, after performing equalization processing on the first sequence using the FFE algorithm to obtain the error sequence between the equalized first sequence and the aligned second sequence, the method further includes: Obtain the FFE coefficients corresponding to each subsequence in the error sequence; Convolution is performed based on the FFE coefficients and the first sequence that has completed bias error calibration, gain error calibration and time mismatch error calibration to complete signal impairment compensation for each sub-channel.

[0012] More preferably, a second aspect of the present invention provides a TIADC channel mismatch calibration system based on a feedforward equalization algorithm, comprising: a sequence acquisition module, an operation alignment module, and an error calibration module; wherein, The sequence acquisition module is configured to acquire a first sequence obtained by digital-to-analog conversion and downsampling of a preset PRBS sequence, and a second sequence obtained by alignment and downsampling of a desired sequence of the preset PRBS sequence. The alignment module is configured to perform correlation operations on the first sequence and the second sequence to obtain correlation operation results, and adjust the second sequence to align with the first sequence based on the correlation operation results; the correlation operation results include a maximum correlation value and a minimum correlation value that measure the degree of correlation. The error calibration module is configured to perform equalization processing on the first sequence using the FFE algorithm, obtain the error sequence between the equalized first sequence and the second sequence after alignment adjustment, perform bias error calibration and gain error calibration based on the expected value and standard deviation of the error sequence, respectively; and resample the equalized first sequence based on the number of channels and the baud rate of the first sequence to determine the time error of each channel, and perform time mismatch error calibration using the time error.

[0013] More preferably, a third aspect of the present invention provides an electronic device, including a processor and a memory; the memory has a computer program stored thereon, wherein the computer program, when executed by the processor, implements the TIADC channel mismatch calibration method based on the feedforward equalization algorithm described in the first aspect.

[0014] More preferably, a fourth aspect of the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the TIADC channel mismatch calibration method based on the feedforward equalization algorithm described in the first aspect.

[0015] The TIADC channel mismatch calibration method and system based on the feedforward equalization algorithm of the present invention have the following advantages over the prior art: 1. Alignment is achieved by performing correlation operations on a first sequence obtained by digital-to-analog conversion and downsampling of a preset PRBS sequence, and a second sequence obtained by alignment and downsampling of the expected sequence of the preset PRBS sequence. The error sequences of the two are obtained. Bias error calibration is performed based on the expected value of the error sequences, and gain error calibration is performed based on the standard deviation of the error sequences. At the same time, time mismatch error calibration is performed using a determined time error. The root causes of distortion are systematically eliminated from aspects such as signal spectrum, effective components and waveform period, which significantly improves the fidelity of the signal.

[0016] 2. Based on the results of correlation calculations, the second sequence is aligned with the first sequence. If the absolute value of the maximum correlation value is greater than the absolute value of the minimum correlation value, it indicates that the first and second sequences have a stronger correlation at the first position corresponding to the maximum correlation value. In this case, delaying the adjustment of each subsequence in the second sequence based on this first position allows the second sequence to be more accurately aligned with the first sequence. If the absolute value of the maximum correlation value is less than the absolute value of the minimum correlation value, it indicates that the two sequences may have an inverse correlation, meaning that the second and first sequences exhibit inverse similarity at the second position corresponding to the minimum correlation value. In this case, inverting each subsequence in the second sequence yields an inverted sequence, and then delaying the adjustment of the inverted sequence based on the second position aligns the inverted sequence with the first sequence. This expands the applicability of sequence alignment and improves the comprehensiveness and accuracy of the alignment.

[0017] 3. Based on the expected value, standard deviation, and time error of the error sequence, the corresponding control registers are adjusted until a specific threshold condition is met to complete the calibration. Bias calibration eliminates the influence of DC bias, ensuring accurate zero-level signal; gain calibration guarantees accurate restoration of signal amplitude; and time mismatch calibration ensures the correctness of the signal on the time axis. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating a TIADC channel mismatch calibration method based on a feedforward equalization algorithm provided in an embodiment of the present invention; Figure 2 A typical architecture diagram of TIADC provided in the embodiments of the present invention; Figure 3 A schematic diagram of the FFE algorithm principle provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a TIADC channel mismatch calibration system based on a feedforward equalization algorithm provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] In some embodiments, such as Figure 1 As shown, Figure 1 This is a flowchart illustrating a TIADC channel mismatch calibration method based on a feedforward equalization algorithm provided by an embodiment of the present invention. The TIADC channel mismatch calibration method based on a feedforward equalization algorithm provided by the present invention includes: S110, Obtain the first sequence obtained by digital-to-analog conversion and downsampling of the preset PRBS sequence, and the second sequence obtained by alignment and downsampling of the desired sequence of the preset PRBS sequence.

[0022] In this embodiment, the preset PRBS sequence is a known pseudo-random binary sequence, which can be emitted by a digital-to-analog converter (DAC), such as a bit error rate tester. For example, the preset PRBS sequence is converted from digital to analog and then sampled by an ADC chip, with downsampling performed in the digital domain by the code to obtain the first sequence. The desired sequence of the preset PRBS sequence is the ideal form that the sequence should have. The aligned desired sequence is then downsampled to obtain the second sequence.

[0023] In some embodiments, obtaining a first sequence obtained by digital-to-analog conversion and downsampling of a preset PRBS sequence and a second sequence obtained by alignment and downsampling of a desired sequence of the preset PRBS sequence includes: The preset PRBS sequence is converted from digital to analog to obtain an analog sequence; The simulated sequence is input into a multi-channel ADC for downsampling to obtain the first sequence; the first sequence includes multiple sub-sequences corresponding to the number of channels.

[0024] Here, we assume that the preset PRBS sequence acquired by the ADC is as follows: , The data after analog-to-digital conversion is denoted as The software divides the data into N paths based on the number of sub-ADCs N, obtaining the first sequence. The data acquired by ADC1 can be processed through... It is obtained by downsampling by N times, while the data of ADCk can be used for... Discard the first k-1 data points and then perform downsampling by a factor of N to obtain the final data. Represent the sub-sequences received by sub-channels ADC1, ADC2, ..., ADCN as follows: .

[0025] In some embodiments, obtaining a first sequence obtained by digital-to-analog conversion and downsampling of a preset PRBS sequence and a second sequence obtained by alignment and downsampling of a desired sequence of the preset PRBS sequence includes: The desired sequence of the preset PRBS sequence is sampled in the digital domain and then downsampled using a multi-channel ADC to obtain a second sequence aligned with the sampling rate of each sub-channel; the second sequence includes multiple sub-sequences corresponding to the number of channels.

[0026] Here, will The corresponding known expected sequence Given a sampling rate Fs of the ADC sampled in the digital domain, the desired sequence aligned with the sampling rate is denoted as the second sequence. Among them, the subsequence corresponding to ADC1 can be obtained by... It is obtained by downsampling by a factor of N, and the subsequence corresponding to ADCk can be... After discarding the first k-1 data points, perform downsampling by a factor of N to obtain the desired sequence. Represent the expected sequences corresponding to sub-channel ADC1, sub-channel ADC2, ..., sub-channel ADCN as follows: .

[0027] S120, perform correlation operation on the first sequence and the second sequence to obtain the correlation operation result, and adjust the second sequence to align with the first sequence based on the correlation operation result; the correlation operation result includes the maximum and minimum correlation values ​​that measure the degree of correlation.

[0028] Correlation is based on the similarity of signals. The correlation between two sequences is maximized when they are perfectly aligned in time, and minimized when their time offset results in the lowest similarity. By using the location information of the maximum and minimum correlation values, the offset of the second sequence relative to the first sequence can be determined, and the second sequence can be adjusted to align with the first sequence.

[0029] In some embodiments, adjusting the second sequence to align it with the first sequence based on the results of relevant operations includes: If the absolute value of the maximum correlation value is greater than the absolute value of the minimum correlation value, the subsequences in the second sequence are delayed and adjusted based on the first position corresponding to the maximum correlation value. If the absolute value of the maximum correlation value is less than the absolute value of the minimum correlation value, the subsequences in the second sequence are inverted to obtain the reverse sequence, and the subsequences in the reverse sequence are delayed based on the second position corresponding to the minimum correlation value. If the absolute value of the maximum related value is equal to the absolute value of the minimum related value, discard the current first and second sequences.

[0030] In this embodiment, the sub-sequences received by each sub-channel ADC are respectively... and the corresponding expected sequence Synchronization is performed. Taking the i-th sequence as an example, the sequence is used. and Perform the relevant calculations and record the results as follows: ,Will The maximum and minimum values ​​are denoted as follows: and .like ,in, For absolute value operations, then Polarity remains unchanged, and find a way to make it constant. The position where the maximum value can be obtained By letting Synchronization of the desired sequence and the sampled sequence is completed after a cyclic delay of D units. If... ,but The entire sequence is inverted, and it can record the result. The position where the minimum value can be obtained By letting Synchronization of the desired sequence and the sampled sequence is completed after a cyclic delay of D units. If... ,but If the polarity cannot be determined, discard this set of data and use the next set of data for synchronization.

[0031] S130: The first sequence is equalized using the FFE algorithm to obtain the error sequence between the equalized first sequence and the second sequence after alignment adjustment. The bias error and gain error are calibrated based on the expected value and standard deviation of the error sequence, respectively. The equalized first sequence is resampled based on the number of channels and the baud rate of the first sequence to determine the time error of each channel. The time error is used to calibrate the time mismatch error.

[0032] In some embodiments, the first sequence is subjected to equalization processing using the FFE algorithm to obtain an error sequence between the equalized first sequence and the second sequence after alignment adjustment, including: The first sequence is balanced using the FFE algorithm to obtain the initial error sequence between the first sequence after equalization and the second sequence after alignment adjustment. The FFE coefficients are iteratively optimized using the least mean square algorithm until the initial error sequence is less than a preset threshold, thus obtaining the final error sequence.

[0033] In this embodiment, the FFE algorithm is used for each path of the sequence. Perform equalization processing. Taking the calibration of the i-th ADC channel as an example, let the equalizer length of the i-th channel be m, and its tap coefficient be... ,but It can be represented as During the equalization process, it is necessary to extract sampled sequences of the same length m. Then the data after the i-th path is balanced Use the balanced data. and the expected sequence after synchronization The difference is used to obtain the current error. .Right now The current error for each path is recorded as follows: .

[0034] Update FFE coefficients using the LMS algorithm According to the formula Update. Among them, This represents the k-th update parameter of w for the i-th channel. The length of each step is set by an appropriate value to balance accuracy and step speed. After optimizing the FFE coefficients for a preset number of rounds through the above steps, the final FFE coefficients for each ADC are obtained. and the complete error sequence for each path Here, the preset number of rounds can be flexibly set based on experience or accuracy requirements.

[0035] In some embodiments, bias error calibration and gain error calibration are performed based on the expected value and standard deviation of the error sequence, respectively; and the time error of each channel is determined by resampling the equalized first sequence based on the number of channels and the baud rate of the first sequence, and time mismatch error calibration is performed using the time error, including: The bias value of the bias control register is adjusted based on the expected error sequence until the bias value is less than the first threshold, thus completing the bias error calibration. The gain value of the gain control register is adjusted based on the standard deviation of the error sequence until the gain value is less than the second threshold, thus completing the gain error calibration. The sampling time of the sampling time control register is adjusted based on the time error until the time error is less than the third threshold, thus completing the time mismatch error calibration.

[0036] In this embodiment, the statistical error sequence Expectations Taking the calibration of the i-th sub-ADC as an example, if... This indicates that the bias size of the i-th sub-ADC is... At this point, the bias control register of the i-th sub-ADC is adjusted until... That's it. Here, LSB is the smallest level of ADC quantization, at which point the bias error is calibrated. Statistical error sequence. Standard deviation Taking the calibration of the i-th sub-ADC as an example, if... Too large, for example This indicates that the gain of the i-th sub-ADC is not 1. In this case, the gain control register of the i-th sub-ADC is modulated until... That's it. The gain error calibration is now complete.

[0037] The MMTED statistical method was used to perform time error statistics on the output data of FFE. The output data of FFE was denoted as follows. .Will Resampling to a sampling rate of B / N, where B is... The Buad rate, the resampled data is denoted as Their initial sampling times are respectively ,in, Let be the total sampling period of the ADC. Taking the time calibration of the i-th sub-ADC as an example, the formula is used. To calculate the time error of the i-th sub-ADC, where, Let i be the time error of the i-th sub-ADC. for The kth data point, for The k-th data point. When This indicates that the sampling in this channel was too late. This indicates that the sampling time of this channel is too early. At this point, adjust the sampling time control register of the i-th sub-ADC until... A value close to 0 is sufficient; at this point, the time mismatch error has been calibrated.

[0038] In some embodiments, after performing equalization processing on the first sequence using the FFE algorithm to obtain the error sequence between the equalized first sequence and the aligned second sequence, the method further includes: Obtain the FFE coefficients corresponding to each subsequence in the error sequence; Convolution is performed on the FFE coefficients and the first sequence that has completed bias error calibration, gain error calibration and time mismatch error calibration to complete signal impairment compensation for each sub-channel.

[0039] In this embodiment, the FFE coefficient is used. Channel impairment compensation is performed on each sub-ADC, through And the data received from each channel to complete the three types of mismatch error calibration By performing convolution, signal impairments for each sub-ADC can be compensated. The compensated data is denoted as... Then there is .in, This is the data after channel impairment compensation for the i-th sub-ADC. For convolution operations, Let be the final FFE coefficient of the i-th path ADC.

[0040] In an alternative embodiment, please refer to Figure 2 , Figure 2 This is a typical architecture diagram of a TIADC provided in an embodiment of the present invention. The TIADC architecture mainly consists of an analog input section, a clock distribution section, a digital control circuit, and multiple sub-ADC channels. Each sub-ADC channel includes a sample-and-hold (T / H) circuit, gain adjustment, offset calibration, and a sub-ADC module. In addition, there is an N-channel clock phase generation circuit used to provide alternating sampling clocks for each sub-ADC channel. The analog signal enters the system from the left and is distributed to N parallel sub-ADC channels. Each sub-ADC channel has a sample-and-hold circuit used to sample the input analog signal at a specific time point and hold the voltage value for subsequent analog-to-digital conversion. The gain adjustment module is used to adjust the gain of each sub-ADC channel to ensure that the output of each channel has consistent amplitude characteristics. This helps reduce errors caused by gain mismatch. The offset calibration module is used to eliminate DC offset errors in each sub-ADC channel, ensuring that the sub-ADC output is zero or close to zero at zero input. Each sub-ADC module is responsible for converting the analog signal output from the sample-and-hold circuit into a digital signal. The N-channel clock phase generation circuit is configured to generate N clock signals with different phases, each clock signal used to control the sample-and-hold circuit of one sub-ADC channel. The digital control circuit is responsible for coordinating the operation of each sub-ADC channel, including clock distribution, gain and offset calibration control, as well as synchronizing and integrating the outputs of each sub-ADC, ultimately outputting a high-speed serial data stream.

[0041] In an alternative embodiment, please refer to Figure 3 , Figure 3 A schematic diagram of the FFE algorithm principle provided in this embodiment of the invention; analog signal After ADC conversion, N-channel sub-ADC parallel data is generated. These data contain the raw signal information as well as errors introduced due to system imperfections. Synchronization is performed using a pseudo-random binary sequence (PRBS). The FFE module processes the input parallel data. Filtering is performed. By adjusting the filter coefficients, FFE can enhance or weaken certain components of the signal to compensate for distortion. The parallel data from the N-channel equalizer ADC after FFE processing is fed into an adder for summation to obtain the error sequence. The expected value of the statistical error power is then calculated. and standard deviation The error level of the quantified system is then calculated. By calculating the time error between each sub-ADC, the FFE coefficients are adjusted more precisely to compensate for the effects of clock phase mismatch. The feedback path is used for further error calculation and coefficient updates, forming a closed-loop control system that continuously optimizes the performance of FFE.

[0042] In some embodiments, please refer to Figure 4 , Figure 4 This is a schematic diagram of a TIADC channel mismatch calibration system based on a feedforward equalization algorithm, provided in an embodiment of the present invention. The present invention provides a TIADC channel mismatch calibration system 400 based on a feedforward equalization algorithm, comprising: a sequence acquisition module 410, an operation and alignment module 420, and an error calibration module 430; wherein,

[0043] The sequence acquisition module 410 is configured to acquire a first sequence obtained by digital-to-analog conversion and downsampling of a preset PRBS sequence, and a second sequence obtained by alignment and downsampling of a desired sequence of the preset PRBS sequence. The operation alignment module 420 is configured to perform correlation operations on the first sequence and the second sequence to obtain the correlation operation results, and adjust the second sequence to align with the first sequence based on the correlation operation results; the correlation operation results include the maximum and minimum correlation values ​​that measure the degree of correlation. The error calibration module 430 is configured to perform equalization processing on the first sequence using the FFE algorithm, obtain the error sequence between the equalized first sequence and the second sequence after alignment adjustment, perform bias error calibration and gain error calibration based on the expected value and standard deviation of the error sequence, and resample the equalized first sequence based on the number of channels and the baud rate of the first sequence to determine the time error of each channel, and perform time mismatch error calibration using the time error.

[0044] In some embodiments, the sequence acquisition module 410 is specifically configured as follows: The preset PRBS sequence is converted from digital to analog to obtain an analog sequence; The simulated sequence is input into a multi-channel ADC for downsampling to obtain the first sequence; the first sequence includes multiple sub-sequences corresponding to the number of channels.

[0045] In some embodiments, the sequence acquisition module 410 is specifically configured as follows: The desired sequence of the preset PRBS sequence is sampled in the digital domain and then downsampled using a multi-channel ADC to obtain a second sequence aligned with the sampling rate of each sub-channel; the second sequence includes multiple sub-sequences corresponding to the number of channels.

[0046] In some embodiments, the operation alignment module 420 is specifically configured as follows: If the absolute value of the maximum correlation value is greater than the absolute value of the minimum correlation value, the subsequences in the second sequence are delayed and adjusted based on the first position corresponding to the maximum correlation value. If the absolute value of the maximum correlation value is less than the absolute value of the minimum correlation value, the subsequences in the second sequence are inverted to obtain the reverse sequence, and the subsequences in the reverse sequence are delayed based on the second position corresponding to the minimum correlation value. If the absolute value of the maximum related value is equal to the absolute value of the minimum related value, discard the current first and second sequences.

[0047] In some embodiments, the error calibration module 430 is specifically configured as follows: The first sequence is balanced using the FFE algorithm to obtain the initial error sequence between the first sequence after equalization and the second sequence after alignment adjustment. The FFE coefficients are iteratively optimized using the least mean square algorithm until the initial error sequence is less than a preset threshold, thus obtaining the final error sequence.

[0048] In some embodiments, the basis error calibration module 430 is specifically configured as follows: The bias value of the bias control register is adjusted based on the expected error sequence until the bias value is less than the first threshold, thus completing the bias error calibration. The gain value of the gain control register is adjusted based on the standard deviation of the error sequence until the gain value is less than the second threshold, thus completing the gain error calibration. The sampling time of the sampling time control register is adjusted based on the time error until the time error is less than the third threshold, thus completing the time mismatch error calibration.

[0049] In some embodiments, the error calibration module 430 is further configured as follows: Obtain the FFE coefficients corresponding to each subsequence in the error sequence; Convolution is performed on the FFE coefficients and the first sequence that has completed bias error calibration, gain error calibration and time mismatch error calibration to complete signal impairment compensation for each sub-channel.

[0050] It should be noted that the TIADC channel mismatch calibration system based on feedforward equalization algorithm provided in this application embodiment and the TIADC channel mismatch calibration method based on feedforward equalization algorithm provided in this application embodiment are based on the same application concept. Therefore, the specific implementation of this embodiment can refer to the implementation of the aforementioned TIADC channel mismatch calibration method based on feedforward equalization algorithm, and the repeated parts will not be described again.

[0051] In some embodiments, please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 500 provided in this application includes a processor 510 and a memory 520; the memory 520 stores a computer program, wherein the computer program, when executed by the processor, implements the aforementioned TIADC channel mismatch calibration method based on a feedforward equalization algorithm.

[0052] Specifically, processor 510 may include, for example, a general-purpose microprocessor, an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. Processor 510 may also include onboard memory for caching purposes. Processor 510 may be a single processing unit or multiple processing units for performing different actions of the method flow according to embodiments of this application.

[0053] Memory 520 may be any medium capable of containing, storing, transmitting, propagating, or transmitting instructions. For example, memory 520 may include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, instruments, or propagation media. Specific examples of memory 520 include: magnetic storage devices such as magnetic tape or hard disk drives (HDDs); optical storage devices such as optical discs (CD-ROMs); and may also be random access memory (RAM) or flash memory; and / or wired / wireless communication links.

[0054] This application also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, this program implements the aforementioned TIADC channel mismatch calibration method based on a feedforward equalization algorithm. This computer-readable medium may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into that device / apparatus / system. The aforementioned computer-readable medium carries one or more programs, which, when executed, implement the method according to the embodiments of this application.

[0055] According to embodiments of this application, a computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wired, optical fiber, radio frequency signals, etc., or any suitable combination thereof.

[0056] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application. Therefore, the scope of this application should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A TIADC channel mismatch calibration method based on a feedforward equalization algorithm, characterized in that, include: A first sequence is obtained by converting a preset PRBS sequence to an analog-to-digital converter and downsampling, and a second sequence is obtained by aligning and downsampling the desired sequence of the preset PRBS sequence. Perform correlation operations on the first sequence and the second sequence to obtain the correlation operation result, and adjust the second sequence to align with the first sequence based on the correlation operation result; The correlation calculation results include the maximum and minimum correlation values, which measure the degree of correlation. The first sequence is equalized using the FFE algorithm to obtain the error sequence between the first sequence after equalization and the second sequence after alignment adjustment. Bias error calibration and gain error calibration are performed based on the expected value and standard deviation of the error sequence, respectively. Based on the number of channels and the baud rate of the first sequence, the first sequence after equalization is resampled to determine the time error of each channel, and the time error is used to calibrate the time mismatch error.

2. The TIADC channel mismatch calibration method based on feedforward equalization algorithm as described in claim 1, characterized in that, The process of obtaining a first sequence from a preset PRBS sequence through digital-to-analog conversion and downsampling, and a second sequence from a desired sequence of the preset PRBS sequence through alignment and downsampling, includes: The preset PRBS sequence is converted from digital to analog to obtain an analog sequence; The simulated sequence is input into a multi-channel ADC for downsampling to obtain a first sequence; the first sequence includes multiple sub-sequences corresponding to the number of channels.

3. The TIADC channel mismatch calibration method based on feedforward equalization algorithm as described in claim 1, characterized in that, The process of obtaining a first sequence from a preset PRBS sequence through digital-to-analog conversion and downsampling, and a second sequence from a desired sequence of the preset PRBS sequence through alignment and downsampling, includes: The desired sequence of the preset PRBS sequence is sampled in the digital domain and combined with multi-channel ADC downsampling processing to obtain a second sequence aligned with the sampling rate of each sub-channel; the second sequence includes multiple sub-sequences corresponding to the number of channels.

4. The TIADC channel mismatch calibration method based on feedforward equalization algorithm as described in claim 1, characterized in that, The step of adjusting the second sequence to align it with the first sequence based on the relevant calculation results includes: If the absolute value of the maximum correlation value is greater than the absolute value of the minimum correlation value, the subsequences in the second sequence are delayed and adjusted based on the first position corresponding to the maximum correlation value. If the absolute value of the maximum correlation value is less than the absolute value of the minimum correlation value, each subsequence in the second sequence is inverted to obtain a reverse sequence, and each subsequence in the reverse sequence is delayed based on the second position corresponding to the minimum correlation value. If the absolute value of the maximum related value is equal to the absolute value of the minimum related value, discard the current first sequence and second sequence.

5. The TIADC channel mismatch calibration method based on feedforward equalization algorithm as described in claim 1, characterized in that, The step of performing equalization processing on the first sequence using the FFE algorithm to obtain the error sequence between the equalized first sequence and the aligned second sequence includes: The first sequence is balanced using the FFE algorithm to obtain the initial error sequence between the first sequence after equalization and the second sequence after alignment adjustment. The FFE coefficients are iteratively optimized using the least mean square algorithm until the initial error sequence is less than a preset threshold, thus obtaining the final error sequence.

6. The TIADC channel mismatch calibration method based on feedforward equalization algorithm as described in claim 1, characterized in that, The bias error calibration and gain error calibration are performed based on the expected value and standard deviation of the error sequence, respectively. Based on the number of channels and the baud rate of the first sequence, the equalized first sequence is resampled to determine the time error of each channel. The time error is then used to perform time mismatch error calibration, including: The bias value of the bias control register is adjusted based on the expected value of the error sequence until the bias value is less than the first threshold, thus completing the bias error calibration. The gain value of the gain control register is adjusted based on the standard deviation of the error sequence until the gain value is less than the second threshold, thus completing the gain error calibration. The sampling time of the sampling time control register is adjusted based on the time error until the time error is less than the third threshold, thus completing the time mismatch error calibration.

7. The TIADC channel mismatch calibration method based on feedforward equalization algorithm as described in claim 1, characterized in that, After performing equalization processing on the first sequence using the FFE algorithm to obtain the error sequence between the equalized first sequence and the aligned second sequence, the process further includes: Obtain the FFE coefficients corresponding to each subsequence in the error sequence; Convolution is performed based on the FFE coefficients and the first sequence that has completed bias error calibration, gain error calibration and time mismatch error calibration to complete signal impairment compensation for each sub-channel.

8. A TIADC channel mismatch calibration system based on a feedforward equalization algorithm, characterized in that, include: The module comprises a sequence acquisition module, an operation and alignment module, and an error calibration module; among which, The sequence acquisition module is configured to acquire a first sequence obtained by digital-to-analog conversion and downsampling of a preset PRBS sequence, and a second sequence obtained by alignment and downsampling of a desired sequence of the preset PRBS sequence. The alignment module is configured to perform correlation operations on the first sequence and the second sequence to obtain correlation operation results, and adjust the second sequence to align with the first sequence based on the correlation operation results; the correlation operation results include a maximum correlation value and a minimum correlation value that measure the degree of correlation. The error calibration module is configured to perform equalization processing on the first sequence using the FFE algorithm, obtain the error sequence between the equalized first sequence and the second sequence after alignment adjustment, perform bias error calibration and gain error calibration based on the expected value and standard deviation of the error sequence, respectively; and resample the equalized first sequence based on the number of channels and the baud rate of the first sequence to determine the time error of each channel, and perform time mismatch error calibration using the time error.

9. An electronic device comprising a processor and a memory; said memory storing a computer program, wherein, When the computer program is executed by the processor, it implements the TIADC channel mismatch calibration method based on the feedforward equalization algorithm as described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium, characterized in that, It stores a computer program, wherein when the computer program is executed by a processor, it implements the TIADC channel mismatch calibration method based on the feedforward equalization algorithm as described in any one of claims 1 to 7.

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