Intelligent network card abnormal traffic real-time monitoring and defense method based on lightweight model

Abstract

The application discloses a kind of intelligent network card abnormal flow real-time monitoring and defense method and system based on light model, benchmark abnormal detection model is executed to forward load sensing compression, each layer of model is divided into micro-computing block according to computing amount, and the execution time of each micro-computing block does not exceed the preset quantile value of packet processing gap duration distribution, using hardware flow table matching engine, traffic is pre-screened into three levels of trusted release, high-risk block and detection, maintain inference state context for detection data stream, and execute micro-inference in packet processing gap stage by stage, trigger graded defense action according to abnormal probability score, drift detection is scheduled as low-priority microtask in gap and triggers incremental update when divergence value is out of limit.The application realizes abnormal flow real-time detection and active defense under the premise of guaranteeing line-speed forwarding.

Description

Technical Field

[0001] This application relates to the fields of network security and artificial intelligence technology, specifically to a method for real-time monitoring and defense of abnormal traffic of smart network interface cards based on a lightweight model. Background Technology

[0002] With the continuous expansion of data centers and high-speed networks, the challenges of anomaly traffic detection are becoming increasingly severe. Traditional anomaly traffic detection solutions are typically deployed on the host side or dedicated security devices, with the server CPU or GPU performing the inference calculations for the detection model. In this architecture, all network traffic must first be transmitted to the host memory via the network interface before being analyzed and processed by the host-side detection engine, which not only increases detection latency but also places a significant computational burden on the host CPU. Smart network interface cards (NICs), due to their embedded on-chip processors, are increasingly being used to directly perform traffic analysis and anomaly detection functions on the network data plane, thereby reducing the processing pressure on the host side and lowering detection latency. Currently, research has explored deploying lightweight models such as shallow multilayer perceptrons, quantized neural networks, or decision trees on smart NICs to achieve intrusion detection or traffic classification, and has achieved initial success.

[0003] However, existing smart NIC anomaly detection schemes have fundamental shortcomings in the design of model compression strategies. Current model compression technologies for embedded hardware or edge devices, including structured pruning and mixed-precision quantization, aim to reduce the overall computational load or storage footprint of the model. Their compression strategies are only adapted to the computing power configuration and instruction set characteristics of the target chip. These compression methods implicitly assume that inference computation is the only or primary task of the target processor, treating the inference process as a continuously executable overall computational flow. This assumption holds true for general-purpose servers, edge computing devices, and even embedded GPUs, but it does not hold true for the on-chip processor of smart NICs. This is because the on-chip processing core of a smart NIC simultaneously undertakes real-time data plane tasks such as packet transmission and reception, flow table matching, and forwarding decisions. Model inference computation must share the same processing core, cache levels, and memory bandwidth as these packet processing tasks. Existing compression methods do not consider the frequent interruptions to inference execution caused by packet processing tasks. This results in unpredictable latency jitter in the compressed model during actual operation due to repeated interruptions and recovery, and the effective inference throughput is far lower than the theoretical value of offline benchmark tests.

[0004] In high-speed network scenarios, data packets arrive continuously at microsecond or even sub-microsecond intervals, requiring on-chip processors to process each packet within extremely tight time windows. When inference computation for anomaly detection models is inserted into the packet processing pipeline, direct resource contention arises between inference and packet forwarding tasks. During traffic bursts, intensive packet processing tasks frequently preempt processing cores, causing repeated interruptions to inference computation; conversely, during periods of intensive inference computation, packet forwarding is delayed, leading to receive queue overflow and packet loss. This resource contention between inference and forwarding fluctuates continuously with the dynamic changes in real-time traffic load. Existing solutions lack the ability to finely schedule inference execution on the time scale of the packet processing pipeline, failing to enable coordinated coexistence between inference and packet forwarding tasks in the time dimension.

[0005] Furthermore, existing anomaly detection solutions for smart NICs typically send all incoming traffic indiscriminately to the model inference stage, failing to fully utilize the smart NIC's built-in hardware flow table matching engine for pre-classification of traffic. In real-world network environments, a large amount of traffic belongs to known safe or known malicious types, which can be directly determined through flow table rules without consuming inference resources. However, existing solutions fail to establish a collaborative mechanism between flow table pre-screening and model inference, causing the inference module to bear unnecessary load pressure and further exacerbating resource contention between inference and forwarding.

[0006] The distribution characteristics of network traffic also change over time, a phenomenon known as concept drift. Existing concept drift detection and incremental model learning schemes all assume that the model update process can exclusively or preferentially utilize computing resources. However, on smart NICs, the statistical calculations for drift detection and the parameter adjustments for incremental updates also compete with packet processing for limited on-chip computing resources. Currently, there is no technical solution to address the problem of drift monitoring and online model updates under the resource constraints of smart NICs. This results in the continuous degradation of detection performance of deployed models after traffic distribution shifts, while failing to achieve adaptive adjustments without interrupting data plane forwarding services. Summary of the Invention

[0007] To address the technical problem of dynamic resource contention between anomaly detection model inference computation and data breading processing in existing smart network interface cards (NICs), this invention provides a method and system for real-time monitoring and defense of abnormal traffic on smart NICs based on a lightweight model. By decomposing model inference computation into a sequence of micro-inference stages adapted to the timing of packet processing pipelines, and combining a forwarding load-aware model compression strategy, a traffic pre-screening mechanism coordinated with hardware flow tables, and a drift monitoring and incremental update mechanism under resource budget constraints, real-time detection and proactive defense of abnormal traffic on the NIC side are achieved.

[0008] One aspect of the present invention provides a method for real-time monitoring and defense of abnormal traffic of intelligent network interface cards based on a lightweight model, comprising the following steps: Step S1: Perform forwarding load-aware compression on the benchmark anomaly detection model. Divide each layer of the model into micro-computation blocks according to computational load. The execution time of each micro-computation block does not exceed a preset quantile value of the packet processing interval duration distribution on the smart network card processor. Specifically, firstly, a benchmark deep neural network model for anomaly traffic detection is trained in an offline environment. The benchmark model adopts a multi-layer architecture including a feature extraction layer, a temporal modeling layer, and an anomaly scoring layer. The feature extraction layer is used to extract flow-level feature vectors from the header fields and payload statistical summaries of data packets. The temporal modeling layer is used to capture the temporal correlation patterns between consecutive data packets. The anomaly scoring layer is used to output the anomaly probability score of the current flow. Further, perform forwarding load-aware compression processing on the benchmark model for the smart network card processor. In the objective function of compression optimization, a forwarding interruption tolerance constraint term is introduced. The forwarding interruption tolerance constraint term requires that the single execution time of each micro-computation block of the model does not exceed a preset quantile value of the packet processing interval duration distribution. On the target on-chip processor of the smart network interface card, the timing characteristic spectrum of the packet processing pipeline under different traffic load conditions is pre-collected. The timing characteristic spectrum includes the duration distribution of available computation gaps between adjacent packet processing, the frequency and duration distribution of packet processing interruptions, and the switching mode of cache resident state. Based on the timing characteristic spectrum, each layer of the model is divided into several micro-computation blocks according to the amount of computation and memory access. The single execution time of each micro-computation block is constrained to not exceed a preset percentile value of the duration distribution of available computation gaps, preferably the 25th percentile value, thereby ensuring that each micro-computation block can be fully executed within the vast majority of packet processing gaps (hereinafter referred to as packet gaps).

[0009] Further, in step S1, the forwarding load-aware compression includes gap-adaptive structured pruning. Guided by the requirement that the execution time of each layer's micro-computation blocks meets the gap constraints, the convolutional kernels or fully connected weight matrices are structurally pruned row by row or column. Priority is given to removing structural units that, after pruning, reduce the execution time of the corresponding micro-computation block to below a preset quantile and have the least impact on detection accuracy. After each round of pruning, the execution time of the micro-computation blocks is measured on the target processor to verify the gap constraints. Specifically, the gap-adaptive structured pruning is performed iteratively. Based on the pruning evaluation criteria, priority is given to removing structural units that, after pruning, reduce the execution time of the corresponding micro-computation block to below a preset quantile and have the least impact on the model's detection accuracy. After each round of pruning, the execution time of each micro-computation block is measured on the target processor to verify whether it meets the gap constraints, and the degree of detection accuracy degradation is evaluated on the validation set until all micro-computation blocks meet the constraints and the accuracy degradation is within a preset tolerance range.

[0010] Furthermore, step S1 also includes performing cache-aligned mixed-precision quantization on the pruned model. The quantization bit width is allocated based on the ratio of the amount of weight data accessed by each micro-computation block to the capacity of the on-chip processor's final-level cache. Quantization is performed when the weight data of a micro-computation block can completely reside in the final-level cache at the corresponding bit width. Specifically, the quantization strategy assigns different quantization bit widths to different micro-computation blocks, thereby avoiding additional latency caused by cache misses during micro-computation block execution. Preferably, micro-computation blocks closer to the input side of the feature extraction layer use lower quantization bit widths to reduce memory access, while micro-computation blocks closer to the output side of the anomaly scoring layer retain higher quantization bit widths to maintain scoring accuracy.

[0011] Step S2 involves using the smart network interface card (NIC) hardware flow table matching engine to pre-screen input traffic into three levels: trusted allow, high-risk block, and pending detection. Specifically, the pre-defined matching rules in the hardware flow table are compiled based on historical traffic analysis results and known threat intelligence. The first level is the trusted allow level, matching traffic from a pre-defined set of trusted source addresses, established connection heartbeat packets, or traffic conforming to known security protocol characteristics. This type of traffic directly enters the forwarding path without entering the model inference stage. The second level is the high-risk block level, matching traffic with known malicious signature features, blacklisted addresses, or severely abnormal protocol formats. This type of traffic directly triggers blocking actions and reports an alarm, also without consuming model inference resources. The third level is the pending detection level, where traffic not matched by the previous two levels is marked as pending detection and enters the model inference queue to await anomaly scoring.

[0012] Furthermore, step S2 establishes a dynamic threshold adjustment mechanism. When the backlog depth of the model inference queue exceeds a preset upper limit, the matching leniency of the trusted release level is increased and the trigger threshold of the high-risk blocking level is decreased to reduce the amount of traffic entering the inference queue. When the backlog depth of the inference queue returns to a normal level, the original threshold setting is restored. Specifically, the dynamic threshold adjustment mechanism adaptively adjusts the classification boundary of traffic pre-screening by monitoring the inference queue depth in real time, preventing inference backlog from further encroaching on packet processing resources.

[0013] Step S3 involves maintaining an inference state context for each data stream to be detected. The inference process of the compressed model is decomposed into an ordered sequence of micro-inference stages. In the main loop of the packet processing pipeline, when the remaining time interval after forwarding the current packet is greater than the sum of the execution time of the micro-computation block and the safety margin, the highest priority data stream to be detected is retrieved from the inference queue to execute its next micro-inference stage. After updating the inference state context, the process returns to the main loop of packet processing. Specifically, the complete inference process of the lightweight model obtained in step S1 is decomposed into an ordered sequence of micro-inference stages. Each micro-inference stage corresponds to the execution of a micro-computation block. An inference state context is maintained for each data stream to be detected in the dedicated memory area of ​​the on-chip processor. Inference scheduling logic is embedded in the main loop of the packet processing pipeline. After the on-chip processor completes the forwarding of the current data packet, the inference scheduler checks the remaining time interval until the next data packet is expected to arrive. If the remaining time interval is greater than the execution time of a micro-computation block plus a safety margin, the inference state context of the highest priority stream to be detected is retrieved from the inference queue, and the next micro-inference stage of that stream is executed. After execution, the updated inference state context is written back to memory, and then the main loop of packet processing is returned. If the remaining time interval is insufficient, the inference operation is not performed, and the process directly proceeds to the next round of packet reception processing.

[0014] Further, in step S3, the inference state context includes the currently completed micro-inference stage number, the activation value cache of each intermediate layer, and the cumulative inference time count. The inference state context is stored in a cache line-aligned manner. The remaining time interval is estimated based on the exponentially weighted moving average of the current packet reception queue depth and the recent packet arrival interval. Specifically, storing the inference state context in a cache line-aligned manner ensures that context saving and restoring operations do not generate additional cache miss overhead, thus improving context switching efficiency.

[0015] Furthermore, step S3 also includes an inference timeout management mechanism, which sets a maximum allowable completion time limit for the inference process of each data stream to be detected. The time limit is measured in units of the number of data packets that the data stream has passed since entering the inference queue. If the inference process fails to complete all micro-inference stages within the maximum time limit, the handling strategy for the data stream is upgraded to conservative blocking or rate limiting. Specifically, the inference timeout management mechanism ensures that potential threat traffic does not pass uncontrollably due to incomplete inference, and adopts a conservative security handling strategy for the data stream after the timeout.

[0016] Further, in step S3, the inference scheduler performs adaptive phase merging based on the real-time monitored packet processing gap duration. When the gap is ample, adjacent micro-inference phases are merged into consecutive execution batches, and the execution time after merging does not exceed a preset proportion of the gap margin. Before the current packet processing is completed, the inference state context of the next pending flow in the inference queue is preloaded into the cache according to its identifier. Specifically, the adaptive phase merging mechanism enables full utilization of idle computing resources to accelerate the inference progress when the gap is long during periods of low traffic. The preloading mechanism reduces the cache cold start overhead when the inference phase starts by loading the inference state context of the next pending flow into the cache in advance at the end of the packet processing stage.

[0017] Furthermore, in step S3, the inference queue adopts a priority sorting strategy based on risk weights. The risk weights comprehensively consider the initial risk assessment value of the data stream when it was assigned to the detection level in step S2 and the length of time the data stream has been waiting in the inference queue. Specifically, data streams with longer waiting times are assigned higher priorities to prevent low-risk traffic from blocking the inference queue for extended periods, ensuring that all traffic to be detected can obtain inference resources within a reasonable timeframe.

[0018] Step S4: Based on the comparison between the anomaly probability score output after completing all micro-inference stages and the multi-level thresholds, trigger tiered defense actions such as allowing, rate limiting, or blocking. Specifically, after a data flow completes all micro-inference stages, the anomaly scoring layer outputs the anomaly probability score for that flow. When the anomaly score is lower than the normal threshold, the flow is marked as safe, and the trusted allow flag of the corresponding entry in the hardware flow table is updated. Subsequent data packets belonging to this flow directly take the fast forwarding path. When the anomaly score is between the normal threshold and the alarm threshold, bandwidth rate limiting is performed on the flow, restricting its forwarding rate to within a preset safe bandwidth, and an alarm notification is sent to the host-side security management module. When the anomaly score exceeds the alarm threshold, session blocking is immediately performed on the flow, discarding subsequent data packets of the flow and reporting the blocking event to the security management module. Furthermore, the multi-level thresholds can be configured and adjusted according to the requirements of the network management policy, and the security management module can dynamically modify the threshold parameters and defense policies on the smart network card by issuing commands.

[0019] Step S5 involves scheduling drift detection computation as a low-priority microtask during packet processing intervals. When the distribution divergence value exceeds the drift alarm threshold, an incremental model update is triggered. Specifically, in the micro-inference staged interleaved scheduling framework, drift detection computation is included as a special low-priority microtask in the scheduling. During packet processing intervals, when the inference queue is empty and the remaining interval time meets the execution conditions, the inference scheduler executes one round of drift detection microtasks.

[0020] Further, in step S5, during the hardware flow table matching process in step S2, incremental accumulation of online mean and online variance is performed synchronously on the flow-level feature vectors; the drift detection micro-task uses a simplified Mahalanobis distance metric based on online mean and online variance to calculate the divergence value between the current statistic and the reference distribution; when the divergence value continuously exceeds the drift alarm threshold and reaches the preset confirmation window length, an incremental update is triggered, performed only on the weight parameters of the anomaly scoring layer. The incremental update is decomposed into a sequence of micro-tasks and executed with the lowest priority during packet processing intervals. After the update is completed, the parameters are switched atomically. Specifically, the incremental accumulation uses an online calculation method to complete the update during the flow table matching process of each data packet, without generating additional independent computational overhead. The incremental update only updates the weight parameters in the anomaly scoring layer, keeping the parameters of the feature extraction layer and the temporal modeling layer unchanged, so as to keep the computational load required for the update within a minimum range. During the execution of the incremental update, the anomaly detection continues to run using the model parameters before the update. Only after all update micro-tasks have been executed and the new parameters have passed verification, the system switches to the updated parameters atomically, ensuring the continuity of the detection service.

[0021] Another aspect of the present invention provides a real-time monitoring and defense system for abnormal traffic of smart network interface cards (NICs) based on a lightweight model, comprising: a model compression module, used to perform forwarding load-aware compression on a benchmark anomaly detection model, dividing each layer of the model into micro-computation blocks according to computational load, wherein the execution time of each micro-computation block does not exceed a preset quantile value of the duration distribution of packet processing intervals on the smart NIC processor; a traffic pre-screening module, used to pre-screen input traffic into three levels—trustworthy passage, high-risk blocking, and pending detection—using the smart NIC hardware flow table matching engine; and a micro-inference scheduling module, used to maintain an inference state context for each pending data stream, decomposing the inference process of the compressed model into ordered micro-inferences. In the packet processing pipeline's main loop, when the remaining time interval after forwarding the current packet is greater than the sum of the execution time and safety margin of the micro-computation block, the highest-priority data stream to be detected is retrieved from the inference queue to execute its next micro-inference stage. After updating the inference state context, it returns to the packet processing main loop. A tiered defense module is used to trigger tiered defense actions such as allowing, rate limiting, or blocking based on the comparison between the anomaly probability score output after completing all micro-inference stages and multi-level thresholds. A drift monitoring module is used to schedule drift detection computation as a low-priority micro-task during packet processing intervals. When the distribution divergence value exceeds the drift alarm threshold, it triggers incremental model updates. Specifically, the forwarding load-aware compression performed by the model compression module includes gap-adaptive structured pruning and cache-aligned hybrid precision quantization. The traffic pre-screening module sets a dynamic threshold adjustment mechanism to adaptively adjust the number of traffic entering the inference queue. The inference state context maintained by the micro-inference scheduling module is stored in a cache line-aligned manner and scheduled using a risk-weight-based priority sorting strategy. The drift monitoring module synchronously performs incremental accumulation of statistics during hardware flow table matching.

[0022] The technical solution of this invention eliminates the temporal coupling conflict between inference computation and packet forwarding processing by decomposing the model inference process into a sequence of micro-inference stages adapted to the timing of packet processing gaps, thereby reducing the model compression strategy. The forwarding load-aware compression strategy compresses the model based on the duration distribution of packet processing gaps, ensuring that each micro-computation block can be fully executed within the packet gap, fundamentally solving the problem that existing hardware-aware compression methods do not consider the coexisting architecture characteristics of intelligent network interface cards (NICs) computation and forwarding. A three-level traffic pre-screening mechanism with hardware flow table collaboration diverts traffic by risk level before inference, concentrating limited inference resources on suspicious traffic that truly requires deep detection, and forming a closed-loop control of inference load with dynamic threshold adjustment. Micro-inference staged interleaving scheduling executes inference computation stage by stage according to gap availability in the main packet processing loop, combining cache line-aligned storage of the inference state context, adaptive stage merging, and preloading mechanisms to maximize inference throughput while ensuring line-rate packet forwarding. Tiered defense actions implement differentiated handling based on anomaly scores, and a conservative safety fallback strategy is provided for traffic that has not completed inference through an inference timeout management mechanism. The traffic distribution drift monitoring and model incremental update mechanism under resource budget constraints utilizes the byproducts of hardware flow table matching to perform online statistical accumulation and drift determination. The incremental update process is executed in the form of micro-tasks in the lowest priority gaps and the continuity of detection services is ensured by switching atomic parameters, enabling the model to continuously adapt to changes in traffic distribution without interrupting data surface functionality. Attached Figure Description

[0023] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0024] Figure 1 This is an overall flowchart of the method for real-time monitoring and defense of abnormal traffic of smart network interface cards based on a lightweight model provided in the embodiments of the present invention.

[0025] Figure 2 This is a timing diagram of micro-inference staged interleaving scheduling in a packet processing pipeline provided by an embodiment of the present invention.

[0026] Figure 3 This is a flowchart of the forwarding load awareness model compression process provided in an embodiment of the present invention.

[0027] Figure 4 This is a structural block diagram of the intelligent network interface card abnormal traffic real-time monitoring and defense system based on a lightweight model provided in an embodiment of the present invention.

[0028] Figure 5 This is a diagram showing the adaptation relationship between the execution time of the microcomputation block and the duration of the packet processing gap in this invention.

[0029] Figure 6This is the state transition diagram for the flow distribution drift monitoring and model incremental update of this invention.

[0030] Figure 7 This is a diagram showing the multi-core resource allocation and memory region spatial layout of the on-chip processor of this invention.

[0031] Figure 8 This is a deployment scenario diagram for abnormal traffic detection in the data center border gateway of this invention.

[0032] Figure 9 This is a comparison chart of multiple schemes for anomaly detection performance of the present invention.

[0033] Figure 10 This is a thermal diagram showing the ablation experimental effect of the key technical component of this invention.

[0034] Figure 11 This is a graph showing the changes in inference latency and throughput under different traffic load conditions according to the present invention. Detailed Implementation

[0035] To make the objectives and technical solutions of this invention clearer, the embodiments of this invention will be further described in detail below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of this invention and should not be construed as limiting the scope of protection of this invention.

[0036] Example 1 like Figure 1 As shown, this embodiment provides a method for real-time monitoring and defense of abnormal traffic of smart network interface cards (NICs) based on a lightweight model. It is applied to a smart NIC platform equipped with an on-chip processor. The on-chip processor is a multi-core ARM architecture processor with no fewer than 8 processing cores, a final-level cache capacity of 1MB to 4MB, and a clock speed range of 1.5GHz to 2.5GHz. The smart NIC connects to a host server via a PCIe interface and has a built-in hardware flow table matching engine and a programmable data plane forwarding pipeline. The method includes the following steps.

[0037] Step 1: Construct a lightweight anomaly detection model that is aware of forwarding load.

[0038] A benchmark deep neural network model for anomaly traffic detection was trained in an offline environment. The benchmark model employs a multi-layer architecture comprising a feature extraction layer, a temporal modeling layer, and an anomaly scoring layer. The feature extraction layer consists of three one-dimensional convolutional networks with kernel widths of 3, 5, and 7, and channel numbers of 64, 128, and 64 respectively. It uses ReLU activation and batch normalization to extract flow-level feature vectors from packet header fields and payload statistical summaries. The header fields include source and destination IP address hashes, port numbers, protocol types, packet lengths, TTL values, and TCP flags. The payload statistical summaries include the entropy of the payload byte distribution, the frequency characteristics of the first 64 bytes of n-grams, and the payload length variance. The temporal modeling layer uses a two-layer gated recurrent unit structure with a hidden state dimension of 128. It is used to model the feature vector sequence of consecutive packets in the same data stream, capturing the temporal correlation patterns of the traffic. The anomaly scoring layer is a classification head containing two fully connected layers with a hidden dimension of 64 and an output dimension of 1. It outputs the anomaly probability score of the current stream through a sigmoid activation function.

[0039] The training data for the baseline model comes from full traffic mirror data collected continuously for no less than 30 days in the target network environment, with a data scale of no less than 5 million data flow records. The training data annotation adopts a semi-automatic method. First, an existing rule-based intrusion detection system is used for initial screening and annotation of traffic, and then security analysts manually verify and confirm high-confidence anomaly samples and boundary samples. The ratio of the training set, validation set, and test set is 7:1.5:1.5, and the partitioning is performed in chronological order to avoid data leakage. In the data preprocessing stage, zero-mean unit variance standardization is performed on numerical features, one-hot encoding is performed on discrete features, and missing fields are filled with zero values. The training process uses the AdamW optimizer, with an initial learning rate of 2.3 x 10⁻⁴, and a cosine annealing decay strategy is used to decay the learning rate to one percent of the initial value over 150 training epochs. The batch size is set to 128, and the weight decay coefficient is 1.5 x 10⁻⁴. The loss function uses weighted binary cross-entropy loss, with the positive-to-negative sample weight ratio automatically calculated based on the reciprocal of the ratio of normal to abnormal traffic samples in the training set. An early stopping mechanism is implemented during training: training is terminated and the optimal checkpoint is restored if the F1 score on the validation set fails to improve for 15 consecutive training epochs. Training hardware utilizes a server equipped with a single GPU, and training time is approximately 4 to 8 hours. The benchmark model's evaluation metrics on the test set are anomaly detection recall of at least 97.5%, a false positive rate of at least 1.2%, and an F1 score of at least 0.96.

[0040] like Figure 3As shown, forwarding load-aware compression processing for the on-chip processor of the smart network card is performed on the benchmark model. In the preparation phase before compression, a traffic replay tool is deployed on the target on-chip processor to collect the timing characteristic spectrum of the packet processing pipeline using real traffic replay at different rates. The collection of the timing characteristic spectrum covers five typical load scenarios, including low-speed steady-state traffic, medium-speed steady-state traffic, high-speed steady-state traffic, burst traffic, and mixed protocol traffic, with a collection duration of no less than 10 minutes for each scenario. The collected timing characteristic spectrum includes the duration distribution of available computation gaps between adjacent packet processing, the frequency and duration distribution of packet processing interruptions, and the resident state switching modes of the on-chip processor's various levels of cache. In the high-speed steady-state traffic scenario, the duration distribution of available computation gaps exhibits a long-tail characteristic, with its 25th percentile value falling within the range of 0.8 microseconds to 1.5 microseconds. This percentile value is selected as the upper limit constraint for the execution time of micro-computation blocks.

[0041] Based on the aforementioned temporal feature spectrum, each layer of the baseline model is divided into several micro-computation blocks according to computational and memory access requirements. The division principle is that the execution time of each micro-computation block does not exceed the 25th percentile of the available computation gap duration distribution. For each convolutional layer of the feature extraction layer, it is divided into 2 to 4 micro-computation blocks according to the output channel dimension; for the gated recurrent unit of the temporal modeling layer, each update is divided into two micro-computation blocks: gate computation and state update, according to the time step dimension; for the fully connected layer of the anomaly scoring layer, due to the small number of parameters, the entire layer is treated as a single micro-computation block. The divided baseline model contains a total of 12 to 18 micro-computation blocks.

[0042] like Figure 5 As shown, taking a 10Gbps medium-speed steady-state traffic scenario as an example, the adaptation relationship between the execution time of microcomputation blocks and packet processing gaps is illustrated. The curves in the figure represent the probability density distribution of the duration of packet processing gaps, exhibiting a clear long-tail characteristic. Three key quantiles are marked in the figure: P25=2.8us, P50=5.6us, and P75=12.3us. Above the distribution curves, the execution time of each microcomputation block is marked with a horizontal color band, including FE-1 (1.2us), FE-2 (1.4us), and FE-3 (2.1us) in the feature extraction stage; TM-1 (1.8us), TM-2 (1.9us), and TM-3 (1.7us) in the time series modeling stage; and AS-1 (0.8us) and AS-2 (0.5us) in the anomaly scoring stage.

[0043] The gap-adaptive structured pruning uses the P25 quantile as a constraint threshold to ensure that the execution time of each microcomputation block does not exceed this threshold, thereby guaranteeing that a microcomputation block can be executed in at least 75% of the packet gaps. The highlighted areas in the figure represent the executable regions of the microcomputation blocks; all microcomputation blocks are located to the left of the constraint threshold, satisfying the gap-adaptive requirements.

[0044] Sub-step 1: Perform gap-adaptive structured pruning. Guided by ensuring the execution time of each layer's microcomputation blocks meets the gap constraints, structured pruning is performed on the convolutional kernels of the feature extraction layer by output channel dimension, the gated recurrent units of the temporal modeling layer by hidden dimension, and the fully connected weight matrix of the anomaly scoring layer by column dimension. Pruning is performed iteratively. In each iteration, the importance score of each candidate structural unit is calculated. The importance score comprehensively considers the weight magnitude of the structural unit, its contribution to the variance of the output activation value, and the reduction effect on the execution time of the microcomputation block after removal. In each iteration, the structural unit with the lowest importance score is pruned, and the execution time of each microcomputation block is measured on the target processor after pruning. When the execution time of all microcomputation blocks drops below the gap constraint threshold, the model detection accuracy is evaluated on the validation set. If the accuracy degradation exceeds a preset tolerance range (F1 score drops by more than 0.02), several rounds of fine-tuning and recovery training are performed. During fine-tuning, the learning rate is set to one-tenth of the original training learning rate, and the number of training rounds is 10 to 20. The aforementioned iterative process of pruning, testing, evaluation, and fine-tuning continues until all microcomputation blocks meet the time constraints and accuracy degradation is within tolerable limits. After gap-fitting structured pruning, the number of parameters in the model is reduced to 30% to 50% of the original baseline model.

[0045] Sub-step 2 involves performing cache-aligned mixed-precision quantization on the pruned model. The quantization bit width is allocated based on the ratio of the amount of weight data accessed by each micro-computation block to the capacity of the on-chip processor's final-level cache. When the amount of weight data for a micro-computation block under 8-bit integer quantization is less than 80% of the available capacity of the final-level cache, 8-bit integer quantization is used for that micro-computation block; when the amount of weight data under 8-bit quantization exceeds this threshold but can be satisfied under 4-bit quantization, 4-bit integer quantization is used for that micro-computation block. Micro-computation blocks closer to the input side of the feature extraction layer, due to their larger number of channels and weights, are preferentially allocated 4-bit quantization bit widths to compress their weight data within the cache capacity; micro-computation blocks closer to the output side of the anomaly scoring layer, with fewer parameters, retain 8-bit quantization bit widths to maintain scoring accuracy. The quantization process uses quantization-aware training, simulating quantization noise during training to reduce accuracy loss caused by quantization. The learning rate for quantization-aware training is set to 5.7 x 10^-5, and the training epochs are 30. After quantization, the execution time of each micro-computation block was retested on the target processor to verify whether the quantized memory access pattern met the cache residency constraint. After the above compression process, the execution time of each micro-computation block of the final lightweight model on the target processor did not exceed the 25th percentile of the available computation gap. The total number of model parameters was 15% to 25% of the original baseline model, and the inference accuracy F1 score on the test set was not lower than 0.94.

[0046] Step 2: Construct a traffic pre-screening module based on hardware flow tables.

[0047] The system utilizes the built-in hardware flow table matching engine of the smart network interface card (NIC) to perform rapid feature extraction and risk level pre-classification of input traffic, dividing it into three levels. The pre-defined matching rules in the hardware flow table are compiled based on historical traffic analysis results and known threat intelligence. The number of rule entries is configured according to the flow table capacity, preferably not exceeding 60% of the total flow table capacity to reserve expansion space. The first level is the trusted allowance level, whose matching rules cover addresses in the preset trusted source address set, normal heartbeat packets and keep-alive packets of established TCP connections, and traffic conforming to known security protocols such as steady-state data transmission after a TLS handshake. Traffic matching this level directly enters the forwarding path without consuming inference resources. The second level is the high-risk blocking level, whose matching rules cover known malicious signature features such as publicly disclosed attack payload byte patterns, traffic matching the blacklist address set, and traffic with severely abnormal protocol header formats such as invalid TCP flag combinations or malformed IP option field formats. Traffic matching this level directly triggers blocking actions and reports alarm events. The third level is the pending detection level; traffic not matching the previous two levels is marked and entered into the model inference queue.

[0048] The traffic pre-screening module employs a dynamic threshold adjustment mechanism, adaptively adjusting based on real-time monitoring of the inference queue backlog depth. When the number of data streams waiting to be processed in the inference queue exceeds a preset upper limit (preferably 75% of the total inference queue capacity), the matching range for trusted release levels automatically expands, including traffic with source address reputation scores higher than a preset security threshold within the trusted release scope. Simultaneously, the triggering conditions for high-risk blocking levels are appropriately relaxed, reducing the stringency of protocol anomaly detection. When the inference queue backlog depth falls below 40% of the total capacity, the original matching rule threshold is restored. This dynamic threshold adjustment forms a closed-loop control loop for inference load, preventing resource contention caused by inference backlog from propagating to the packet processing pipeline.

[0049] Step 3: Perform micro-inference staged interleaving scheduling in the packet processing pipeline.

[0050] like Figure 2 As shown, this step decomposes the complete inference process of the lightweight model obtained in step one into an ordered sequence of micro-inference stages. Each micro-inference stage corresponds to the execution of a micro-computation block. By performing inference computation stage by stage according to the gap availability in the packet processing main loop, the temporal coupling conflict between inference computation and packet forwarding processing is resolved.

[0051] Sub-step 1 involves maintaining an inference state context for each data stream to be detected in a dedicated memory area of ​​the on-chip processor. The inference state context includes the following fields: the number of the currently completed micro-inference stage (initially 0), the activation value cache for each intermediate layer (storage space allocated according to the output dimension of the micro-computation block), and the cumulative inference time count (in processor clock cycles). The inference state context is stored in a cache line aligned manner, meaning the starting address of each state context is aligned to a 64-byte boundary, and padding bytes are inserted between fields as needed to avoid cross-cache line access. Aligned storage ensures that context saving and restoring operations are completed in a single cache line read / write operation, without generating additional cache miss overhead, and the context switching time is controlled within 100 nanoseconds. The capacity of the dedicated memory area pre-allocated by the on-chip processor for the inference state context is determined based on the maximum number of concurrent data streams to be detected simultaneously, preferably supporting the state maintenance of no less than 1024 concurrent streams.

[0052] Sub-step 2 involves embedding inference scheduling logic into the main loop of the packet processing pipeline. After the on-chip processor completes the forwarding of the current data packet, the inference scheduler first estimates the remaining time interval until the next data packet is expected to arrive. The estimation method for the remaining time interval is as follows: read the depth of the current packet receiving queue; if there are already data packets to be processed in the queue, the remaining interval is zero, and the inference scheduler immediately skips the inference stage and enters the next round of packet processing; if the queue is empty, the arrival time of the next packet is estimated based on the exponentially weighted moving average of the recent packet arrival intervals. The decay coefficient of the exponentially weighted moving average is set to 0.125 to quickly track short-term changes in the flow rate. When the estimated remaining time interval is greater than the execution time of the currently pending microcomputation block plus a safety margin (preferably 20% of the microcomputation block execution time), the inference scheduler retrieves the inference state context of the highest priority stream to be detected from the inference queue, loads it into the processor register and cache, and executes the next micro-inference stage of that stream. After execution, the updated intermediate activation value and stage number are written back to the memory area where the inference state context is located, and then the main loop of packet processing is returned. The inference scheduler also supports an adaptive stage merging mechanism. When the estimated remaining gap time is sufficient to execute two or more consecutive micro-inference stages, adjacent stages are merged into consecutive execution batches, with the total execution time after merging not exceeding 85% of the gap margin. At the end of the pipeline before the current packet is processed, the inference scheduler initiates a cache preloading request for the inference state context in advance based on the identifier of the next pending flow in the inference queue, reducing cache cold start latency when the inference stage starts.

[0053] Sub-step 3: Set up an inference timeout management mechanism. A maximum allowable completion time limit is set for the inference process of each data stream to be detected. This time limit is measured in units of the number of data packets that the data stream has passed since entering the inference queue, preferably set to 1000 data packets. When the inference process of a data stream has not completed all micro-inference stages after 1000 data packet processing cycles, the inference scheduler marks the data stream as timed out, and its security handling strategy is upgraded to conservative blocking or rate limiting. Conservative blocking is suitable for data streams with high initial risk assessment values, while rate limiting is suitable for data streams with low initial risk assessment values. The rate limiting bandwidth is set to one-tenth of the normal bandwidth. The inference state context of the timed-out data stream is released, and the restored memory space is reallocated to new data streams in the inference queue.

[0054] The inference queue employs a priority sorting strategy based on risk weights. The risk weight is calculated as follows: risk weight equals the initial risk assessment value multiplied by the risk coefficient, plus the waiting time multiplied by the time aging coefficient. The initial risk assessment value is calculated based on the flow features extracted during the hardware flow table pre-screening in step two, and its value ranges from 0 to 1. The waiting time is measured in units of the number of data packets that the data flow passes through after entering the inference queue. The risk coefficient is preferably set to 0.6, and the time aging coefficient is preferably set to 0.4 divided by the timeout limit. This design ensures that the contribution of the time aging component is comparable to that of the risk component when approaching the timeout limit, preventing low-risk traffic from timed out due to long queuing times.

[0055] Step 4: Execute tiered defense actions based on the anomaly score results.

[0056] After a data stream completes all micro-inference stages, the anomaly scoring layer outputs an anomaly probability score for that stream, ranging from 0 to 1. This score is compared to preset multi-level thresholds to trigger corresponding defense actions. The multi-level thresholds include two dividing points: a normal threshold and an alarm threshold. Preferably, the normal threshold is set to 0.3 and the alarm threshold to 0.7. When the anomaly score is below 0.3, the stream is considered safe traffic. The inference scheduler updates the status flag of the corresponding five-tuple entry in the hardware flow table to trusted and allowed. Subsequent packets belonging to this stream will directly use the fast forwarding path and will not enter the inference queue. This operation is performed through the atomic update interface of the hardware flow table to avoid race conditions. When the anomaly score is between 0.3 and 0.7, the stream is considered suspicious traffic. Bandwidth limiting is applied to this stream, restricting its forwarding rate to within a preset safe bandwidth (preferably one-twentieth of the stream's original bandwidth). Simultaneously, an alarm event is generated and sent to the host-side security management module via the PCIe channel. The alarm event includes the stream's five-tuple information, the anomaly score, and the trigger timestamp. When the anomaly score exceeds 0.7, the traffic is identified as high-risk. A session blocking operation is immediately performed on this flow, setting the corresponding entry in the hardware flow table to "drop." Subsequent packets from this flow are directly dropped during the flow table matching phase, no longer consuming processor resources. The blocking event is simultaneously reported to the security management module. The security management module can dynamically modify the normal and alarm threshold parameters on the smart network interface card, as well as the configuration of defense strategies at each level, by issuing commands.

[0057] Step 5: Perform traffic distribution drift monitoring and incremental model update for forwarding load adaptation.

[0058] During the hardware flow table matching process in step two, a lightweight statistical accumulation is performed synchronously on the extracted flow-level feature vectors. The statistics include the online mean and online variance of each feature dimension. The Welford online algorithm is used to perform single-step updates during the flow table matching process of each data packet. Each update involves only one addition, one subtraction, and two multiplication operations, without generating independent computational overhead. The online statistics are stored in a fixed-size circular buffer, preferably with a buffer length corresponding to the statistical window of the 100,000 most recently processed data flow records.

[0059] In the micro-inference staged interleaved scheduling framework, drift detection computation is included as a low-priority microtask in the scheduling. When the inference queue is empty during packet processing intervals and the remaining interval time meets the execution conditions, the inference scheduler executes one round of drift detection microtasks. The drift detection microtask compares the traffic feature distribution represented by the current online statistics with the reference distribution saved during model training. The distribution divergence value is calculated using a simplified Mahalanobis distance metric based on the online mean and online variance, and the root mean square value of the normalized deviation of each feature dimension is taken as the comprehensive divergence value. When the comprehensive divergence value continuously exceeds a preset drift alarm threshold and reaches a preset confirmation window length (preferably, the results of 50 consecutive drift detection microtasks all exceed the threshold), traffic distribution drift is determined to be established, triggering the model incremental update process.

[0060] The incremental update process only updates the weight and bias parameters of the two fully connected layers in the anomaly scoring layer, keeping the parameters of the feature extraction layer and the temporal modeling layer unchanged, and controlling the number of parameters involved in the update to within 5% of the total number of model parameters. Specifically, the incremental update adopts an online gradient descent method, using the anomaly scoring results accumulated during the drift detection window and the actual handling effect fed back by the hardware flow table as weak supervision signals to calculate the gradient update amount of the anomaly scoring layer parameters. The parameter update process is decomposed into multiple micro-tasks, each micro-task updating a small batch of parameters, scheduled for execution in the packet processing gap with the lowest priority. During the execution of the incremental update, anomaly detection continues to run in the main parameter buffer using the parameters before the update, and the updated parameters are written to the shadow parameter buffer. After all update micro-tasks have been executed, the new parameters in the shadow buffer are verified, including checking the range of parameter values ​​and the consistency of scores on the small batch of verification samples. After the verification passes, the parameter reading address for inference calculation is switched from the main buffer to the shadow buffer using an atomic pointer switching method, completing the parameter update and ensuring that the continuity of the detection service is not interrupted.

[0061] like Figure 6As shown, the drift monitoring and incremental update mechanism includes four states: normal monitoring, drift warning, incremental update in progress, and parameter switching. In the normal monitoring state, the system continuously accumulates online statistics. When the calculated divergence value exceeds a preset threshold, it switches to the drift warning state. If the divergence value subsequently falls below the threshold, it returns to the normal monitoring state; if 50 consecutive detections exceed the threshold, a traffic distribution drift is confirmed, and the system enters the incremental update state.

[0062] In incremental update mode, the update microtask sequence is executed in the lowest priority packet gaps, without affecting normal packet processing and anomaly inference tasks. During incremental updates, anomaly detection continues to use the old parameters to ensure uninterrupted service. Once all microtasks are completed and the new parameters pass verification, the system enters parameter switching mode, completing the parameter update through atomic pointer switching between the main buffer and the shadow buffer; if verification fails, it reverts to normal monitoring mode and continues using the original parameters.

[0063] Example 2 In a preferred embodiment of the present invention, the technical implementation of the micro-inference staged interleaving scheduling in step S3 is described in detail. This embodiment uses a smart network card equipped with a quad-core ARM Cortex-A72 processor as the target hardware platform. The on-chip processor has a main frequency of 2.0 GHz, a final-level cache capacity of 1 MB, and a single-core available memory bandwidth of approximately 4 GB / s.

[0064] In terms of the micro-inference stage partitioning strategy, the lightweight model compressed in step S1 includes three functional layers: a feature extraction layer, a temporal modeling layer, and an anomaly scoring layer. When further dividing these three layers into micro-computation blocks, the floating-point operation volume, memory access volume, and storage requirements of intermediate activation values ​​for each micro-computation block must be comprehensively considered. In this embodiment, considering the computing power and cache configuration of the target hardware platform, the baseline model adopts network architecture parameters different from those in Embodiment 1. Specifically, the feature extraction layer includes three sets of one-dimensional convolution operations with a kernel size of 3, 32 input channels, and 64, 64, and 128 output channels respectively. Each set of convolution operations is followed by batch normalization and ReLU activation functions. Each set of convolution operations and its subsequent normalization and activation operations are divided into a micro-computation block, forming three feature extraction micro-computation blocks FE-1, FE-2, and FE-3. The temporal modeling layer adopts a single-layer gated recurrent unit structure with a hidden state dimension of 128. Since the computation of the gated recurrent unit involves three sets of matrix operations—reset gate, update gate, and candidate hidden state—each set of matrix operations is divided into a micro-computation block, forming three temporal modeling micro-computation blocks: TM-1, TM-2, and TM-3. The anomaly scoring layer adopts a two-layer fully connected structure with a hidden dimension of 64 and an output dimension of 1. The two fully connected layers and their activation functions are each divided into a micro-computation block, forming two anomaly scoring micro-computation blocks: AS-1 and AS-2. Thus, the complete inference process is decomposed into eight ordered micro-inference stages.

[0065] The execution time of each microcomputing block was measured on the target processor under a packet processing gap environment with a 10Gbps mixed traffic load. The results show that the execution time of FE-1 is 1.2 microseconds, FE-2 is 1.4 microseconds, FE-3 is 2.1 microseconds, TM-1 to TM-3 are 1.8 microseconds, 1.9 microseconds, and 1.7 microseconds respectively, AS-1 is 0.8 microseconds, and AS-2 is 0.5 microseconds. Under 10Gbps line-rate forwarding conditions, the 25th percentile of the packet processing gap duration distribution is approximately 2.8 microseconds, the 50th percentile is approximately 5.6 microseconds, and the 75th percentile is approximately 12.3 microseconds. The execution time of all microcomputing blocks is below the 25th percentile, meeting the gap constraint requirements.

[0066] The data structure design of the inference state context directly impacts scheduling efficiency. The memory space occupied by the inference state context for each data stream to be detected includes: 4 bytes for the current micro-inference stage number, 8 bytes for the cumulative inference time count, 512 bytes (128 x 4) for the intermediate activation value cache of the feature extraction layer, 512 bytes (128 x 4) for the hidden state cache of the temporal modeling layer, 1536 bytes (128 x 3 x 4) for the intermediate gate value cache of the gated loop unit, and 256 bytes (64 x 4) for the intermediate value cache of the anomaly scoring layer. The total inference state context for a single data stream is approximately 2828 bytes, which, after alignment with 64-byte cache lines, occupies 2880 bytes (45 cache lines). When concurrently maintaining the inference state contexts for 512 data streams to be detected, the total memory usage is approximately 1.44 MB. Preferably, the storage area for the inference state context is pre-allocated during system initialization, and a circular buffer structure is used to manage the free slots. New data streams entering the inference queue obtain free slots from the circular buffer, and data streams that have completed inference or timed out release slots and return to the buffer, thus avoiding dynamic memory allocation operations at runtime.

[0067] like Figure 7 As shown, the on-chip processor contains eight processing cores arranged in a 2x4 grid. Cores 0 to 3 are responsible for the interleaved execution of packet processing and micro-inference, cores 4 and 5 are responsible for hardware flow table management, core 6 is dedicated to the cumulative calculation of drift monitoring statistics, and core 7 is responsible for management communication with the host side.

[0068] The processor's central section houses a shared final-level cache area, ranging from 1 to 4 MB in size. Internally, it's divided into three functional areas: a model weight cache of approximately 0.3 MB, used to store quantization weight parameters for lightweight models; an inference context cache of approximately 1.44 MB, used to store intermediate inference states for each data stream; and the remaining space is used as a packet buffer. All inference state context data is stored aligned to 64-byte cache lines, eliminating additional latency caused by cross-cache line accesses. The bottom interface connects to on-chip DDR memory via the memory controller, used to store complete model parameters and statistical data.

[0069] In the specific implementation of the inference scheduling judgment logic, after the packet processing main loop completes the forwarding of the current data packet, the inference scheduler first reads the current depth value of the packet receiving queue and the exponentially weighted moving average of the recent packet arrival intervals. The product of the two is used as an estimate of the remaining time interval before the expected arrival of the next data packet. Preferably, the smoothing factor of the exponentially weighted moving average is between 0.1 and 0.3. A smaller smoothing factor makes the estimate more conservative in response to burst traffic, while a larger smoothing factor makes the estimate track load changes faster. The setting of the safety margin needs to consider the variance of the microcomputation block execution time and the time consumed by the inference state context saving operation. Preferably, it is set to 20% to 30% of the maximum execution time of the microcomputation block, which is about 0.4 to 0.6 microseconds in this embodiment. When the estimated remaining time interval minus the safety margin is still greater than the execution time of the microcomputation block to be executed, the scheduler executes the micro-inference phase.

[0070] The adaptive phase merging mechanism further improves inference throughput when there is ample gap. When the remaining time interval estimated by the inference scheduler is greater than the sum of the execution time of the currently pending microcomputation block and its adjacent subsequent microcomputation blocks plus the safety margin, these adjacent microcomputation blocks are merged into a single continuous execution batch. The upper limit of merging is constrained by a preset ratio of gap margin, preferably 60% to 80%, meaning that the execution time after merging does not exceed 60% to 80% of the estimated remaining gap, leaving sufficient margin to cope with fluctuations in packet arrival time. During periods of low traffic, the duration of packet gaps may reach tens of microseconds. In this case, all 8 micro-inference phases can be merged into one continuous execution to complete the inference of the entire data stream, with a total inference time of approximately 11.4 microseconds. When the proportion of short packets in the input traffic exceeds 70%, causing the packet gaps to generally shorten to below 3 microseconds, the phase merging mechanism automatically degenerates into a single-phase execution mode, where only one microcomputation block is executed per packet gap. In this case, the complete inference of a single data stream requires at least 8 packet gap cycles.

[0071] The inference context preloading mechanism works in conjunction with stage merging. When the current packet forwarding process enters the tail stage (specifically, within the time window after packet descriptor write-back and before the packet processing completion interruption), the inference scheduler, based on the identifier of the next pending flow in the inference queue, issues a prefetch instruction to the cache controller, preloading the inference state context of that flow from main memory to the last-level cache. The prefetched data consists of the input activation values ​​and corresponding model weight parameters required for the next pending micro-inference stage in the inference state context of that flow. In actual testing on the target platform, the preloading operation reduces the cache cold start latency at the start of the inference stage from approximately 0.8 microseconds to approximately 0.1 microseconds. This latency reduction is significant for completing micro-inference stages within tight intervals.

[0072] In the risk-weighted priority ranking strategy, the priority weight W of each data stream to be detected is determined by a weighted combination of the initial risk assessment value R and the waiting time factor T. The calculation formula is W = alpha × R + (1 - alpha) × T / T_max, where alpha is the risk preference coefficient, preferably ranging from 0.6 to 0.8, T is the number of packets that the data stream has been waiting in the inference queue, and T_max is the maximum number of packets allowed in the inference timeout management mechanism. When alpha has a higher value, high-risk traffic gets priority access to inference resources; when alpha has a lower value, the impact of waiting time increases, which can reduce queue starvation. Preferably, when the inference queue depth exceeds 75% of the total capacity, the alpha value is dynamically adjusted towards 0.5 to strengthen the weight of the waiting time factor and ensure the overall flow efficiency of the queue.

[0073] The beneficial effects of the aforementioned micro-inference staged interleaving scheduling scheme are reflected in the following aspects. Regarding inference throughput, under a 10Gbps mixed traffic load as the test condition, the on-chip processor can complete approximately 15,000 to 25,000 complete inference operations per second while maintaining line-rate forwarding. The specific value depends on the packet length distribution and burst characteristics of the traffic. When the traffic is mainly composed of large packets (average packet length greater than 512 bytes), the packet gaps are longer, and the inference throughput approaches its upper limit; when the traffic is mainly composed of small packets (average packet length less than 128 bytes), the packet gaps are shorter, and the inference throughput approaches its lower limit, but still maintains usable detection coverage. Regarding the impact on forwarding performance, the packet processing latency increment introduced by micro-inference scheduling does not exceed the sum of the execution time of a single micro-computation block and the context switching overhead, which is approximately 2.5 to 3.0 microseconds under the hardware configuration of this embodiment. Compared to the packet forwarding latency without inference load (approximately 1.5 microseconds), the latency increment is approximately 167% to 200%, but the total forwarding latency remains at the microsecond level, not affecting the service quality requirements of most network applications. Regarding resource utilization, the pre-allocated memory for the inference state context is 1.44MB, and the storage usage of the model weight parameters after cache alignment and quantization is approximately 0.3MB, totaling approximately 1.74MB, which does not exceed a reasonable proportion of the available memory resources of the on-chip processor. It should be noted that when network traffic exhibits extreme burst characteristics (such as micro-burst intervals less than 1 microsecond), the packet gaps may be consistently shorter than the execution time of any micro-computation block. Under such extreme conditions, the inference scheduler will continuously skip inference execution, and the inference throughput may drop to near zero. The traffic awaiting detection will trigger the inference timeout management mechanism for conservative handling.

[0074] The principle behind the aforementioned technical effects lies in the fact that the interleaved scheduling of micro-inference stages reduces the time granularity of inference computation from the millisecond level of complete model inference to the microsecond level of a single micro-computation block, thus matching the execution unit of inference computation with the time scale of packet processing gaps. Traditional continuous inference methods require exclusive access to several milliseconds of processor core time, during which packet reception and forwarding cannot be responded to, leading to a sharp increase in packet processing latency and even packet loss. However, by decomposing inference into multiple micro-inference stages, the execution time of each stage is controlled within the quantile constraints of the packet gap duration. The processor can execute only one or a few micro-inference stages in each packet gap before returning to the main packet processing loop, thereby "embedding" inference computation into the idle time slots of the packet processing pipeline. The cache line-aligned storage of the inference state context ensures that state saving and restoration operations between stages do not generate additional overhead from cache misses. The adaptive stage merging mechanism reduces the scheduling overhead caused by the number of context switches when the gaps are sufficient, and the preloading mechanism eliminates the cache cold start latency when inference starts. All three together guarantee the execution efficiency of micro-inference stages in compact gaps. Prioritization based on risk weights ensures that inference resources are prioritized for high-risk traffic, while waiting time factors and dynamic alpha adjustments prevent indefinite starvation of low-risk traffic, thus achieving a reasonable allocation of detection resources under the constraint of limited inference throughput.

[0075] Example 3 In another embodiment of the present invention, an abnormal traffic detection scheme for smart network interface cards based on flow-level feature caching and batch inference scheduling is provided. This scheme adopts a different inference scheduling strategy and model architecture than that of Embodiment 1 to adapt to the processing characteristics of different types of smart network interface card hardware platforms.

[0076] In this embodiment, the on-chip processor does not perform inference computations during packet processing intervals. Instead, it centrally schedules inference computations for batch execution within a dedicated inference time window. Specifically, during the reception and forwarding of data packets, the packet processing pipeline only performs lightweight flow-level feature extraction and accumulation operations, appending the header field features and payload statistics of each data packet to a flow feature cache table maintained in on-chip memory according to the flow identifier. The flow feature cache table maintains a fixed-length feature vector sequence buffer for each active data stream, with the buffer length being a preset observation window size, preferably 16 to 64 data packets. When the feature buffer accumulation of a data stream meets the observation window requirements, the stream is marked as inference-ready and added to the inference-ready queue.

[0077] The inference time window scheduling employs a combination of periodic triggering and load adaptation. The on-chip processor maintains an inference trigger counter within the packet processing main loop, triggering an inference time window after forwarding a preset number of data packets. Preferably, this trigger interval is 1000 to 5000 data packets. After the inference time window is triggered, the packet processing main loop pauses receiving new data packets. The on-chip processor forwards all buffered data packets in the current packet receiving queue and then enters the inference execution phase. During the inference execution phase, a batch of data streams to be detected is retrieved from the inference ready queue. The batch size is constrained by the available memory of the on-chip processor, preferably 8 to 32 data streams. The feature vector sequences of all data streams in this batch are assembled into a batch input tensor and fed into the anomaly detection model to perform a batch forward inference, obtaining an anomaly probability score for each data stream. After inference execution is completed, the processor exits the inference time window and resumes the packet processing main loop.

[0078] The anomaly detection model used in this embodiment is a time-series classification network based on one-dimensional dilated causal convolution, which differs from the gated recurrent unit structure in Embodiment 1. The one-dimensional dilated causal convolution network consists of multiple stacked causal convolutions, with the dilation coefficients of each layer increasing exponentially (preferably 1, 2, 4, 8), a kernel size of 3, and 64 channels. Causal convolution ensures that the output at time t depends only on the input at time t and earlier by unidirectional padding of the input sequence, satisfying the physical constraint of causality in traffic time-series analysis. Dilated convolution increases the receptive field exponentially with the number of layers by inserting gaps between kernel elements. The effective receptive field of a four-layer dilated causal convolution can cover an input sequence of length 25, and when the observation window is set to 32 data packets, it can cover approximately 78% of the window range. Unlike the stepwise recursive computation of gated loop units, each layer of dilated causal convolution is a matrix multiplication operation, which is suitable for batch parallel execution. In batch inference scenarios, it can make full use of the processor's SIMD (Single Instruction Multiple Data) instruction set to accelerate the process.

[0079] In terms of model compression, this implementation adopts a strategy combining channel pruning and uniform 8-bit integer quantization across the entire model. Channel pruning uses the contribution of each convolutional channel to the final detection accuracy as the evaluation index, employing a gradient-based importance assessment method to uniformly prune the number of channels in each layer from 64 to 48 or 32, until the execution time of a single batch inference (batch size of 16) is lower than the budgeted duration of the inference time window. Unlike the differentiated bit-width quantization at the micro-computation block granularity in Example 1, this implementation uniformly performs 8-bit integer quantization on the entire model, leveraging the regularity of data access patterns during batch inference and achieving efficient utilization of the processor cache through the continuous storage layout of model weights.

[0080] The total duration of the inference time window is constrained by the packet processing latency budget. During the inference time window, packets in the packet receive queue are paused from being forwarded, and the queue depth continues to grow. The maximum allowed duration of the inference time window is determined by the remaining capacity of the packet receive queue and the current traffic rate, calculated by dividing the remaining queue capacity by the current packet arrival rate. When the time taken for the inference execution phase is about to exceed the maximum allowed duration, the inference process is interrupted. Data streams that have completed inference receive an anomaly score, while data streams that have not completed inference are rolled back to the inference-ready queue to wait for the next inference time window. Under 10Gbps line-rate conditions, if the packet receive queue depth is 4096 descriptors and the current occupancy rate is 50%, and the maximum packet arrival rate calculated with a minimum packet length of 64 bytes is approximately 14.88 million packets per second, then the maximum allowed duration of the inference time window is approximately 137 microseconds. Within this duration, a single batch inference executed with a batch size of 16 can be completed in approximately 35 to 50 microseconds, leaving sufficient margin.

[0081] In terms of executing defensive actions, the anomaly scoring results in this implementation also trigger release, rate limiting, or blocking operations based on multi-level thresholds, and the processing logic is consistent with step S4. Regarding drift monitoring, drift detection calculations are scheduled to be performed at the end of the inference time window. When batch inference is completed and the remaining duration of the inference time window meets the execution conditions, a round of divergence calculation is performed using the statistics accumulated in the flow feature cache table.

[0082] As an alternative, this implementation is suitable for smart NIC platforms where the on-chip processor does not support efficient context switching or where packet gap durations fluctuate greatly. On such platforms, frequent micro-inference stage switching can generate high scheduling overhead, while batch inference reduces the number of context switches through centralized execution and can improve computational efficiency by leveraging the parallelism of batch data. The limitation of this approach is that packet processing is paused during the inference time window. If the traffic rate remains near line speed and the packet receiving queue capacity is limited, the available inference time window duration is compressed, thus restricting inference throughput. Furthermore, since the data stream needs to accumulate a certain number of feature packets to meet the observation window requirements before entering the inference ready queue, there is an inherent observation delay between the first suspicious packet and obtaining an anomaly score. For detection scenarios requiring immediate judgment of individual data packets, the response speed of this approach is slower than the staged inference method in Embodiment 1.

[0083] Example 4 like Figure 4As shown, this embodiment provides a real-time monitoring and defense system for abnormal traffic of smart network interface cards (NICs) based on a lightweight model. The system is deployed on a smart NIC platform equipped with an on-chip processor, which is a multi-core processor. The smart NIC connects to a host server via a PCIe interface and incorporates a hardware flow table matching engine and a programmable data plane forwarding pipeline. The system includes a model compression module, a traffic pre-screening module, a micro-inference scheduling module, a tiered defense module, and a drift monitoring module.

[0084] The model compression module performs forwarding load-aware compression on the benchmark anomaly detection model, dividing each layer of the model into micro-computation blocks based on computational load. The execution time of each micro-computation block does not exceed a preset percentile value of the duration distribution of packet processing gaps on the smart network card's processor. The model compression module first trains a benchmark deep neural network model for anomaly traffic detection in an offline environment. This benchmark model employs a multi-layer architecture including a feature extraction layer, a temporal modeling layer, and an anomaly scoring layer. The feature extraction layer extracts flow-level feature vectors from the header fields and payload statistical summaries of data packets. The temporal modeling layer captures temporal correlation patterns between consecutive data packets, and the anomaly scoring layer outputs an anomaly probability score for the current flow. The model compression module pre-collects temporal feature spectra of the packet processing pipeline under different traffic load conditions on the target on-chip processor of the smart network card. These temporal feature spectra include the duration distribution of available computational gaps between adjacent packet processing, the frequency and duration distribution of packet processing interruptions, and the switching patterns of cache residency states. Based on these temporal feature spectra, each layer of the model is divided into several micro-computation blocks, with the single execution time of each micro-computation block constrained to not exceed the 25th percentile value of the duration distribution of available computational gaps. The forwarding load-aware compression performed by the model compression module includes two sub-processes: gap-adaptive structured pruning and cache-aligned hybrid precision quantization. Gap-adaptive structured pruning is guided by the requirement that the execution time of each layer of micro-computation blocks meets the gap constraint. It performs structured pruning of convolutional kernels or fully connected weight matrices by row or column. After each round of pruning, the execution time of the micro-computation blocks is measured on the target processor to verify the gap constraint. Cache-aligned hybrid precision quantization allocates the quantization bit width according to the ratio between the amount of weight data accessed by each micro-computation block and the capacity of the on-chip processor's last-level cache. When the amount of weight data of a micro-computation block can completely reside in the last-level cache under the corresponding bit width, that bit width is used for quantization.

[0085] The traffic pre-screening module utilizes a smart network interface card (NIC) hardware flow table matching engine to pre-screen input traffic into three levels: trusted allowance, high-risk blocking, and pending detection. The module pre-configures matching rules based on historical traffic analysis and known threat intelligence in the hardware flow table. Traffic matching the preset trusted source address set, established connection heartbeat packets, or those conforming to known security protocol characteristics is assigned to the trusted allowance level and directly enters the forwarding path. Traffic matching known malicious signatures, blacklisted addresses, or severely abnormal protocol formats is assigned to the high-risk blocking level, directly triggering blocking actions and alarm reporting. Traffic not matched by either of the aforementioned levels is marked as pending detection and pushed into the model inference queue. The traffic pre-screening module employs a dynamic threshold adjustment mechanism. When the backlog depth in the model inference queue exceeds a preset upper limit, the matching leniency of the trusted allowance level is increased, and the trigger threshold of the high-risk blocking level is decreased to reduce the amount of traffic entering the inference queue. When the backlog depth in the inference queue returns to a normal level, the original threshold setting is restored, thus adaptively adjusting the amount of traffic entering the inference queue, forming a closed-loop control of the inference load.

[0086] The micro-inference scheduling module maintains an inference state context for each data stream to be detected. It decomposes the inference process of the compressed model into an ordered sequence of micro-inference stages. In the main loop of the packet processing pipeline, when the remaining time interval after forwarding the current packet is greater than the sum of the micro-computation block execution time and the safety margin, the highest-priority data stream to be detected is retrieved from the inference queue to execute its next micro-inference stage. After updating the inference state context, it returns to the main loop of packet processing. The micro-inference scheduling module maintains an inference state context for each data stream to be detected in a dedicated memory area of ​​the on-chip processor. The inference state context includes the number of the currently completed micro-inference stage, the activation value cache of each intermediate layer, and the cumulative inference time count. It is stored in a cache line-aligned manner to ensure that saving and restoring the context does not generate additional cache miss overhead. The micro-inference scheduling module uses a risk-weighted priority sorting strategy to schedule the inference queue. The risk weight comprehensively considers the initial risk assessment value extracted during hardware flow table pre-screening and the length of time the data stream has been waiting in the inference queue. Data streams with longer waiting times are assigned higher priorities to ensure that all traffic to be detected can obtain inference resources within a reasonable time. The micro-inference scheduling module also supports an adaptive stage merging mechanism and an inference state context preloading mechanism. When there is sufficient gap, adjacent micro-inference stages are merged into consecutive execution batches to accelerate the inference progress. Before the current packet is processed, the inference state context of the next stream to be executed is preloaded into the cache to reduce cold start overhead. The micro-inference scheduling module sets an inference timeout management mechanism for each data stream to be detected. When the inference process has not completed all micro-inference stages within the maximum allowed completion time limit, the handling strategy for the data stream is upgraded to conservative blocking or rate limiting.

[0087] The tiered defense module is used to trigger tiered defense actions such as allowing, rate limiting, or blocking based on the comparison between the anomaly probability score output after completing all micro-inference stages and multi-level thresholds. When the anomaly score is lower than the normal threshold, the tiered defense module marks the flow as safe and updates the trusted allow flag of the corresponding entry in the hardware flow table. Subsequent packets belonging to this flow will directly take the fast forwarding path. When the anomaly score is between the normal threshold and the alarm threshold, the tiered defense module performs bandwidth rate limiting on the flow, restricting its forwarding rate to within a preset safe bandwidth, and simultaneously sends an alarm notification to the host-side security management module. When the anomaly score exceeds the alarm threshold, the tiered defense module immediately performs session blocking on the flow, discarding subsequent packets of the flow and reporting the blocking event to the security management module. The multi-level thresholds can be configured and adjusted according to the requirements of network management policies, and the security management module can dynamically modify the threshold parameters and defense policies on the smart network interface card by issuing commands.

[0088] The drift monitoring module schedules drift detection calculations as low-priority micro-tasks during packet processing intervals. When the distribution divergence value exceeds the drift alarm threshold, it triggers an incremental model update. During the hardware flow table matching process of the flow pre-screening module, the drift monitoring module synchronously performs incremental accumulation of the online mean and online variance of the flow-level feature vectors. The drift detection micro-task uses a simplified Mahalanobis distance metric based on the online mean and online variance to calculate the divergence value between the current statistic and the reference distribution. When the divergence value continuously exceeds the drift alarm threshold to reach the preset confirmation window length, the drift monitoring module triggers an incremental update performed only on the anomaly scoring layer weight parameters. This incremental update is decomposed into a sequence of micro-tasks and executed with the lowest priority during packet processing intervals. After the update is completed, parameters are switched atomically to ensure the continuity of the detection service.

[0089] The data flow relationship between the five functional modules is as follows: the output of the model compression module, i.e., the lightweight model parameters, is deployed to the micro-inference scheduling module for inference computation; the traffic pre-screening module receives the input traffic from the smart NIC data plane and pushes the data stream of the level to be detected to the inference queue of the micro-inference scheduling module; after completing all micro-inference stages, the micro-inference scheduling module transmits the anomaly scoring results to the hierarchical defense module to execute defense actions; the handling results of the hierarchical defense module are fed back to the traffic pre-screening module to update the status flags in the hardware flow table; the drift monitoring module obtains online statistical data from the traffic pre-screening module and sends the updated model parameters to the micro-inference scheduling module when an incremental update is triggered. The system can be deployed on a smart NIC hardware platform equipped with a multi-core ARM architecture on-chip processor and communicates with the host-side security management module through the PCIe interface for command and event interaction.

[0090] Example 5 This embodiment provides an application case of a real-time monitoring and defense method for abnormal traffic of smart network interface cards (NICs) based on a lightweight model. The technical solution of this invention is applied to a border gateway traffic detection scenario in a large data center. The data center border gateway carries multi-tenant mixed service traffic, with a peak traffic rate of 40Gbps for a single gateway interface. The number of concurrent data streams passing through in real time exceeds 120,000 during peak periods. The traffic components cover various types, including HTTP / HTTPS application layer protocols, database access protocols, real-time audio and video streams, and internal management protocols. Due to the mixed traffic types and drastic fluctuations in traffic rate, traditional solutions that bypass and mirror traffic to an independent detection server suffer from mirroring latency and packet loss issues. Furthermore, solutions that directly run a complete anomaly detection model on a general-purpose processor cannot maintain low-latency packet forwarding simultaneously at a 40Gbps line speed. Therefore, it is necessary to implement coordinated anomaly detection and forwarding processing on the smart NIC side.

[0091] like Figure 8 As shown, in a data center border gateway deployment scenario, external internet traffic enters the border gateway server at a rate of 40Gbps. The smart network interface card (NIC) embedded in the server performs anomaly detection and tiered defense processing on all incoming data packets in real time. After processing by the smart NIC, normally allowed traffic is forwarded to the tenant server clusters in the internal network area, rate-limited traffic is forwarded at a controlled rate, and blocked traffic is discarded at the NIC side.

[0092] The smart network interface card (NIC) communicates with the host-side security management module via the PCIe interface, reporting alarm events and detection logs, and receiving security policy instructions and flow table update rules. This deployment method eliminates the need to install additional security software in the host operating system; all detection and defense actions are performed on the smart NIC's on-chip processor, achieving line-speed processing without consuming host computing resources.

[0093] During the model building and compression phase, the baseline anomaly detection model was trained on a historical traffic dataset from a data center. The training data covered 45 days of full traffic mirroring records, containing approximately 8.2 million data streams, of which anomaly traffic samples accounted for about 3.6%. Anomaly types covered port scanning, distributed denial-of-service attack traffic, covert channel communication, data theft and transmission, and protocol abuse. The baseline model achieved an anomaly detection recall of 98.1% and a false positive rate of 1.05% on the test set, with an F1 score of 0.971. After forwarding load-aware compression, the lightweight model's parameter count was reduced to 18.7% of the baseline model. The execution time of each micro-computation block was controlled within the 25th percentile of the target processor's packet processing interval (1.2 microseconds). The compressed model achieved an F1 score of 0.948, a recall of 96.3%, and a false positive rate of 1.58% on the test set.

[0094] In actual deployment and operation, the hardware flow table pre-screening module categorizes incoming traffic into three levels. Under typical workloads, approximately 62% of traffic is classified as trusted and allowed to proceed directly, approximately 4.8% of traffic hits the high-risk blocking level and is directly blocked, and the remaining approximately 33.2% of traffic enters the inference queue for testing. A dynamic threshold adjustment mechanism reduces the proportion of traffic entering the inference queue to approximately 25% during sudden traffic spikes, returning to normal levels after the spike.

[0095] The micro-inference staged interleaving scheduling operates under 40Gbps line-rate forwarding conditions, with the lightweight model decomposed into 16 micro-inference stages. Under medium-speed steady-state traffic conditions, the complete inference process for a single data stream to be detected is completed within an average of 380 packet processing cycles, corresponding to an end-to-end inference latency of approximately 1.9 milliseconds. Under high-speed burst traffic conditions, the inference completion cycle extends to approximately 620 packets, corresponding to a latency of approximately 3.1 milliseconds. The inference timeout rate (the percentage of traffic that has not completed inference within the time limit of 1000 packets) is less than 0.3% under medium-speed steady-state conditions and approximately 1.7% under high-speed burst conditions. The average additional latency for packet forwarding (the extra processing time per packet introduced by the inference scheduling judgment logic) is 43 nanoseconds, not exceeding 1.8% of a single packet processing cycle.

[0096] To verify the technical effectiveness of this invention, comparative experiments were conducted on the same data center traffic test set, with a continuous test duration of 72 hours. Comparative scheme one is a direct deployment scheme without model compression and inference stage decomposition, running the complete baseline model directly on the smart network card processor, with each inference cycle occupying a full processor computation cycle. Comparative scheme two is a continuous inference scheme on the smart network card using a model compressed with general hardware-aware pruning and uniform quantization strategies, without introducing micro-computation block partitioning and interleaving scheduling mechanisms for packet gap adaptation. Comparative scheme three is a traditional flow table matching and detection scheme based on static rules, without using a deep learning model.

[0097] like Figure 9As shown, in terms of detection performance, the method of this invention achieves an F1 score of 0.948 on the test set, a recall rate of 96.3%, and a false positive rate of only 1.58%, outperforming other comparative schemes in all three metrics. Comparative scheme one suffers packet loss due to resource contention and cannot operate continuously at 40Gbps line speed, with an effective detection coverage of only 71.4%, and a large number of packets are dropped due to forwarding timeouts. Comparative scheme two has an F1 score of 0.923, a recall rate of 93.8%, and a false positive rate of 2.34%. Due to the lack of micro-computation block adaptation for packet processing gaps, the inference process frequently interrupts the packet forwarding pipeline, leading to a decrease in detection accuracy under high load. Comparative scheme three has an F1 score of only 0.761, a recall rate of 72.5%, and a false positive rate as high as 4.67%, indicating that static rules are difficult to cope with complex and ever-changing abnormal traffic patterns.

[0098] Regarding forwarding performance, the method of this invention exhibits a packet forwarding throughput reduction rate of less than 0.15% under 40Gbps line-rate conditions, with a 99th percentile packet forwarding latency increment of 67 nanoseconds. In contrast, Scheme 1, under the same conditions, shows a throughput reduction rate of 23.6% and a tail latency increment exceeding 12 microseconds. Scheme 2 shows a throughput reduction rate of 5.8% and a tail latency increment of 2.3 microseconds.

[0099] To verify the contribution of each key technology component, ablation experiments were conducted by removing each component under the same test environment. Four indicators were observed: the rate of decrease in forwarding throughput, the increase in inference timeout rate, the change in F1 score, and the change in inference completion cycle. For example... Figure 10 As shown, after removing the gap adaptation constraint in the forwarding load-aware compression strategy and replacing it with a proportionally evenly divided micro-computation block, approximately 34% of the micro-computation blocks had execution times exceeding the 25th percentile of the packet gap. This led to increased interference with packet forwarding during the inference phase, a 3.2% decrease in forwarding throughput, and a 5.1% increase in inference timeout rate. This demonstrates that the gap adaptation constraint plays a crucial role in ensuring both forwarding performance and inference timeliness. Removing the hardware flow table pre-screening mechanism and sending all traffic to the inference queue resulted in a rapid increase in inference queue backlog, a 18.4% increase in inference timeout rate, and a drop in detection coverage to 79%. This indicates that the flow table pre-screening mechanism effectively alleviated inference resource pressure by reducing the amount of traffic to be detected. Removing the adaptive phase merging and context preloading mechanisms extended the average inference completion cycle of a single flow by approximately 41% and decreased inference throughput by approximately 29%, demonstrating that this mechanism is crucial for improving micro-inference scheduling efficiency. After removing the drift monitoring and incremental update mechanism, the model's F1 score gradually decreased from 0.948 to 0.891 during a 72-hour continuous test, a drop of 0.057. In contrast, the complete scheme with drift monitoring enabled maintained an F1 score between 0.941 and 0.952 during the same period, verifying the necessity of drift monitoring and incremental update mechanism for maintaining long-term detection accuracy.

[0100] The experimental results above show that the forwarding load-aware compression strategy, hardware flow table pre-screening mechanism, micro-inference staged interleaving scheduling, and drift monitoring and incremental update mechanism of the present invention each have independent and significant technical contributions to the detection performance and forwarding performance of the system. The collaborative work of each component enables abnormal traffic detection to be performed in real time on the smart network card side with line-speed forwarding as a prerequisite.

[0101] To verify the stability of the inference performance of the method of the present invention under different traffic load conditions, tests were conducted under five traffic scenarios: low-speed steady state, medium-speed steady state, high-speed steady state, burst pulse, and extreme micro-burst. The changing trends of three indicators, namely inference latency, number of packets completed inference, and inference throughput, were recorded.

[0102] like Figure 11 As shown, in low-speed and medium-speed steady-state scenarios, the inference latency is 0.8ms and 1.9ms, respectively, while the inference throughput reaches approximately 28,000 times / second and 25,000 times / second, respectively. The inference timeout rate is less than 0.3%, and the system operates stably. In the high-speed steady-state scenario, the inference latency increases to 3.1ms, the inference timeout rate is approximately 1.7%, and the inference throughput drops to 18,000 times / second, but remains within an acceptable range. In the burst scenario, the inference latency further increases to 5.8ms, and the number of packets completed inference is close to 850, which has not yet reached the timeout threshold of 1,000 packets. In the extreme micro-burst scenario, due to the drastic shortening of packet gaps, the inference latency increases significantly, and the inference throughput drops to near zero. At this time, the system relies on hardware flow table pre-screening and hierarchical defense mechanisms to ensure network security. Overall, the results show that the method of this invention can effectively utilize packet processing gaps to complete micro-inference scheduling under medium- and high-speed traffic conditions, maintaining a low inference timeout rate and a high detection throughput.

[0103] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for real-time monitoring and defense of abnormal traffic of intelligent network interface cards based on a lightweight model, characterized in that, Includes the following steps: Step S1: Perform forwarding load-aware compression on the benchmark anomaly detection model, divide each layer of the model into micro-computation blocks according to the amount of computation, and the execution time of each micro-computation block does not exceed the preset quantile value of the duration distribution of the packet processing gap on the intelligent network card. Step S2: Use the smart network interface card hardware flow table matching engine to pre-screen the input traffic into three levels: trusted to allow, high-risk to block, and to be detected. Step S3: Maintain an inference state context for each data stream to be detected, decompose the inference process of the compressed model into an ordered sequence of micro-inference stages, and in the main loop of the packet processing pipeline, when the remaining time interval after the current packet forwarding is greater than the sum of the execution time of the micro-computation block and the safety margin, take the highest priority data stream to be detected from the inference queue to execute its next micro-inference stage, update the inference state context and return to the main loop of packet processing. Step S4: Based on the comparison between the anomaly probability score output after completing all micro-inference stages and the multi-level threshold, trigger a graded defense action of allowing passage, limiting speed, or blocking. Step S5: The drift detection calculation is scheduled as a low-priority microtask and executed during the packet processing interval. When the distribution divergence value exceeds the drift alarm threshold, the model incremental update is triggered.

2. The method according to claim 1, characterized in that, In step S3, the inference state context includes the number of the currently completed micro-inference stage, the activation value cache of each intermediate layer, and the cumulative inference time count. The inference state context is stored in a cache line aligned manner. The remaining time interval is estimated based on the exponentially weighted moving average of the current packet receiving queue depth and the recent packet arrival interval.

3. The method according to claim 1, characterized in that, In step S1, the forwarding load-aware compression includes gap-adaptive structured pruning. Guided by the requirement that the execution time of each layer of micro-computing blocks meets the gap constraint, the convolutional kernel or fully connected weight matrix is ​​structured and pruned by row or column. Prioritize the removal of structural units that reduce the execution time of the corresponding micro-computing block to below the preset quantile value and have the least impact on detection accuracy after pruning. After each round of pruning, the execution time of the micro-computing block is measured on the processor of the smart network card to verify the gap constraint.

4. The method according to claim 3, characterized in that, Step S1 also includes performing cache-aligned mixed-precision quantization on the pruned model. The quantization bit width is allocated according to the ratio between the amount of weight data accessed by each microcomputation block and the capacity of the final cache of the processor on the smart network card. When the amount of weight data of the microcomputation block can completely reside in the final cache at the corresponding bit width, the bit width is used for quantization.

5. The method according to claim 1, characterized in that, In step S5, during the hardware flow table matching process in step S2, incremental accumulation of online mean and online variance is performed on the flow-level feature vectors simultaneously; the drift detection microtask uses a simplified Mahalanobis distance metric based on online mean and online variance to calculate the divergence value between the current statistic and the reference distribution. When the divergence value continuously exceeds the drift alarm threshold and reaches the preset confirmation window length, an incremental update is triggered that is only performed on the weight parameters of the abnormal scoring layer. The incremental update is decomposed into a sequence of micro-tasks and executed with the lowest priority in the packet processing interval. After the update is completed, the parameters are switched in an atomic operation manner.

6. The method according to claim 1, characterized in that, Step S3 also includes an inference timeout management mechanism, which sets a maximum allowable completion time limit for the inference process of each data stream to be detected. The time limit is measured by the number of data packets that the data stream has passed since entering the inference queue. When the inference process has not completed all micro-inference stages within the time limit, the handling strategy of the data stream is upgraded to conservative blocking or rate limiting.

7. The method according to claim 1, characterized in that, In step S3, the inference scheduler performs adaptive phase merging based on the real-time monitored packet processing gap duration. When the gap is sufficient, adjacent micro-inference phases are merged into consecutive execution batches, and the execution time after merging does not exceed a preset proportion of the gap margin. Before the current packet processing is completed, the inference state context of the next pending flow in the inference queue is preloaded into the cache according to the identifier of the next pending flow.

8. The method according to claim 1, characterized in that, In step S3, the inference queue adopts a priority sorting strategy based on risk weights. The risk weights take into account the initial risk assessment value when the data stream is assigned to the detection level in step S2 and the length of time the data stream has been waiting in the inference queue.

9. The method according to claim 1, characterized in that, In step S2, a dynamic threshold adjustment mechanism is set. When the backlog depth of the model inference queue exceeds the preset upper limit, the matching leniency of the trusted release level is increased and the trigger threshold of the high-risk blocking level is reduced to reduce the amount of traffic entering the inference queue. When the backlog depth of the inference queue falls back to the normal level, the original threshold setting is restored.

10. A real-time monitoring and defense system for abnormal traffic of intelligent network interface cards based on a lightweight model, characterized in that, include: The model compression module is used to perform forwarding load-aware compression on the benchmark anomaly detection model. It divides each layer of the model into micro-computation blocks according to the amount of computation. The execution time of each micro-computation block does not exceed the preset quantile value of the duration distribution of the packet processing gap on the processor card. The traffic pre-screening module is used to pre-screen incoming traffic into three levels: trusted to allow, high-risk to block, and to be detected, using the smart network interface card hardware flow table matching engine. The micro-inference scheduling module is used to maintain the inference state context for each data stream to be detected. It decomposes the inference process of the compressed model into an ordered sequence of micro-inference stages. In the main loop of the packet processing pipeline, when the remaining time interval after the current packet forwarding is greater than the sum of the execution time of the micro-computation block and the safety margin, the highest priority data stream to be detected is taken from the inference queue to execute its next micro-inference stage. After updating the inference state context, it returns to the main loop of packet processing. The tiered defense module is used to trigger tiered defense actions such as allowing passage, limiting speed, or blocking based on the comparison results between the anomaly probability score output after completing all micro-inference stages and multi-level thresholds. The drift monitoring module is used to schedule drift detection calculations as low-priority microtasks during packet processing intervals. When the distribution divergence value exceeds the drift alarm threshold, it triggers incremental model updates.

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