Method of forming flash memory

Abstract

The present application provides a method for forming a flash memory, the method includes forming an isolation structure around a plurality of active regions, forming a plurality of first gate electrode layers on the active regions, depositing a first silicon oxide layer along the upper surfaces and sidewalls of the first gate electrode layers and the upper surface of the isolation structure, performing a first dry etching process to thin the first silicon oxide layer, performing a first wet etching process to remove the first silicon oxide layer and recess the isolation structure, and forming a second gate electrode layer around the first gate electrode layers.

Description

Technical Field

[0001] This invention relates to a method for forming a flash memory, and more particularly to a method for forming a floating gate electrode layer of a flash memory. Background Technology

[0002] To increase the component density within flash memory devices and improve their overall performance, flash memory device manufacturing technology continues to strive towards miniaturization of component size, which is also an important issue that needs to be addressed in improving the process. Summary of the Invention

[0003] This invention provides a method for forming a flash memory. The method includes forming an isolation structure around a plurality of active regions, forming a plurality of first gate electrode layers respectively on the active regions, depositing a first silicon oxide layer along the upper surface and sidewalls of the first gate electrode layers and the upper surface of the isolation structure, performing a first dry etching process to thin the first silicon oxide layer, performing a first wet etching process to remove the first silicon oxide layer and etch the isolation structure, and forming a second gate electrode layer around the first gate electrode layers.

[0004] This invention provides a method for forming a flash memory. The method includes forming an elongated pattern on a semiconductor substrate, the elongated pattern including an active region and a masking layer above the active region. The method further includes forming an isolation structure around the elongated pattern, removing the masking layer of the elongated pattern, forming a floating gate electrode layer above the active region, and trimming the floating gate electrode layer. Trimming includes oxidizing a first portion of the floating gate electrode layer to form a first silicon oxide layer. The method further includes performing a wet etching process to remove the first silicon oxide layer and etch the isolation structure, and forming a control gate electrode layer on the isolation structure and the floating gate electrode layer.

[0005] Based on the above, embodiments of the present invention provide a flash memory and a method for forming the same. Embodiments of the present invention utilize one or more cycles of trimming, dry etching, and wet etching processes to precisely control the floating gate electrode layer to have a desired profile, while simultaneously controlling the isolation structure to be etched to a desired depth. Therefore, the risk of defects forming in the floating gate electrode layer and / or within the control gate electrode layer is reduced, which improves the yield and reliability of the semiconductor memory device, and also enhances the performance of the semiconductor memory device. Attached Figure Description

[0006] To make the features and advantages of the present invention more apparent and understandable, different embodiments are described below in detail with reference to the accompanying drawings:

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 These are cross-sectional schematic diagrams showing different stages of forming a flash memory according to some embodiments of the present invention.

[0008] Figure 13 This is a schematic diagram illustrating the relationship between the number of atomic layer deposition cycles and silicon consumption according to some embodiments of the present invention.

[0009] Symbol Explanation

[0010] 101: Long strip pattern

[0011] 102H: Noodles

[0012] 104: Active Zone

[0013] 106: Pad oxide layer

[0014] 108: Masking layer

[0015] 110: Isolation Structure

[0016] 110T1, 110T2: Upper surface

[0017] 112: Trench

[0018] 114: Tunneling oxide layer

[0019] 116': Electrode material

[0020] 116: Floating gate electrode layer

[0021] 118: Trench

[0022] 120: First silicon oxide layer

[0023] 122: Second silicon oxide layer

[0024] 124: Third silicon oxide layer

[0025] 126: Fourth silicon oxide layer

[0026] 128: Intergate dielectric structure

[0027] 130, 134: Oxide layer

[0028] 132: Nitride layer

[0029] 136: Control gate electrode layer

[0030] 1000, 1000': Trimming

[0031] 1050, 1050': Dry etching process

[0032] 1100, 1100': Wet etching process

[0033] Angles A1, A2, and A3

[0034] Depths D1, D2, and D3

[0035] T1, T1', T1", T2, T3, T4: Thickness Detailed Implementation

[0036] refer to Figure 1 Multiple elongated patterns 101 are formed on a semiconductor substrate (not shown). In some embodiments, the semiconductor substrate is an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, the semiconductor substrate may be a semiconductor-on-insulator (SOI) substrate.

[0037] The elongated pattern 101 includes an active region 104, a pad oxide layer 106, and a mask layer 108. Forming the elongated pattern 101 includes sequentially forming the pad oxide layer 106 and the mask layer 108 on a semiconductor substrate, and then performing a patterning process on the mask layer 108, the pad oxide layer 106, and the semiconductor substrate to form multiple trenches and an elongated pattern 101 protruding from between the trenches.

[0038] In some embodiments, the pad oxide layer 106 is a silicon oxide layer, which can be formed by thermal oxidation, in-situ steam generation (ISSG), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The mask layer 108 is a silicon nitride layer, which can be formed by chemical vapor deposition or atomic layer deposition. The portion of the semiconductor substrate protruding from between the trenches forms the active region 104.

[0039] An isolation structure 110 is formed to fill the trenches and surround the strip pattern 101. The isolation structure 110 may comprise multiple silicon oxide layers formed by different deposition techniques. For example, a high aspect ratio (HARP) process can be used to deposit a liner oxide layer along the sidewalls and top surface of the strip pattern 101, followed by the deposition of a spin-coated glass (SOG) on top of the liner oxide layer and the trenches. The spin-coated glass is then annealed, planarized by chemical mechanical polishing (CMP), and etched to re-form trenches between the strip patterns 101.

[0040] Subsequently, a silicon oxide layer was deposited on the spin-coated glass using high-density plasma chemical vapor deposition (HDPCVD), and the trenches were overfilled. The HDPCVD silicon oxide layer was then planarized by chemical mechanical polishing (CMP) until the mask layer 108 was exposed. Although Figure 1 There is no physical boundary between the isolation structure 110 and the pad oxide layer 106, however, in other embodiments, there may be a physical boundary between them.

[0041] refer to Figure 2 The mask layer 108 of the elongated pattern 101 is removed using an etching process (e.g., wet etching) to form a trench 112. Next, an etching process (e.g., wet etching) is performed to shrink the isolation structure 110, thereby laterally expanding the trench 112. Enlarging the trench 112 reduces the difficulty of subsequent deposition of the floating gate electrode layer, for example, reducing the risk of voids or seams forming within the floating gate electrode layer, thereby improving the yield and reliability of the semiconductor memory device. Furthermore, it can improve the gate coupling ratio between the control gate electrode layer and the floating gate electrode layer.

[0042] Next, a tunneling oxide layer 114 is formed on the upper surface of the active region 104. Forming the tunneling oxide layer 114 involves etching the pad oxide layer 106 using a cleaning process (e.g., a wet etching process), followed by oxidizing the active region 104 using in-situ vapor generation to form silicon oxide on the remaining pad oxide layer 106. Thinning the pad oxide layer 106 using a cleaning process and forming silicon oxide using in-situ vapor generation improves the quality of the tunneling oxide layer 114.

[0043] refer to Figure 3 Electrode material 116' is formed in Figure 2 On top of the semiconductor structure, trenches 112 are overfilled and an isolation structure 110 is covered. The electrode material 116' can be polysilicon, amorphous silicon, or a combination thereof. Chemical vapor deposition electrode material 116' can be used.

[0044] refer to Figure 4 The electrode material 116' is planarized by chemical mechanical polishing to expose the upper surface of the isolation structure 110. The remaining electrode material 116' forms a floating gate electrode layer 116, which is located above the active region 104.

[0045] refer to Figure 5The isolation structure 110 is etched using an etching process (e.g., wet etching) to form a trench 118 that partially exposes the sidewalls of the floating gate electrode layer 116. The ratio (D1 / T1) of the depth D1 of the trench 118 to the thickness T1 of the floating gate electrode layer 116 ranges from about 1 / 10 to about 7 / 10. The sidewalls of the floating gate electrode layer 116 intersect a surface 102H parallel to the main surface of the semiconductor substrate 102 on the outer side of the floating gate electrode layer 116 at an angle A1 (sidewall angle), which ranges from about 90 degrees to about 93 degrees.

[0046] Figure 6 , Figure 7 , Figure 8 This describes the first cycle of finishing process 1000, dry etching process 1050, and wet etching process 1100, which is used to adjust the contour of the floating gate electrode layer 116 and the etching depth of the isolation structure 110. (Reference) Figure 6 The gate electrode layer 116 is then trimmed 1000. Trimming 1000 includes depositing a first silicon oxide layer 120. The first silicon oxide layer 120 extends over the upper surface and exposed sidewalls of the floating gate electrode layer 116, and over the upper surface of the isolation structure 110. In one embodiment, the deposition process is an atomic layer deposition process. The atomic layer deposition process can be a thermal atomic layer deposition process or a plasma-enhanced atomic layer deposition process.

[0047] Atomic layer deposition can comprise multiple stages, such as a heating stage, a deposition stage, a cooling stage, and / or other suitable stages. In embodiments using thermal atomic layer deposition, the deposition stage of atomic layer deposition can comprise multiple cycles, for example, 10 to 300 cycles. Each cycle sequentially comprises (1) introducing a silicon-containing precursor into the deposition chamber, wherein the silicon-containing precursor is adsorbed onto active vacancies on the surface of the chip; (2) vacuuming and purging the silicon-containing precursor; (3) introducing an oxygen-containing precursor into the deposition chamber, wherein the oxygen-containing precursor reacts with the silicon precursor adsorbed on the vacancies to form a monolayer of the first silicon oxide layer 120; and (4) vacuuming and purging the oxygen-containing precursor and reaction byproducts. The deposition stage cycle can continue until the first silicon oxide layer 120 has the desired thickness.

[0048] The silicon-containing precursor may be hexachlorodisilane (Si₂Cl₆), bis(diethylamino)silane (BDEAS), and / or combinations thereof. The oxygen-containing precursor may be a mixture of oxygen radicals, hydrogen radicals, and hydroxyl radicals, which can be formed by homolytic cracking through the flow of a mixture of oxygen (O₂) and hydrogen (H₂) into the deposition chamber. In some embodiments, the ratio of hydrogen flow rate to oxygen flow rate ranges from about 0.1 to about 0.3. Hydrogen can facilitate homolytic cracking of oxygen, increasing the concentration of oxygen radicals.

[0049] In embodiments using thermal atomic layer deposition (TLD), atomic layer deposition can be a high-temperature process in a furnace tube apparatus that processes multiple batches of chips at once, also known as batch isotropic oxidation. In some embodiments, atomic layer deposition can be performed at a temperature of about 500 degrees Celsius to about 800 degrees Celsius, or it can be a low-temperature process of about 50 degrees Celsius to about 100 degrees Celsius for monolithic applications. In embodiments using plasma-enhanced atomic layer deposition (PELD), the oxygen-containing precursor can be oxygen plasma.

[0050] During each cycle of the oxygen-containing precursor introduction step, oxygen radicals can diffuse through one or more monolayers of the first silicon oxide layer 120 to reach the surface of the floating gate electrode layer 116. The semiconductor material (e.g., silicon) of the floating gate electrode layer 116 is consumed by oxidation from the oxygen radicals. Thus, during the atomic layer deposition process of the first silicon oxide layer 120, the contour of the floating gate electrode layer 116 is trimmed, and a second silicon oxide layer 122 (displayed only on one floating gate electrode layer 116 for illustrative purposes) is formed. Since the amount of oxidation is negatively correlated with the diffusion distance, the amount of consumption of the floating gate electrode layer 116 can gradually decrease from top to bottom. That is, the width of the portion of the second silicon oxide layer 122 on the side of the floating gate electrode layer 116 gradually decreases from top to bottom. The second silicon oxide layer 122 may have different material properties than the first silicon oxide layer 120, such as lattice structure, crystallinity, etc. The second silicon oxide layer 122 is also formed on the top surface of the floating gate electrode layer 116.

[0051] Figure 13This is a schematic diagram illustrating the relationship between the number of atomic layer deposition cycles and silicon consumption. In one embodiment, the trimming process 1000 uses a thermal atomic layer deposition process at 600 degrees Celsius. As the number of deposition stages increases, the silicon consumption of the floating gate electrode layer 116 increases accordingly. In some embodiments, the silicon consumption rate is not constant. For example, the silicon consumption rate may decrease as the number of cycles increases. For example, the silicon consumption rate in the early stages of a cycle may be higher than the silicon consumption rate in the later stages of a cycle. In other embodiments, the silicon consumption rate may be constant.

[0052] refer to Figure 7 A dry etching process 1050 is performed on the first silicon oxide layer 120 to reduce its thickness. The dry etching process 1050 may use fluorocarbon plasma as the etchant. After the dry etching process 1050, the first silicon oxide layer 120 has a thickness T2 along the sidewall of the floating gate electrode layer 116, a thickness T3 along the upper surface of the floating gate electrode layer 116, and a thickness T4 along the upper surface of the isolation structure 110. Thickness T2 is greater than thickness T3 and greater than thickness T4. In some embodiments, the first silicon oxide layer 120 is not completely removed along the upper surface of the floating gate electrode layer 116 (thickness T3 is greater than zero), which avoids plasma damage to the gate electrode layer 116 from the dry etching process 1050, thereby improving the yield and reliability of the semiconductor memory device. In some embodiments, the dry etching process 1050 can remove a portion of the first silicon oxide layer 120 along the upper surface of the isolation structure 110 (i.e., the thickness T4 is zero) to expose the upper surface of the isolation structure 110.

[0053] refer to Figure 8 A wet etching process 1100 is performed. The wet etching process 1100 may use a buffered hydrofluoric acid solution (BHF). The wet etching process 1100 removes the first silicon oxide layer 120 and the second silicon oxide layer 122, and etches the isolation structure 110 to vertically enlarge the trench 118. The ratio (D2 / T1') of the trench depth D2 to the thickness T1' of the floating gate electrode layer 116 ranges from about 1 / 5 to about 4 / 5. The ratio (D2 / T1') is greater than the ratio (D1 / T1). The thickness T1' is less than the thickness T1 because of the oxidation on the upper part of the floating gate electrode layer 116.

[0054] The trimming process 1000 gives the top of the trench 118 a larger opening width, which can improve the difficulty of subsequent deposition of the control gate electrode layer, such as avoiding the formation of voids or seams in the control gate electrode layer, thereby improving the yield and reliability of semiconductor memory devices.

[0055] In some embodiments, since the thickness T2 of the first silicon oxide layer 120 along the sidewall of the floating gate electrode layer 116 is greater than the thickness T4 of the first silicon oxide layer 120 along the upper surface of the isolation structure 110, the depth D2 can be controlled to a deeper position. Furthermore, this also helps the etched upper surface 110T1 of the isolation structure 110 to have a V-shaped profile, which helps reduce the parasitic capacitance between the floating gate electrode layers 116, thereby improving the program / erase efficiency of the flash memory device.

[0056] After wet etching process 1100, the sidewall of the floating gate electrode layer 116 and the surface 102H parallel to the main surface of the semiconductor substrate 102 intersect at an angle A2 (sidewall angle) on the side outside the floating gate electrode layer 116, which ranges from about 91 degrees to about 98 degrees. Angle A2 is greater than angle A1.

[0057] Figure 9 , Figure 10 , Figure 11 This describes the second cycle of finishing process 1000, dry etching process 1050, and wet etching process 1100 to further adjust the contour of the floating gate electrode layer 116 and the etching depth of the isolation structure 110. (Reference) Figure 9 A trimming process 1000' is performed on the gate electrode layer 116. Trimming process 1000' includes depositing a third silicon oxide layer 124, which extends over the upper surface and exposed sidewalls of the floating gate electrode layer 116, as well as the upper surface of the isolation structure 110. In one embodiment, the deposition process is an atomic layer deposition process. During the atomic layer deposition process of the third silicon oxide layer 124, the floating gate electrode layer 116 is oxidized to form a fourth silicon oxide layer 126, thereby trimming the contour of the floating gate electrode layer 116. Trimming process 1000' may be similar to trimming process 1000, but may use process parameters different from trimming process 1000 (e.g., number of cycles, temperature, etc.).

[0058] refer to Figure 10 A dry etching process 1050' is performed on the third silicon oxide layer 124 to reduce its thickness. In some embodiments, the third silicon oxide layer 124 may be removed along the upper surface of the isolation structure 110 to expose the upper surface of the isolation structure 110. The dry etching process 1050' may be similar to the dry etching process 1050, but may use process parameters different from those of the dry etching process 1050 (e.g., process time, plasma power, etc.).

[0059] refer to Figure 11An etching process (e.g., wet etching) 1100' is performed on the third silicon oxide layer 124 and the fourth silicon oxide layer 126. The wet etching process 1100' completely removes the third silicon oxide layer 124 and the fourth silicon oxide layer 126, and etches the isolation structure 110 to further vertically enlarge the trench 118. The wet etching process 1100' may be similar to the wet etching process 1100, but may use different process parameters (e.g., process time) than the wet etching process 1100.

[0060] The ratio (D3 / T1") of the trench depth D3 to the thickness T1” of the floating gate electrode layer 116 ranges from about 3 / 10 to about 9 / 10. This ratio (D3 / T1”) is greater than the ratio (D2 / T1’). The thickness T1” can be less than the thickness T1’ due to oxidation on the upper part of the floating gate electrode layer 116. After the wet etching process 1100’, the sidewall of the floating gate electrode layer 116 intersects the surface 102H parallel to the main surface of the semiconductor substrate 102 on the outer side of the floating gate electrode layer 116 at an angle A3 (sidewall angle), which ranges from about 92 degrees to about 99 degrees. Angle A3 is greater than angle A2. Furthermore, the etched upper surface 110T2 of the isolation structure 110 can have a smaller radius of curvature than the upper surface 110T1.

[0061] Although the method embodiments use a cycle of two trimming processes 1000, a dry etching process 1050, and a wet etching process 1100, the embodiments of the present invention are not limited thereto. Only one cycle may be performed, or multiple cycles (e.g., 3-4), depending on the desired profile of the floating gate electrode layer 116 and / or the desired depth of the isolation structure 110. For example, excessive consumption of the floating gate electrode layer 116 may reduce the gate coupling ratio between the control gate electrode layer and the floating gate electrode layer; insufficient consumption of the floating gate electrode layer 116 may increase the risk of voids or seams forming within the control gate electrode layer. Trench 118 that is too shallow increases parasitic capacitance between the floating gate electrode layers 116; trench 118 that is too deep increases the risk of unintentionally opening channels in the control gate electrode layer.

[0062] refer to Figure 12 A gate-to-gate dielectric structure 128 is formed along the upper surface and sidewalls of the floating gate electrode layer 116 and the upper surface 110T2 of the isolation structure 110 to partially fill the trench 118. Next, a control gate electrode layer 136 is formed on the gate-to-gate dielectric structure 128 to overfill the trench 118, thereby fabricating a flash memory, such as a NOR flash memory.

[0063] The inter-gate dielectric structure 128 may be a three-layer structure comprising an oxide layer 130, a nitride layer 132, and an oxide layer 134. The control gate electrode layer 136 is formed of a conductive material, such as polysilicon, amorphous silicon, or a combination thereof, and / or other conductive materials. The inter-gate dielectric structure 128 and the control gate electrode layer 136 may be formed using chemical vapor deposition (CVD).

[0064] Based on the above, embodiments of the present invention provide a flash memory and a method for forming the same. Embodiments of the present invention utilize one or more cycles of trimming, dry etching, and wet etching processes to precisely control the floating gate electrode layer to have a desired profile, while simultaneously controlling the isolation structure to be etched to a desired depth. Therefore, the risk of defects forming in the floating gate electrode layer and / or within the control gate electrode layer is reduced, which improves the yield and reliability of the semiconductor memory device, and also enhances the performance of the semiconductor memory device.

[0065] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the claims.

Claims

1. A method for forming a flash memory, characterized in that, include: A separate structure is formed around multiple active regions; Multiple first gate electrode layers are formed on these active regions respectively; A first silicon oxide layer is deposited along the upper surface and sidewalls of these first gate electrode layers and the upper surface of the isolation structure; A first dry etching process is performed to thin the first silicon oxide layer; A first wet etching process is performed to remove the first silicon oxide layer and etch the isolation structure. as well as A second gate electrode layer is formed around these first gate electrode layers.

2. The method for forming a flash memory as described in claim 1, characterized in that, The step of depositing the first silicon oxide layer includes an atomic layer deposition process.

3. The method for forming a flash memory as described in claim 1, characterized in that, The steps for depositing the first silicon oxide layer include: Introduce a silicon-containing precursor; and An oxygen-containing precursor is introduced, wherein the silicon-containing precursor reacts with the oxygen-containing precursor to form the first silicon oxide layer.

4. The method for forming a flash memory as described in claim 3, characterized in that, The oxygen-containing precursor diffuses through the first silicon oxide layer and oxidizes the first gate electrode layers to form a plurality of second silicon oxide layers on the first gate electrode layers respectively.

5. The method for forming a flash memory as described in claim 1, characterized in that, The etched surface of the isolation structure gives it a V-shaped upper surface.

6. The method for forming a flash memory as described in claim 1, characterized in that, After the first dry etching process, the first silicon oxide layer remains covering the upper surfaces and sidewalls of the first gate electrode layers.

7. The method for forming a flash memory as described in claim 1, characterized in that, After the first dry etching process, the first silicon oxide layers have a first thickness along the sidewalls of the first gate electrode layers, and the first silicon oxide layers have a second thickness along the upper surface of the isolation structure, and the second thickness is less than the first thickness.

8. The method for forming a flash memory as described in claim 1, characterized in that, Furthermore, this includes the process prior to forming the second gate electrode layer around these first gate electrode layers: A second silicon oxide layer is deposited along the upper surfaces and sidewalls of the first gate electrode layers and the upper surface of the isolation structure; A second dry etching process is performed to thin the second silicon oxide layer; as well as A second wet etching process is performed to remove the second silicon oxide layer and etch the isolation structure. The first wet etching process etches the isolation structure to form a first trench, and the depth of the first trench is a first ratio to the thickness of the first gate electrode layer. The second wet etching process etches the isolation structure to form a second trench, and the depth of the second trench is a second ratio to the thickness of the first gate electrode layer, and the second ratio is greater than the first ratio.

9. The method for forming a flash memory as described in claim 8, characterized in that, During the deposition of the second silicon oxide layer, the first gate electrode layers are oxidized to form a plurality of third silicon oxide layers on the first gate electrode layers respectively.

10. A method for forming a flash memory, characterized in that, include: A strip pattern is formed on a semiconductor substrate, wherein the strip pattern includes an active region and a masking layer on the active region; A separating structure is formed around the long strip pattern; Remove the mask layer of the long strip pattern; A floating gate electrode layer is formed on the active region; The floating gate electrode layer is modified by a first modification process, the first modification process including oxidizing a first portion of the floating gate electrode layer to form a first silicon oxide layer. A first wet etching process is performed to remove the first silicon oxide layer and etch the isolation structure. as well as A control gate electrode layer is formed on the isolation structure and the floating gate electrode layer.

11. The method for forming a flash memory as described in claim 10, characterized in that: Prior to the first trimming process, the sidewall of the floating gate electrode layer intersects a surface parallel to a surface of a semiconductor substrate at a first sidewall angle; and After the first trimming process, the sidewall of the floating gate electrode layer intersects with a side of the surface parallel to the semiconductor substrate at a second sidewall angle, which is greater than the first sidewall angle.

12. The method for forming a flash memory as described in claim 10, characterized in that, The first trimming process includes performing a deposition process having multiple cycles to form a second silicon oxide layer, wherein during the deposition process, the first portion of the floating gate electrode layer is oxidized to form the first silicon oxide layer.

13. The method for forming a flash memory as described in claim 12, characterized in that: Each cycle of this deposition process includes: Introduce a silicon-containing precursor; and A mixture of hydrogen and oxygen is introduced, wherein the oxygen homolytically cleaves to form oxygen free radicals.

14. The method for forming a flash memory as described in claim 13, characterized in that: The oxygen free radical diffuses through the second silicon oxide layer to the floating gate electrode layer to oxidize the first portion of the floating gate electrode layer; In a first cycle of these cycles, the floating gate electrode layer is oxidized at a first rate; In a second cycle of these cycles, the floating gate electrode layer is oxidized at a second rate; The second cycle is performed after the first cycle; as well as The second rate is lower than the first rate.

15. The method for forming a flash memory as described in claim 12, characterized in that, The second silicon oxide layer is further removed by performing the first wet etching process.

16. The method for forming a flash memory as described in claim 12, characterized in that, It further includes: after the first trimming process and before the first wet etching process: performing a dry etching process to partially etch the second silicon oxide layer.

17. The method for forming a flash memory as described in claim 10, characterized in that, Including: An inter-gate dielectric structure is formed on the floating gate electrode layer, wherein the control gate electrode layer is formed on the inter-gate dielectric structure.

18. The method for forming a flash memory as described in claim 10, characterized in that, Furthermore, this includes the process after the first wet process and before the formation of the control gate electrode layer: A second trimming process is performed on the floating gate electrode layer, the second trimming process including a deposition process to form a second silicon oxide layer, wherein during the deposition process, a second portion of the floating gate electrode layer is oxidized to form the third silicon oxide layer. A dry etching process is performed to partially etch the second silicon oxide layer; as well as A second wet etching process is performed to remove the second silicon oxide layer and the third silicon oxide layer and to etch the isolation structure.

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