MIS-hemt power device and manufacturing method thereof

Abstract

The application discloses a MIS-HEMT power device and a manufacturing method thereof. The MIS-HEMT power device comprises an epitaxial structure, a source electrode, a drain electrode and a gate electrode matched with the epitaxial structure, and a gate dielectric layer, the epitaxial structure has a two-dimensional electron gas, the source electrode and the drain electrode are electrically connected through the two-dimensional electron gas, the gate dielectric layer comprises an insulating high-resistance TaN thin film arranged on the epitaxial structure, and the gate electrode is arranged on the high-resistance TaN thin film. The application can effectively reduce the bombardment damage to the surface of a semiconductor material when a thin film is grown by magnetron sputtering, the MIS-HEMT device has small gate leakage, low off-state loss, good interface state quality, high withstand voltage and stable dynamic performance, compared with a single-layer silicon nitride gate dielectric, the dielectric can effectively reduce the influence of the body defects of the silicon nitride material on the overall performance of the device.

Description

Technical Field

[0001] This invention specifically relates to a MIS-HEMT power device and its fabrication method, belonging to the fields of GaN HEMT power devices and micro / nano fabrication technology. Background Technology

[0002] Third-generation semiconductor materials possess characteristics such as wider band gaps, higher thermal conductivity, higher radiation resistance, and greater electron saturation drift velocity. Nitride semiconductors, as important third-generation semiconductor materials, have large band gaps, high electron mobility, high breakdown electric fields, and high electron saturation drift velocities, and are widely used in industries such as power systems, transportation, communications, and consumer electronics.

[0003] AlGaN / GaN semiconductor heterojunctions can form high concentrations (>10) due to spontaneous polarization and piezoelectric polarization. 13 cm -2 ) and high electron mobility (>10 3 cm 2 A two-dimensional electron gas (electron gas) of 1 / V·s. High electron mobility transistors (HEMTs) fabricated based on this characteristic of nitride semiconductor heterojunctions can operate at frequencies up to 10MHz as power switching devices. Depletion-type HEMTs require a negative bias applied to the gate to deplete the two-dimensional electron gas beneath it in order to turn the HEMT off. However, leakage current is often encountered under the gate in these devices, necessitating the introduction of an insulating layer to form a metal-insulator-semiconductor (MISHEMT) structure. Summary of the Invention

[0004] The main objective of this invention is to provide a MIS-HEMT power device and its fabrication method, thereby overcoming the shortcomings of the prior art.

[0005] To achieve the aforementioned objectives, the technical solution adopted by this invention includes: A first aspect of the present invention provides a MIS-HEMT power device, including an epitaxial structure and a source, drain and gate matched with the epitaxial structure, wherein the epitaxial structure has a two-dimensional electron gas, the source and the drain are electrically connected through the two-dimensional electron gas, and the MIS-HEMT power device further includes: a gate dielectric layer, the gate dielectric layer including an insulating high-resistivity TaN thin film, and the gate disposed on the high-resistivity TaN thin film.

[0006] A second aspect of this invention provides a method for fabricating a MIS-HEMT power device, including a step of fabricating an epitaxial structure and a step of fabricating a source, drain, and gate electrode matching the epitaxial structure, wherein the epitaxial structure has a two-dimensional electron gas, and the source and drain are electrically connected via the two-dimensional electron gas. The method for fabricating a MIS-HEMT power device further includes: An insulating high-resistivity TaN thin film is fabricated on the epitaxial structure to form a gate dielectric layer, and the gate is disposed on the high-resistivity TaN thin film.

[0007] Compared with the prior art, the advantages of the present invention include: This invention can effectively reduce the bombardment damage to the semiconductor material surface during magnetron sputtering growth of thin films. Furthermore, the fabrication process of this invention is simple and time-saving, and the resulting MIS-HEMT device has low gate leakage current, low off-state loss, good interface state quality, high withstand voltage, and stable dynamic performance. Compared with single-layer silicon nitride gate dielectric, the dielectric can effectively reduce the impact of bulk defects of silicon nitride material itself on the overall performance of the device. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the structure of a GaN MIS-HEMT power device with a single-layer gate dielectric layer provided in a typical embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a GaN MIS-HEMT power device with a high-resistivity TaN / SiN gate dielectric layer provided in a typical embodiment of the present invention; Figures 3a to 3e This diagram illustrates a fabrication process of a GaN MIS-HEMT power device with a high-resistivity TaN / SiN gate dielectric layer, provided in a typical embodiment of the present invention. Figures 4a-4d The transfer, output, withstand voltage, and dynamic characteristics test results of the GaN MIS-HEMT power device with a high-resistivity TaN / SiN gate dielectric layer and the GaN MIS-HEMT power device with different gate dielectric layers in Embodiment 1 of the present invention are shown respectively. Figures 5a-5d The transfer characteristic curves, withstand voltage curves, breakdown characteristic curves, and current collapse characteristic curves of the GaN MIS-HEMT power device with TaN gate dielectric and the GaN MIS-HEMT power device with Al2O3 gate dielectric in Embodiment 2 of the present invention are shown respectively. Detailed Implementation

[0009] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0010] This invention applies a high-resistivity TaN layer to HEMT devices, which greatly improves the performance of HEMT devices. Under certain conditions, appropriate high-resistivity TaN preparation parameters and special processing methods are required to prepare stable high-resistivity TaN films and improve device performance.

[0011] A first aspect of the present invention provides a MIS-HEMT power device, including an epitaxial structure and a source, drain and gate matched with the epitaxial structure, wherein the epitaxial structure has a two-dimensional electron gas, the source and the drain are electrically connected through the two-dimensional electron gas, and the MIS-HEMT power device further includes: a gate dielectric layer, the gate dielectric layer including an insulating high-resistivity TaN thin film, and the gate disposed on the high-resistivity TaN thin film.

[0012] Furthermore, the thickness of the high-resistivity TaN film is 2 nm to 100 nm, preferably 5 nm to 40 nm.

[0013] Furthermore, the high-resistivity TaN thin film is grown by magnetron sputtering, and the high-resistivity TaN thin film is annealed at 350℃~450℃ for 3 min~10 min.

[0014] Furthermore, the magnetron sputtering process used to grow the high-resistivity TaN thin film employs a sputtering power of 100 W to 300 W, with a nitrogen to argon flow rate ratio of (2~3):(4~5).

[0015] Furthermore, the nitrogen flow rate during the magnetron sputtering process for growing the high-resistivity TaN thin film is 20 sccm to 25 sccm, and the argon flow rate is 30 sccm to 50 sccm.

[0016] In another more specific embodiment, the gate dielectric layer further includes an insertion protection layer, which is stacked on the epitaxial structure, and the high-resistivity TaN thin film is disposed on the insertion protection layer.

[0017] Furthermore, the inserted protective layer includes at least one of SiN film, Al2O3 film, and SiO2 film, but is not limited thereto.

[0018] Furthermore, the thickness ratio of the inserted protective layer in the gate dielectric layer is (1~3) / (7~9).

[0019] Furthermore, the thickness of the inserted protective layer is 2 nm to 20 nm, preferably 2 nm to 6 nm.

[0020] Furthermore, the inserted protective layer is grown using any one of the following processes: low-pressure chemical vapor deposition (LPCVD), plasma-enhanced atomic layer deposition (PEALD), or atomic layer deposition (ALD).

[0021] In a more specific embodiment, the gate dielectric layer is grown by the following method: The insertion protective layer is grown on the epitaxial structure using any one of the following processes: low-pressure chemical vapor deposition, plasma-enhanced atomic layer deposition, and atomic layer deposition. A high-resistivity TaN thin film is grown on the insertion protective layer using a magnetron sputtering process to form the gate dielectric layer; The epitaxial structure with the gate dielectric layer formed thereon is annealed at 350°C to 450°C for 3 min to 10 min.

[0022] Furthermore, the epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked sequentially. The first semiconductor layer and the second semiconductor layer cooperate to form a heterojunction. A two-dimensional electron gas is formed between the first semiconductor layer and the second semiconductor layer. The third semiconductor layer is disposed between the source region and the drain region. The third semiconductor layer is used to deplete the two-dimensional electron gas located in the region below it. The gate dielectric layer is stacked on the third semiconductor layer.

[0023] Furthermore, both the first semiconductor layer and the second semiconductor layer are made of III-V compound materials, but are not limited thereto.

[0024] Furthermore, the material of the first semiconductor layer includes GaN, but is not limited to this.

[0025] Furthermore, the material of the second semiconductor layer includes AlGaN, but is not limited to this.

[0026] Furthermore, the material of the third semiconductor layer includes GaN-CaP, but is not limited to this.

[0027] A second aspect of this invention provides a method for fabricating a MIS-HEMT power device, including a step of fabricating an epitaxial structure and a step of fabricating a source, drain, and gate electrode matching the epitaxial structure, wherein the epitaxial structure has a two-dimensional electron gas, and the source and drain are electrically connected via the two-dimensional electron gas. The method for fabricating a MIS-HEMT power device further includes: An insulating high-resistivity TaN thin film is fabricated on the epitaxial structure to form a gate dielectric layer, and the gate is disposed on the high-resistivity TaN thin film.

[0028] Furthermore, the fabrication method of the MIS-HEMT power device specifically includes: growing the high-resistivity TaN thin film using a magnetron sputtering process, wherein the sputtering power used in growing the high-resistivity TaN thin film is 100 W to 300 W, and the flow rate ratio of nitrogen to argon is (2~3):(4~5). The epitaxial structure with the high-resistivity TaN thin film formed thereon was annealed at 350°C to 450°C for 3 min to 10 min.

[0029] Furthermore, the nitrogen flow rate during the magnetron sputtering process for growing the high-resistivity TaN thin film is 20 sccm to 25 sccm, and the argon flow rate is 30 sccm to 50 sccm.

[0030] Furthermore, the thickness of the high-resistivity TaN film is 2 nm to 100 nm, preferably 5 nm to 40 nm.

[0031] In a more specific implementation, the method for fabricating the MIS-HEMT power device further includes: firstly, forming an insertion protection layer on the epitaxial structure, and then forming the high-resistivity TaN thin film on the insertion protection layer, with the stacked insertion protection layer and the high-resistivity TaN thin film serving together as the gate dielectric layer.

[0032] Furthermore, the inserted protective layer includes at least one of SiN film, Al2O3 film, and SiO2 film, but is not limited thereto.

[0033] Furthermore, the thickness ratio of the inserted protective layer in the gate dielectric layer is (1~3) / (7~9).

[0034] Furthermore, the thickness of the inserted protective layer is 2 nm to 20 nm, preferably 2 nm to 6 nm.

[0035] In a more specific implementation, the fabrication method of the MIS-HEMT power device specifically includes: growing the insertion protective layer on the epitaxial structure using any one of low-pressure chemical vapor deposition, plasma-enhanced atomic layer deposition, and atomic layer deposition. A high-resistivity TaN thin film is grown on the insertion protective layer using a magnetron sputtering process to form the gate dielectric layer; The epitaxial structure with the gate dielectric layer formed thereon is annealed at 350°C to 450°C for 3 min to 10 min.

[0036] Furthermore, the epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked sequentially. The first semiconductor layer and the second semiconductor layer cooperate to form a heterojunction. A two-dimensional electron gas is formed between the first semiconductor layer and the second semiconductor layer. The third semiconductor layer is disposed between the source region and the drain region. The third semiconductor layer is used to deplete the two-dimensional electron gas located in the region below it. The gate dielectric layer is disposed on the third semiconductor layer.

[0037] Furthermore, both the first semiconductor layer and the second semiconductor layer are made of III-V compound materials, but are not limited thereto.

[0038] Furthermore, the material of the first semiconductor layer includes GaN, but is not limited to this.

[0039] Furthermore, the material of the second semiconductor layer includes AlGaN, but is not limited to this.

[0040] Furthermore, the material of the third semiconductor layer includes GaN-CaP, but is not limited to this.

[0041] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise specified, the preparation processes involved in the following embodiments are all existing processes known to those skilled in the art, and their specific process parameters can be set according to the circumstances, without specific limitations here.

[0042] Example 1 Please see Figure 2 A GaN MIS-HEMT power device with a high-resistivity TaN / SiN gate dielectric layer, comprising: The epitaxial structure includes a GaN channel layer, an AlGaN barrier layer, and a GaN-CaP cap layer stacked sequentially along a specified direction (i.e., the longitudinal or thickness direction of the epitaxial structure). The GaN channel layer and the AlGaN barrier layer cooperate to form a heterojunction. A two-dimensional electron gas is formed at the interface between the GaN channel layer and the AlGaN barrier layer. The GaN-CaP cap layer is used to deplete the two-dimensional electron gas in the heterojunction located below it. The heterojunction comprises a source, a drain, and a gate, wherein the source and the drain are electrically connected through a two-dimensional electron gas within the heterojunction, and the gate is disposed on the GaN-CaP cap layer and located between the source and the drain. A gate dielectric layer continuously covers the GaN-CaP cap layer below the source, drain, and gate, and a window is provided on the gate dielectric layer, with at least a partial area of ​​the source, drain, and gate exposed from the window.

[0043] In this embodiment, the gate dielectric layer includes a SiN thin film and an insulating high-resistivity TaN thin film stacked on top of each other. The SiN thin film is stacked on the GaN-CaP cap layer. The thickness of the SiN thin film is 2nm~6nm, and the thickness of the high-resistivity TaN thin film is 2nm~100nm, preferably 5nm~40nm.

[0044] Please see Figures 3a-3e A method for fabricating a GaN MIS-HEMT power device with a high-resistivity TaN / SiN gate dielectric layer includes the following steps: 1) Fabricating epitaxial structures, such as Figure 3a As shown, the epitaxial structure includes a GaN channel layer, an AlGaN barrier layer, and a GaN-CaP cap layer sequentially stacked on a substrate along a specified direction. The GaN channel layer and the AlGaN barrier layer cooperate to form a heterojunction, and the GaN-CaP cap layer is used to deplete the two-dimensional electron gas located below the GaN-CaP cap layer in the heterojunction.

[0045] In this embodiment, the GaN channel layer and AlGaN barrier layer can of course be other III-V compounds, which will not be elaborated here.

[0046] In this embodiment, an epitaxial structure can be grown on a substrate using methods such as MOCVD, PECVD, or MBE. The substrate can be a sapphire substrate, a silicon substrate, a gallium nitride single crystal substrate, etc., and is not limited to these.

[0047] 2) Fabricate the source and drain electrodes in the ohmic region on the device surface, such as... Figure 3b As shown; 3) SiN thin films and insulating high-resistivity TaN thin films are sequentially grown in the non-ohmic region on the device surface to form a gate dielectric layer.

[0048] Specifically, the SiN thin film can be grown on the device surface using any one of the following processes: low-pressure chemical vapor deposition, plasma-enhanced atomic layer deposition, and atomic layer deposition. The thickness of the SiN thin film is 2 nm to 20 nm, preferably 2 nm to 6 nm. A high-resistivity TaN thin film is grown on the SiN thin film using magnetron sputtering. The magnetron sputtering process for growing the high-resistivity TaN thin film uses a sputtering power of 100 W to 300 W, a nitrogen flow rate of 20 sccm to 25 sccm, and an argon flow rate of 30 sccm to 50 sccm. The thickness of the high-resistivity TaN thin film is 2 nm to 100 nm, preferably 5 nm to 40 nm, thereby forming the gate dielectric layer. The formed gate dielectric layer is annealed at a temperature of 350℃ to 450℃ for 3 min to 10 min. Annealing can recrystallize the thin film of the gate dielectric, reduce the stress of the film, and thus improve the adhesion of the film constituting the gate dielectric layer.

[0049] It should be noted that Al2O3 thin films or SiO2 thin films grown by processes such as plasma-enhanced atomic layer deposition and atomic layer deposition can also be used instead of SiN thin films.

[0050] 4) A gate is fabricated on the gate dielectric layer to obtain a series of GaN MIS-HEMT power devices with different thicknesses of high-resistivity TaN / SiN gate dielectric layers.

[0051] The electrical transfer characteristics of a series of GaN MIS-HEMT power devices with high-resistivity TaN / SiN gate dielectric layers obtained in this embodiment, as well as GaN MIS-HEMT power devices using SiN thin films or TaN thin films alone as gate dielectric layers, were characterized. The results of the electrical transfer characteristic characterization are as follows: Figure 4a , Figure 4b As shown, the GaN MIS-HEMT power device with a high-resistivity TaN / SiN gate dielectric layer has an ION / IOFF switching ratio greater than 10. 10 The device exhibits excellent electrical switching characteristics and, compared to single-layer TaN gate dielectric HEMT devices, a lower gate leakage level, indicating reduced surface damage. In CV testing, the breakdown voltage of different gate dielectric layers and the interface state trap density at the gate dielectric layer-barrier layer interface of the GaN MIS-HEMT power device were obtained using frequencies ranging from 2MHz to 20kHz. The results are as follows: Figure 4c , Figure 4d As shown.

[0052] Example 2 Please see Figure 1 A GaN MIS-HEMT power device with a high-resistivity TaN gate dielectric layer, comprising: The epitaxial structure includes a GaN channel layer, an AlGaN barrier layer, and a GaN-CaP cap layer stacked sequentially along a specified direction (i.e., the longitudinal or thickness direction of the epitaxial structure). The GaN channel layer and the AlGaN barrier layer cooperate to form a heterojunction. A two-dimensional electron gas is formed at the interface between the GaN channel layer and the AlGaN barrier layer. The GaN-CaP cap layer is used to deplete the two-dimensional electron gas in the heterojunction located below it. The heterojunction comprises a source, a drain, and a gate, wherein the source and the drain are electrically connected through a two-dimensional electron gas within the heterojunction, and the gate is disposed on the GaN-CaP cap layer and located between the source and the drain. A gate dielectric layer continuously covers the GaN-CaP cap layer below the source, drain, and gate, and a window is provided on the gate dielectric layer, with at least a partial area of ​​the source, drain, and gate exposed from the window.

[0053] In this embodiment, the gate dielectric layer includes an insulating high-resistivity TaN thin film, which is stacked on the GaN-CaP cap layer. The thickness of the high-resistivity TaN thin film is 2nm~100nm, preferably 5nm~40nm.

[0054] A method for fabricating a GaN MIS-HEMT power device with a high-resistivity TaN gate dielectric layer includes the following steps: 1) Fabricating epitaxial structures, such as Figure 3a As shown, the epitaxial structure includes a GaN channel layer, an AlGaN barrier layer, and a GaN-CaP cap layer sequentially stacked on a substrate along a specified direction. The GaN channel layer and the AlGaN barrier layer cooperate to form a heterojunction, and the GaN-CaP cap layer is used to deplete the two-dimensional electron gas located below the GaN-CaP cap layer in the heterojunction.

[0055] In this embodiment, the GaN channel layer and AlGaN barrier layer can of course be other III-V compounds, which will not be elaborated here.

[0056] In this embodiment, an epitaxial structure can be grown on a substrate using methods such as MOCVD, PECVD, or MBE. The substrate can be a sapphire substrate, a silicon substrate, a gallium nitride single crystal substrate, etc., and is not limited to these.

[0057] 2) Fabricate the source and drain electrodes in the ohmic region on the device surface, such as... Figure 3b As shown; 3) An insulating high-resistivity TaN thin film is grown in the non-ohmic region on the device surface to form a gate dielectric layer.

[0058] Specifically, a high-resistivity TaN thin film is grown using a magnetron sputtering process. The sputtering power used in the magnetron sputtering process for growing the high-resistivity TaN thin film is 100W~300W, the nitrogen flow rate is 20 sccm~25 sccm, the argon flow rate is 30 sccm~50 sccm, and the thickness of the high-resistivity TaN thin film is 2nm~100nm, preferably 5nm~40nm, thereby forming the gate dielectric layer. The formed gate dielectric layer is annealed at a temperature of 350℃ to 450℃ for 3 min to 10 min. Annealing can recrystallize the thin film of the gate dielectric, reduce the stress of the film, and thus improve the adhesion of the film constituting the gate dielectric layer.

[0059] 4) A gate is fabricated on the gate dielectric layer to obtain a series of GaNMIS-HEMT power devices with different thicknesses of high-resistivity TaN gate dielectric layers.

[0060] The electrical transfer characteristics of a series of GaN MIS-HEMT power devices obtained in this embodiment, as well as a GaN MIS-HEMT power device using Al2O3 as the gate dielectric layer, were characterized, and the results are as follows: Figure 5a , Figure 5b , Figure 5c , Figure 5d As shown.

[0061] Specifically, the transfer characteristic curves of MIS-HEMT power devices with TaN and Al2O3 gate dielectrics with a thickness of 20nm are shown in the figure. Figure 5a As shown, compared to MIS-HEMT devices with a single-layer 20nm-Al2O3 gate dielectric, the TaN gate dielectric MIS-HEMT power device in this embodiment has a gate leakage current that is about two orders of magnitude lower, and an on / off ratio of approximately 10. 9 This demonstrates good gate control capability. Specifically, the breakdown voltage curves of the gate dielectric layer in MIS-HEMT power devices with a 20nm thick TaN gate dielectric and Al2O3 gate dielectric are shown in the figure. Figure 5b As shown, compared to Al2O3 gate dielectric, TaN, as the gate dielectric layer of the device, has a higher gate breakdown voltage. Specifically, the device breakdown characteristic curves of MIS-HEMT power devices with 20nm thick TaN and Al2O3 gate dielectrics are shown in the figure. Figure 5c As shown, compared to MIS-HEMT devices with a single-layer 20nm Al2O3 gate dielectric, the MIS-HEMT power device with a TaN gate dielectric in this embodiment has a higher gate breakdown voltage, approximately 1180V. Specifically, the current collapse characteristic curves of the MIS-HEMT power devices with a 20nm thick TaN gate dielectric and Al2O3 gate dielectric are shown in the figure. Figure 5dAs shown, compared to the MIS-HEMT device with a single-layer 20nm-Al2O3 gate dielectric, the specific on-resistance of the TaN gate dielectric MIS-HEMT power device in this embodiment is about 1.39 times that of the MIS-HEMT device with an Al2O3 gate dielectric at 400V. Obviously, the TaN gate dielectric MIS-HEMT power device in this embodiment has better suppression of current collapse effect.

[0062] In summary, the ION / IOFF switching ratio of the device in this embodiment is greater than 10. 9 The device exhibits excellent electrical switching characteristics and, compared to single-layer alumina gate dielectric HEMT devices, has a lower gate leakage level, indicating that the gate dielectric has a stronger ability to suppress leakage current, and both the breakdown voltage and the ability to suppress current collapse have been improved.

[0063] This invention can effectively reduce the bombardment damage to the semiconductor material surface during magnetron sputtering growth of thin films, thereby reducing shallow level traps in interface states and thus reducing gate leakage current of the device, thereby improving the interface state quality of the device. Furthermore, the fabrication process of this invention is simple and time-saving.

[0064] The MIS-HEMT device provided in this embodiment of the invention has low gate leakage current, low off-state loss, good interface state quality, high withstand voltage, and stable dynamic performance. Compared with single-layer silicon nitride gate dielectric, the dielectric can effectively reduce the impact of bulk defects of silicon nitride material itself on the overall performance of the device.

[0065] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A MIS-HEMT power device, comprising an epitaxial structure and a source, drain, and gate matched with the epitaxial structure, wherein the epitaxial structure contains a two-dimensional electron gas, and the source and drain are electrically connected via the two-dimensional electron gas, characterized in that, Also includes: The gate dielectric layer includes an insulating insertion protection layer and an insulating high-resistivity TaN thin film sequentially stacked on the epitaxial structure, and the gate is disposed on the high-resistivity TaN thin film.

2. The MIS-HEMT power device with a composite gate dielectric layer according to claim 1, characterized in that: The thickness of the high-resistivity TaN thin film is 2nm~100nm, preferably 5nm~40nm.

3. The MIS-HEMT power device with a composite gate dielectric layer according to claim 1, characterized in that, The gate dielectric layer further includes: an insertion protection layer, wherein the insertion protection layer is stacked on the epitaxial structure, and the high-resistivity TaN thin film is disposed on the insertion protection layer; Preferably, the inserted protective layer includes at least one of SiN film, Al2O3 film, and SiO2 film; Preferably, the thickness ratio of the inserted protective layer in the gate dielectric layer is approximately (1~3) / (7~9). Preferably, the thickness of the inserted protective layer is 2 nm to 20 nm, more preferably 2 nm to 6 nm; Preferably, the insert protective layer is grown by any one of the following processes: low-pressure chemical vapor deposition, plasma-enhanced atomic layer deposition, and atomic layer deposition. Preferably, the gate dielectric layer is grown by the following method: The insertion protective layer is grown on the epitaxial structure using any one of the following processes: low-pressure chemical vapor deposition, plasma-enhanced atomic layer deposition, and atomic layer deposition. A high-resistivity TaN thin film is grown on the insertion protective layer using a magnetron sputtering process to form the gate dielectric layer; The epitaxial structure with the gate dielectric layer formed thereon is annealed at 350°C to 450°C for 3 min to 10 min.

4. The MIS-HEMT power device according to claim 1, characterized in that: The epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked sequentially. The first semiconductor layer and the second semiconductor layer cooperate to form a heterojunction. A two-dimensional electron gas is formed between the first semiconductor layer and the second semiconductor layer. The third semiconductor layer is disposed between the source region and the drain region. The third semiconductor layer is used to deplete the two-dimensional electron gas located in the region below it. The gate dielectric layer is stacked on the third semiconductor layer.

5. The MIS-HEMT power device according to claim 4, characterized in that: Both the first semiconductor layer and the second semiconductor layer are made of III-V compound materials; Preferably, the material of the first semiconductor layer includes GaN; Preferably, the material of the second semiconductor layer includes AlGaN; And / or, the material of the third semiconductor layer includes GaN-CaP.

6. A method for fabricating a MIS-HEMT power device, comprising the steps of fabricating an epitaxial structure and fabricating a source, drain, and gate electrode matching the epitaxial structure, wherein the epitaxial structure contains a two-dimensional electron gas, and the source and drain are electrically connected via the two-dimensional electron gas, characterized in that... Also includes: An insulating high-resistivity TaN thin film is fabricated on the epitaxial structure to form a gate dielectric layer, and the gate is disposed on the high-resistivity TaN thin film.

7. The method for fabricating the MIS-HEMT power device according to claim 6, characterized in that, Specifically, it includes: The high-resistivity TaN thin film was grown using magnetron sputtering. The sputtering power used in the magnetron sputtering process was 100 W to 300 W, and the flow rate ratio of nitrogen to argon was (2~3):(4~5). The epitaxial structure with the high-resistivity TaN thin film formed thereon was annealed at 350℃~450℃ for 3 min~10 min; Preferably, the nitrogen flow rate during the magnetron sputtering process for growing the high-resistivity TaN thin film is 20 sccm to 25 sccm, and the argon flow rate is 30 sccm to 50 sccm. Preferably, the thickness of the high-resistivity TaN film is 2nm~100nm, and more preferably 5nm~40nm.

8. The method for fabricating the MIS-HEMT power device according to claim 6 or 7, characterized in that, Also includes: First, an insertion protection layer is formed on the epitaxial structure, and then the high-resistivity TaN film is formed on the insertion protection layer. The stacked insertion protection layer and the high-resistivity TaN film together serve as the gate dielectric layer. Preferably, the inserted protective layer includes at least one of SiN film, Al2O3 film, and SiO2 film; Preferably, the thickness ratio of the inserted protective layer in the gate dielectric layer is (1~3) / (7~9). Preferably, the thickness of the inserted protective layer is 2 nm to 20 nm, more preferably 2 nm to 6 nm; Preferably, the method for fabricating the MIS-HEMT power device specifically includes: The insertion protective layer is grown on the epitaxial structure using any one of the following processes: low-pressure chemical vapor deposition, plasma-enhanced atomic layer deposition, and atomic layer deposition. A high-resistivity TaN thin film is grown on the insertion protective layer using a magnetron sputtering process to form the gate dielectric layer; The epitaxial structure with the gate dielectric layer formed thereon is annealed at 350°C to 450°C for 3 min to 10 min.

9. The method for fabricating the MIS-HEMT power device according to claim 6, characterized in that: The epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked sequentially. The first semiconductor layer and the second semiconductor layer cooperate to form a heterojunction. A two-dimensional electron gas is formed between the first semiconductor layer and the second semiconductor layer. The third semiconductor layer is disposed between the source region and the drain region. The third semiconductor layer is used to deplete the two-dimensional electron gas located in the region below it. The gate dielectric layer is stacked on the third semiconductor layer.

10. The method for fabricating the MIS-HEMT power device according to claim 6, characterized in that: Both the first semiconductor layer and the second semiconductor layer are made of III-V compound materials; Preferably, the material of the first semiconductor layer includes GaN; Preferably, the material of the second semiconductor layer includes AlGaN; And / or, the material of the third semiconductor layer includes GaN-CaP.

Images