A depletion-mode GaN HEMT device and its fabrication method

Abstract

The application belongs to the technical field of semiconductor devices, and particularly relates to a depletion-mode GaN HEMT device and a manufacturing method thereof. In view of the problem of difficult etching of the field plate height of the multi-layer gate field plate of the depletion-mode HEMT device, the application proposes a multi-layer etching stop layer, and uses the holes provided by the P-type semiconductor interlayer to improve the trap center de-trapping capability, so as to realize a GaN HEMT device structure with high gate field plate height uniformity and low current collapse, and significantly inhibit the current collapse effect of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a depletion-type GaN HEMT device and its manufacturing method. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) currently employ two main technological approaches: depletion-mode and enhancement-mode. The depletion region offers advantages in on-resistance and reliability per unit area, particularly for high-power devices, where it significantly outperforms enhancement-mode. A typical depletion-mode device's core structure consists of a channel layer and a barrier layer, forming a high-carrier-concentration (up to 1E¹³ cm⁻²) two-dimensional electron gas with high mobility; this is then turned off via a metal-insulator-semiconductor junction or a Schottky junction. To optimize the electric field distribution during device turn-off, current depletion-mode devices often utilize multi-layer gate field plates; however, the height of these multi-layer field plates depends on the etching depth of each field plate. Technically, this is often achieved by etching a stop layer. Currently, the main stop layers are aluminum oxide or aluminum nitride grown by low-temperature atomic layer deposition. Thin films grown in this way will form a large number of defect centers, which will not only increase the leakage current between the gate, drain, and source when the device is turned off, but also become electron trapping centers during the rapid switching process of the device, capturing a large number of electrons and forming negative charge centers, which will greatly aggravate the current collapse effect of depletion-type HEMT devices. Summary of the Invention

[0003] To address the aforementioned problems, this invention proposes a depletion-mode GaN HEMT device and its manufacturing method. Addressing the difficulty in etching the field plate height of the multilayer gate field plate in depletion-mode HEMT devices, a multilayer etching stop layer is proposed. Furthermore, holes provided by P-type semiconductor intercalation are used to enhance the trap center's decapitation capability, thereby achieving a GaN HEMT device structure with high gate field plate height uniformity and low current collapse.

[0004] The technical solution of this invention is:

[0005] A depletion-mode GaN HEMT device comprises, from bottom to top along the vertical direction of the device, a substrate 100, a buffer layer and a high-resistivity layer 200, a channel layer 300 and a barrier layer 500 stacked together; a dielectric layer stop layer composite structure is provided on the barrier layer 500, which is composed of a first dielectric layer 601, a first stop layer 602, a second dielectric layer 603, a second stop layer 604 and a third dielectric layer 605 stacked together from bottom to top, wherein the first dielectric layer 601 is located on the upper surface of the barrier layer 500;

[0006] The dielectric stop layer composite structure has source trenches and drain trenches on both sides. The source trenches and drain trenches are spaced from the device end face and extend vertically through the entire dielectric stop layer composite structure. Source P-type intercalation layers 701 are located on the two sidewalls of the source trenches, and drain P-type intercalation layers 702 are located on the two sidewalls of the drain trenches. Both the source P-type intercalation layers 701 and 702 are P-type. A gallium nitride (GaN) layer is provided; a source 801 is provided in the source trench, and the two sides of the source 801 are in contact with the source P-type intercalation layer 701. The bottom of the source 801 extends vertically along the device to penetrate the barrier layer 500 and then contacts the channel layer 300. At the same time, the top of the source 801 extends horizontally along the device to cover the top of the source P-type intercalation layer 701 and contacts part of the upper surface of the third dielectric layer 605. A drain 802 is provided in the drain trench, and the two sides of the drain 802 are in contact with the drain P-type intercalation layer 702. The bottom of the drain 802 extends vertically along the device to penetrate the barrier layer 500 and then contacts the channel layer 300. At the same time, the top of the drain 802 extends horizontally along the device to cover the top of the drain P-type intercalation layer 702 and then contacts part of the upper surface of the third dielectric layer 605.

[0007] A cover dielectric layer 900 is provided on the upper surface of the third dielectric layer 605, and the cover dielectric layer 900 completely covers the surfaces of the third dielectric layer 605, the source 801 and the drain 802.

[0008] A gate electrode 1001 is provided on the upper surface of the upper cover dielectric layer 900. The gate electrode 1001 is located between the source electrode 801 and the drain electrode 802. The gate electrode 1001 extends along the device direction and sequentially penetrates the upper cover dielectric layer 900, the third dielectric layer 605, the second stop layer 604, the second dielectric layer 603, and the first stop layer 602 before contacting the first dielectric layer 601. The lateral width of the portion of the gate electrode 1001 located on the upper surface of the upper cover dielectric layer 900 is greater than the lateral width of the portion located in the upper cover dielectric layer 900, the third dielectric layer 605, and the second stop layer 604. At the same time, the lateral width of the portion of the gate electrode 1001 located in the upper cover dielectric layer 900, the third dielectric layer 605, and the second stop layer 604 is greater than the lateral width of the portion located in the second dielectric layer 603 and the first stop layer 602.

[0009] Furthermore, the substrate 100 is made of one of the following materials: silicon, gallium nitride, sapphire, and silicon carbide.

[0010] Furthermore, in the buffer layer and the high-resistivity layer 200, the buffer layer is a stacked structure of AlN and AlxGa1-xN with a thickness of 1um-3um, and the high-resistivity layer is carbon-doped gallium nitride.

[0011] Furthermore, the channel layer 300 is unintentionally doped gallium nitride with a thickness of 50-300 nm, the barrier layer 500 is an AlxGa1-xN material with x greater than 0.1 but not higher than 0.4, and the thickness of the barrier layer 500 is 8 nm-30 nm; a two-dimensional electron gas is formed in the channel layer near the interface between the channel layer 300 and the barrier layer 500.

[0012] Furthermore, the thickness of the first dielectric layer 601 is 40-80nm, the thickness of the second dielectric layer 603 is 50-250nm, the thickness of the third dielectric layer 605 is 200-600nm, and the thickness of the first stop layer 602 and the second stop layer 604 is the same, which is 3-10nm.

[0013] A method for manufacturing a depletion-mode GaN HEMT device includes the following steps:

[0014] Step 1: On substrate 100, a buffer layer and a gallium phosphate high-resistivity layer 200, a channel layer 300, a barrier layer 500, a first dielectric layer 601, a first stop layer 602, a second dielectric layer 603, a second stop layer 604, and a third dielectric layer 605 are epitaxially grown sequentially. The first dielectric layer 601, the first stop layer 602, the second dielectric layer 603, the second stop layer 604, and the third dielectric layer 605 constitute a dielectric layer-stop layer composite structure.

[0015] Step 2: Using photolithography, etched hole structures 610 are formed on both sides of the dielectric layer stop layer composite structure;

[0016] Step 3: Epitaxial growth of a P-type gallium nitride layer;

[0017] Step 4: Etch back the P-type gallium nitride layer to remove the P-type gallium nitride layer except for the two sides of the etch hole structure (610) to obtain the source P-type intercalation layer 701 and the drain P-type intercalation layer 702. Continue to etch the barrier layer 500 between the source P-type intercalation layer 701 and the drain P-type intercalation layer 702 to obtain the etch hole.

[0018] Step 5: Fabricate source electrode 801 and drain electrode 802;

[0019] Step 6: Deposit the top cover medium layer at 900°C;

[0020] Step 7: Between the source 801 and the drain 802, near the source, a portion of the third dielectric layer 605 is etched away. Then, the exposed second stop layer 604 is removed by wet cleaning. Continue etching to remove a portion of the second dielectric layer 603. The exposed first stop layer 602 is removed by wet cleaning to obtain the gate hole required for the gate electrode 1001.

[0021] Step 8: Fabricate gate electrode 1001.

[0022] The beneficial effects of this invention are as follows: By adopting a composite structure of a stop layer and a dielectric layer, and utilizing the high etching selectivity of the dielectric layer and the stop layer in fluorine-based gas, the etching depth of the gate field plate is changed from "etching time control" to "material layer thickness control," completely avoiding the hole depth deviation caused by etching time fluctuations, significantly improving the uniformity and consistency of the gate field plate height, reducing the difficulty of process implementation, and exhibiting good compatibility with existing GaN power device production lines. Through a secondary epitaxy + inert gas etch-back process, source / drain P-type gallium nitride intercalation layers are fabricated on the sidewalls of the etched holes. During device operation, the source / drain electric field drives the holes in the P-type intercalation layers to migrate along the sidewalls towards the dielectric-stop layer composite structure. The holes recombine with the trapped electrons at the defect center of the stop layer, effectively eliminating negative charge centers, reducing the virtual gate effect, and ultimately significantly improving the electron decapitation capability of the trap center, thus significantly suppressing the current collapse effect of the device. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of the depletion-type GaN HEMT device of the present invention;

[0024] Figure 2 This is a schematic diagram of the structure of a depletion-mode GaN HEMT device after the first step of the process is completed.

[0025] Figure 3 This is a schematic diagram of the structure of a depletion-type GaN HEMT device after the second step of the process is completed.

[0026] Figure 4 This is a schematic diagram of the structure of a depletion-type GaN HEMT device after the third step of the process is completed.

[0027] Figure 5 This is a schematic diagram of the structure of a depletion-type GaN HEMT device after the fourth step of the process is completed.

[0028] Figure 6 This is a schematic diagram of the structure of a depletion-mode GaN HEMT device after the fifth step of the process is completed.

[0029] Figure 7 This is a schematic diagram of the structure of a depletion-type GaN HEMT device after the sixth step of the process is completed.

[0030] Figure 8 This is a schematic diagram of the structure completed after one etching step in the seventh process of a depletion-type GaN HEMT device.

[0031] Figure 9 This is a schematic diagram of the structure after one cleaning step in the seventh process of a depletion-type GaN HEMT device.

[0032] Figure 10This is a schematic diagram of the structure of a depletion-type GaN HEMT device after secondary etching and cleaning in the seventh step of the process.

[0033] Figure 11 This is a schematic diagram of the structure of a depletion-type GaN HEMT device after the completion of the eighth process step. Detailed Implementation

[0034] The present invention will now be described in further detail with reference to the accompanying drawings.

[0035] like Figure 1 As shown, the depletion-type GaN HEMT device of the present invention comprises a buffer layer and a high-resistivity layer 200, a channel layer 300, and a barrier layer 500 sequentially on a substrate 100. The substrate 100 can be silicon, gallium nitride, sapphire, silicon carbide, etc. The buffer layer is a buffer structure for GaN growth on the substrate, optionally on a silicon substrate. The buffer layer is a stacked structure of AlN and AlxGa1-xN with a thickness of 1µm-3µm. The high-resistivity layer can be carbon-doped gallium nitride, and the doping source can also be elements such as Zn and Mg. The channel layer is unintentionally doped gallium nitride with a thickness of 50-300nm. The barrier layer 500 is an AlxGa1-xN material, where x is generally greater than 0.1 but not higher than 0.4, and the thickness of the barrier layer is 8nm-30nm. A two-dimensional electron gas 400 is formed in the channel layer near the interface between the channel layer 300 and the barrier layer 500.

[0036] On the side of the barrier layer 500 meters away from the channel layer, there is a composite structure of dielectric and stop layers. This composite structure typically includes n stop layers and n+1 dielectric layers, where n is the number of gate field plates, usually 2-4 layers. The dielectric and stop layers alternate. The number and thickness of the composite structure determine the number and height of the multilayer gate field plates. Figure 1 The structure shown has two field plates, and the composite structure sequentially includes a first dielectric layer 601, a first stop layer 602, a second dielectric layer 603, a second stop layer 604, and a third dielectric layer 605. The dielectric layers are typically made of silicon oxide or silicon nitride, while the stop layers are typically made of aluminum nitride or aluminum oxide, exhibiting a very high etching selectivity in fluorine-based gas etching. The number of 'n' values ​​is typically 2-4. Taking a two-layer gate field plate as an example, the thicknesses of the first to third dielectric layers are 40-80 nm, 50-250 nm, and 200-600 nm, respectively; preferably, they are 60 nm, 200 nm, and 500 nm. The thickness of the etching stop layer is generally the same, ranging from 3-10 nm, preferably 5 nm. If the number of field plates is 3 or 4, the thickness of the dielectric layers is proportionally calculated according to the number of field plates when there are 2 field plates, while the thickness of the etching stop layer remains unchanged.

[0037] In the composite structure, there are two through-hole etched vias defining the positions of the source and drain electrodes. The width of the etched vias is defined as the source-drain spacing, typically 10µm-30µm, which determines the device's resistance and turn-off voltage. The two sidewalls of the two etched vias are covered with source P-type intercalation layers and drain P-type intercalation layers, respectively. Both sets of intercalation layers are obtained through the same process, with a thickness of 10-100nm. Near the bottom of the two etched vias, close to the barrier layer, there are two more etched vias extending 500µm into the barrier layer. The depth of the etched vias typically exceeds the thickness of the barrier layer by 2-5nm to form ohmic contacts. The two etched vias are filled with metallic source and drain electrodes, respectively. The electrode material can be a Ti / Al / Ti or Ti / TiN / Al / TiN stacked structure, with thicknesses of 30nm / 400nm / 30nm and 20nm / 20nm / 300nm / 80nm, respectively. The metal stack structure forms an ohmic contact with the GaN HEMT device through deposition and RTA annealing.

[0038] Above the composite structure, in order to protect the source and drain metal layers, a top cover dielectric layer 900 is grown. The dielectric layer can be made of silicon oxide or silicon nitride, and the thickness of the dielectric layer can be 0-200 nm.

[0039] Defined as pointing "down" towards the channel layer, the composite structure and the top cover dielectric layer 900 are located in the gate definition region, with n etched vias from bottom to top. The depth of the nth etched via is determined by the thickness of the nth stop layer and the (n+1)th dielectric layer, rather than by the depth defined by the etching time. This significantly increases the uniformity and consistency of the etched via depth. The depth of the last etched via also needs to be superimposed with the thickness of the top cover dielectric layer 900, and the height of the first dielectric layer determines the thickness of the gate dielectric. The size of the first etched via determines the gate length of the device, the size of the nth (n>1) etched via determines the length of the (n-1)th field plate, and the size of the etched vias increases sequentially. A gate electrode 1001 exists in the etched via, and on the side away from the channel layer, the gate electrode size exceeds the size of the last etched via; this size defines the width of the nth field plate. The number of n is typically 2-4. Taking n=2 as an example, the gate length is 1-3 μm, the length of the first field plate is 2-5 μm, and the length of the second field plate is typically 3-10 μm. The gate electrode 1001 is usually made of a metallic material, preferably a Ti / Al / Ti sandwich structure. Ti can increase the adhesion between the metal and the dielectric layer, while Al exists as a low-resistivity metal that is easy to etch. Preferably, the thickness can be 100 nm / 500 nm / 100 nm.

[0040] The fabrication process of the device of the present invention includes:

[0041] First step:

[0042] like Figure 2 As shown: A buffer layer and a gallium nitride (GaN) high-resistivity layer 200, a channel layer 300, and a barrier layer 500 are epitaxially grown on a substrate 100. The growth method is typically MOCVD (Metal-Organic Chemical Vapor Deposition), but MBE (Molecular Beam Epitaxy) can also be used. The substrate can be one of silicon, gallium nitride, sapphire, or silicon carbide. The buffer layer is a buffer structure for GaN growth on the substrate, optionally on a silicon substrate. The buffer layer is a stacked structure of AlN or AlxGa1-xN with a thickness of 1µm-3µm. The gallium nitride high-resistivity layer can be carbon-doped gallium nitride, and the doping source can also be elements such as Zn or Mg. The channel layer is unintentionally doped gallium nitride with a thickness of 50-300nm. The barrier layer is an AlxGa1-xN material, where x is generally greater than 0.1 but not higher than 0.4, and the thickness of the barrier layer is 8nm-30nm. A two-dimensional electron gas 400 is formed within the channel layer near the interface between the channel layer and the barrier layer.

[0043] One approach involves continuing to grow the first dielectric layer 601, the first stop layer 602, the second dielectric layer 603, the second stop layer 604, and the third dielectric layer 605 of the composite structure in situ within the MOCVD reaction chamber. The dielectric layer material is silicon nitride, and the stop layer material is aluminum nitride. The thickness can be 40-80 nm, 3-8 nm, 50-250 nm, 3-8 nm, or 200-600 nm. Preferably, the thicknesses are 50 nm, 5 nm, 100 nm, 5 nm, and 300 nm, respectively.

[0044] Another approach involves growing the dielectric layer using either LPCVD (low-pressure vapor deposition) or PECVD (plasma-enhanced vapor deposition), and the stop layer using ALD (atomic layer deposition). The dielectric layer material can be silicon nitride or silicon oxide, and the stop layer material can be aluminum nitride or aluminum oxide. Preferably, it is silicon nitride and aluminum oxide. The thickness can be 40-80 nm, 3-8 nm, 50-250 nm, 3-8 nm, or 200-600 nm. Preferably, the thicknesses are 50 nm, 5 nm, 100 nm, 5 nm, and 300 nm, respectively.

[0045] Other implementation methods include using a combination of MOCVD in-situ growth of the first few layers and LPCVD+ALD growth of the last few layers. This approach can balance film quality and process cost.

[0046] Second step:

[0047] Based on step 1, photolithography and etching are used to form an etched hole structure 610 on the composite structure, such as... Figure 3 As shown, the etched vias define the source and drain of the HEMT device. The distance between the etched vias is the source-drain pitch, typically 10-30 μm, preferably 25 μm. The etched vias penetrate the entire composite structure.

[0048] Third step:

[0049] Based on step 2, a second p-type gallium nitride layer 700 is grown in an MOCVD epitaxial growth apparatus, with a thickness of 20-200 nm. Figure 4 As shown. The thickness of the secondary epitaxial p-type gallium nitride determines the width of the p-type gallium nitride intercalation layer. Typically, the sidewall growth thickness is 50%-80% of the vertically grown thickness. P-type gallium nitride is achieved by doping with magnesium, calcium, zinc, etc., during gallium nitride growth. The doping concentration of p-type gallium nitride is typically in the range of 1E19 to 5E19 cm⁻³. Preferably, the thickness is 50 nm, the intercalation element is magnesium, and the doping concentration is 2E19 cm⁻³. -3 .

[0050] Fourth step:

[0051] Based on step three, the P-type gallium nitride layer 700 is etched back to remove the P-type gallium nitride layer outside the sidewalls of the etch hole. After the etch back is completed, the barrier layer 500 is etched again to form the etch hole 510. The etching depth is typically 2-5 nm greater than the barrier layer thickness to form an ohmic contact, such as... Figure 5 As shown, the P-type gallium nitride on the sidewalls after etching are source P-type intercalation layer 701 and drain P-type intercalation layer 702, respectively. For both etching conditions in this step, inert gases such as Ar are used as the etching gas source to increase horizontal bombardment capability and reduce sidewall etching capability.

[0052] Fifth step:

[0053] Based on step four, source and drain electrodes 801 and 802 are fabricated, as shown in Figure 6. In one embodiment, this can be achieved using methods such as top-coating, vapor deposition, lift-off, resist removal, and RTA (rapid annealing). The metal is Ti / Al / Ti, with a Ti thickness of 20-60 nm and an Al thickness of 200-500 nm. Preferably, the three metal layers are 30 nm / 400 / 30 nm. In another embodiment, this can be achieved through magnetron sputtering, photolithography, etching, resist removal, and RTA. The metal ratio is Ti / Al / TiN or Ti / TiN / Al / TiN, with a Ti thickness of 10-30 nm, a TiN thickness of 10-100 nm, and an Al thickness of 200-500 nm. Preferably, the four metal layers are 20 / 20 / 300 / 80 nm thick. Both processes can achieve low-resistance ohmic contacts with an ohmic contact resistivity Rc of less than 0.4 Ωmm.

[0054] Step Six:

[0055] Building upon step five, a cover medium layer of 900 is deposited, such as... Figure 7 As shown, this layer primarily protects the source and drain electrodes from etching and oxidation during gate fabrication, preventing degradation. The material of the top cover dielectric layer is typically silicon nitride or silicon oxide, with a thickness of 20-100 nm, preferably silicon nitride with a thickness of 50 nm. The thin film is typically grown using PECVD.

[0056] Step 7:

[0057] Based on step six, fabricate gate dielectric vias 910 and 920, as follows: Figure 8-10 As shown. First, 605 ( ) is etched away between the source and drain electrodes, near the source electrode, using photolithography, dielectric etching, and resist removal. Figure 8 The stop layer 604 is then removed by wet cleaning. Figure 9 Then, repeat the previous two steps to form the dielectric aperture 920. Figure 10 ).

[0058] Step 8

[0059] Building upon step seven, gate metal 1001 is formed sequentially through metal deposition, photolithography, and etching of the metal thin film. The material is typically a TiN / Al / TiN combination, where TiN serves primarily as the insulating metal and dielectric layer, and Al is a commonly used low-resistivity metal in semiconductor processes. The TiN thickness of the gate metal and source is typically 60-200 nm, while the Al thickness of the gate metal is typically 400-1500 nm. (See Figure 11.)

[0060] After this step, the source, drain, and gate of the device are fabricated. Electrodes can then be brought out using metal interconnect technology to realize the functionality of the product-level device. This part of the process is a standard technology in the semiconductor industry and will not be elaborated upon in this solution. The final structure of the device after this step is shown in Figure 11.

[0061] Depletion-mode HEMT devices are typically used in cascade with low-voltage MOSFETs. To ensure capacitance matching, a gate field plate structure is an essential design feature. Furthermore, the gate is at its lowest potential when the device is turned off. Therefore, the height of the gate field plate and the uniformity and consistency of the gate dielectric thickness are crucial to the device performance.

[0062] Existing technologies typically use a single etch stop layer to control the field plate height, and the alumina / aluminum nitride stop layer has numerous defects. In the off state, these defects easily trap electrons, forming negative charge centers, leading to a decrease in the two-dimensional electron gas concentration when the device is turned on, resulting in a severe current collapse effect. This new technology, through innovative structural design and process optimization, fundamentally solves these problems, achieving two core technological advantages:

[0063] High uniformity and consistency of grid plate height:

[0064] This solution employs a composite structure of n stop layers + n+1 dielectric layers. By utilizing the high etching selectivity of the dielectric and stop layers in fluorine-based gas, the etching depth of the gate field plate is changed from "etching time control" to "material layer thickness control," completely avoiding hole depth deviations caused by etching time fluctuations. This significantly improves the uniformity and consistency of the gate field plate height, reduces the difficulty of process implementation, and has good compatibility with existing GaN power device production lines.

[0065] Significantly reduces the current collapse effect of the device:

[0066] This scheme uses a secondary epitaxy process followed by inert gas etching to fabricate source / drain P-type gallium nitride intercalation layers on the sidewalls of the etched holes. When the device is in operation, the source / drain electric field drives the holes in the P-type intercalation layers to migrate along the sidewalls to the dielectric-stop layer recombination structure. The holes recombine with the trapped electrons at the defect centers of the stop layer, effectively eliminating negative charge centers, reducing the virtual gate effect, and ultimately significantly improving the electron detrapping capability of the trap centers, thus significantly suppressing the current collapse effect of the device.

Claims

1. A depletion-mode GaN HEMT device, comprising, from bottom to top along the vertical direction of the device, a substrate (100), a buffer layer and a high-resistivity layer (200), a channel layer (300), and a barrier layer (500) stacked together; characterized in that, The barrier layer (500) has a dielectric layer stop layer composite structure, which is composed of a first dielectric layer (601), a first stop layer (602), a second dielectric layer (603), a second stop layer (604), and a third dielectric layer (605) stacked sequentially from bottom to top, wherein the first dielectric layer (601) is located on the upper surface of the barrier layer (500); The dielectric stop layer composite structure has source trenches and drain trenches on both sides. The source trenches and drain trenches are spaced from the device end face and extend through the entire dielectric stop layer composite structure in the vertical direction of the device. There are source P-type intercalation layers (701) on the two sidewalls of the source trench and drain P-type intercalation layers (702) on the two sidewalls of the drain trench. Both the source P-type intercalation layers (701) and the drain P-type intercalation layers (702) are P-type gallium nitride layers. There is a source (801) in the source trench. The two sides of the source (801) in the source trench are in contact with the source P-type intercalation layers (701). The bottom of the source (801) extends in the vertical direction of the device to penetrate the barrier layer (500) and then contacts the channel layer (300). At the same time, the top of the source (801) extends in the lateral direction of the device to cover the top of the source P-type intercalation layers (701) and partially connects with the upper surface of the third dielectric layer (605). Contact; a drain (802) is present in the drain trench, and the two sides of the drain (802) in the drain trench are in contact with the drain P-type intercalation layer (702). The bottom of the drain (802) extends vertically along the device to penetrate the barrier layer (500) and then contacts the channel layer (300). At the same time, the top of the drain (802) extends horizontally along the device to cover the top of the drain P-type intercalation layer (702) and contacts part of the upper surface of the third dielectric layer (605). A top cover dielectric layer (900) is provided on the upper surface of the third dielectric layer (605), the top cover dielectric layer (900) completely covering the surfaces of the third dielectric layer (605), the source (801) and the drain (802); A gate electrode (1001) is provided on the upper surface of the upper cover dielectric layer (900). The gate electrode (1001) is located between the source (801) and the drain (802). The gate electrode (1001) extends along the device direction and passes through the upper cover dielectric layer (900), the third dielectric layer (605), the second stop layer (604), the second dielectric layer (603), and the first stop layer (602) in sequence before contacting the first dielectric layer (601). The lateral width of the portion of the gate electrode (1001) located on the upper surface of the upper cover dielectric layer (900) is greater than the lateral width of the portion located in the upper cover dielectric layer (900), the third dielectric layer (605), and the second stop layer (604). At the same time, the lateral width of the portion of the gate electrode (1001) located in the upper cover dielectric layer (900), the third dielectric layer (605), and the second stop layer (604) is greater than the lateral width of the portion located in the second dielectric layer (603) and the first stop layer (602).

2. The depletion-mode GaN HEMT device according to claim 1, characterized in that, The substrate (100) is made of one of the following materials: silicon, gallium nitride, sapphire, and silicon carbide.

3. The depletion-mode GaN HEMT device according to claim 1, characterized in that, In the buffer layer and the high-resistivity layer (200), the buffer layer is a stacked structure of AlN and AlxGa1-xN with a thickness of 1um-3um, and the high-resistivity layer is carbon-doped gallium nitride.

4. A depletion-mode GaN HEMT device according to claim 1, characterized in that, The channel layer (300) is unintentionally doped gallium nitride with a thickness of 50-300 nm. The barrier layer (500) is an AlxGa1-xN material with x greater than 0.1 but not higher than 0.

4. The thickness of the barrier layer (500) is 8 nm-30 nm. A two-dimensional electron gas is formed in the channel layer near the interface between the channel layer (300) and the barrier layer (500).

5. A depletion-mode GaN HEMT device according to claim 1, characterized in that, The thickness of the first dielectric layer (601) is 40-80nm, the thickness of the second dielectric layer (603) is 50-250nm, the thickness of the third dielectric layer (605) is 200-600nm, and the thickness of the first stop layer (602) and the second stop layer (604) is the same, which is 3-10nm.

6. A method for manufacturing a depletion-mode GaN HEMT device, used in the depletion-mode GaN HEMT device as described in any one of claims 1-5, characterized in that, Includes the following steps: Step 1: Epitaxially grow a buffer layer and a gallium phosphate high-resistivity layer (200), a channel layer (300), a barrier layer (500), a first dielectric layer (601), a first stop layer (602), a second dielectric layer (603), a second stop layer (604), and a third dielectric layer (605) on the substrate (100). The first dielectric layer (601), the first stop layer (602), the second dielectric layer (603), the second stop layer (604), and the third dielectric layer (605) constitute a dielectric layer-stop layer composite structure. Step 2: Using photolithography, etched hole structures (610) are formed on both sides of the dielectric layer stop layer composite structure. Step 3: Epitaxial growth of a P-type gallium nitride layer; Step 4: Etch away the P-type gallium nitride layer except for the two sides of the etch hole structure (610) to obtain the source P-type intercalation layer (701) and the drain P-type intercalation layer (702). Continue to etch the barrier layer (500) between the source P-type intercalation layer (701) and the drain P-type intercalation layer (702) to obtain the etch hole. Step 5: Fabricate the source (801) and drain (802); Step 6: Deposit the top cover medium layer (900); Step 7: Between the source (801) and the drain (802), a portion of the third dielectric layer (605) is etched away near the source. The exposed second stop layer (604) is then removed by wet cleaning. A portion of the second dielectric layer (603) is etched away, and the exposed first stop layer (602) is removed by wet cleaning to obtain the gate hole required for the gate electrode (1001). Step 8: Fabricate the gate electrode (1001).

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