Horizontal structure double heterojunction insulated gate diamond field effect transistor and preparation method thereof

Abstract

The application discloses a horizontal structure double-heterojunction insulated gate diamond field effect transistor and a preparation method thereof. The field effect transistor comprises a substrate layer and an N-type gallium oxide layer which are stacked; the N-type gallium oxide layer is sequentially and spacedly provided with a source region, a gate region and a drain region in a horizontal direction; the N-type gallium oxide layer locally forms an N+ high-doped gallium oxide region, and a source electrode is arranged on the upper surface of the N+ high-doped gallium oxide region; the gate region of the N-type gallium oxide layer is sequentially and stackedly provided with a first P-type diamond part, a gate dielectric layer and a gate electrode; and the drain region of the N-type gallium oxide layer is sequentially and stackedly provided with a second P-type diamond part and a drain electrode. The field effect transistor has a double-heterojunction structure, the PN heterojunction of the gate electrode forms a depletion region under zero gate voltage by using a built-in electric field, realizes a normally-off characteristic and optimizes gate control efficiency; and the PN heterojunction of the drain electrode widens a depletion region under a reverse bias, modulates an electric field distribution and significantly improves a breakdown voltage.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a horizontal structure double heterojunction insulated gate diamond field-effect transistor and its fabrication method. Background Technology

[0002] Diamond, as an ultrawide bandgap semiconductor material, possesses excellent properties such as a bandgap of 5.5 eV, a breakdown electric field strength exceeding 10 MV / cm, a thermal conductivity higher than 2000 W / (m·K), and a high carrier saturation velocity, making it highly promising for applications in high-voltage, high-frequency, and high-temperature power electronic devices. Early diamond field-effect transistors (DFJs) primarily used Schottky junctions for gate control, but this structure suffers from inaccurate threshold voltage control and difficulty in achieving normally-off operation. Hydrogen-terminated diamond field-effect transistors (DFJs) circumvent the bulk material doping problem by inducing two-dimensional hole gas as a channel through surface treatment, potentially achieving higher output current and cutoff frequency. However, the carrier mobility of the surface channel is relatively low, and long-term reliability is significantly affected by environmental stability and interface states. Insulated-gate diamond field-effect transistors (IGDTs) use a gate dielectric layer instead of a Schottky gate, which improves the breakdown voltage, but the mismatch between the gate dielectric and the diamond interface introduces trapped states, affecting performance stability. Horizontal diamond heterojunction devices circumvent bulk doping challenges by introducing a two-dimensional carrier gas at the heterojunction interface. However, lattice mismatch and differences in thermal expansion coefficients in the heterojunction lead to interface defects, which restrict carrier transport and breakdown voltage improvement.

[0003] The existing technology is a horizontally structured insulated-gate diamond heterojunction field-effect transistor. This approach involves epitaxially growing a heterojunction material on a diamond substrate to form a heterojunction interface that induces a two-dimensional carrier gas as a channel, with gate control via an insulated gate. The device employs a horizontal layout, with the source, gate, and drain arranged laterally, and functional regions defined through photolithography, etching, and deposition processes. However, this approach still has limitations: the heterojunction interface quality is affected by lattice mismatch and differences in thermal expansion coefficients, potentially leading to interface defects; high-quality deposition of the insulated gate dielectric on the diamond surface requires low-damage and precisely controllable process steps; and the low-resistance ohmic contact of the heterojunction barrier layer still needs further improvement.

[0004] In summary, the main drawbacks of existing technologies include the following aspects: First, Schottky gate diamond field-effect transistors (SMTs) suffer from difficulties in threshold voltage regulation. Highly doped channel layers are not conducive to complete depletion, making it difficult to achieve reliable normally-off operation. Furthermore, the high interface state density leads to Fermi level pinning, which limits the ability of the metal work function to modulate the threshold voltage.

[0005] Second, the carrier mobility of hydrogen-terminated diamond field-effect transistors is low. The two-dimensional hole gas on the surface is affected by surface scattering, and the mobility is significantly lower than the theoretical value of the bulk material, which leads to an increase in on-resistance and parasitic resistance. At the same time, the long-term reliability of the device is constrained by environmental stability and interface states, and contamination and plasma damage must be avoided in the process.

[0006] Third, the lattice mismatch and difference in thermal expansion coefficient between the gate dielectric and the diamond surface in insulated-gate diamond field-effect transistors can easily introduce interface trap states, reduce the effective channel mobility, and affect the stability of the threshold voltage.

[0007] Fourth, horizontal heterojunction diamond field-effect transistors have high interface trap density, defects affect carrier transport, ohmic contact fabrication is difficult, and lateral size design restricts current density and breakdown voltage.

[0008] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0009] To address the aforementioned problems in the prior art, this invention provides a horizontal structure double heterojunction insulated-gate diamond field-effect transistor and its fabrication method. Under the premise of effectively controlling interface defects and process damage, this invention achieves a horizontal structure diamond field-effect transistor with normally-off characteristics, high breakdown voltage, low on-resistance, and excellent heat dissipation. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a horizontal structure double heterojunction insulated gate diamond field-effect transistor, comprising a substrate layer and an N-type gallium oxide layer disposed on the substrate layer; The N-type gallium oxide layer includes a source region, a gate region, and a drain region that are sequentially spaced along a horizontal direction. The N-type gallium oxide layer is doped to form an N+ highly doped gallium oxide region, and the orthographic projection of the N+ highly doped gallium oxide region on the substrate layer overlaps with the orthographic projection of the source region on the substrate layer; the source is disposed on the side of the N+ highly doped gallium oxide region away from the substrate layer. The gate region corresponding to the N-type gallium oxide layer is sequentially stacked with a first P-type diamond portion, a gate dielectric layer and a gate. The drain region corresponding to the N-type gallium oxide layer is provided with a second P-type diamond portion and a drain electrode stacked sequentially.

[0010] Secondly, the present invention provides a method for fabricating the horizontal structure double heterojunction insulated gate diamond field-effect transistor, comprising the following steps: S1. Obtain a P-type diamond substrate with a hydrogen-terminated surface as the substrate layer; S2. An N-type gallium oxide layer is grown on the hydrogen-terminated surface side of the P-type diamond substrate; S3. A first insulating dielectric layer is formed on the N-type gallium oxide layer, and the first insulating dielectric layer is patterned to form a window in a preset gate region to expose the underlying N-type gallium oxide layer. S4. A first P-type diamond portion is formed in the preset gate region using microwave plasma chemical vapor deposition process. S5. A second insulating dielectric layer is formed on the upper surface of the N-type gallium oxide layer and the first P-type diamond portion. The second insulating dielectric layer is patterned to form a window in a preset drain region to expose the underlying N-type gallium oxide layer. A second P-type diamond portion is formed in the preset drain region using a microwave plasma chemical vapor deposition process. S6. A third insulating dielectric layer is formed on the upper surface of the N-type gallium oxide layer, the first P-type diamond portion and the second P-type diamond portion, and the third insulating dielectric layer is patterned to form a window in a preset source region to expose the underlying N-type gallium oxide layer. S7. Perform silicon ion implantation on the preset source region to form a doping concentration of 4.5 × 10⁻⁶. 19 cm -3 Up to 5.5×10 19 cm -3 A heavily doped gallium oxide region of N+ with a depth of 40nm to 60nm; S8. Using atomic layer deposition process, a gate dielectric layer is deposited on the side of the first P-type diamond portion away from the substrate layer; S9. A source is formed on the side of the N+ highly doped gallium oxide region away from the substrate, a drain is formed on the side of the second P-type diamond region away from the substrate, and a gate is formed on the side of the gate dielectric layer away from the substrate.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The horizontal structure double heterojunction insulated gate diamond field-effect transistor provided by the present invention adopts a double heterojunction design, in which P-type diamond and N-type β-Ga2O3 PN heterojunctions are constructed at the gate and drain respectively. The gate heterojunction utilizes the built-in electric field to form a depletion region under zero gate voltage, realizes normally off characteristics, and optimizes gate control efficiency. The drain heterojunction widens the depletion region under reverse bias, modulates the electric field distribution, and significantly improves the breakdown voltage.

[0012] 2. This invention utilizes a selective region growth process, employing a first insulating dielectric layer and a second insulating dielectric layer as a hard mask to pattern a local epitaxial P-type diamond layer, thereby avoiding overall epitaxial defects, reducing carrier scattering, and lowering on-resistance.

[0013] 3. In the field-effect transistor of the present invention, the gate dielectric layer is made up of a high-quality interface through atomic layer deposition process, which effectively suppresses gate leakage current and improves gate control accuracy and reliability.

[0014] 4. This invention combines the excellent thermal conductivity of diamond, so that the current mainly flows through the low-resistance N-type gallium oxide layer when it is on, thus achieving a balance between low on-resistance and excellent heat dissipation, which helps to reduce device temperature rise and improve long-term reliability.

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the sample prepared in step 2 of embodiment 3 of the present invention; Figure 2 This is a schematic diagram of the structure of the sample prepared in step 3 of embodiment 3 of the present invention; Figure 3 This is a schematic diagram of the structure of the sample prepared in step 4.1 of embodiment three of the present invention; Figure 4 This is a schematic diagram of the structure of the silicon dioxide sample prepared in step 4.2 of embodiment three of the present invention before etching; Figure 5 This is a schematic diagram of the structure of the silicon dioxide etched sample prepared in step 4.2 of embodiment three of the present invention; Figure 6 This is a schematic diagram of the structure of the sample prepared in step 4.3 of embodiment three of the present invention; Figure 7 This is a schematic diagram of the structure of the sample prepared in step 4.4 of embodiment three of the present invention; Figure 8 This is a schematic diagram of the structure of the sample prepared in step 5 of embodiment 3 of the present invention; Figure 9 This is a schematic diagram of the structure of silicon dioxide deposition in step 6.1 of embodiment three of the present invention; Figure 10 This is a schematic diagram of the structure of the photoresist defining the source region in step 6.1 of embodiment three of the present invention; Figure 11 This is a schematic diagram of the structure for removing photoresist in step 6.1 of embodiment three of the present invention; Figure 12 This is a schematic diagram of the structure of the sample prepared in step 6.2 of embodiment three of the present invention; Figure 13 This is a schematic diagram of the structure of the sample prepared in step 6.3 of embodiment three of the present invention; Figure 14 This is a schematic diagram of the structure of the sample prepared in step 7 of embodiment 3 of the present invention; Figure 15This is a schematic diagram of the structure of the sample prepared in step 8 of embodiment 3 of the present invention; Figure 16 This is a schematic diagram of the structure of the sample prepared in step 9 of embodiment 3 of the present invention; Figure 17 This is a schematic diagram of the structure of the sample prepared in step 10 of embodiment three of the present invention.

[0017] Explanation of reference numerals in the attached figures: 1-Substrate layer; 2-N-type gallium oxide layer; 3-N+ heavily doped gallium oxide region; 4-Source; 5-First P-type diamond section; 6-Gate dielectric layer; 7-Gate; 8-Second P-type diamond section; 9-Drain; IM1-First insulating dielectric layer; IM3-Third insulating dielectric layer; PR-Photoresist. Detailed Implementation

[0018] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for fabricating a horizontal structure double heterojunction insulated gate diamond field-effect transistor and the same.

[0019] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0020] It should be noted that, in this document, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element.

[0021] Example 1 This invention provides a horizontally structured double heterojunction insulated-gate diamond field-effect transistor, see [link to relevant documentation]. Figure 17The system includes a substrate layer 1 and an N-type gallium oxide layer 2 disposed on the substrate layer 1. The N-type gallium oxide layer 2 includes a source region, a gate region, and a drain region disposed sequentially and spaced apart along the lateral direction. The N-type gallium oxide layer 2 is doped to form an N+ highly doped gallium oxide region 3, and the orthographic projection of the N+ highly doped gallium oxide region 3 onto the substrate layer 1 overlaps with the orthographic projection of the source region onto the substrate layer 1. A source 4 is disposed on the side of the N+ highly doped gallium oxide region 3 away from the substrate layer 1. The corresponding gate region on the N-type gallium oxide layer 2 is sequentially stacked with a first P-type diamond portion 5, a gate dielectric layer 6, and a gate 7. The corresponding drain region on the N-type gallium oxide layer 2 is sequentially stacked with a second P-type diamond portion 8 and a drain 9.

[0022] In some examples, the thickness of the first P-type diamond portion 5 is 40 nm to 60 nm, and the doping concentration is 1 × 10⁻⁶. 18 cm -3 ~2×10 18 cm -3 .

[0023] In some examples, the thickness of the second P-type diamond portion 8 is 40 nm to 60 nm, and the doping concentration is 1 × 10⁻⁶. 18 cm -3 ~2×10 18 cm -3 .

[0024] For example, the material of the N-type gallium oxide layer 2 is one of β-Ga2O3, ZnO, and AlN; the thickness of the N-type gallium oxide layer 2 is 1µm to 2µm, and the depth of the N+ highly doped gallium oxide region 3 is 40 nm to 60 nm.

[0025] For example, the material of the gate dielectric layer 6 is any one of SiO2, HfO2, and Al2O3, and the thickness is 20 nm to 40 nm. The presence of the built-in electric field of the PN heterojunction formed by the first P-type diamond portion 5 and the N-type gallium oxide layer 2 optimizes the gate control efficiency, and the Al2O3 insulating gate dielectric layer suppresses the gate leakage current, improving the gate control accuracy and reliability.

[0026] In the horizontally structured dual heterojunction insulated-gate diamond field-effect transistor provided in this embodiment of the invention, a PN heterojunction composed of a first P-type diamond portion 5 and an N-type gallium oxide layer 2 is constructed below the insulating gate dielectric layer. This heterojunction utilizes the Fermi level alignment at zero gate voltage to form an interface depletion region, achieving the device's normally-off characteristic. Furthermore, a PN heterojunction composed of a second P-type diamond portion 8 and an N-type gallium oxide layer 2 is constructed at the drain. Under reverse bias, the electric field distribution is modulated. The heterojunction's bandgap characteristics help widen the depletion region, alleviate the electric field concentration effect, and improve the device's breakdown voltage. The horizontal layout of the gate, source, and drain regions in this invention simplifies the device integration process and facilitates multi-level interconnection and large-scale manufacturing.

[0027] Example 2 This invention also provides a method for fabricating the above-mentioned horizontal structure double heterojunction insulated gate diamond field-effect transistor, such as... Figures 1 to 17 As shown, it includes the following steps: S1, see also Figure 1 A P-type diamond substrate with a hydrogen-terminated surface was obtained as the substrate layer.

[0028] For example, in step S1, the preparation process of the hydrogen terminal surface includes: using microwave plasma chemical vapor deposition, treating the P-type diamond substrate with hydrogen plasma for 3 min to 8 min at a microwave power of 900W to 1000W, a temperature of 850°C to 900°C, and a hydrogen gas flow rate of 100 sccm to 500 sccm.

[0029] S2, see also Figure 2 An N-type gallium oxide layer 2 is grown on the hydrogen-terminated surface side of a P-type diamond substrate.

[0030] S3, see also Figure 3 , Figure 4 and Figure 5 A first insulating dielectric layer IM1 is formed on the N-type gallium oxide layer 2. The first insulating dielectric layer IM1 is patterned to form a window in a predetermined gate region, exposing the underlying N-type gallium oxide layer 2, such as... Figure 5 .

[0031] For example, the first insulating dielectric layer IM1 is made of silicon dioxide and has a thickness of 200nm to 400nm.

[0032] In one example, in step S3, the material of the N-type gallium oxide layer 2 is N-type β-Ga2O3, ZnO or AlN, and the thickness of the N-type gallium oxide layer 2 is 1µm to 2µm.

[0033] S4, see also Figure 6 A first P-type diamond portion 5 is formed in a preset gate region using microwave plasma chemical vapor deposition.

[0034] In one example, forming the first P-type diamond portion 5 includes: using CH4 as the carbon source, H2 as the carrier gas, and B2H6 as the P-type dopant source, epitaxially growing a thickness of 40 nm to 60 nm in a predetermined gate region, with a doping concentration of 1 × 10⁻⁶. 18 cm -3 ~2×10 18 cm -3 The first P-type diamond section 5; the gas flow ratio is CH4:B2H6:H2=5sccm:0.1sccm:450sccm.

[0035] S5, see also Figure 8 A second insulating dielectric layer is formed on the upper surface of the N-type gallium oxide layer 2 and the first P-type diamond portion 5. The second insulating dielectric layer is patterned to form a window in the preset drain region, exposing the underlying N-type gallium oxide layer 2. A second P-type diamond portion 8 is formed in the preset drain region using a microwave plasma chemical vapor deposition process.

[0036] In one example, forming the second P-type diamond portion 8 includes using CH4 as a carbon source and H2 as a carrier gas, introducing B2H6 as a P-type dopant source, and epitaxially growing a thickness of 40nm to 60nm in a predetermined drain region with a doping concentration of 1×10⁻⁶. 18 cm -3 ~2×10 18 cm -3 The second P-type diamond section 8; the gas flow ratio is CH4:B2H6:H2=5sccm:0.1sccm:450sccm.

[0037] For example, the material of the second insulating dielectric layer is silicon dioxide, and the thickness is 200nm to 400nm.

[0038] S6, see also Figure 9 , Figure 10 and Figure 11 A third insulating dielectric layer IM3 is formed on the upper surface of the N-type gallium oxide layer 2, the first P-type diamond portion 5, and the second P-type diamond portion 8. The third insulating dielectric layer IM3 is patterned to form a window in a preset source region, exposing the underlying N-type gallium oxide layer 2.

[0039] For example, the material of the third insulating dielectric layer IM3 is silicon dioxide, and the thickness is 200nm to 400nm.

[0040] S7, see also Figure 12 Silicon ions were implanted into the preset source region to form a doping concentration of 4.5 × 10⁻⁶. 19 cm -3 -5.5×10 19 cm -3 3. A heavily doped gallium oxide region with a depth of 40nm to 60nm.

[0041] In one example, step S7, silicon ion implantation of the preset source region includes two ion implantations. The first ion implantation: using an implantation dose of 5 × 10⁻⁶. 14 Si ions with an energy of 10 keV are used to form a doping concentration of 4.5 × 10⁻⁶ ppm in the predetermined source region of the N-type gallium oxide layer 2. 19 cm -3 -5.5×10 19 cm -3The doped region is implanted with a depth of 15nm to 25nm.

[0042] Second ion implantation: Continue implanting ion dose of 5 × 10⁻⁶ in the doped region. 14 The Si ions with an energy of 25 keV were ultimately used to form a doping concentration of 4.5 × 10⁻⁶. 19 cm -3 -5.5×10 19 cm -3 3. An N+ heavily doped gallium oxide region with an implantation depth of 40nm to 60nm was formed.

[0043] S8, see also Figure 14 Atomic layer deposition process is used to deposit a gate dielectric layer 6 on the side of the first P-type diamond section 5 away from the substrate layer 1.

[0044] For example, the gate dielectric layer 6 is made of SiO2, HfO2, or Al2O3, and has a thickness of 20 nm to 40 nm. It is understood that the gate dielectric layer 6 can also be made of other dielectric materials with high dielectric constants.

[0045] S9, see also Figure 17 A source electrode 4 is formed on the side of the N+ highly doped gallium oxide region 3 away from the substrate layer 1, a drain electrode 9 is formed on the side of the second P-type diamond portion 8 away from the substrate layer 1, and a gate electrode 7 is formed on the side of the gate dielectric layer 6 away from the substrate layer 1.

[0046] The method for fabricating a horizontal structure double heterojunction insulated gate diamond field-effect transistor provided in this invention adopts a horizontal structure and selective region growth process. By combining hard mask patterning with epitaxial growth, local doping or heterojunction formation of the gate region, source region, and drain region is achieved, avoiding the high defect density caused by overall epitaxy, reducing carrier scattering, and improving channel mobility.

[0047] Example 3 Step 1: Clean and pre-treat the P-type diamond substrate.

[0048] A 100 μm thick

[100] oriented P-type diamond substrate was selected and cleaned for 35 min in a 1:1 volume ratio of sulfuric acid and nitric acid in a 200°C water bath. Subsequently, it was ultrasonically cleaned for 10 min each with acetone, ethanol and deionized water, respectively. After cleaning, the surface was dried with high-purity nitrogen.

[0049] Step 2, forming hydrogen terminal surfaces, such as Figure 1 As shown.

[0050] The substrate treated in step 1 was placed in a microwave plasma chemical vapor deposition (MPCVD) reaction chamber and subjected to hydrogen plasma treatment for 5 minutes by introducing high-purity hydrogen gas.

[0051] The process conditions for hydrogen plasma treatment by MPCVD are as follows: reaction chamber gas: H2; reaction chamber temperature: 880℃; reaction chamber gas flow rate: 100sccm-500sccm; RF source: 950W.

[0052] Step 3, N-type gallium oxide layer 2 (β-Ga2O3 epitaxial layer) is grown, as follows: Figure 2 As shown.

[0053] The sample processed in step 2 was transferred to a metal-organic chemical vapor deposition (MOCVD) chamber. The growth temperature was set to 750°C and the chamber pressure to 85 mbar. TMGa (trimethylgallium) and O2 were used as the reaction gas source, and high-purity N2 was used as the carrier gas to grow a 1.5 µm thick β-Ga2O3 epitaxial layer. After growth, the epitaxial wafer was annealed in an O2 atmosphere at 400°C for 30 min.

[0054] The process conditions for MOCVD epitaxial growth of β-Ga2O3 epitaxial layers are as follows: reaction chamber pressure: 85 mbar; reaction chamber gases: TMGa, O2, N2; reaction chamber gas flow rate ratio: TMGa:O2:N2 = 5 sccm:500 sccm:1500 sccm; reaction chamber temperature: 750℃.

[0055] Step 4: Selectively grow a first P-type diamond portion 5 in a preset gate region, such as... Figures 3-7 : 4.1) First, a 300 nm thick SiO2 layer (first insulating dielectric layer IM1) is deposited on the surface of the β-Ga2O3 epitaxial layer using plasma-enhanced chemical vapor deposition (PECVD) process, such as... Figure 3 As shown; 4.2) Photoresist PR is coated on the surface of the SiO2 layer, exposed and developed using a mask to define the gate region pattern. Figure 4 ), using reactive ion etching to remove SiO2 from the gate region ( Figure 5 Then, acetone was used to remove the photoresist PR. 4.3) The sample was placed in the MPCVD reaction chamber, and the microwave power was set to 3500W, the chamber pressure to 110mbar, and the growth temperature to 1050°C. CH4 was used as the carbon source, H2 as the carrier gas, and B2H6 was introduced as the P-type doping source. Epitaxial growth with a thickness of 40nm was performed in the defined gate region, and the doping concentration was 1×10⁻⁶. 18 cm -3 The first P-type diamond part 5, such as Figure 6 As shown; 4.4) Immerse the epitaxial wafer in HF solution to wash away any remaining SiO2 (first insulating dielectric layer IM1) on the surface of the epitaxial wafer, then rinse with deionized water and dry with nitrogen gas. Figure 7 As shown.

[0056] The process conditions for depositing SiO2 using plasma-enhanced chemical vapor deposition are as follows: reaction chamber pressure: 1000 mtorr; reaction chamber gases: SiH4, N2O, N2; reaction chamber gas flow rate ratio: SiH4:N2O:N2 = 20 sccm:600 sccm:500 sccm; reaction chamber temperature: 350℃; RF source: 50W.

[0057] The process conditions for etching SiO2 using reactive ion etching (RIE) are as follows: reaction chamber pressure: 300 mtorr; reaction chamber gases: SF6, CHF3, He; reaction chamber gas flow rate ratio: SF6:CHF3:He = 15 sccm:20 sccm:150 sccm; RF source: 200W.

[0058] Step 5: Selectively grow a second P-type diamond portion 8 in the drain region, such as... Figure 8 As shown.

[0059] On the sample surface after step 4, the hard mask fabrication and patterning process of step 4 is repeated to define the drain region pattern. The sample is placed in the MPCVD reaction chamber at a chamber pressure of 110 mbar and a growth temperature of 1050°C. CH4 is used as the carbon source, H2 as the carrier gas, and B2H6 is introduced as the P-type doping source. A 50 nm thick epitaxial growth is performed on the defined drain region with a doping concentration of 1.5 × 10⁻⁶. 18 cm -3 The second P-type diamond section 8. The epitaxial wafer is placed in HF solution to wash away the remaining SiO2 on the surface of the epitaxial wafer, then rinsed with deionized water and dried with nitrogen.

[0060] The process conditions for MPCVD epitaxial growth of the second P-type diamond section 8 are as follows: reaction chamber pressure: 110 mbar; reaction chamber gas: CH4, B2H6, H2; reaction chamber gas flow rate ratio: CH4:B2H6:H2=5 sccm:0.1 sccm:450 sccm; reaction chamber temperature: 1050℃; RF source: 3500W.

[0061] Step 6, the source region corresponding to the N-type gallium oxide layer 2 undergoes N... + Highly doped, such as Figures 9-13 As shown: 6.1) Repeat the hard mask fabrication and patterning process in step 4 to define the source region pattern, such as... Figures 9-11 As shown; 6.2) The exposed β-Ga2O3 epitaxial layer was subjected to two Si ion implantations to form a doping concentration of 5×10⁻⁶. 19 cm -3A square, highly doped region with a depth of 50 nm was formed. After ion implantation, it was annealed for 30 minutes in a N2 atmosphere at 950 °C. Figure 12 As shown; 6.3) Immerse the annealed epitaxial wafer in HF solution to wash away any remaining SiO2 on the surface, then rinse with deionized water and dry with nitrogen gas. Figure 13 As shown.

[0062] The specific steps of ion implantation are as follows: First, implant an ion dose of 5 × 10⁻⁶ onto the epitaxial wafer. 14 Si ions with an energy of 10 keV are used to form a doping concentration of 5 × 10⁻⁶. 19 cm -3 A square highly doped region with an implantation depth of 20 nm was created; then, a dose of 5 × 10⁻⁶ was implanted into this square highly doped region. 14 The ionic Si with an energy of 25 keV was eventually used to form a doping concentration of 5 × 10⁻⁶. 19 cm -3 A square, highly doped region with an implantation depth of 50 nm was created.

[0063] Step 7, Al2O3 gate dielectric layer deposition, such as Figure 14 As shown.

[0064] Photoresist was coated onto the sample surface, and the Al2O3 gate dielectric deposition area was defined by exposure and development using a mask. Atomic layer deposition (ALD) was then performed to deposit a 30 nm thick layer of Al2O3 on the sample surface (the side of the first P-type diamond portion 5 furthest from the substrate layer 1). After deposition, the photoresist was removed with acetone solution, which also carried away the Al2O3 covering the photoresist. The sample was then rinsed with deionized water and dried with nitrogen.

[0065] The process conditions for depositing Al2O3 using atomic layer deposition (ALD) are as follows: reaction chamber pressure: 880 Pa; reaction chamber gas: high-purity nitrogen; reaction chamber gas flow rate: 300 sccm; Al2O3 growth rate: 0.5 nm / min; Al2O3 growth time: 40 min - 100 min.

[0066] Step 8, source electrode fabrication, such as... Figure 15 As shown.

[0067] Photoresist was coated onto the sample surface, and the source region was defined by exposure and development using a mask. An electron beam evaporation process was then used to deposit a Ti / Au metal layer with a thickness of (60nm / 120nm)-(80nm / 140nm) (70nm / 130nm in this embodiment) in the source region. After deposition, the sample was immersed in a stripping solution to remove excess metal, and then annealed in an Ar atmosphere at 475°C for 25 min.

[0068] Step 9, Drain electrode fabrication, as follows Figure 16 As shown.

[0069] Photoresist was coated on the sample surface, and the drain region was defined by exposure and development using a mask. A Ti / Pt / Au metal layer with a thickness of 50 nm / 50 nm / 190 nm was deposited in the drain region using electron beam evaporation. After deposition, the sample was placed in a stripping solution to remove excess metal, and then annealed at 475°C in an argon atmosphere for 25 min.

[0070] Step 10, gate electrode fabrication, as follows: Figure 17 As shown.

[0071] Photoresist was coated onto the sample surface, and the gate region was defined by exposure and development using a mask. An electron beam evaporation process was then used to deposit a Ni / Au metal layer with a thickness of (50nm / 100nm)-(60nm / 120nm) (55nm / 110nm in this embodiment) in this region. After deposition, the sample was immersed in a stripping solution to remove excess metal, forming the gate electrode and completing the device fabrication.

[0072] The horizontal structure double heterojunction insulated gate diamond field-effect transistor provided by this invention fully leverages the advantages of diamond material, such as ultra-wide bandgap, ultra-high thermal conductivity, high breakdown field strength, and high carrier saturation velocity, through the synergistic design of the double heterojunction and the insulating gate dielectric layer 6. It can be applied to high-voltage high-efficiency power conversion systems and highly integrated advanced electronic systems.

[0073] In high-voltage, high-efficiency power conversion systems, such as smart grids, new energy power generation, and industrial motor drives, this device not only achieves normally-off characteristics, enhancing gate control accuracy and switching reliability, but its structure also effectively mitigates the electric field concentration effect under high reverse bias, significantly improving withstand voltage levels. Diamond material possesses high thermal conductivity, enabling efficient heat dissipation at high power densities, reducing the system's reliance on cooling devices, and facilitating miniaturization and weight reduction.

[0074] In extreme environment applications, such as power management for deep space probes, downhole electronic systems for oil and gas drilling, and high-temperature industrial sensing and control nodes, the inherent high-temperature stability and strong radiation resistance of diamond materials, along with high-quality insulating gate dielectrics and low-defect interfaces, ensure that the device can operate stably for a long time in high-temperature or high-radiation environments, with minimal performance degradation and a lifespan far exceeding that of traditional devices.

[0075] In high-frequency applications, such as RF power amplifiers in communication base stations and transceiver components in phased array radars, this device can serve as a core power amplifier unit, significantly improving the amplifier's power-added efficiency, output power, and linearity in the millimeter-wave band. In phased array radar transceiver components, the horizontally structured double heterojunction insulated-gate diamond field-effect transistor provided by this invention is easily integrated monolithically with circuits such as phase shifters and low-noise amplifiers. Its excellent thermal conductivity effectively manages the heat generated by the transceiver components within a compact space, ensuring signal consistency and reliability of the radar system under long-term, high duty cycle operation.

[0076] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0077] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A horizontally structured double heterojunction insulated-gate diamond field-effect transistor, characterized in that, Includes a substrate layer and an N-type gallium oxide layer disposed on the substrate layer; The N-type gallium oxide layer includes a source region, a gate region, and a drain region that are sequentially spaced along a horizontal direction. The N-type gallium oxide layer is doped to form an N+ highly doped gallium oxide region, and the orthographic projection of the N+ highly doped gallium oxide region on the substrate layer overlaps with the orthographic projection of the source region on the substrate layer; the source is disposed on the side of the N+ highly doped gallium oxide region away from the substrate layer. The gate region corresponding to the N-type gallium oxide layer is sequentially stacked with a first P-type diamond portion, a gate dielectric layer and a gate. The drain region corresponding to the N-type gallium oxide layer is provided with a second P-type diamond portion and a drain electrode stacked sequentially.

2. The horizontal structure double heterojunction insulated gate diamond field-effect transistor according to claim 1, characterized in that, The thickness of the first P-type diamond portion is 40 nm to 60 nm, and the doping concentration is 1 × 10⁻⁶. 18 cm -3 ~2×10 18 cm -3 ; The thickness of the second P-type diamond portion is 40 nm to 60 nm, and the doping concentration is 1 × 10⁻⁶. 18 cm -3 ~2×10 18 cm -3 .

3. The horizontal structure double heterojunction insulated gate diamond field-effect transistor according to claim 1 or 2, characterized in that, The material of the N-type gallium oxide layer is any one of β-Ga2O3, ZnO, and AlN; The thickness of the N-type gallium oxide layer is 1µm to 2µm, and the depth of the N+ highly doped gallium oxide region is 40nm to 60nm.

4. The horizontal structure double heterojunction insulated gate diamond field-effect transistor according to claim 3, characterized in that, The material of the gate dielectric layer is any one of SiO2, HfO2, and Al2O3; the thickness of the gate dielectric layer is 20nm to 40nm.

5. A method for fabricating a horizontal structure double heterojunction insulated gate diamond field-effect transistor according to any one of claims 1-4, characterized in that, Includes the following steps: S1. Obtain a P-type diamond substrate with a hydrogen-terminated surface as the substrate layer; S2. An N-type gallium oxide layer is grown on the hydrogen-terminated surface side of the P-type diamond substrate; S3. A first insulating dielectric layer is formed on the N-type gallium oxide layer, and the first insulating dielectric layer is patterned to form a window in a preset gate region to expose the underlying N-type gallium oxide layer. S4. A first P-type diamond portion is formed in the preset gate region using microwave plasma chemical vapor deposition process. S5. A second insulating dielectric layer is formed on the upper surface of the N-type gallium oxide layer and the first P-type diamond portion, and the second insulating dielectric layer is patterned to form a window in a preset drain region to expose the underlying N-type gallium oxide layer. A second P-type diamond portion is formed in the preset drain region using microwave plasma chemical vapor deposition. S6. A third insulating dielectric layer is formed on the upper surface of the N-type gallium oxide layer, the first P-type diamond portion and the second P-type diamond portion, and the third insulating dielectric layer is patterned to form a window in a preset source region to expose the underlying N-type gallium oxide layer. S7. Perform silicon ion implantation on the preset source region to form a doping concentration of 4.5 × 10⁻⁶. 19 cm -3 Up to 5.5×10 19 cm -3 A heavily doped gallium oxide region of N+ with a depth of 40nm to 60nm; S8. Using atomic layer deposition process, a gate dielectric layer is deposited on the side of the first P-type diamond portion away from the substrate layer; S9. A source is formed on the side of the N+ highly doped gallium oxide region away from the substrate, a drain is formed on the side of the second P-type diamond region away from the substrate, and a gate is formed on the side of the gate dielectric layer away from the substrate.

6. The method for fabricating a horizontal structure double heterojunction insulated gate diamond field-effect transistor according to claim 5, characterized in that, In step S7, the silicon ion implantation of the preset source region includes two ion implantations. First ion implantation: using an implantation dose of 5 × 10⁻⁶ 14 Si ions with an energy of 10 keV are used to form a doping concentration of 4.5 × 10⁻⁶ ppm in a predetermined source region of the N-type gallium oxide layer. 19 cm -3 -5.5×10 19 cm -3 Doped regions with an implantation depth of 15nm to 25nm; Second ion implantation: Implantation continues in the doped region at a dose of 5 × 10⁻⁶. 14 The Si ions with an energy of 25 keV were ultimately used to form a doping concentration of 4.5 × 10⁻⁶. 19 cm -3 -5.5×10 19 cm -3 An N+ heavily doped gallium oxide region with an implantation depth of 40nm to 60nm was formed.

7. The method for fabricating a horizontal structure double heterojunction insulated gate diamond field-effect transistor according to claim 6, characterized in that, The material of the N-type gallium oxide layer is any one of β-Ga₂O₃, ZnO, and AlN; the thickness of the N-type gallium oxide layer is 1µm to 2µm. The gate dielectric layer is made of any one of SiO2, HfO2, and Al2O3, and the thickness of the gate dielectric layer is 20nm to 40nm.

8. The method for fabricating a horizontal structure double heterojunction insulated gate diamond field-effect transistor according to claim 5, characterized in that, The formation of the first P-type diamond portion includes: using CH4 as the carbon source, H2 as the carrier gas, and B2H6 as the P-type dopant source, epitaxially growing a thickness of 40 nm to 60 nm in a predetermined gate region, with a doping concentration of 1 × 10⁻⁶. 18 cm -3 ~2×10 18 cm -3 The first P-type diamond section; the gas flow ratio is CH4:B2H6:H2=5sccm:0.1sccm:450sccm; The formation of the second P-type diamond portion includes: using CH4 as the carbon source and H2 as the carrier gas, introducing B2H6 as the P-type dopant source, and epitaxially growing a thickness of 40nm to 60nm in a predetermined drain region, with a doping concentration of 1×10⁻⁶. 18 cm -3 ~2×10 18 cm -3 The second P-type diamond section; the gas flow ratio is CH4:B2H6:H2=5sccm:0.1sccm:450sccm.

9. The method for fabricating a horizontal structure double heterojunction insulated gate diamond field-effect transistor according to claim 5, characterized in that, The first insulating dielectric layer, the second insulating dielectric layer, and the third insulating dielectric layer are all made of silicon dioxide, and their thicknesses are all 200nm to 400nm.

10. The method for fabricating a horizontal structure double heterojunction insulated gate diamond field-effect transistor according to claim 5, characterized in that, In step S1, the preparation process of the hydrogen terminal surface includes: using microwave plasma chemical vapor deposition, the P-type diamond substrate is subjected to hydrogen plasma treatment for 3 min to 8 min at a microwave power of 900W to 1000W, a temperature of 850°C to 900°C, and a hydrogen gas flow rate of 100 sccm to 500 sccm.

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