Semiconductor device and method of forming the same

Abstract

Semiconductor devices and methods of forming the same are provided. A semiconductor device can include a first nanostructure, a first source / drain region on a sidewall of the first nanostructure, a first gate structure around the first nanostructure, a second nanostructure over the first nanostructure, a second source / drain region on a sidewall of the second nanostructure, and a second gate structure around the second nanostructure. The first nanostructure can include a first material having a first composition and a first crystal orientation. The second nanostructure can include a second material having a second composition and a second crystal orientation. The first composition can be different from the second composition, and the first crystal orientation can be different from the second crystal orientation.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum part size, allowing more components to be integrated into a given area. As the semiconductor industry further moves towards increased device density, higher performance, and lower costs, challenges from manufacturing and design have led to stacked device configurations, such as stacked transistors, including complementary field-effect transistors (CFETs). While the minimum part size decreases, additional components are introduced. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor device, including: a first nanostructure, wherein the first nanostructure includes a first material having a first composition and a first crystal orientation; a first source / drain region located on the sidewall of the first nanostructure; a first gate structure located around the first nanostructure; a second nanostructure located above the first nanostructure, wherein the second nanostructure includes a second material having a second composition and a second crystal orientation, wherein the first composition is different from the second composition, and wherein the first crystal orientation is different from the second crystal orientation; a second source / drain region located on the sidewall of the second nanostructure; and a second gate structure located around the second nanostructure.

[0005] Other embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a first multilayer stack, wherein the first multilayer stack comprises: a first nanostructure having a first material with a first composition and a first crystal orientation; a first pseudo-nanostructure located above the first nanostructure; a second nanostructure located above the first pseudo-nanostructure having a second material with a second composition and a second crystal orientation, wherein the first composition is different from the second composition, and wherein the first crystal orientation is different from the second crystal orientation; and a second pseudo-nanostructure located above the second nanostructure; growing a first source / drain region on the sidewall of the first nanostructure; growing a second source / drain region on the sidewall of the second nanostructure; and replacing the first pseudo-nanostructure with a first gate structure and replacing the second pseudo-nanostructure with a second gate structure.

[0006] Further embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a first structure, wherein the first structure includes: a first semiconductor layer located over a first substrate, wherein the first semiconductor layer includes a first material; and a first bonding layer located over the first semiconductor layer; forming a second structure, wherein the second structure includes: a second semiconductor layer located over a second substrate, wherein the second semiconductor layer includes a second material, wherein the first material and the second material have different compositions; and a second bonding layer located over the second semiconductor layer; bonding the first bonding layer and the second bonding layer to form a multilayer stack; forming a groove in the multilayer stack, wherein the groove extends through the first semiconductor layer, the first bonding layer, the second semiconductor layer and the second bonding layer; and forming a first source / drain region and a second source / drain region above the first source / drain region in the groove. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of an exemplary stacked transistor according to some embodiments is shown.

[0009] Figure 2A , Figure 2B , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 These are various views of intermediate stages in the fabrication of stacked transistors according to some embodiments.

[0010] Figure 11 , Figure 12 and Figure 13 These are various views of intermediate stages in the fabrication of stacked transistors according to some embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0013] Various embodiments provide semiconductor devices and methods for forming the same. The semiconductor device may be a stacked transistor comprising a vertically stacked upper transistor and a lower transistor. The upper and lower transistors may include gate structures enclosing corresponding semiconductor nanostructures (e.g., channel regions) and source / drain regions located on the sidewalls of the corresponding semiconductor nanostructures. The semiconductor nanostructures of the upper and lower transistors may be formed over semiconductor substrates with different crystal orientations, which may result in the upper and lower transistors being made of materials with different compositions and crystal orientations. Therefore, carrier mobility in the channel regions of the upper and lower transistors can be improved, thereby improving the performance and reliability of the stacked transistor.

[0014] Figure 1An example of a stacked transistor 10 according to some embodiments is shown. Figure 1 This is a perspective view, and some components of the stacked transistors are omitted for clarity. The stacked transistors comprise multiple vertically stacked FETs. For example, the stacked transistors may include a lower nanostructure FET 10L of a first device type (e.g., n-type or p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type or n-type). When the stacked transistors are complementary field-effect transistors (CFETs), the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. The upper nanostructure FET 10U and the lower nanostructure FET 10L include semiconductor nanostructures 24 (including semiconductor nanostructures 24B and 24C), wherein the semiconductor nanostructure 24 serves as a channel region for the nanostructure FET. Semiconductor nanostructure 24C is used for the lower nanostructure FET 10L, and selected semiconductor nanostructure 24B is used for the upper nanostructure FET 10U. In other embodiments, the stacked transistors may be adapted to other types of transistors, nanofield-effect transistors (nanoFETs), fin field-effect transistors (finFETs), etc.

[0015] A gate dielectric 78 surrounds the corresponding semiconductor nanostructure 24. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. Each of the source / drain regions 62 may refer to a source or a drain, individually or collectively, depending on the context. Isolation components (not shown) may be formed to separate selected source / drain regions 62 and / or selected gate electrodes 80. Figure 1 A reference section A-A' is also shown. The reference section A-A' can be a vertical section parallel to the longitudinal axis of the semiconductor nanostructure 24 of the stacked transistor 10 and, for example, in the direction of the current between the source / drain regions 62 of the stacked transistor 10.

[0016] Figures 2A to 10 It is a stacked transistor according to some embodiments, including a lower nanostructure FET and an upper nanostructure FET (which may be similar to...). Figure 1 Various views of intermediate stages in the fabrication of the stacked transistors 10 shown. Figure 2A , Figure 2B , Figure 3 and Figure 4 The overall cross-sectional view is shown. Figure 5 It is similar to Figure 1 A three-dimensional image. Figures 6 to 10 yes Figure 5 The structure shown in the diagram is partly along a path similar to... Figure 1 The cross-sectional view of the reference section A-A' shown in the figure.

[0017] exist Figure 2A and Figure 2B Two substrates, 20L and 20U, are provided separately. Figure 2A Substrate 20L is shown, and Figure 2B Substrate 20U is shown. In subsequent processes, substrate 20U may be bonded over substrate 20L. Substrates 20L and 20U may be semiconductor substrates, such as semiconductor wafers. Substrates 20L and 20U may be doped or undoped. Substrates 20L and 20U may comprise materials having the same composition but different crystal orientations. In some embodiments, substrate 20L comprises silicon with a (110) orientation, and substrate 20U comprises silicon with a (100) orientation.

[0018] Multilayer stacks 14L and 14U are formed over substrates 20L and 20U, respectively. Multilayer stack 14L may include alternating dummy semiconductor layers 14A and semiconductor layers 14C, and a semiconductor layer 14B located above the alternating dummy semiconductor layers 14A and 14C. Multilayer stack 14U may include alternating dummy semiconductor layers 14A and 14B. Figure 2A and Figure 2B The number of pseudo semiconductor layers 14A, semiconductor layers 14B and semiconductor layers 14C in the multilayer stacks 14L and 14U shown are provided as examples, and other numbers of pseudo semiconductor layers 14A, semiconductor layers 14B and semiconductor layers 14C in the multilayer stacks 14L and 14U are considered.

[0019] The pseudo-semiconductor layer 14A, semiconductor layer 14B, and semiconductor layer 14C above substrate 20L may comprise different materials having the same crystal orientation as substrate 20L (such as (110) orientation). The pseudo-semiconductor layer 14A and semiconductor layer 14B above substrate 20U may comprise different materials having the same crystal orientation as substrate 20U (such as (100) orientation). The semiconductor layer 14B above substrate 20L and the semiconductor layer 14B above substrate 20U may comprise materials having the same composition but different crystal orientations. The semiconductor layer 14C above substrate 20L and the semiconductor layer 14B above substrate 20U may comprise different materials with different crystal orientations. The material of the pseudo-semiconductor layer 14A may have etch selectivity for the materials of semiconductor layers 14B and 14C.

[0020] In subsequent processes, as described in more detail below, the semiconductor layer 14C above substrate 20L can be patterned to form the channel region of the lower nanostructure FET, and the semiconductor layer 14B above substrate 20U can be patterned to form the channel region of the upper nanostructure FET. The patterned dummy semiconductor layer 14A can be removed substantially without removing the patterned semiconductor layers 14B and 14C. Because the semiconductor layer 14C above substrate 20L and the semiconductor layer 14B above substrate 20U can include materials with different compositions and crystal orientations, the carrier mobility in the channel regions of both the lower and upper nanostructure FETs can be improved, thereby improving the performance of the subsequently formed stacked transistors.

[0021] In some embodiments, the pseudo-semiconductor layer 14A comprises silicon-germanium having a first germanium concentration (e.g., atomic percentage). In some embodiments, the semiconductor layer 14B above the substrate 20U comprises a semiconductor material suitable for the n-type channel region, such as silicon having a (100) orientation. In some embodiments, the semiconductor layer 14B above the substrate 20L comprises silicon having a (110) orientation. In some embodiments, the semiconductor layer 14C comprises a semiconductor material suitable for the p-type channel region, such as silicon-germanium having a (110) orientation and a second germanium concentration (e.g., atomic percentage) different from the first germanium concentration.

[0022] In some embodiments, the first germanium concentration is in the range of about 35% to about 60%, the second germanium concentration is in the range of about 15% to about 30%, and the first germanium concentration is greater than the second germanium concentration. In some embodiments, the first germanium concentration is in the range of about 15% to about 30%, the second germanium concentration is in the range of about 35% to about 60%, and the first germanium concentration is less than the second germanium concentration.

[0023] The pseudo-semiconductor layer 14A may have a first thickness T1 ranging from about 3 nm to about 12 nm. The semiconductor layer 14B may have a second thickness T2 ranging from about 3 nm to about 12 nm. In some embodiments, the second thickness T2 is greater than the first thickness T1. The semiconductor layer 14C may have a third thickness T3 ranging from about 3 nm to about 12 nm. In some embodiments, the third thickness T3 is greater than the first thickness T1. In some embodiments, the third thickness T3 is equal to the second thickness T2.

[0024] The pseudo-semiconductor layer 14A, semiconductor layer 14B, and semiconductor layer 14C can be formed by: a series of suitable growth processes, such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.; a series of suitable deposition processes, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.; or combinations thereof. In some embodiments, the pseudo-semiconductor layer 14A, semiconductor layer 14B, and semiconductor layer 14C are formed by a series of CVD processes at a temperature ranging from about 500°C to about 760°C and at a pressure ranging from about 1 Torr to about 100 Torr. In such embodiments, silane, disilane, dichlorosilane, diiodosilane, germanane, germanium tetrachloride, germanium diiodide, hydrochloric acid, hydrogen chloride, bromine, and iodine can be used as precursors, and different germanium concentrations in the pseudo-semiconductor layer 14A and semiconductor layer 14C can be achieved by controlling the flow rate of the selected precursor during the corresponding deposition process.

[0025] Bonding layers 18L and 18U can be formed on the multilayer stack 14L and multilayer stack 14U, respectively. Bonding layers 18L and 18U can facilitate… Figure 2A and Figure 2B The subsequent bonding process between the structures shown. Bonding layers 18L and 18U may comprise dielectric materials suitable for dielectric-to-dielectric bonding processes, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, etc. In some embodiments, bonding layers 18L and 18U comprise the same dielectric material. Bonding layer 18L may have a thickness T4 ranging from about 3 nm to about 15 nm. Bonding layer 18U may have a thickness T5 ranging from about 3 nm to about 15 nm. In some embodiments, thickness T4 and thickness T5 are equal. Bonding layers 18L and 18U may be formed by suitable deposition processes, such as physical vapor deposition (PVD), CVD, ALD, etc.

[0026] exist Figure 3 middle, Figure 2A The structure shown is flipped and joined by bonding layers 18L and 18U together. Figure 2B The structure is shown. Bonding layers 18L and 18U can be bonded together using a suitable bonding process, such as a dielectric-to-dielectric bonding process. After the bonding process, the lower bonding layer 18L and bonding layer 18U can be collectively referred to as bonding layer 18. After the bonding process, the interface between bonding layers 18L and bonding layer 18U may disappear or remain. For illustrative purposes, in Figure 3The interface between bonding layers 18L and 18U is omitted in the following figures. The bonding process may include a surface treatment step, such as plasma treatment, followed by a cleaning step performed on the surfaces of bonding layers 18L and 18U. Bonding layer 18U may then be placed on top of and aligned with bonding layer 18L. Bonding layers 18L and 18U may then be pressed together to initiate bonding between them at room temperature during a pressing step. Bonding layers 18L and 18U may then be heated during an annealing step to strengthen the bonding between them.

[0027] exist Figure 4 In this process, a thinning process is performed to remove the pseudo-semiconductor layer 14A that contacts the substrate 20U and the multilayer stack 14U. After the thinning process, the remaining portion of the multilayer stack 14U can be referred to as the multilayer stack 14U'. After the thinning process, the surface of the semiconductor layer 14B of the multilayer stack 14U can be exposed. The thinning process can be a grinding process, chemical mechanical polishing (CMP), an etching process, or a combination thereof. The etching process can be a dry etching process, a wet etching process, or a combination thereof.

[0028] exist Figure 5 In this process, a multilayer stack 14U, a bonding layer 18, a multilayer stack 14L, and a substrate 20L are patterned to form a semiconductor strip 28 extending upward from the substrate 20L. Each semiconductor strip 28 may include a semiconductor fin 20' (which may be a patterned portion of the substrate 20L) and a multilayer stack 22 located above the semiconductor fin 20'. Each multilayer stack 22 may include a pseudo-nanostructure 24A, a semiconductor nanostructure 24B, a semiconductor nanostructure 24C, and a dielectric isolation structure 56. The pseudo-nanostructure 24A can be patterned... Figure 4 The pseudo-semiconductor layer 14A in the structure shown is formed. The semiconductor nanostructure 24B can be formed by patterning. Figure 4 The semiconductor layer 14B in the structure shown is formed. The semiconductor nanostructure 24C can be formed by patterning. Figure 4 The semiconductor layer 14C in the structure shown is formed. The dielectric isolation structure 56 can be formed by patterning. Figure 4 The structure shown is formed by bonding layer 18. Pseudo-nanostructure 24A, semiconductor nanostructure 24B, and semiconductor nanostructure 24C can be collectively referred to as semiconductor nanostructure 24.

[0029] As described in more detail below, the semiconductor nanostructure 24C beneath the dielectric isolation structure 56 can serve as the channel region of the lower nanostructure FET, and the semiconductor nanostructure 24B above the dielectric isolation structure 56 can serve as the channel region of the upper nanostructure FET. The dielectric isolation structure 56, together with the semiconductor nanostructure 24B (which may be a dummy component) in contact with the dielectric isolation structure 56, can define the boundary between the lower and upper nanostructure FETs. The semiconductor fin 20', the semiconductor nanostructure 24, and the dielectric isolation structure 56 can be formed by a suitable patterning process, which may include suitable masking and suitable photolithography.

[0030] Similarly, Figure 5 As shown, an STI region 34 is formed above the substrate 20L and between adjacent semiconductor fins 20'. The STI region 34 may include a dielectric pad and a dielectric material located above the dielectric pad. The dielectric pad and the dielectric material may include dielectric materials such as silicon oxide, silicon nitride, or combinations thereof. The STI region 34 can be formed by depositing a dielectric layer through an ALD, CVD, or similar process, and then performing a planarization process such as CMP to remove excess portions of the dielectric material. An annealing process may be performed after the planarization process. The dielectric layer can then be further recessed using a suitable etching process to form the STI region 34. After the etching process, the semiconductor fins 20' may protrude above the STI region 34.

[0031] After forming the STI region 34, a dummy gate stack 42 can be formed above the upper portion of the semiconductor strip 28 and along the sidewalls of the upper portion of the semiconductor strip 28. This upper portion can be a portion protruding above the STI region 34. Forming the dummy gate stack 42 can include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 can be formed of a dielectric material, such as silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown. A dummy gate layer 38 can be formed above the dummy dielectric layer 36. The dummy gate layer 38 can be formed of amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, etc. The dummy gate layer 38 can be deposited by PVD, CVD, etc. Then, the dummy gate layer 38 can be planarized by CMP, etc.

[0032] Then, a mask layer 40' is formed over the planarized dummy gate layer 38. The mask layer 40' may include silicon nitride, silicon oxynitride, etc. The mask layer 40' can then be patterned using appropriate photolithography and etching processes to form the mask 40 ( Figure 6 (As shown in the diagram), then mask 40 can be used to pattern the dummy gate layer 38 and the dummy dielectric layer 36. Mask 40, the remainder of the dummy gate layer 38, and the dummy dielectric layer 36 can be referred to as dummy gate stack 42 ( Figure 6 (as shown in the image).

[0033] exist Figure 6 In this process, a gate spacer 44 and a source / drain recess 46 are formed. First, the gate spacer 44 is formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by suitable deposition processes such as CVD, ALD, etc. The mask 40 and the gate spacer 44 can be used to protect the dummy gate layer 38 during the subsequent etching process.

[0034] Subsequently, source / drain recesses 46 are formed in semiconductor strip 28. The source / drain recesses 46 are formed by etching and can extend through the multilayer stack 22 and into the semiconductor fin 20'. The bottom surface of the source / drain recesses 46 can be above, below, or flush with the top surface of the STI region 34 (not shown). During the etching process, gate spacers 44 and dummy gate stacks 42 mask portions of semiconductor strip 28. Etching can include a single etching process or multiple etching processes. When the source / drain recesses 46 reach a selected depth, a timing etching process can be used to stop the etching of the source / drain recesses 46.

[0035] exist Figure 7 In the process, the pseudo-nanostructure 24A is partially removed, and an internal spacer 54 is formed. After the partial removal of the pseudo-nanostructure 24A, the sidewalls of the pseudo-nanostructure 24A can be recessed. The pseudo-nanostructure 24A can be partially removed by a suitable etching process. The etching process can selectively remove the material of the pseudo-nanostructure 24A without significantly removing the material of the semiconductor nanostructure 24B, semiconductor nanostructure 24C, dielectric isolation structure 56, or semiconductor fin 20'. The etching process can be a dry etching process using an etchant such as chlorine. The internal spacer 54 can be formed on the recessed sidewalls of the pseudo-nanostructure 24A. Subsequently, a source / drain region can be formed in the source / drain recess 46, and the remaining portion of the pseudo-nanostructure 24A can be replaced with a corresponding gate structure in a subsequent process. The internal spacer 54 can be used to isolate the subsequently formed source / drain region from the subsequently formed gate structure.

[0036] The internal spacer 54 can be formed by conformally depositing a suitable dielectric material on the sidewalls of the pseudo-nanostructure 24A. The dielectric material can then be etched to remove excess portions. The dielectric material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbonitride, silicon oxycarbonate, silicon carbonitride, etc. Other low dielectric constant (low-k) materials with a k value less than about 3.5 can be utilized. The dielectric material can be formed by a suitable deposition process, such as ALD, CVD, etc. The etching of the dielectric material can be anisotropic or isotropic etching processes.

[0037] exist Figure 8 In the source / drain groove 46, a lower epitaxial source / drain region 62L, an upper epitaxial source / drain region 62U, a first contact etch stop layer (CESL) 66, a first interlayer dielectric (ILD) 68, a second CESL 70, and a second ILD 72 are formed. The lower epitaxial source / drain region 62L can refer to either the source or the drain, individually or collectively depending on the context. The upper epitaxial source / drain region 62U can refer to either the source or the drain, individually or collectively depending on the context. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain groove 46. The lower epitaxial source / drain region 62L may contact the semiconductor nanostructure 24C but may not contact the semiconductor nanostructure 24B. The upper epitaxial source / drain region 62U may contact the semiconductor nanostructure 24B but may not contact the semiconductor nanostructure 24C. The lower epitaxial source / drain region 62L can contact the internal spacer 54, which electrically insulates the lower epitaxial source / drain region 62L from the pseudo-nanostructure 24A. The upper epitaxial source / drain region 62U can contact the internal spacer 54, which electrically insulates the upper epitaxial source / drain region 62U from the pseudo-nanostructure 24A. In subsequent processes, the pseudo-nanostructure 24A can be replaced with a replacement gate.

[0038] The lower epitaxial source / drain region 62L is epitaxially grown from the exposed surface of the semiconductor nanostructure 24C and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus or arsenic. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium doped with p-type dopants such as boron or indium. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopants. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surface of the semiconductor nanostructure 24B (e.g., sidewalls) may be masked to prevent undesirable epitaxial growth on the semiconductor nanostructure 24B. After growing the lower epitaxial source / drain region 62L, the mask on the semiconductor nanostructure 24B can then be removed.

[0039] Due to the epitaxial process used to form the lower epitaxial source / drain regions 62L, the upper surface of the lower epitaxial source / drain regions 62L has small planes that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process. In other embodiments, adjacent lower epitaxial source / drain regions 62L are merged together.

[0040] The first CESL 66 and the first ILD 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 can be formed from a dielectric material with high etch selectivity relative to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed from a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0041] The formation process may include: depositing a conformal CESL layer; depositing material for the first ILD 68; a subsequent planarization process; and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the conformal CESL layer unetched. An anisotropic etching process is then performed to remove the portion of the conformal CESL layer above the recessed first ILD 68. After recessing, the sidewalls of the semiconductor nanostructure 24B are exposed.

[0042] Then, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can be epitaxially grown from the exposed surface of the semiconductor nanostructure 24B. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower epitaxial source / drain region 62L, depending on the selected conductivity type of the upper epitaxial source / drain region 62U. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. The upper epitaxial source / drain region 62U can be doped in opposite ways to the lower epitaxial source / drain region 62L. Alternatively, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can have the same conductivity type. The upper epitaxial source / drain region 62U can be in situ doped with n-type or p-type dopants and / or implanted with n-type or p-type dopants.

[0043] Due to the epitaxial process used to form the upper epitaxial source / drain region 62U, the upper surface of the upper epitaxial source / drain region 62U has a small plane that extends laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent upper epitaxial source / drain regions 62U remain separated after the epitaxial process is completed. In other embodiments, adjacent upper epitaxial source / drain regions 62U are merged together.

[0044] After forming the upper epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods can be similar to those of the first CESL 66 and the first ILD 68, respectively. The formation process may include: depositing a conformal CESL layer and the second ILD 72; and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask 40 are substantially coplanar (within process variations). In the illustrated embodiment, the mask 40 is retained after the removal process. In other embodiments, the mask 40 is removed, thereby exposing the top surface of the dummy gate layer 38.

[0045] exist Figure 9In this embodiment, a gate replacement process is implemented to replace the dummy gate stack 42 and the dummy nanostructure 24A with the gate structure 90. The gate replacement process may include first removing the dummy gate stack 42 and the dummy nanostructure 24A. The dummy gate stack 42 can be removed by one or more suitable etching processes. Then, the dummy nanostructure 24A can be removed by an additional suitable etching process. The etching process for removing the dummy nanostructure 24A can selectively remove the material of the dummy nanostructure 24A without significantly removing the material of the semiconductor nanostructures 24B and 24C. The etching process for removing the dummy nanostructure 24A can be a wet isotropic etching process, and etchants such as hydrofluoric acid, nitric acid, and hydrogen peroxide can be used.

[0046] A gate dielectric 78 can then be formed on the exposed surfaces of the semiconductor nanostructure 24 and the internal spacer 54. In some embodiments, the gate dielectric 78 encloses all (e.g., four) sides of the selected semiconductor nanostructure 24. Specifically, the gate dielectric 78 can be formed on the top surface of the semiconductor fin 20'; the top, sidewalls, and bottom surfaces of the selected semiconductor nanostructure 24; and the sidewalls of the internal spacer 54. The gate dielectric 78 can comprise a high dielectric constant (high-k) material having a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric 78 can include MBD, ALD, PECVD, etc., and subsequent planarization processes, such as CMP, to remove the portion of the gate dielectric 78 above the second ILD 72. While a single-layer gate dielectric 78 can be shown, the gate dielectric 78 can comprise multiple layers, such as an interface layer and an upper high-k dielectric layer.

[0047] A lower gate electrode 80L can be formed on the gate dielectric 78 surrounding the semiconductor nanostructure 24C. The lower gate electrode 80L can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. Although a single-layer gate electrode is shown, the lower gate electrode 80L can include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials. The lower gate electrode 80L can be formed by conformally depositing one or more gate electrode layers and recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, or combinations thereof, can be performed to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 80L can expose the semiconductor nanostructure 24B.

[0048] The lower gate electrode 80L can be formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function adjustment layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 80L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or optionally, the lower gate electrode 80L may include a dipole inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0049] In some embodiments, an isolation layer (not shown) may optionally be formed on the lower gate electrode 80L. The isolation layer serves as an isolation component between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc.) and subsequently recessing the dielectric material to expose the semiconductor nanostructure 24B.

[0050] An upper gate electrode 80U may be formed on the isolation layer (if present) or the lower gate electrode 80L described above. The upper gate electrode 80U may be formed around the semiconductor nanostructure 24B. The upper gate electrode 80U may be formed from the same or similar material as the lower gate electrode 80L and by the same or similar process as the lower gate electrode 80L. The upper gate electrode 80U may be formed from a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U may include one or more work function adjustment layers (e.g., an n-type work function adjustment layer or a p-type work function adjustment layer) formed from a material suitable for the device type of the upper nanostructure FET. Although a single-layer upper gate electrode 80U is shown, the upper gate electrode 80U may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0051] A gate mask 92 can be formed on the upper gate structure 90U. The formation process may include: recessing the upper gate structure 90U; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc.; and performing a planarization process to remove excess dielectric material above the second ILD 72 and to make the top surfaces of the gate mask 92 and the second ILD 72 flush. The planarization process may be CMP, etch-back, a combination thereof, etc. After the planarization process, the top surfaces of the gate mask 92, the gate dielectric 78, the second ILD 72, and the gate spacer 44 may be substantially coplanar (within process variations). Each corresponding pair of the gate dielectric 78 and the gate electrode 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) may be collectively referred to as the “gate structure” 90 (including the upper gate structure 90U and the lower gate structure 90L).

[0052] A semiconductor nanostructure 24C located below the dielectric isolation structure 56 and between the lower epitaxial source / drain region 62L can be enclosed by a lower gate structure 90L and used as the channel region of a lower nanostructure FET, which can be a p-type device. A semiconductor nanostructure 24B located above the dielectric isolation structure 56 and between the upper epitaxial source / drain region 62U can be enclosed by an upper gate structure 90U and can be used to form the channel region of an upper nanostructure FET, which can be an n-type device. The semiconductor layer 14C above the substrate 20L can include silicon germanium with a (110) orientation, which can result in improved carrier mobility in the channel region of a p-type device, and the semiconductor layer 14B above the substrate 20U can include silicon with a (100) orientation, which can result in improved carrier mobility in the channel region of an n-type device. Therefore, the carrier mobility in the channel regions of the lower nanostructure FET and the upper nanostructure FET can be improved, thereby improving the performance of the subsequently formed stacked transistors.

[0053] exist Figure 10In this configuration, a metal-semiconductor alloy region 94 is formed on the upper epitaxial source / drain region 62U, and a source / drain contact 96 is formed through the second ILD 72 to electrically couple to the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L. Initially, an opening can be formed through the second ILD 72 and the second CESL 70 using acceptable photolithography and etching processes. Pads (not shown separately), such as diffusion barrier layers and adhesive layers, as well as conductive material, are formed in the opening. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A removal process can then be performed to remove excess material from the top surface of the gate spacer 44 and the second ILD 72. The remaining pads and conductive material form the source / drain contact 96 in the opening. In some embodiments, planarization processes such as CMP, etch-back, and combinations thereof are utilized. After the planarization process, the top surfaces of the gate spacer 44, the second ILD 72, and the source / drain contact 96 are substantially coplanar (within process variations).

[0054] Optionally, a metal-semiconductor alloy region 94 is formed at the interface between the source / drain region 62 and the source / drain contact 96. The metal-semiconductor alloy region 94 can be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanide region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 94 can be formed prior to the material of the source / drain contact 96 by depositing metal in the opening for the source / drain contact 96 and then performing an annealing process. The metal can be any metal capable of reacting with the semiconductor material of the source / drain region 62 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. Metals can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following the annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from openings used for the source / drain contacts 96 (such as from the surface of the metal-semiconductor alloy region 94). Material for the source / drain contacts 96 can then be formed on the metal-semiconductor alloy region 94.

[0055] Then, a third CESL 104 and a third ILD 106 are formed. In some embodiments, the third CESL 104 may include a dielectric material with high etch selectivity relative to the etching of the third ILD 106, such as aluminum oxide, aluminum nitride, silicon carbide, etc. The third ILD 106 may be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which may be deposited by any suitable method, such as CVD, PECVD, etc.

[0056] Subsequently, a gate contact 108 and a source / drain via 110 are formed to contact the upper gate electrode 80U and the source / drain contact 96, respectively. As an example of forming the gate contact 108 and the source / drain via 110, openings for the gate contact 108 and the source / drain via 110 are formed through the third ILD 106 and the third CESL 104. The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately), such as diffusion barrier layers and adhesive layers, as well as conductive material, are formed in the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be implemented to remove excess material from the top surface of the third ILD 106. The remaining pads and conductive material form the gate contact 108 and the source / drain via 110 in the openings. The gate contact 108 and the source / drain via 110 can be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 108 and the source / drain via 110 can be formed in a different cross section, which can avoid short circuits in the contacts.

[0057] A front-side interconnect structure 114 is formed on the third ILD 106. The front-side interconnect structure 114 includes a dielectric layer 116 and a layer of conductive components 118 within the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may also include a passivation layer formed of a non-low-k and dense dielectric material above the low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, or combinations thereof. The dielectric layer 116 may also include a polymer layer.

[0058] Conductive components 118 may include wires and vias, which can be formed using an inlay process. Conductive components 118 may include metal wires and metal vias, which include diffusion barriers and copper-containing material above the diffusion barriers. Aluminum pads electrically connected to the metal wires and vias may also be present above the metal wires and vias. In some embodiments, contacts may be formed through the back side of the substrate 20 (e.g., the side opposite the front interconnect structure 114) to the lower gate structure 90L and the lower epitaxial source / drain region 62L. Figure 10 The structure in it can be called stacked transistor 150.

[0059] Figures 11 to 13 These are various views of intermediate stages in the manufacture of the stacked transistor 150 according to some embodiments. Figure 11 The structure shown is based on Figure 6 The structures shown indicate that the same reference numerals refer to identical parts formed using the same process. Figure 11 In this process, a sacrificial structure 58 is formed to replace the pseudo-nanostructure 24A. This can be achieved through methods similar to those described above. Figure 9 The etching process described is used to remove the pseudo-nanostructure 24A. Replacing the pseudo-nanostructure 24A with a sacrificial structure 58 can provide advantages. For example, in subsequent processes, one or more high-temperature processes, such as source / drain annealing, can be performed, which may cause the material of the pseudo-nanostructure 24A (if not removed) to mix with the materials of the semiconductor nanostructures 24B and 24C. One or more high-temperature processes can also increase the roughness at the interface between the semiconductor nanostructure 24B and the pseudo-nanostructure 24A, as well as at the interface between the semiconductor nanostructure 24C and the pseudo-nanostructure 24A. By replacing the pseudo-nanostructure 24A with the sacrificial structure 58 before one or more high-temperature processes, manufacturing defects can be reduced.

[0060] Forming the sacrificial structure 58 may include depositing a sacrificial material layer in the gaps previously occupied by the source / drain trench 46 and the pseudo-nanostructure 24A. The sacrificial material layer may be deposited using a conformal deposition process such as CVD, ALD, etc. The sacrificial material layer may include an insulating material, such as silicon oxide, which may have high etch selectivity for the dielectric isolation structure 56, the semiconductor nanostructure 24B, and the semiconductor nanostructure 24C. The sacrificial material layer may then be partially removed to form the sacrificial structure 58. The etching process may be isotropic or anisotropic. In some embodiments, the sacrificial material layer is etched using a wet etching process with diluted HF, etc. While the sidewalls of the sacrificial structure 58 are shown aligned with the sidewalls of the semiconductor nanostructure 24, in some embodiments, the sidewalls of the sacrificial structure 58 may be recessed from the sidewalls of the semiconductor nanostructure 24.

[0061] Figure 12 It shows the results of the study on the topic of Figure 11 The structural implementation shown is about Figure 7 The description refers to structures that can be obtained after similar processes, where the same designation indicates the same component formed by the same process. For example... Figure 12 As shown, the sacrificial structure 58 is removed by recessing the sidewalls of the sacrificial structure 58, and an internal spacer 54 is formed on the recessed sidewalls of the sacrificial structure 58. In some embodiments, recessing the sidewalls of the sacrificial structure 58 is related to... Figure 11 The etching process described is performed during the partial removal of the sacrificial material layer. In some embodiments, the sidewalls of the sacrificial structure 58 are recessed by means similar to those described above. Figure 11 The etching process described is completed by another etching process for partially removing the sacrificial material layer.

[0062] Figure 13 It shows that it can be used on Figure 12 The structural implementation shown is about Figure 8 , Figure 9 and Figure 10 The stacked transistors 150 obtained after a similar process are described, wherein the same reference numerals refer to the same components formed by the same process. For example... Figure 13 As shown, the sacrificial structure 58 is removed, and the gate structure 90 is formed in the gap that the sacrificial structure 58 once occupied. This can be achieved as described above. Figure 9 The sacrificial structure 58 is removed in a similar step to the described removal of the pseudo-nanostructure 24A. This can be achieved through steps similar to those described regarding... Figure 11 The etching process described is used to partially remove the sacrificial material layer in order to remove the sacrificial structure 58.

[0063] The embodiments disclosed herein have several advantageous features. Because semiconductor layers 14C and 14B can be formed comprising materials with different compositions and crystal orientations, carrier mobility in the channel regions of the upper and lower nanostructure FETs can be improved. Therefore, the performance of the stacked transistor 150 can be improved.

[0064] In an embodiment, the semiconductor device includes: a first nanostructure, wherein the first nanostructure includes a first material having a first composition and a first crystal orientation; a first source / drain region located on a sidewall of the first nanostructure; a first gate structure located around the first nanostructure; a second nanostructure located above the first nanostructure, wherein the second nanostructure includes a second material having a second composition and a second crystal orientation, wherein the first composition is different from the second composition, and wherein the first crystal orientation is different from the second crystal orientation; a second source / drain region located on a sidewall of the second nanostructure; and a second gate structure located around the second nanostructure. In an embodiment, the first crystal orientation is (110), and the second crystal orientation is (100). In an embodiment, the first composition is silicon-germanium, and the second composition is silicon. In an embodiment, the first composition has a germanium concentration in the range of 35% to 60%. In an embodiment, the first composition has a germanium concentration in the range of 15% to 30%. In an embodiment, the first crystal orientation is (110), and the second crystal orientation is (100). In an embodiment, the semiconductor device further includes a dielectric isolation structure located between the first nanostructure and the second nanostructure.

[0065] In an embodiment, a method for forming a semiconductor device includes: forming a first multilayer stack, wherein the first multilayer stack includes: a first nanostructure having a first material with a first composition and a first crystal orientation; a first pseudo-nanostructure located above the first nanostructure; a second nanostructure located above the first pseudo-nanostructure having a second material with a second composition and a second crystal orientation, wherein the first composition is different from the second composition, and wherein the first crystal orientation is different from the second crystal orientation; and a second pseudo-nanostructure located above the second nanostructure; growing a first source / drain region on the sidewall of the first nanostructure; growing a second source / drain region on the sidewall of the second nanostructure; and replacing the first pseudo-nanostructure with a first gate structure and replacing the second pseudo-nanostructure with a second gate structure. In an embodiment, the first composition is silicon-germanium, and the second composition is silicon. In an embodiment, the first crystal orientation is (110), and the second crystal orientation is (100). In an embodiment, the method further includes forming a dielectric layer between the first source / drain region and the second source / drain region. In one embodiment, forming the first multilayer stack includes: growing a first nanostructure over a first substrate, wherein the first substrate has a first crystal orientation; growing a first pseudo-nanostructure over the first nanostructure; and depositing a first bonding layer over the first pseudo-nanostructure. In another embodiment, forming the first multilayer stack further includes: growing a second nanostructure over a second substrate, wherein the second substrate has a second crystal orientation; growing a second pseudo-nanostructure over the second nanostructure; and depositing a second bonding layer over the second pseudo-nanostructure. In yet another embodiment, forming the first multilayer stack further includes: bonding the first bonding layer to the second bonding layer via dielectric-to-dielectric bonding; and removing the second substrate.

[0066] In an embodiment, a method of forming a semiconductor device includes: forming a first structure, wherein the first structure includes: a first semiconductor layer located over a first substrate, wherein the first semiconductor layer includes a first material; and a first bonding layer located over the first semiconductor layer; forming a second structure, wherein the second structure includes: a second semiconductor layer located over a second substrate, wherein the second semiconductor layer includes a second material, wherein the first material and the second material have different compositions; and a second bonding layer located over the second semiconductor layer; bonding the first bonding layer and the second bonding layer to form a multilayer stack; forming a groove in the multilayer stack, wherein the groove extends through the first semiconductor layer, the first bonding layer, the second semiconductor layer, and the second bonding layer; and forming a first source / drain region and a second source / drain region above the first source / drain region in the groove. In an embodiment, the first material and the second material have different crystal orientations. In an embodiment, the first structure further includes a first dummy layer located between the first bonding layer and the first semiconductor layer, wherein the method further includes: removing the first dummy layer to form a first opening; and forming a dielectric sacrificial structure in the first opening before forming the first source / drain region. In one embodiment, the method further includes removing the dielectric sacrificial structure after forming the first source / drain region. In another embodiment, the first structure further includes a first dummy layer located between the first bonding layer and the first semiconductor layer, wherein the first material is silicon-germanium with a first germanium concentration, wherein the first dummy layer includes silicon-germanium with a second germanium concentration, and wherein the first germanium concentration is greater than the second germanium concentration. In yet another embodiment, the first structure further includes a first dummy layer located between the first bonding layer and the first semiconductor layer, wherein the first material is silicon-germanium with a first germanium concentration, wherein the first dummy layer includes silicon-germanium with a second germanium concentration, and wherein the first germanium concentration is less than the second germanium concentration.

[0067] Some embodiments of this application provide a semiconductor device, including: a first nanostructure, wherein the first nanostructure includes a first material having a first composition and a first crystal orientation; a first source / drain region located on the sidewall of the first nanostructure; a first gate structure located around the first nanostructure; a second nanostructure located above the first nanostructure, wherein the second nanostructure includes a second material having a second composition and a second crystal orientation, wherein the first composition is different from the second composition, and wherein the first crystal orientation is different from the second crystal orientation; a second source / drain region located on the sidewall of the second nanostructure; and a second gate structure located around the second nanostructure.

[0068] In some embodiments, the first crystal orientation is (110), and the second crystal orientation is (100). In some embodiments, the first composition is silicon-germanium, and the second composition is silicon. In some embodiments, the first composition has a germanium concentration in the range of 35% to 60%. In some embodiments, the first composition has a germanium concentration in the range of 15% to 30%. In some embodiments, the first crystal orientation is (110), and the second crystal orientation is (100). In some embodiments, the semiconductor device further includes a dielectric isolation structure located between the first nanostructure and the second nanostructure.

[0069] Other embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a first multilayer stack, wherein the first multilayer stack comprises: a first nanostructure having a first material with a first composition and a first crystal orientation; a first pseudo-nanostructure located above the first nanostructure; a second nanostructure located above the first pseudo-nanostructure having a second material with a second composition and a second crystal orientation, wherein the first composition is different from the second composition, and wherein the first crystal orientation is different from the second crystal orientation; and a second pseudo-nanostructure located above the second nanostructure; growing a first source / drain region on the sidewall of the first nanostructure; growing a second source / drain region on the sidewall of the second nanostructure; and replacing the first pseudo-nanostructure with a first gate structure and replacing the second pseudo-nanostructure with a second gate structure.

[0070] In some embodiments, the first component is silicon-germanium, and the second component is silicon. In some embodiments, the first crystal orientation is (110), and the second crystal orientation is (100). In some embodiments, the method further includes forming a dielectric layer between the first source / drain region and the second source / drain region. In some embodiments, forming the first multilayer stack includes: growing the first nanostructure over a first substrate, wherein the first substrate has the first crystal orientation; growing the first pseudo-nanostructure over the first nanostructure; and depositing a first bonding layer over the first pseudo-nanostructure. In some embodiments, forming the first multilayer stack further includes: growing the second nanostructure over a second substrate, wherein the second substrate has the second crystal orientation; growing the second pseudo-nanostructure over the second nanostructure; and depositing a second bonding layer over the second pseudo-nanostructure. In some embodiments, forming the first multilayer stack further includes: bonding the first bonding layer to the second bonding layer by a dielectric-to-dielectric bonding; and removing the second substrate.

[0071] Further embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a first structure, wherein the first structure includes: a first semiconductor layer located over a first substrate, wherein the first semiconductor layer includes a first material; and a first bonding layer located over the first semiconductor layer; forming a second structure, wherein the second structure includes: a second semiconductor layer located over a second substrate, wherein the second semiconductor layer includes a second material, wherein the first material and the second material have different compositions; and a second bonding layer located over the second semiconductor layer; bonding the first bonding layer and the second bonding layer to form a multilayer stack; forming a groove in the multilayer stack, wherein the groove extends through the first semiconductor layer, the first bonding layer, the second semiconductor layer and the second bonding layer; and forming a first source / drain region and a second source / drain region above the first source / drain region in the groove.

[0072] In some embodiments, the first material and the second material have different crystal orientations. In some embodiments, the first structure further includes a first dummy layer located between the first bonding layer and the first semiconductor layer, wherein the method further includes: removing the first dummy layer to form a first opening; and forming a dielectric sacrificial structure in the first opening before forming the first source / drain region. In some embodiments, the method further includes removing the dielectric sacrificial structure after forming the first source / drain region. In some embodiments, the first structure further includes a first dummy layer located between the first bonding layer and the first semiconductor layer, wherein the first material is silicon-germanium with a first germanium concentration, wherein the first dummy layer includes silicon-germanium with a second germanium concentration, and wherein the first germanium concentration is greater than the second germanium concentration. In some embodiments, the first structure further includes a first dummy layer located between the first bonding layer and the first semiconductor layer, wherein the first material is silicon-germanium with a first germanium concentration, wherein the first dummy layer includes silicon-germanium with a second germanium concentration, and wherein the first germanium concentration is less than the second germanium concentration.

[0073] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor device, comprising: A first nanostructure, wherein the first nanostructure comprises a first material having a first composition and a first crystal orientation; The first source / drain region is located on the sidewall of the first nanostructure; A first gate structure is located around the first nanostructure; A second nanostructure is located above the first nanostructure, wherein the second nanostructure includes a second material having a second composition and a second crystal orientation, wherein the first composition is different from the second composition, and wherein the first crystal orientation is different from the second crystal orientation; The second source / drain region is located on the sidewall of the second nanostructure; and A second gate structure is located around the second nanostructure.

2. The semiconductor device according to claim 1, wherein, The first crystal orientation is (110), and the second crystal orientation is (100).

3. The semiconductor device according to claim 1, wherein, The first component is silicon-germanium, and the second component is silicon.

4. The semiconductor device according to claim 3, wherein, The first component has a germanium concentration in the range of 35% to 60%.

5. The semiconductor device according to claim 3, wherein, The first component has a germanium concentration in the range of 15% to 30%.

6. The semiconductor device according to claim 3, wherein, The first crystal orientation is (110), and the second crystal orientation is (100).

7. The semiconductor device according to claim 1 further includes a dielectric isolation structure located between the first nanostructure and the second nanostructure.

8. A method of forming a semiconductor device, the method comprising: A first multilayer stack is formed, wherein the first multilayer stack comprises: a first nanostructure having a first material with a first composition and a first crystal orientation; a first pseudo-nanostructure located above the first nanostructure; a second nanostructure located above the first pseudo-nanostructure having a second material with a second composition and a second crystal orientation, wherein the first composition is different from the second composition, and wherein the first crystal orientation is different from the second crystal orientation; and a second pseudo-nanostructure located above the second nanostructure. A first source / drain region is grown on the sidewall of the first nanostructure; A second source / drain region is grown on the sidewall of the second nanostructure; and The first pseudo-nanostructure is replaced with a first gate structure, and the second pseudo-nanostructure is replaced with a second gate structure.

9. The method according to claim 8, wherein, The first component is silicon-germanium, and the second component is silicon.

10. A method of forming a semiconductor device, the method comprising: A first structure is formed, wherein the first structure includes: a first semiconductor layer located above a first substrate, wherein the first semiconductor layer includes a first material; and a first bonding layer located above the first semiconductor layer; A second structure is formed, wherein the second structure includes: a second semiconductor layer located above a second substrate, wherein the second semiconductor layer includes a second material, wherein the first material and the second material have different compositions; and a second bonding layer located above the second semiconductor layer; The first bonding layer and the second bonding layer are joined to form a multilayer stack; A groove is formed in the multilayer stack, wherein the groove extends through the first semiconductor layer, the first bonding layer, the second semiconductor layer, and the second bonding layer; and A first source / drain region and a second source / drain region above the first source / drain region are formed in the groove.

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