Cpo multi-chip solder joint packaging method and system

Abstract

The application provides a CPO multi-chip eutectic packaging method and system, which comprises the following steps: controlling a plurality of chip moving adjustment mechanisms to respectively pick up a plurality of chips and move to corresponding preset positions above a chip carrier; collecting image information of the chip carrier and the plurality of chips, and respectively controlling each chip moving adjustment mechanism to adjust the posture of the corresponding chip according to the image information, so that the pads of each chip are coarsely aligned with the corresponding pads on the chip carrier; controlling the chip moving adjustment mechanism to drive the optical chip to perform coupling light finding, and monitoring the optical power in real time; when the detected optical power reaches a specified value, the coupling light finding is completed; controlling the chip moving adjustment mechanism to drive the electrical chip to perform fine adjustment, and monitoring the electrical parameter until the electrical parameter meets the set requirement, and determining that the fine alignment of the electrical chip is completed; after the coupling light finding is completed, the optical chip is fixed with the chip carrier; and after the fine alignment of the electrical chip is completed, the electrical chip is fixed with the chip carrier.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, specifically relating to a CPO multi-chip eutectic packaging method and system. Background Technology

[0002] In related technologies, aligning multiple chips with chip carriers is difficult and time-consuming. Summary of the Invention

[0003] The purpose of this invention is to overcome at least one defect in the prior art and to provide a CPO multi-chip eutectic packaging method and system.

[0004] The technical solution of this invention is implemented as follows: This invention provides a CPO multi-chip eutectic packaging method, comprising the following steps:

[0005] Multiple chip movement and adjustment mechanisms are controlled to pick up multiple chips and move them to the corresponding preset positions above the chip carrier;

[0006] The image information of the chip carrier and multiple chips is collected. Based on the image information of the chip carrier and multiple chips, the movement and adjustment mechanism of each chip is controlled to adjust the attitude of the corresponding chip, so that the pad of the optical chip is roughly aligned with the first pad on the chip carrier and the pad of the electrical chip is roughly aligned with the second pad on the chip carrier.

[0007] The control chip movement and adjustment mechanism drives the optical chips in multiple chips to couple and find light, and monitors the optical power in real time. When the detected optical power reaches the specified value, the coupling and finding of light is completed. The control chip movement and adjustment mechanism drives the electrical chips in multiple chips to make micro-adjustments and monitors the electrical parameters until the electrical parameters meet the set requirements, and the electrical chip is judged to be finely aligned.

[0008] After the optical coupling and light-finding are completed, the optical chip is fixed to the chip carrier. After the electrical chip is precisely aligned, the electrical chip is fixed to the chip carrier.

[0009] In some embodiments, mounting the chip carrier specifically includes: mounting the chip carrier onto the stage by vacuum adsorption.

[0010] In some embodiments, the CPO multi-chip eutectic packaging method of the present invention further includes the following steps: connecting the optical chip to the optical test circuit, so that the test light emitted by the light source is input into the optical chip, and the emitted light of the optical chip is received and monitored in real time by an optical power meter.

[0011] In some embodiments, electrical parameters are monitored until they meet the set requirements, and the electrical chip alignment is determined to be complete. Specifically, this includes monitoring the contact resistance and characteristic impedance until the contact resistance is less than the resistance threshold and the characteristic impedance matches the target value, and the electrical chip alignment is determined to be complete.

[0012] In some embodiments, after the optical coupling and light-finding are completed, the position of the chip movement adjustment mechanism corresponding to the optical chip is locked, and after the electrical chip is precisely aligned, the position of the chip movement adjustment mechanism corresponding to the electrical chip is locked to ensure that there is no offset in the relative pose of the optical chip, the electrical chip and the chip carrier.

[0013] The micro probe is connected to the test point of the pads on the electrical chip and the second pad on the chip carrier. The contact resistance and characteristic impedance data are collected in real time using an impedance analyzer or a micro resistance tester.

[0014] In some embodiments, after the optical coupling is completed, the optical chip is bonded and fixed to the chip carrier using eutectic solder.

[0015] In some embodiments, after the electrical chip is precisely aligned, the electrical chip is bonded and fixed to the chip carrier using eutectic solder.

[0016] This invention also discloses a CPO multi-chip eutectic packaging system, comprising:

[0017] A stage, the stage being configured to fix a chip carrier;

[0018] Multiple chip movement and adjustment mechanisms are provided, each equipped with a chip clamp. The chip clamp is configured to pick up a chip. The chip movement and adjustment mechanisms are electrically connected to a control unit. Each chip movement and adjustment mechanism is configured to drive the chip clamp mounted on it to move and adjust the chip posture.

[0019] A vision mechanism is configured to acquire image information of a chip carrier and multiple chips, and transmit the image information of the chip carrier and multiple chips to a control unit.

[0020] In some embodiments, the chip fixture includes a suction head and a heating module, the heating module being used to heat the suction head;

[0021] The suction head is equipped with a cooling unit for cooling the chip.

[0022] In some embodiments, the CPO multi-chip eutectic packaging system of the present invention further includes an optical power monitoring unit, which includes a light source and an optical power monitoring module. The test light emitted by the light source is input to the optical chip via a coupling component. The emitted light from the optical chip is received and monitored in real time by the optical power monitoring module, and the power value is fed back to the control unit.

[0023] And / or,

[0024] It also includes an electrical parameter monitoring unit, which includes a microprobe assembly and an electrical testing module. The microprobe of the microprobe assembly is electrically connected between the pad of the electrical chip and the test point of the second pad on the chip carrier. The electrical testing module is used to collect contact resistance and characteristic impedance data and feed the contact resistance and characteristic impedance data back to the control unit.

[0025] The chip movement adjustment mechanism is a six-axis displacement stage. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic flowchart of a CPO multi-chip eutectic packaging method disclosed in one embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0030] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; in the description of this invention, unless otherwise stated, "a plurality of" or "several" means two or more.

[0031] See Figure 1 This invention provides a CPO multi-chip eutectic packaging method, comprising the following steps:

[0032] Mounting chip carrier;

[0033] Multiple chip movement and adjustment mechanisms are controlled to pick up multiple chips and move them to the corresponding preset positions above the chip carrier;

[0034] The image information of the chip carrier and multiple chips is collected. Based on the image information of the chip carrier and multiple chips, the movement and adjustment mechanism of each chip is controlled to adjust the attitude of the corresponding chip, so that the pad of the optical chip is roughly aligned with the first pad on the chip carrier and the pad of the electrical chip is roughly aligned with the second pad on the chip carrier.

[0035] The control chip movement and adjustment mechanism drives the optical chips in multiple chips to couple and find light, and monitors the optical power in real time. When the detected optical power reaches the specified value, the coupling and finding of light is completed. The control chip movement and adjustment mechanism drives the electrical chips in multiple chips to make micro-adjustments (micro-steps) and monitors the electrical parameters until the electrical parameters meet the set requirements, and the electrical chip is judged to be finely aligned.

[0036] After the optical coupling and light-finding are completed, the optical chip is fixed to the chip carrier. After the electrical chip is precisely aligned, the electrical chip is fixed to the chip carrier.

[0037] The solution adopts a composite alignment strategy that combines image recognition coarse alignment with optical power closed-loop fine alignment / electrical parameter closed-loop fine alignment. Image coarse alignment quickly converges the alignment error by recognizing the feature marks of the chip and chip carrier pads, solving the problems of "difficult alignment and long time consumption". The optical power fine alignment / electrical parameter closed-loop fine alignment greatly improves the alignment accuracy and directly solves the problem of excessive coupling loss caused by insufficient mechanical alignment accuracy.

[0038] In some embodiments, the chip carrier is a silicon interposer.

[0039] In CPO chip packaging technology, the silicon interposer is the core interconnect and carrier platform, playing a crucial "bridging" role. It serves as the fixing carrier for optical and electrical chips, as well as the bonding substrate for the chip (FA), while simultaneously enabling high-density interconnection of optoelectronic signals. The silicon interposer has a first pad for fixing the optical chip and a second pad for fixing the electrical chip.

[0040] In some embodiments, mounting the chip carrier specifically includes: mounting the chip carrier onto the stage by vacuum adsorption.

[0041] In some embodiments, the CPO multi-chip eutectic packaging method of the present invention further includes the following steps: connecting the optical chip to the optical test circuit, so that the test light emitted by the light source is input into the optical chip, and the emitted light of the optical chip is received and monitored in real time by an optical power meter.

[0042] In some embodiments, electrical parameters are monitored until they meet the set requirements, and the electrical chip alignment is determined to be complete. Specifically, this includes monitoring the contact resistance and characteristic impedance until the contact resistance is less than the resistance threshold (e.g., 50 mΩ, the resistance threshold is set as needed) and the characteristic impedance matches the target value (e.g., 50 Ω, the target value is set as needed), and the electrical chip alignment is determined to be complete.

[0043] In some embodiments, after the optical coupling and light-finding are completed, the position of the chip movement adjustment mechanism corresponding to the optical chip is locked, and after the electrical chip is precisely aligned, the position of the chip movement adjustment mechanism corresponding to the electrical chip is locked to ensure that there is no offset in the relative pose of the optical chip, the electrical chip and the chip carrier.

[0044] The micro probe is connected to the test point of the pads on the electrical chip and the second pad on the chip carrier. The contact resistance and characteristic impedance data are collected in real time using an impedance analyzer or a micro resistance tester.

[0045] In some embodiments, coupling and light-finding are performed, and the optical power is monitored in real time. The coupling and light-finding is completed when the optical power to be detected reaches a specified value. This includes: using a gradient descent algorithm to drive the chip micro-scan until the optical power of each channel reaches a specified value (such as more than 95% of the preset peak value) and stabilizes for a set time.

[0046] In some embodiments, after the optical coupling is completed, the optical chip is bonded and fixed to the chip carrier using eutectic solder.

[0047] In some embodiments, after the electrical chip is precisely aligned, the electrical chip is bonded and fixed to the chip carrier using eutectic solder.

[0048] In some embodiments, the optical chip and the electrical chip can employ the same eutectic process.

[0049] In some embodiments, the eutectic process includes: preheating the chip to a first set temperature using a heating module;

[0050] Move the chip above the chip carrier solder layer and align the chip with the corresponding chip carrier solder layer. Then control the heating end face of the suction head to heat up to the second set temperature to melt the eutectic solder between the chip and the chip carrier.

[0051] After the heating end face of the pick-up tip is heated to the eutectic temperature and stabilized for a first set time, the pick-up tip applies a set bonding pressure to spread the molten solder evenly on the interface between the chip and the chip carrier. The heat and pressure are maintained for a second set time to ensure that the solder is completely melted.

[0052] In some embodiments, after the heat preservation and pressure holding are completed, the following steps are also included: starting the cooling module to cool and reduce the temperature of the chip and chip carrier, so that the molten eutectic solder can be quickly solidified to form a bonding layer;

[0053] When the chip temperature drops below the third set temperature, the suction head releases the bonding pressure, shuts off the vacuum adsorption, and then transfers back to the pick-up station, completing the transfer of a chip and eutectic bonding.

[0054] This invention enables precise alignment and temperature and pressure control, ensuring submicron-level alignment between the chip and the chip carrier solder layer, improving the optical transmission efficiency of subsequent fiber coupling in the CPO module, and reducing optical loss.

[0055] This invention adds an active cooling step after heat preservation and pressure holding, which enables the molten solder to solidify rapidly, inhibits the abnormal growth of intermetallic compounds, forms a dense and uniform bonding layer, and improves bonding strength and thermal conductivity.

[0056] In some embodiments, the first set temperature is lower than the eutectic temperature, the second set temperature is equal to the eutectic temperature, and the third set temperature is lower than the first set temperature. The solder completely solidifies when the chip temperature drops below the third set temperature.

[0057] This invention also discloses a CPO multi-chip eutectic packaging system, comprising:

[0058] A stage, the stage being configured to fix a chip carrier;

[0059] Multiple chip movement and adjustment mechanisms are provided, each equipped with a chip clamp. The chip clamp is configured to pick up a chip. The chip movement and adjustment mechanisms are electrically connected to a control unit. Each chip movement and adjustment mechanism is configured to drive the chip clamp mounted on it to move and adjust the chip posture.

[0060] A vision mechanism is configured to acquire image information of a chip carrier and multiple chips, and transmit the image information of the chip carrier and multiple chips to a control unit.

[0061] In some embodiments, the chip fixture includes a suction head and a heating module for heating the suction head.

[0062] In some embodiments, the suction head is provided with a cooling unit for cooling the chip.

[0063] In some embodiments, the CPO multi-chip eutectic packaging system of the present invention further includes an optical power monitoring unit, which includes a light source and an optical power monitoring module. The test light emitted by the light source is input to the optical chip via a coupling component. The emitted light from the optical chip is received and monitored in real time by the optical power monitoring module, and the power value is fed back to the control unit.

[0064] In some embodiments, the CPO multi-chip eutectic packaging system of the present invention further includes an electrical parameter monitoring unit, which includes a micro probe assembly and an electrical testing module. The micro probe of the micro probe assembly is electrically connected between the pad of the chip and the test point of the second pad on the chip carrier. The electrical testing module is used to collect contact resistance and characteristic impedance data and feed the contact resistance and characteristic impedance data back to the control unit.

[0065] In some embodiments, the chip movement adjustment mechanism is a six-axis displacement stage.

[0066] In some embodiments, the stage may have a built-in heating / cooling module. The stage uses vacuum adsorption to hold the chip carrier.

[0067] In some embodiments, the vision mechanism includes a first vision module for acquiring images of a preset area from a top-down perspective. The optical axis of the first vision module is vertically downward, pointing towards the preset area.

[0068] In some embodiments, the vision mechanism includes a second vision module for acquiring images from a side view of a preset area. The optical axis of the second vision module is tilted downwards, toward the attitude adjustment station.

[0069] Each vision module is connected to the control unit, and each vision module is used to transmit the acquired images to the control unit. This invention is not limited to the aforementioned vision modules; vision modules with other perspectives can be added as needed.

[0070] In some embodiments, the CPO multi-chip eutectic packaging system of the present invention further includes a temperature sensor, which is connected to the input terminal of the control unit and the output terminal of the control unit is electrically connected to the heating module. The temperature sensor is used to provide real-time feedback of chip temperature data to the control unit so that the control unit can control the temperature of the heating module.

[0071] In some embodiments, the CPO multi-chip eutectic packaging system of the present invention further includes a pressure sensor, which is used to collect the actual bonding pressure between the chip and the substrate and feed the pressure signal back to the control unit. The control unit controls the Z-axis displacement of the material movement adjustment mechanism through PID closed-loop adjustment based on the deviation between the set pressure value and the actual pressure, thereby accurately controlling the bonding pressure applied to the chip and ensuring pressure stability during the holding pressure stage.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A CPO multi-chip eutectic packaging method, characterized in that, Includes the following steps: Multiple chip movement and adjustment mechanisms are controlled to pick up multiple chips and move them to the corresponding preset positions above the chip carrier; The image information of the chip carrier and multiple chips is collected. Based on the image information of the chip carrier and multiple chips, the movement and adjustment mechanism of each chip is controlled to adjust the attitude of the corresponding chip, so that the pad of the optical chip is roughly aligned with the first pad on the chip carrier and the pad of the electrical chip is roughly aligned with the second pad on the chip carrier. The control chip movement and adjustment mechanism drives the optical chips in multiple chips to couple and find light, and monitors the optical power in real time. When the detected optical power reaches the specified value, the coupling and finding of light is completed. The control chip movement and adjustment mechanism drives the electrical chips in multiple chips to make micro-adjustments and monitors the electrical parameters until the electrical parameters meet the set requirements, and the electrical chip is judged to be finely aligned. After the optical coupling and light-finding are completed, the optical chip is fixed to the chip carrier. After the electrical chip is precisely aligned, the electrical chip is fixed to the chip carrier.

2. The CPO multi-chip eutectic packaging method as described in claim 1, characterized in that: The process of mounting the chip carrier specifically includes: mounting the chip carrier onto the stage using vacuum adsorption.

3. The CPO multi-chip eutectic packaging method as described in claim 1, characterized in that: It also includes the following steps: connecting the optical chip to the optical test circuit, so that the test light emitted by the light source is input into the optical chip, and the emitted light of the optical chip is received and monitored in real time by the optical power meter.

4. The CPO multi-chip eutectic packaging method as described in claim 1, characterized in that: The electrical parameters are monitored until they meet the set requirements, at which point the precision alignment of the electrical chip is considered complete. Specifically, this includes monitoring the contact resistance and characteristic impedance until the contact resistance is less than the resistance threshold and the characteristic impedance matches the target value, at which point the precision alignment of the electrical chip is considered complete.

5. The CPO multi-chip eutectic packaging method as described in claim 1, characterized in that: After the optical coupling and light-finding are completed, the position of the chip movement adjustment mechanism corresponding to the optical chip is locked. After the electrical chip is precisely aligned, the position of the chip movement adjustment mechanism corresponding to the electrical chip is locked to ensure that there is no offset in the relative pose of the optical chip, electrical chip and chip carrier.

6. The CPO multi-chip eutectic packaging method as described in claim 1, characterized in that: After the optical coupling is completed, the optical chip is bonded and fixed to the chip carrier using eutectic solder.

7. The CPO multi-chip eutectic packaging method as described in claim 1, characterized in that: After the electrical chip is precisely aligned, it is bonded and fixed to the chip carrier using eutectic solder.

8. A CPO multi-chip eutectic packaging system, characterized in that, include: A stage, the stage being configured to fix a chip carrier; Multiple chip movement and adjustment mechanisms are provided, each equipped with a chip clamp. The chip clamp is configured to pick up a chip. The chip movement and adjustment mechanisms are electrically connected to a control unit. Each chip movement and adjustment mechanism is configured to drive the chip clamp mounted on it to move and adjust the chip posture. A vision mechanism is configured to acquire image information of a chip carrier and multiple chips, and transmit the image information of the chip carrier and multiple chips to a control unit.

9. The CPO multi-chip eutectic packaging system as described in claim 8, characterized in that: The chip fixture includes a suction head and a heating module, the heating module being used to heat the suction head; The suction head is equipped with a cooling unit for cooling the chip.

10. The CPO multi-chip eutectic packaging system as described in claim 8, characterized in that: It also includes an optical power monitoring unit, which includes a light source and an optical power monitoring module. The test light emitted by the light source is input to the optical chip through a coupling component. The emitted light from the optical chip is received and monitored in real time by the optical power monitoring module, and the power value is fed back to the control unit. And / or, It also includes an electrical parameter monitoring unit, which includes a microprobe assembly and an electrical testing module. The microprobe of the microprobe assembly is electrically connected between the pad of the electrical chip and the test point of the second pad on the chip carrier. The electrical testing module is used to collect contact resistance and characteristic impedance data and feed the contact resistance and characteristic impedance data back to the control unit.

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