A PCBA fault detection method and system

Abstract

This invention discloses a PCBA fault detection method and system, relating to the field of electronic manufacturing inspection technology. The method includes: scanning the surface and internal dielectric layer of a fault-free PCBA in a static state using a non-contact dielectric sensor array to obtain intrinsic dielectric constant distribution data; generating a three-dimensional dielectric topological reference field model based on the intrinsic dielectric constant distribution data; capturing the dynamic change waveform of the global dielectric constant of the PCBA under test in a powered-on operating state using a dielectric probe array; performing a spatiotemporal superposition comparison between the dynamic change waveform and the reference field model; identifying regions where the dielectric constant offset exceeds a preset threshold and marking them as potential fault areas. This invention achieves high-precision, non-destructive online fault location, significantly improving the detection rate of internal PCBA defects and reducing the risk of misjudgment.

Description

Technical Field

[0001] This invention relates to the field of electronic manufacturing inspection technology, and in particular to a PCBA fault detection method and system. Background Technology

[0002] As a core component of various electronic devices, the operational stability of the PCBA (Printed Circuit Board Assembly) directly determines the overall performance and safety level of the device. In the context of the rapid development of the current electronics manufacturing industry, the design of circuit board assemblies is becoming increasingly sophisticated, and the density of component placement is constantly increasing, posing increasingly severe challenges to traditional fault detection methods. Traditional testing techniques mainly rely on contact measurement methods, requiring the establishment of physical connections on the pins or test points of the circuit board under test. This method is not only cumbersome but also prone to causing additional physical damage to the delicate circuit board. At the same time, traditional methods also require applying additional test excitation signals to the circuit board, which may interfere with the normal operation of the circuit board and affect the accuracy of the test results.

[0003] More importantly, traditional contact-based testing methods have significant blind spots. Traditional visual inspection can only detect obvious defects on the surface of the circuit board, and is often powerless to detect latent faults hidden in the internal dielectric layer, such as loose solder joints, minor breaks in the circuit, and drifting of component parameters. These latent faults are difficult to detect when the circuit board leaves the factory, but will gradually emerge during actual use, seriously affecting the reliability and lifespan of electronic products, posing safety hazards to users, and causing high after-sales maintenance costs and market reputation losses for manufacturers. Summary of the Invention

[0004] In view of this, the present invention proposes a PCBA fault detection method and system to solve the problem of missed detection of latent faults in the prior art.

[0005] The specific technical solution of this invention is as follows: A PCBA fault detection method, comprising: When a fault-free PCBA is in a static state, its surface and internal dielectric layer are scanned by a non-contact dielectric sensor array to obtain intrinsic dielectric constant distribution data. Based on the intrinsic dielectric constant distribution data, a three-dimensional dielectric topological reference field model is generated; For the PCBA under test in the powered-on working state, the dynamic waveform of its global dielectric constant change during operation is captured by a dielectric probe array; The dynamic waveform is spatiotemporally superimposed and compared with the reference field model; Identify areas where the dielectric constant offset exceeds a preset threshold in the comparison results and mark them as potential fault areas.

[0006] Specifically, within the potential fault region, the conduction path of the node with a sudden change in dielectric constant is traced in reverse along the direction of the dielectric equipotential line; it is determined whether the conduction path forms a closed loop within a preset time window; it is determined whether the closed-loop conduction path has a logical conflict with the known circuit topology; if the conduction path forms a closed loop within the time window and has a logical conflict, then the node is determined to be a real fault point.

[0007] Specifically, generating the three-dimensional dielectric topology reference field model includes: acquiring intrinsic dielectric constant measurements of the fault-free PCBA at multiple spatial locations and frequencies using a non-contact dielectric sensor array; constructing a three-dimensional continuous field model reflecting the spatial distribution of the dielectric constant of the dielectric layer of the fault-free PCBA through spatial interpolation and frequency domain fitting algorithms based on the measurements; and normalizing the three-dimensional continuous field model to obtain the three-dimensional dielectric topology reference field model.

[0008] Specifically, capturing the dynamic change waveform of the global dielectric constant includes: during the power-on operation of the PCBA under test, the instantaneous value of the dielectric constant of each spatial point in the global domain is collected in real time through a dielectric probe array at a preset sampling frequency and spatial resolution; the sequence of the change of the dielectric constant of each spatial point over time is recorded to form the dynamic change waveform of the global dielectric constant.

[0009] Specifically, identifying regions where the dielectric constant offset exceeds a preset threshold includes: processing data obtained by spatiotemporal superposition and comparison using a dielectric property change analysis algorithm; the algorithm is used to calculate the spatial gradient and time rate of change of the dielectric constant; and identifying regions exceeding the preset threshold based on the gradient and rate of change.

[0010] Specifically, the spatiotemporal superposition and comparison of the dynamically changing waveform with the reference field model includes: in the time dimension, comparing the dielectric constant distribution data of each time point in the dynamically changing waveform with the reference value at the corresponding spatial location in the reference field model point by point; in the spatial dimension, calculating the gradient change of the dielectric constant of the dynamically changing waveform relative to the reference field model in a preset spatial neighborhood; and combining the comparison results in the time dimension and the gradient change in the spatial dimension to identify spatial regions where the dielectric constant offset exceeds a preset threshold.

[0011] Specifically, the reverse tracing of the conduction path of the dielectric constant abrupt change node along the direction of the dielectric equipotential line includes: locating the node where the dielectric constant changes abruptly in the potential fault region as the starting point of the tracing; starting from the tracing starting point, tracing in the opposite direction of the maximum gradient of the dielectric equipotential line at that point; and recording the sequence of spatial nodes traversed during the tracing process to form the conduction path.

[0012] A PCBA fault detection system for performing the above method includes: The reference field modeling unit is configured to generate a three-dimensional dielectric topology reference field model by scanning with a non-contact dielectric sensor array when the PCBA is in a fault-free static state. The dynamic data acquisition unit is configured to capture the dynamic change waveform of the global dielectric constant through a dielectric probe array when the PCBA under test is powered on. An abnormal region identification unit is configured to perform spatiotemporal superposition and comparison of dynamically changing waveforms with a reference field model, and identify and mark potential fault areas through a dielectric property change analysis algorithm.

[0013] Specifically, the system also includes a fault point determination unit, configured to trace the conduction path of the dielectric constant mutation node in reverse along the direction of the dielectric equipotential line within the potential fault area, and determine the actual fault point based on whether the path forms a closed loop and has a logical conflict with the known circuit topology.

[0014] Specifically, the system also includes: a control processing unit, which connects and coordinates the workflow of the control reference field modeling unit, dynamic data acquisition unit, abnormal area identification unit, and fault point determination unit; a data storage unit, which stores the three-dimensional dielectric topology reference field model, the dynamic change waveform of the global dielectric constant, the identified abnormal area information, the traced conduction path information, and the determination results; and a result output unit, which outputs the location information of the actual fault point and the determination basis.

[0015] The beneficial effects of this invention are as follows: 1. By non-contact full-domain scanning of fault-free PCBA samples and constructing their exclusive three-dimensional dielectric characteristic benchmark model, a unique and reliable fault-free state reference standard is established for this model of PCBA, which significantly improves the accuracy and reliability of subsequent fault detection.

[0016] 2. When the PCBA under test is in actual working condition, a high-sensitivity non-contact detection method is used to synchronously capture its full-domain dielectric dynamic changes, realizing truly non-invasive online detection without shutdown, disassembly, physical contact or damage, greatly expanding the applicability of the detection scenarios.

[0017] 3. By using computer algorithms to perform in-depth comparative analysis of real-time dielectric dynamic data and benchmark models, it is possible to quickly and automatically identify and accurately locate abnormal areas where dielectric properties deviate significantly from the normal range, providing a clear target for troubleshooting.

[0018] 4. Within the identified abnormal area, the conduction path of dielectric property changes is traced through a specific logic verification mechanism, which can effectively distinguish between abnormalities caused by real circuit faults and misjudgments caused by environmental interference and other factors, further improving the accuracy of fault location.

[0019] 5. The system can output detailed information including fault location, characteristic data, and maintenance suggestions, providing accurate and efficient technical guidance for subsequent maintenance or repair work, and significantly reducing equipment downtime and maintenance costs. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating the PCBA fault detection method of the present invention. Detailed Implementation

[0022] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0023] This invention proposes a PCBA fault detection method and system, whose core technical principle is based on the inherent correlation between the dielectric properties of the dielectric material and the operating state of the circuit. When a PCBA is in different operating states, the dielectric material inside it will experience subtle changes in its dielectric constant due to current heating effects and electromagnetic field disturbances. Although these changes are extremely weak, they can be completely captured by highly sensitive sensing detection methods and will exhibit regular characteristics that highly match the normal fault-free state of the PCBA. This invention utilizes this principle to achieve accurate identification and location of PCBA faults by establishing a benchmark reference model and comparing and analyzing real-time detection data.

[0024] like Figure 1As shown, the method of the present invention mainly includes the following steps: When the fault-free PCBA is in a static state, a non-contact dielectric sensor array scans the intrinsic dielectric constant distribution of its surface and internal dielectric layers to generate a three-dimensional dielectric topology reference field model; zero additional excitation is applied to the PCBA under test in a powered-on state, and the dynamic change waveform of the global dielectric constant caused by current thermal effects and electromagnetic field disturbances is synchronously captured only by a high-sensitivity dielectric probe array; the dynamic change waveform is spatiotemporally superimposed and compared with the reference field model, and an abnormal region where the dielectric constant offset exceeds a preset threshold is identified by a dielectric constant gradation current algorithm and marked as a potential fault region; within the abnormal region, the conduction path of the dielectric constant mutation node is traced in reverse along the direction of the dielectric equipotential line. If the path forms a closed loop within a preset time window and has a logical conflict with the known circuit topology, it is determined to be a real fault point. The specific implementation of this method is as follows: Step S10: Establish a reference dielectric field model. Specifically, for each type of PCBA product to be tested, firstly, select a batch of good PCBAs from the same period that are completely fault-free and have undergone multiple rounds of quality verification as a reference sample; place this sample in a completely static, non-energized state to ensure that no interference from current or external electromagnetic fields is avoided; then, use a two-dimensional sensor array composed of multiple non-contact dielectric sensors to perform a full-domain scan of the surface and all internal dielectric layers of the PCBA, collecting intrinsic dielectric constant distribution data at different spatial locations; finally, process all the collected point data through a data integration algorithm to construct a three-dimensional dielectric topology reference field model representing the normal fault-free state of this type of PCBA. Step S10 includes steps S11 to S14, as follows: Step S11: Select a suitable PCBA sample as a reference standard. The selection standard is that the PCBA must have undergone multiple rounds of quality verification to confirm that it is completely free of faults and has not experienced any abnormalities during use. Specific selection standards may include no obvious defects in appearance inspection, passing all functional tests, and no performance degradation in aging tests. Only after all requirements are met can it be used as a benchmark sample.

[0025] Step S12: Place the reference sample in a dedicated testing station, keeping it in a static, unpowered state. The reason for requiring the PCBA to be in a static, unpowered state is that in this state, there is no current flow or electromagnetic field activity within the PCBA, and the dielectric properties of the dielectric material are entirely determined by its inherent material properties, unaffected by any external factors. Only the dielectric constant distribution data collected in this state can truly represent the intrinsic dielectric properties of the PCBA itself. If data is collected while the PCBA is powered on, the collected data will contain dynamic changes caused by current heating effects and electromagnetic field disturbances; these components should not be included in the data range of the reference field model.

[0026] In a normal, static state, the inherent dielectric properties of all materials used in a board, including substrate dielectric, conductive lines, soldering materials, and electronic component packaging, are stable and uniform. Boards of the same model exhibit a high degree of consistency in their intrinsic dielectric constant distribution under the same environment.

[0027] Step S13: Activate the non-contact dielectric sensor array to perform a full-range scan of the sample. The dielectric sensor array consists of multiple high-precision sensing elements that can sense the dielectric constant distribution of the surface and internal layers of the object being measured. The sensor array operates on a non-contact principle, ensuring no physical contact with the PCBA surface during scanning. Therefore, it will not cause electrostatic damage or physical scratches to precision components, nor will it adversely affect good PCBAs. The non-contact scanning characteristic also allows the sensor to penetrate surface coverings and completely capture the dielectric distribution information from the PCBA surface to all internal dielectric layers. Whether it's the inner layer circuitry of a multilayer board or the solder joints hidden at the bottom of the chip package, everything can be completely detected.

[0028] When a dielectric sensor array scans a reference sample, it acquires data point-by-point across the surface area of ​​the PCBA and each internal dielectric layer. Since a PCBA is a three-dimensional structure, the dielectric thickness, material composition, and structural characteristics vary at different locations, resulting in different distributions of the dielectric constant. By scanning from multiple angles and positions, the sensor array can obtain intrinsic dielectric constant distribution data for various locations on the PCBA. These scattered spatial point data reflect the dielectric properties at different regions and depths within the PCBA.

[0029] Specifically, the sensor array used consists of M×N distributed dielectric sensor units arranged in a rectangular pattern. Each sensor unit includes a dielectric sensing probe and a signal amplification circuit. The scanning process employs a partitioned scanning strategy, dividing the entire PCBA into multiple scanning sub-regions. Each sub-region is covered by a corresponding sensor sub-array, and adjacent sub-regions maintain a 50% overlap rate to ensure data stitching continuity. The scanning resolution of the sensor array is set according to the complexity of the PCBA.

[0030] Step S14 integrates all spatial point data collected by the sensor array to form a complete dielectric property distribution dataset for the PCBA. However, this raw data still needs to be processed and integrated by a specialized computing system to generate a high-quality reference field model for subsequent testing. The data processing includes filtering and denoising, error correction, and spatial interpolation of the raw data to integrate discrete spatial point data into a continuous three-dimensional dielectric topology distribution image. This three-dimensional dielectric topology reference field model digitally records the intrinsic dielectric property distribution law of this PCBA under normal fault-free conditions, possessing uniqueness and irreplaceability.

[0031] To ensure the accuracy and reliability of the reference field model, the scanning and data acquisition process typically undergoes multiple rounds of repeated verification. By performing multiple independent scans and measurements on the same reference sample, and then comparing and analyzing the results, random errors and environmental interference factors that may occur during a single measurement can be effectively identified and eliminated. For PCBAs with particularly complex structures, the number of scans and sampling density can be appropriately increased to collect more data points to generate the reference field model, further improving the stability and representativeness of the reference data. This multiple averaging process effectively avoids the impact of random errors that may occur during a single scan on the accuracy of the reference field model, ensuring that the final generated reference field model truly reflects the intrinsic properties of the PCBA.

[0032] Each PCBA product with a different design requires a separate reference field model; different PCBA models cannot share the same reference field model. Even PCBAs manufactured by the same company will exhibit significant differences in intrinsic dielectric property distribution if their models, designs, and materials differ. If a reference field model of model A is used to test a PCBA of model B, the test results will be completely invalid because the dielectric property distributions under normal, fault-free conditions are inherently inconsistent. Therefore, before mass production or formal use, each newly designed PCBA product must have its own dedicated reference field model established and stored in the testing system's database.

[0033] The final generated 3D dielectric topology reference field model's data structure is organized in the form of a hierarchical object model. The top layer is the model root object, which includes the following data fields: Model Identifier field stores a globally unique identifier generated using the UUIDv4 algorithm; Model Version Number field stores a triplet of major version number, minor version number, and revision number following semantic versioning specifications; Creation Timestamp field stores complete time information in ISO8601 standard format; PCBA Type Code field stores the product's model code string; Dielectric Layer Count field stores the layer count statistics in integer type; Scan Resolution field stores a triplet containing horizontal resolution, vertical resolution, and depth resolution; 3D Dielectric Constant Field Data field stores 3D matrix data in sparse tensor format, using COO format to store the position index and corresponding value of non-zero elements; Normal Threshold Range field stores threshold distribution parameters calculated based on statistical methods, including the mean vector and covariance matrix; Model Metadata field stores additional information such as sensor configuration parameters, environmental condition parameters, and scan duration.

[0034] Once the reference field model is established, it will be permanently stored in the testing system's database. Subsequent testing of this PCBA model can directly retrieve the corresponding reference field model from the database, eliminating the need to rebuild the model for each test. This one-time modeling and long-term use design significantly improves testing efficiency and reduces the time and resource consumption associated with repetitive modeling. Furthermore, the reference field model can be dynamically optimized and iteratively updated based on a large amount of normal, fault-free product data accumulated during subsequent testing, continuously improving the model's accuracy and adaptability.

[0035] In step S10, the raw analog signal output from the sensor array is first converted into a digital signal by an analog-to-digital converter, then transmitted to the preprocessing module for data cleaning, and then transmitted to the modeling module for 3D field model construction. Finally, the constructed model is serialized and stored in the model database. The model database adopts a distributed storage architecture. The main database stores the model's index information and metadata, while the sharded databases store complete 3D field data according to PCBA model classification.

[0036] Step S20: When testing the PCBA under test, it is only necessary to ensure that the PCBA is in a normal powered-on operating state. No additional test stimulus needs to be applied to the PCBA, nor is it necessary to solder or connect any test lines to the PCBA. The testing process uses only an array of highly sensitive dielectric probes to simultaneously capture the dynamic change waveform of the dielectric constant across the entire range caused by the thermal effect generated by the current and the electromagnetic field disturbance during PCBA operation. This step completely simulates the operating state of the PCBA in actual use scenarios. The acquisition process will not interfere with the normal operation of the PCBA, nor will it cause any physical contact or damage to the PCBA itself, achieving truly non-invasive testing. Step S20 includes steps S21 and S22, as follows: Step S21: Place the PCBA under test into its normal power-on operating state. This includes providing the PCBA with a power supply that meets its design specifications, allowing the various electronic components on the PCBA to operate in their normal working mode. After the PCBA enters its normal operating state, internal current begins to flow, the electronic components begin to perform their respective functions, and the entire PCBA is in an active operating state. In this state, the dielectric material of the PCBA will experience slight changes in its dielectric constant due to the thermal effect generated by the current and electromagnetic field disturbances.

[0037] Although these changes in dielectric constant are extremely small, they exhibit a highly regular correlation with the operating state of the PCBA. When the current load distribution on the PCBA changes, the dielectric material at the corresponding location will change its dielectric properties due to temperature variations. When electromagnetic field fluctuations occur in the circuit, the dielectric material will also undergo polarization response due to the electromagnetic field, resulting in a corresponding change in the dielectric constant. This change is continuous and exhibits dynamic fluctuation characteristics as the PCBA's operating state changes.

[0038] Step S22: When the PCBA under test is in normal power-on operation, a high-sensitivity dielectric probe array is used to perform full-domain synchronous data acquisition on the PCBA. The dielectric probe array is a high-sensitivity sensing device specifically designed to capture changes in the dielectric properties of the medium; its sensitivity is sufficient to detect extremely small fluctuations in the dielectric constant. Similar to the sensor array used when establishing the reference field model, the dielectric probe array also adopts a non-contact working principle, and will not have any physical contact with the PCBA surface during the scanning and acquisition process.

[0039] The dielectric probe array's scanning coverage includes the surface area of ​​the PCBA and all internal dielectric layers, enabling simultaneous capture of continuous waveform data of dielectric dynamic changes across the entire area. This simultaneous full-area capture characteristic ensures comprehensive and complete detection, preventing the omission of any abnormal fluctuations in minute areas and overcoming the limitation of traditional point-based detection methods that can only cover preset test points.

[0040] It is particularly worth emphasizing that the entire dynamic data acquisition process does not require any additional test stimulus signals to the PCBA. The PCBA operates entirely on its own power supply system and functional circuits, and the testing equipment passively receives and acquires the dielectric response signals naturally generated during PCBA operation. This zero-external-stimulation testing method allows testing to be performed while the PCBA is operating normally, without needing to remove the PCBA from the equipment or stop the equipment's operation.

[0041] This characteristic makes this testing method applicable to a wide range of scenarios. In the manufacturing process, it allows for online sampling inspection of finished PCBAs on the production line, eliminating the need for a dedicated inspection station and ensuring uninterrupted production. In operation and maintenance, it enables online testing of running equipment without shutting it down, allowing for troubleshooting without disassembly and significantly reducing economic losses from equipment downtime. In after-sales service, it can quickly pinpoint the problem area of ​​a faulty PCBA, providing precise technical guidance for repair work.

[0042] Specifically, the dielectric probe array consists of P distributed probe units. The spatial arrangement of the probe units is completely consistent with the sensor array topology used when establishing the reference field model, ensuring that the measurement spatial coverage of the two processes is the same. The sampling frequency of the probe array is automatically determined according to the operating characteristics of the PCBA.

[0043] The data structure of the real-time data collected in step S20 includes the following components: (1) The dynamic waveform acquisition data object is the core data structure. The analog signal output by each probe unit is first amplified by a low-noise amplifier, and then filtered by an anti-aliasing filter before being sent to an analog-to-digital converter for digital sampling. The sampled time-series data is organized in units of data frames. Each frame includes the sampled values ​​of all probes at that moment. The frame structure includes a frame number field, a timestamp field, a probe quantity field, and an array field of sampled values ​​for each probe. The frame data is temporarily stored in a circular buffer and then transmitted to the main control processing system via a high-speed data bus.

[0044] (2) The probe array topology data object stores the spatial coordinate position information of each probe. Its data structure is an array of length P, with the array index corresponding to the probe number (from 0 to P-1). Each array element is a probe position object, including the following fields: X-axis coordinate stores the position of the probe in the X direction of the PCBA plane (in millimeters); Y-axis coordinate stores the position of the probe in the Y direction of the PCBA plane (in millimeters); Z-axis coordinate stores the vertical height of the probe from the PCBA surface (in millimeters); probe type identifier stores the specification code of the probe; and calibration coefficient array stores the individualized calibration parameters of the probe. The probe array topology data is loaded from the configuration file during system initialization and remains unchanged during subsequent testing.

[0045] (3) The global waveform data object is the result of fusing the independent sampling data of each probe into continuous spatiotemporal field data, which is represented by a four-dimensional tensor structure. The first dimension represents the spatial X-axis position, and the dimension size is equal to the number of sampling points in the X direction; the second dimension represents the spatial Y-axis position, and the dimension size is equal to the number of sampling points in the Y direction; the third dimension represents the spatial Z-axis position, and the dimension size is equal to the number of sampling points in the Z direction; the fourth dimension represents the time series, and the dimension size is equal to the total number of sampling points within the sampling duration. Each element in the four-dimensional tensor stores the change in dielectric constant after normalization at that spatiotemporal position. The normalization process is to subtract the corresponding position reference value and divide by the reference value to obtain the dimensionless relative change rate. The data generation process of the global waveform data object is as follows: receive the original sampling frame data from each probe, map the scattered data points to the corresponding positions of the four-dimensional tensor according to the frame timestamp and probe position information, and calculate the complete spatiotemporal continuous field data from the surrounding probe data using a trilinear interpolation algorithm for spatial positions not directly covered by the probe.

[0046] Step S30, Abnormal Dielectric Constant Region Location: Specifically, the real-time acquired dynamic waveform data is superimposed and compared with a pre-established reference field model in both time and space dimensions. A dedicated dielectric constant grading algorithm is used to filter out abnormal regions where the dielectric constant offset exceeds a preset threshold, and these regions are marked as potential fault areas. This step fully utilizes the powerful data processing capabilities of computer algorithms to achieve rapid and automatic location of abnormal regions, significantly narrowing the scope of subsequent fault investigation.

[0047] After receiving the real-time dynamic dielectric response data of the PCBA under test, the computing system first preprocesses the data, including data format conversion, noise filtering, and time synchronization, to ensure that the data quality meets the requirements of subsequent analysis. After preprocessing, the computing system overlays and compares the real-time dynamic data with a pre-stored reference field model of the PCBA model.

[0048] The comparative analysis is performed simultaneously in both time and space dimensions. Spatially, the computing system compares the real-time dielectric constant data of each location on the PCBA with the corresponding normal, fault-free state data in the reference field model, calculating the dielectric constant offset at each location. Temporally, the computing system analyzes the waveform characteristics of the dielectric constant change over time at each location in the real-time data, comparing it with the standard waveform in the reference field model. Through this spatiotemporal overlay comparison, regions differing from the normal state can be comprehensively and accurately identified.

[0049] The comparative analysis process utilizes a specialized dielectric constant grading algorithm. This algorithm is specifically optimized for the characteristics of dielectric constant distribution data, enabling efficient processing of massive spatial point data and time-series waveform data. The algorithm calculates and analyzes the dielectric constant offset at each location on the PCBA, identifying areas where the offset exceeds a preset normal threshold as abnormal regions.

[0050] In a normally operating PCBA, the dynamic fluctuation range of the dielectric constant at each location will always remain within a preset reasonable threshold. This is because, under healthy conditions, although the dielectric properties of the dielectric material will change due to current heating effects and electromagnetic field disturbances, these changes are limited and remain within a range consistent with normal operating conditions. Only when a PCBA malfunctions, such as poor solder joint contact leading to abnormal localized heating, a micro-short circuit causing current overload and resulting in electromagnetic field disturbances, or internal component damage causing deviations in operating parameters, will the dielectric constant change at the corresponding location exceed the normal threshold.

[0051] When the algorithm identifies a region where the dielectric constant offset exceeds a normal threshold, it automatically marks that region as a potential fault area. This automatic marking mechanism requires no manual intervention; the system can automatically locate the abnormal region. The algorithm also automatically records relevant data such as the spatial coordinates of the abnormal region, the degree of parameter offset, and the waveform of the change trend, providing rich reference data for subsequent fault determination.

[0052] After locating the abnormal area, the system outputs the marking information of potential fault areas, significantly narrowing down the scope of subsequent troubleshooting. Traditional detection methods require checking every location on the PCBA one by one, resulting in extremely low efficiency. However, with this method, only the marked abnormal areas need to be focused on, improving detection efficiency by several times or even tens of times.

[0053] This anomaly localization method based on dielectric constant variation analysis has unique advantages. Because the detection relies on changes in the dielectric properties of the dielectric material, even faults hidden within the dielectric layers of a PCBA, such as micro-short circuits in the inner layers of a multilayer board or loose connections at the bottom solder joints of a chip package, can be effectively identified through changes in the dielectric constant. This completely solves the problem that traditional optical inspection methods can only identify surface defects.

[0054] The preset offset threshold can be flexibly adjusted according to specific application scenarios and detection requirements. For applications with extremely high reliability requirements, such as aerospace equipment, medical equipment, and industrial control systems, the threshold can be set lower to improve the detection rate of minor anomalies and avoid missing any potential faults. For scenarios with relatively low reliability requirements, such as ordinary consumer electronics products, the threshold can be appropriately increased to reduce the false alarm rate and minimize false alarms caused by oversensitivity.

[0055] The data processing flow for spatiotemporal overlay comparison is divided into the following stages: First, the time alignment stage, which aligns the time axis of the four-dimensional global waveform data with the time reference of the reference field model. Since the reference field model is static (a constant field in the time dimension), it is necessary to compress the global waveform data along the time dimension by taking statistical characteristic values ​​(such as average or peak values) to generate a three-dimensional spatial field as the real-time dielectric response characteristic field. Then, the spatial registration stage, which accurately registers the spatial coordinates of the real-time dielectric response characteristic field with the three-dimensional spatial coordinates of the reference field model to ensure that the spatial sampling points of the two correspond one-to-one. Finally, the difference calculation stage, which calculates the difference in dielectric constant at corresponding positions of the two to generate offset field data.

[0056] The offset field data object maintains the same spatial resolution and topological structure as the three-dimensional dielectric constant field data of the reference field model, but the data type stored at each location differs. The data fields stored at each spatial location in the offset field data object include: a location identifier field storing a unique index triplet (i, j, k) of that location in three-dimensional space; a reference value field storing the original dielectric constant of the corresponding location in the reference field model; a real-time value field storing the value of the corresponding location in the real-time captured dielectric response feature field; an absolute offset field storing the absolute difference between the real-time value and the reference value; a relative offset rate field storing the percentage of the absolute offset relative to the reference value; an offset direction field indicating whether the offset is increasing or decreasing; a confidence score field storing the confidence rating of the offset value based on data quality assessment; and a timestamp field storing the time window information on which the offset calculation is based.

[0057] The preset threshold data object stores standard parameters used to determine anomalies. Its data structure includes the following components: a global threshold field stores a single fixed threshold value; when the relative offset exceeds this threshold, it is directly determined to be an anomaly; a distributed threshold field stores dynamic threshold parameters calculated based on statistical methods, including three subfields: the baseline mean vector, the baseline covariance matrix, and the confidence multiple; during determination, the Mahalanobis distance of the offset at each location is calculated, and when it exceeds the threshold determined by the confidence multiple and the covariance matrix, it is determined to be an anomaly; a hierarchical threshold field stores differentiated thresholds set for different region types, including core functional areas, interface areas, and edge areas, and the thresholds for different region types can be different; a time-varying threshold field stores dynamic thresholds that take into account time factors, using a more lenient threshold at the beginning of detection and gradually tightening the threshold as the detection time increases to improve detection sensitivity.

[0058] The processing flow and data structure of the intermediate elevator speed-up algorithm are as follows: The first step is gradient calculation. For each spatial location in the offset field data object, a three-dimensional gradient vector is calculated. The gradient vector represents the direction and rate of the fastest change in offset at that location. The gradient calculation uses the finite difference method. For non-boundary locations, the central difference formula is used; for boundary locations, forward or backward difference formulas are used for approximation. The calculated gradient field data is stored as a three-dimensional vector field with the same structure as the offset field, storing the three components G of the gradient vector at each location. x G y G z And the gradient magnitude |G|.

[0059] The second step is isosurface extraction, which extracts isosurfaces from the offset field whose offsets equal to a threshold. Isosurface extraction uses the Marching Cubes algorithm to generate a geometric representation composed of multiple triangular facets. The isosurface data is stored as an array of facets, with each facet object including vertex coordinates, a normal vector, facet area, and adjacent facet indices. The isosurfaces divide the offset field into two regions: regions with offsets greater than the threshold and regions with offsets less than or equal to the threshold.

[0060] The third step is region labeling, which identifies connected regions with offsets greater than a threshold as potential fault areas. Connected region identification employs a seed-point-based floodfill algorithm. Starting from seed points within the isosurface, it recursively searches along directions with offsets greater than the threshold, labeling all reachable locations to form a connected region. Each connected region is assigned a unique region number as an independent potential fault area. The region labeling results are stored as a label field data object, with the same data structure as the offset field, but each location stores either a region number or a zero value (representing a non-abnormal region).

[0061] The fourth step is the calculation of regional features, which involves calculating statistical characteristics for each marked potential fault area. Regional features include region volume (number of spatial locations contained within), region centroid location (volume-weighted average coordinates), region average offset rate, maximum offset rate, offset variance, and region shape descriptors (aspect ratio, compactness, etc.). Regional feature data is stored as a regional feature array, with each array element corresponding to a potential fault area and including all statistical feature values ​​for that area.

[0062] Step S40, fault path backtracking verification: Specifically, within the marked abnormal region, the conduction path is traced backward along the direction of the dielectric equipotential line to find the node where the dielectric constant changes abruptly. If this conduction path forms a closed loop within a preset normal time window, and this closed loop logically conflicts with the known circuit topology of the PCBA itself, then this node can be determined to be the actual fault point. This verification mechanism effectively eliminates misjudgments caused by environmental interference and other factors, ultimately confirming the actual existence and specific location of the fault point.

[0063] The potential fault area located in step S30 is an abnormal region identified based on the single condition that the dielectric constant offset exceeds a threshold. However, abnormal offsets in the dielectric constant are not necessarily caused by actual faults; they may also be caused by other non-fault factors. For example, temporary interference from external electromagnetic fields, sudden changes in ambient temperature, and normal fluctuations during PCBA operation can all cause temporary offsets in the dielectric constant of certain areas. If all dielectric anomalies are indiscriminately classified as faults, a large number of misjudgments will occur, severely affecting the accuracy of the detection results.

[0064] To address this issue, this invention specifically designs a fault path backtracking verification mechanism. The core idea of ​​this mechanism is to analyze whether the dielectric constant change in the abnormal region exhibits the conduction characteristics that a real fault should possess. The dielectric anomaly caused by a real fault does not exist in isolation, but rather spreads systematically along the circuit's conduction path. This diffusion path can be traced by analyzing the distribution of dielectric equipotential lines.

[0065] During backtracking verification, the computing system traces the propagation path of dielectric constant abrupt changes along the direction of dielectric constant equipotential lines within the marked potential fault areas. Equipotential lines are curves connecting points with equal dielectric constants; the dielectric constant remains unchanged along the direction of the equipotential lines, while the gradient of change in dielectric constant is greatest perpendicular to the equipotential lines. By tracing the distribution and direction of the equipotential lines, the propagation path of dielectric anomalies within the PCBA can be reconstructed.

[0066] If the traced conduction path forms a closed loop within a reasonable time window, and the logical direction of this closed loop conflicts with the pre-stored normal circuit topology of this PCBA model, then this node can be determined as a real fault point. This is because a real fault will cause abnormal current paths or electromagnetic field distributions in the circuit, and these anomalies will exhibit dielectric properties that conflict with the normal circuit topology. Dielectric anomalies caused by external interference and other factors are usually global and irregular, and will not form closed-loop paths that conflict with the circuit topology; therefore, they can be effectively distinguished and eliminated.

[0067] Through this closed-loop verification logic, the system can effectively eliminate misjudgments caused by external environmental interference, significantly improving the accuracy of detection results. Even latent faults such as poor soldering and poor contact, which only manifest during operation, can be accurately identified.

[0068] After confirming the fault location, the system outputs the precise location coordinates, dielectric offset characteristic data, and corresponding fault type analysis. The system also matches the detection results with common fault types stored in the database, automatically providing possible causes and corresponding repair suggestions. This information provides precise technical guidance for subsequent maintenance and repair work, enabling maintenance personnel to quickly and accurately locate the fault, understand its nature, and take targeted corrective measures.

[0069] Step S40 includes steps S41 to S44: Step S41: Within the marked potential fault region, starting from the position with the highest dielectric constant (determined based on offset field data), reverse tracing is performed along the direction of the dielectric equipotential lines. Equipotential lines are lines connecting points with equal dielectric constants. The tracing process essentially involves finding the path in the opposite direction of the dielectric constant gradient, i.e., searching from high-value points to low-value points. The tracing algorithm employs an improved version of the gradient-based hill-climbing algorithm: starting from the starting point, the dielectric gradient vector of that point is calculated, and then the algorithm moves one step distance in the opposite direction of the gradient vector. This process is repeated after reaching a new position until a local minimum is reached or the tracing range is exceeded. All path node information is recorded during the tracing process.

[0070] The data structure for dielectric equipotential line tracing includes the following components: (1) Path node data object is the basic unit of the tracking process. Its data structure includes: node identifier field, which stores the sequence number of the node in the tracking sequence; spatial coordinate field, which stores the three-dimensional coordinates (x, y, z) of the node; dielectric constant value field, which stores the measured value of the dielectric constant of the node; arrival timestamp field, which stores the system time when the node is accessed; gradient direction field, which stores the normalized gradient vector at the node; previous node reference field, which stores the reference or null value of the previous node in the tracking sequence; and successor node reference field, which stores the reference or null value of the next node in the tracking sequence.

[0071] (2) Tracking path data objects are represented by an ordered linked list structure consisting of multiple path node data objects. The data structure includes: path identifier field, which stores the unique number of the path; path node list field, which stores the array of path nodes connected in order; path start coordinate field, which stores the coordinates of the starting node of the path; path end coordinate field, which stores the coordinates of the ending node of the path; path length field, which stores the total number of nodes included in the path; and path total distance field, which stores the straight-line distance from the starting point to the end point of the path or the weighted sum of the path lengths.

[0072] Step S42: Detect whether the tracked path forms a closed loop within a preset time window. The criteria for loop closure detection include: the spatial distance between the end point and the start point of the path is less than a preset closure threshold; the difference in dielectric properties between the end point and the start point of the path is less than a preset similarity threshold; and the time taken for the path to form a closed loop is within a preset time window (e.g., the time difference from the start point to the end point does not exceed a specified multiple of the sampling period).

[0073] The data structure for loop closure detection includes: a loop closure determination data object, whose fields include a loop closure identifier (Boolean field) indicating whether a loop has been formed; a closure start node reference, storing the node object in the path determined to be the closure start point; a closure end node reference, storing the node object in the path determined to be the closure end point; a closure distance field, storing the spatial distance between the start and end points; a closure time difference field, storing the timestamp difference between the start and end points; and a closure confidence field, storing the comprehensive confidence score based on the above determination conditions.

[0074] Step S43 involves logically comparing the detected closed-loop path with the known PCBA topology to determine if there is a logical conflict within the closed loop. The circuit topology data originates from pre-stored PCBA design information, including circuit schematic connectivity data and PCB layout and routing data.

[0075] The specific method for topology conflict detection is as follows: First, map the closed-loop path to the set of nodes and edges in the circuit topology and identify all circuit nodes traversed by the closed-loop path; then check whether these circuit nodes should have a connection relationship under normal circumstances. If the connection relationship implied by the closed-loop path contradicts the design topology (e.g., the closed-loop path implies a conduction path between two nodes that should not be directly connected), it is determined to be a topology conflict.

[0076] The data structure for topology collision detection includes: a topology collision data object, whose fields include a collision identifier (Boolean field) indicating whether a collision exists; a collision type enumeration field indicating the category of collision (nodes should not be connected, path bypasses prohibited areas, signal type mismatch, etc.); a collision node list, storing an array of circuit node identifiers involved in the collision; a collision description field, storing a textual description of the collision situation; and a collision weight field, storing the fault probability weight corresponding to this type of collision.

[0077] Step S44: Based on the closed-loop detection results and the topology conflict detection results, a comprehensive judgment is made to determine whether the potential fault area is a real fault point.

[0078] The decision logic is implemented using a decision tree model. The input features of the decision tree include: closed loop identifier (Boolean value), closed distance value, closed time difference value, closed loop confidence score, topological conflict identifier (Boolean value), conflict type enumeration value, conflict node number value, and conflict weight value.

[0079] The decision tree's judgment rules are as follows: First, check if the closed-loop indicator is true. If it is, it is determined to be non-faulty (external interference). If the closed-loop indicator is true, then check if the closed-loop confidence exceeds the confidence threshold. If it is lower than the threshold, it is determined to be questionable and requires manual review. If the closed-loop indicator is true and the closed-loop confidence meets the standard, then check if the topology conflict indicator is true. If there is a topology conflict, it is determined to be a real fault point. If there is no topology conflict, it is determined to be a suspected fault and manual review is recommended.

[0080] The system of this invention mainly includes: The reference field modeling unit is configured to generate a three-dimensional dielectric topology reference field model by scanning with a non-contact dielectric sensor array when the PCBA is in a fault-free static state. The dynamic data acquisition unit is configured to capture the dynamic change waveform of the global dielectric constant through a dielectric probe array when the PCBA under test is powered on. An abnormal region identification unit is configured to perform spatiotemporal superposition and comparison of dynamically changing waveforms with a reference field model, and identify and mark potential fault areas through a dielectric property change analysis algorithm. The fault point determination unit is configured to trace the conduction path of the dielectric constant change node in reverse along the direction of the dielectric equipotential line within the potential fault area, and determine the real fault point based on whether the path forms a closed loop and has a logical conflict with the known circuit topology. The control processing unit connects and coordinates the workflows of the control reference field modeling unit, dynamic data acquisition unit, abnormal area identification unit, and fault point determination unit. The data storage unit is used to store the three-dimensional dielectric topological reference field model, the dynamic change waveform of the global dielectric constant, the identified abnormal region information, the traced conduction path information, and the judgment results; The result output unit is used to output the location information of the actual fault point and the basis for judgment.

[0081] The beneficial effects of this invention are as follows: 1. In terms of non-destructive testing, the entire testing process is conducted in a completely non-contact manner, causing no physical contact or damage to the PCBA. Testing can be performed while the PCBA is operating normally, requiring no additional test stimulus signals or removal of the PCBA from the equipment. This non-invasive testing method effectively protects the integrity of precision electronic equipment and avoids the risk of secondary damage that may be caused by traditional testing methods.

[0082] 2. In terms of applicability across all scenarios, this method can be used for mass production line testing, prototype performance testing during the R&D phase, and troubleshooting in after-sales maintenance. Whether in a factory production environment or an on-site maintenance environment, and whether for standardized mass-produced PCBAs or small-batch customized special PCBAs, this method can quickly adapt and complete the testing task without requiring customized tooling development or test program adjustments for different products.

[0083] 3. In terms of efficiency, the system automatically locates abnormal areas and accurately identifies fault points through intelligent algorithms, significantly reducing the time required for testing. Furthermore, the testing process eliminates the need for manual inspection of every location on the PCBA, greatly improving efficiency compared to traditional methods. In addition, pre-test preparation is very simple, requiring no pre-setting of test points or soldering of test circuits on the PCBA, allowing for rapid deployment.

[0084] 4. Regarding accuracy, the system employs a multi-layered verification mechanism to ensure the reliability of the detection results. First, abnormal areas are screened out using a dielectric constant offset threshold. Then, fault path backtracking verification eliminates misjudgments caused by external interference and other factors, ultimately confirming fault points with a high accuracy rate. This method can also accurately locate internal hidden faults that are difficult to detect using traditional methods, such as cold solder joints, micro-short circuits, and component performance drift.

[0085] 5. In terms of cost, this method does not require customized test fixtures or tooling equipment, nor does it require pre-setting test points or reserving test interfaces on the PCBA. The upfront investment cost for testing is far lower than that of traditional customized testing solutions. At the same time, due to its high testing efficiency and accuracy, it can effectively reduce after-sales maintenance costs and market reputation losses caused by missed detections.

[0086] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A PCBA fault detection method, characterized in that, include: When a fault-free PCBA is in a static state, its surface and internal dielectric layer are scanned by a non-contact dielectric sensor array to obtain intrinsic dielectric constant distribution data. Based on the intrinsic dielectric constant distribution data, a three-dimensional dielectric topological reference field model is generated; For the PCBA under test in the powered-on working state, the dynamic waveform of its global dielectric constant change during operation is captured by a dielectric probe array; The dynamic waveform is spatiotemporally superimposed and compared with the reference field model; Identify regions in the comparison results where the dielectric constant offset exceeds a preset threshold and mark them as potential fault areas.

2. The PCBA fault detection method as described in claim 1, characterized in that, Within the potential fault region, the conduction path of the node with a sudden change in dielectric constant is traced in reverse along the direction of the dielectric equipotential line; it is determined whether the conduction path forms a closed loop within a preset time window; it is determined whether the closed-loop conduction path has a logical conflict with the known circuit topology; if the conduction path forms a closed loop within the time window and has a logical conflict, then the node is determined to be a real fault point.

3. The PCBA fault detection method as described in claim 1, characterized in that, The generation of the three-dimensional dielectric topology reference field model includes: using the non-contact dielectric sensor array to obtain the intrinsic dielectric constant measurements of the fault-free PCBA at multiple spatial locations and frequency points; based on the measurements, constructing a three-dimensional continuous field model reflecting the spatial distribution of the dielectric constant of the dielectric layer of the fault-free PCBA through spatial interpolation and frequency domain fitting algorithms; and normalizing the three-dimensional continuous field model to obtain the three-dimensional dielectric topology reference field model.

4. The PCBA fault detection method as described in claim 1, characterized in that, Capturing the dynamic change waveform of the global dielectric constant includes: during the power-on operation of the PCBA under test, acquiring the instantaneous value of the dielectric constant of each spatial point in the global domain in real time through the dielectric probe array at a preset sampling frequency and spatial resolution; recording the sequence of the change of the dielectric constant of each spatial point over time to form the dynamic change waveform of the global dielectric constant.

5. The PCBA fault detection method as described in claim 1, characterized in that, Identifying regions where the dielectric constant offset exceeds a preset threshold includes: processing the data obtained from the spatiotemporal superposition comparison using a dielectric property change analysis algorithm; the algorithm is used to calculate the spatial gradient and time rate of change of the dielectric constant; and identifying regions exceeding the preset threshold based on the gradient and rate of change.

6. The PCBA fault detection method as described in claim 1, characterized in that, The spatiotemporal superposition and comparison of the dynamically changing waveform with the reference field model includes: in the time dimension, comparing the dielectric constant distribution data of each time point in the dynamically changing waveform with the reference value at the corresponding spatial location in the reference field model point by point; in the spatial dimension, calculating the dielectric constant gradient change of the dynamically changing waveform relative to the reference field model in a preset spatial neighborhood; and combining the comparison results in the time dimension and the gradient change in the spatial dimension to identify the spatial region where the dielectric constant offset exceeds a preset threshold.

7. The PCBA fault detection method as described in claim 2, characterized in that, The reverse tracing of the dielectric constant mutation node along the dielectric equipotential line includes: locating the node where the dielectric constant changes abruptly within the potential fault region as the tracing starting point; starting from the tracing starting point, tracing in the opposite direction of the maximum gradient of the dielectric equipotential line at that point; and recording the sequence of spatial nodes traversed during the tracing process to form the tracing path.

8. A PCBA fault detection system, characterized in that, For performing the method according to any one of claims 1 to 8, comprising: The reference field modeling unit is configured to generate a three-dimensional dielectric topology reference field model by scanning with a non-contact dielectric sensor array when the PCBA is in a fault-free static state. The dynamic data acquisition unit is configured to capture the dynamic change waveform of the global dielectric constant through a dielectric probe array when the PCBA under test is powered on. An abnormal region identification unit is configured to perform spatiotemporal superposition and comparison of the dynamically changing waveform with the reference field model, and identify and mark potential fault areas through a dielectric property change analysis algorithm.

9. The PCBA fault detection system as described in claim 8, characterized in that, The system further includes a fault point determination unit, configured to trace the conduction path of the dielectric constant mutation node in reverse along the direction of the dielectric equipotential line within the potential fault region, and determine the actual fault point based on whether the path forms a closed loop and has a logical conflict with the known circuit topology.

10. The PCBA fault detection system as described in claim 9, characterized in that, The system further includes: a control processing unit, which connects and coordinates the workflow of the reference field modeling unit, dynamic data acquisition unit, abnormal region identification unit, and fault point determination unit; a data storage unit, which stores the three-dimensional dielectric topology reference field model, the dynamic change waveform of the global dielectric constant, the identified abnormal region information, the tracked conduction path information, and the determination result; and a result output unit, which outputs the location information of the actual fault point and the determination basis.

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