Dual-processor ethercat motion control integrated machine and control method

Abstract

This invention discloses a dual-processor EtherCAT motion control integrated machine and control method, belonging to the field of industrial automation control. The integrated machine includes a first processor and a second processor interconnected via a high-speed serial interface. The first processor executes user logic and interpolation algorithms, and manages local I / O and pulse output. The second processor is dedicated to running the EtherCAT master protocol and managing bus slaves. The first processor issues commands to the second processor regarding EtherCAT axes and extended I / O via the high-speed interface and receives status feedback, achieving unified control of pulse axes, EtherCAT axes, and local and remote I / O. The method includes steps such as initialization, command parsing, dual-core collaborative processing, and status synchronization. This invention solves the problems of functional dispersion, insufficient real-time performance, and poor compatibility through heterogeneous division of labor and high-speed interconnection, achieving highly integrated, real-time-efficient, and flexibly expandable motion control.

Description

Technical Field

[0001] This invention relates to the field of industrial automation control technology, and more specifically, to a dual-processor EtherCAT motion control integrated machine and control method. Background Technology

[0002] In the field of industrial automation, motion controllers are core components of various automated equipment. They are responsible for receiving commands, performing trajectory planning (interpolation calculations), and driving actuators such as servo motors to complete precise movements. Traditional motion control schemes mostly employ a single control method, which mainly suffers from the following technical problems: 1. Dispersed functions and low integration: Common industrial control boards or PLCs typically only support a single communication protocol (such as pulse, RS485, or CANopen), making it difficult to simultaneously support traditional pulse servo drives and modern high-performance EtherCAT bus devices. When the system requires mixed control, multiple hardware modules (such as main controller, pulse output card, EtherCAT master station card, etc.) are often required, resulting in complex system structure, high cost, and reduced reliability.

[0003] 2. Insufficient real-time performance and synchronization: When using a single-processor solution, all tasks (such as logic control, interpolation calculation, and communication protocol stack processing) must compete for the same CPU resources. Under high-load scenarios, especially in multi-axis linkage interpolation, real-time communication tasks are easily interrupted, leading to unstable control cycles and increased communication jitter, making it difficult to meet the requirements of high-precision and high-synchronization motion control.

[0004] 3. Poor scalability and compatibility: Traditional pulse control methods are limited by physical wiring, making it difficult to expand the number of axes and I / O points, and the wiring is cumbersome. While some existing EtherCAT all-in-one machines support bus expansion, they often abandon the pulse control interface, making them incompatible with the large number of traditional pulse servo drives already in use by users, increasing the difficulty and cost of system upgrades.

[0005] 4. Lack of a unified control perspective: In hybrid control systems, programmers need to program and manage local pulse axes, EtherCAT axes, local I / O and remote I / O separately, which is logically complex and results in low development and maintenance efficiency.

[0006] Despite some attempts in existing technologies, such as integrating multiple functions into a high-performance single chip (e.g., the ARM Cortex-A series) or implementing logic and communication within a single FPGA, it remains difficult to fundamentally solve the aforementioned problems of task load conflicts, real-time bottlenecks, and high hardware and software complexity. Therefore, the industry urgently needs a highly integrated, real-time-capable, compatible, and easy-to-program motion control solution. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a dual-processor EtherCAT motion control integrated machine and control method. This solution aims to deeply integrate traditional pulse control and modern EtherCAT bus control on a single device through heterogeneous division of labor and high-speed interconnection, achieving high functional integration, significantly improved real-time control, greatly simplified system expansion, and unified programming interfaces, thereby reducing system complexity and cost.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a dual-processor EtherCAT motion control all-in-one machine, comprising: a first processor, a second processor, a high-speed serial communication interface, a pulse output module, a local I / O module, and an EtherCAT communication module; The first processor and the second processor communicate bidirectionally via the high-speed serial communication interface; The first processor is configured to execute user program logic, run a multi-axis interpolation algorithm, and generate a pulse control signal based on the interpolation algorithm, the pulse control signal being output through the pulse output module; The second processor is configured to run the EtherCAT master protocol stack and connect to and manage at least one EtherCAT slave device through the EtherCAT communication module; The first processor sends motion control commands to the second processor through the high-speed serial communication interface, and the second processor sends the commands to the corresponding EtherCAT slave devices through the EtherCAT communication module. The second processor also transmits feedback data collected from the EtherCAT slave device back to the first processor via the high-speed serial communication interface.

[0009] Preferably, the high-speed serial communication interface is an SPI interface with a communication rate of not less than 100MHz, and the data transmission delay between the first processor and the second processor is less than 1 microsecond.

[0010] Furthermore, the first processor is also configured to: uniformly manage local axes from the pulse output module, extended axes from the EtherCAT slave device, the local I / O module, and remote I / O modules extended through the EtherCAT slave device, and establish a unified logical address mapping for all managed resources; the first processor maintains a logical address mapping table for dynamically mapping physical axes and physical I / O points to logical axes and logical I / O addresses; the logical address mapping table supports online configuration and adaptive updates when the network topology changes.

[0011] Preferably, the calculation cycle of the interpolation algorithm executed by the first processor is no more than 1 millisecond, and the interpolation calculation cycle of the first processor and the EtherCAT communication cycle of the second processor are clock-aligned and synchronized through the high-speed serial communication interface.

[0012] Preferably, both the first processor and the second processor use microcontrollers with ARM Cortex-M7 or higher performance cores; specifically, the first processor and the second processor use STM32H743 series microcontrollers.

[0013] Preferably, the EtherCAT communication module has a communication rate of 100Mbps and supports the expansion of at least 64 EtherCAT slave devices.

[0014] Furthermore, it also includes an auxiliary communication module, which includes an RS485 interface and an Ethernet interface, supporting the Modbus RTU protocol and the TCP / IP protocol respectively.

[0015] Preferably, the high-speed serial communication interface adopts a DMA triggering mechanism, supports double-buffered data transmission, and the data frame format includes a command header, axis identifier, position / speed data, I / O status, and a check field.

[0016] Secondly, the present invention also provides a control method based on the above-mentioned all-in-one machine, comprising the following steps: Step S1: The first processor receives motion control commands from the host computer; Step S2: The first processor parses the motion control command and runs an interpolation algorithm to generate target control data; Step S3: The first processor sends the target control data to the second processor through the high-speed serial communication interface; Step S4: The second processor sends the target control data to the corresponding EtherCAT slave device through the EtherCAT communication module; Step S5: The second processor collects the real-time status data of the EtherCAT slave device and transmits it back to the first processor through the high-speed serial communication interface.

[0017] Preferably, in step S2, the first processor maintains a unified logical address mapping table to map the local pulse axis and the EtherCAT extended axis as logical axes for unified trajectory planning; In steps S3 and S5, the timing of data transmission and feedback between the first processor and the second processor is matched with the interpolation calculation cycle of the first processor and the EtherCAT communication cycle of the second processor, forming a cycle-bound closed-loop control pipeline.

[0018] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. High Real-Time Performance and Strong Determinism: Employing a dual-processor heterogeneous architecture, the computationally intensive interpolation task is physically isolated from the real-time-critical EtherCAT communication task. Combined with high-speed (≥100MHz), low-latency (<1μs) inter-chip communication, rapid synchronization of control commands and status feedback is ensured. More importantly, by precisely hardware-level binding and clock alignment of the interpolation cycle of the first processor, the EtherCAT communication cycle of the second processor, and the inter-chip data synchronization cycle, a deterministic pipeline workflow is constructed. This design effectively suppresses communication jitter (controllable to the order of 100 nanoseconds) that is unavoidable in traditional single-processor or simple task separation schemes, resulting in a shorter overall system control cycle and stronger determinism, making it particularly suitable for multi-axis high-precision synchronous motion scenarios.

[0019] 2. Excellent compatibility and high integration: This invention provides both a native pulse output interface and a standard EtherCAT master interface within a single device. Users can connect to the system without replacing their existing pulse servo drivers, and can also seamlessly expand high-performance servo axes and a large number of I / O points via the EtherCAT bus, truly achieving smooth integration and unified control of new and old equipment, greatly simplifying the system architecture and reducing upgrade costs.

[0020] 3. Powerful scalability and simplified cabling: Utilizing the daisy-chain topology of the EtherCAT bus, dozens or even hundreds of servo axes and I / O modules can be connected and expanded in series with just one network cable, supporting at least 64 slave devices. This greatly reduces the complex pulse and I / O wiring in traditional control cabinets, improves system reliability, and reduces cabling costs and maintenance difficulty.

[0021] 4. Unified Control Logic and Simplified Programming: Through unified resource management implemented by the first processor, programmers do not need to concern themselves with the physical type of axes (pulse / EtherCAT) or the physical location of I / O (local / remote); they only need to program the "logical axes" and "logical I / O." This significantly reduces software development complexity and improves code reusability and maintainability.

[0022] 5. Balancing Flexibility and Economy: The core of this invention utilizes a mature, high-performance general-purpose microcontroller (such as the STM32H743), which, compared to FPGA solutions, offers lower development difficulty and cost, and is easier to productize and maintain. Furthermore, the dual-chip architecture provides ample performance headroom for future functional upgrades (such as adding more communication protocols or more complex algorithms). Attached Figure Description

[0023] Figure 1 This is a hardware system block diagram of the EtherCAT motion control all-in-one machine provided in an embodiment of the present invention.

[0024] Figure 2 This is a schematic diagram of the data frame format for SPI communication between two processors in an embodiment of the present invention.

[0025] Figure 3 This is a virtual mapping representation of the first processor implementing unified resource management in an embodiment of the present invention.

[0026] Figure 4 This is a general flowchart of the EtherCAT motion control method provided in the embodiments of the present invention.

[0027] Figure 5 This is a detailed flowchart of the multi-axis interpolation command processing and execution in an embodiment of the present invention.

[0028] In the diagram: 101-First processor, 102-Second processor, 103-High-speed SPI interface, 104-Pulse output module, 105-Local I / O module, 106-EtherCAT physical layer chip, 107-EtherCAT port, 108-Auxiliary communication module, 109-Host computer, 110-EtherCAT slave device; 201-Frame header, 202-Instruction type, 203-Axis identifier / IO group identifier, 204-Data area, 205-Checksum, 301-Logical axis mapping table, 302-Logical I / O mapping table, 303-Physical resource pool. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only for explaining the present invention and are not intended to limit the present invention.

[0030] This embodiment provides a dual-processor EtherCAT motion control all-in-one machine, which includes: a first processor 101, a second processor 102, a high-speed serial communication interface, a pulse output module 104, a local I / O module 105, and an EtherCAT communication module.

[0031] The first processor 101 and the second processor 102 communicate bidirectionally via the high-speed serial communication interface.

[0032] The first processor 101 is configured to execute user program logic, run a multi-axis interpolation algorithm, and generate a pulse control signal based on the interpolation algorithm. The pulse control signal is output to a conventional pulse servo driver through the pulse output module 104.

[0033] The second processor 102 is configured to run the EtherCAT master protocol stack and connect to and manage at least one EtherCAT slave device through the EtherCAT communication module.

[0034] The first processor 101 sends motion control commands to the second processor 102 via the high-speed serial communication interface, and the second processor 102 sends the commands to the corresponding EtherCAT slave devices via the EtherCAT communication module. Simultaneously, the second processor 102 also transmits real-time status data collected from the EtherCAT slave devices back to the first processor 101 via the high-speed serial communication interface.

[0035] As a key improvement of this invention, the interpolation calculation task executed by the first processor 101 and the EtherCAT communication task executed by the second processor 102 are physically isolated and periodically hard-synchronized through the high-speed serial communication interface. The interpolation calculation cycle of the first processor 101, the EtherCAT communication cycle of the second processor 102, and the data synchronization cycle between them are configured to match each other and be clock-aligned, forming a conflict-free pipeline control loop, thereby fundamentally eliminating the periodic interference between the calculation task and the communication task in a mixed control scenario.

[0036] Preferably, the high-speed serial communication interface is an SPI interface with a communication rate of not less than 100MHz and a data transmission delay of less than 1 microsecond, which ensures real-time data synchronization between the two processors.

[0037] Furthermore, the first processor 101 has a unified resource management function, which can map the local axis from the pulse output module 104, the extended axis from the EtherCAT slave device, the local I / O module 105, and the remote EtherCAT I / O module into a unified logical address space, thereby providing users with a single, transparent programming view.

[0038] This embodiment also provides a control method based on the above-mentioned all-in-one machine, including the following steps: 1. The first processor 101 receives motion control commands issued by the host computer 109.

[0039] 2. The first processor 101 parses the instructions and runs the interpolation algorithm to generate target control data.

[0040] 3. The first processor 101 sends the target control data to the second processor 102 through a high-speed serial communication interface.

[0041] 4. The second processor 102 periodically sends the target control data to the corresponding EtherCAT slave device through the EtherCAT communication module.

[0042] 5. The second processor 102 collects real-time status data of the EtherCAT slave device and transmits it back to the first processor 101 through a high-speed serial communication interface to complete status synchronization.

[0043] Specific embodiments are provided below. These embodiments are intended to enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way.

[0044] Example 1: See Figure 1 The hardware core of the all-in-one machine in this embodiment includes two high-performance microcontrollers as the first processor 101 and the second processor 102, preferably STMicroelectronics' STM32H743 series chips. The two chips are connected through a dedicated high-speed SPI interface 103, which is configured in full-duplex mode, with a clock frequency of 100MHz and DMA transfer enabled to reduce CPU overhead. The measured data transfer latency between the chips is less than 1 microsecond.

[0045] The first processor 101 is responsible for upper-layer application and control calculations. It connects to and manages the pulse output module 104 and the local I / O module 105; the pulse output module 104 can output multiple pulse / direction signals up to 100kHz, and the local I / O module 105 adopts 16-channel optocoupler-isolated digital input / output. The first processor 101 internally runs user applications, including combinational logic and sequential logic processing units, and has built-in linear interpolation and circular interpolation algorithm libraries, with the interpolation calculation cycle stable within 1ms.

[0046] The second processor 102 is dedicated to real-time communication. It connects to the EtherCAT port 107 via an EtherCAT physical layer chip 106, preferably a Microchip LAN9252. This master station supports a communication rate of 100 Mbps and can automatically scan, identify, and manage EtherCAT slave devices, such as servo drives or distributed I / O modules, connected to the EtherCAT port 107 in a daisy-chain configuration. The second processor 102 runs open-source or commercial EtherCAT master protocol stacks, such as SOEM and IgH, which can support the management of at least 64 slave devices and achieve microsecond-level synchronization.

[0047] In addition, the device also integrates an auxiliary communication module 108, including an RS485 interface supporting the Modbus RTU protocol and a 10 / 100M Ethernet interface supporting the TCP / IP protocol, for non-real-time or configuration communication with a host computer 109 or other intelligent devices, wherein the host computer 109 is preferably an industrial PC or HMI.

[0048] Key Implementation Detail 1: High-speed SPI Communication and Period Synchronization See Figure 2 To ensure efficient and reliable data exchange between the two processors, a simplified SPI communication data frame format was designed. Each frame includes: a frame header 201, an instruction type 202, an axis identifier / IO group identifier 203, a data area 204, and a checksum 205. The communication process employs a periodic synchronization mechanism and utilizes double buffering technology to avoid data overwriting. The frame header 201 is a fixed value used for frame synchronization. The instruction type 202 includes commands such as "axis control instruction," "IO output," and "status query." The data area 204 carries specific position instructions, speed instructions, or IO status data. The checksum 205 is preferably CRC8.

[0049] To achieve periodic hard synchronization, the interpolation calculation task of the first processor 101 and the EtherCAT master task of the second processor 102 both run with a base period of 1ms. The period timers of the two processors are synchronized during initialization. After completing the interpolation calculation for the current period, the first processor 101 immediately sends data to the designated buffer of the second processor 102 via the SPI interface 103; the second processor 102 then reads data from the buffer and packages it for transmission during its EtherCAT communication cycle. The fixed phase point is 100μs after the start of the communication cycle. This design ensures that the total delay from data generation to transmission to the bus is determined and minimized, effectively suppressing communication jitter.

[0050] Key Implementation Detail 2: Dynamic and Unified Resource Management See Figure 3 This is the core software of the present invention. Two core mapping tables are maintained in the memory of the first processor 101: a logical axis mapping table 301 and a logical I / O mapping table 302. During system initialization, based on hardware configurations such as the number of pulse axes and scanned EtherCAT slave information, all physical axes in the physical resource pool 303 are automatically mapped to consecutive logical axis numbers, such as Axis1, Axis2..., regardless of whether these physical axes are driven by pulses or EtherCAT; simultaneously, all physical I / O points are automatically mapped to consecutive logical I / O addresses, regardless of whether these physical I / O points are located onboard or on a remote EtherCAT module.

[0051] The mapping relationship is dynamic and configurable. Users can modify the binding relationship between logical axes and physical axes or adjust motion parameters without system downtime using a host computer configuration tool. When the EtherCAT network topology changes dynamically, such as during slave hot-plugging, the second processor 102 will notify the first processor 101 of the detected changes in real time via the SPI interface 103. The first processor 101 can then pause the control of the relevant logical axes and prompt the user for reconfiguration, or automatically allocate new physical resources according to a preset strategy, thereby ensuring the continuity of control logic and system robustness. The user-written control program operates entirely based on these logical addresses. During operation, the first processor 101 is responsible for translating and distributing operations targeting logical addresses to the actual physical channels, which can be accomplished through internal pulse generation or forwarding to the second processor 102 via SPI.

[0052] Example 2: See Figure 4 The control method of this embodiment is applied to the above-mentioned all-in-one machine, and specifically includes the following steps: S401: System Initialization and Cycle Alignment. The first processor 101 initializes its own clock and peripherals, loads the user program and interpolation algorithm, and starts a 1ms cycle timer. Simultaneously, the second processor 102 starts, initializes the EtherCAT master protocol stack, scans and configures all connected slave devices via the EtherCAT network, establishes process data communication mapping relationships, and starts its own 1ms communication cycle timer. The two processors exchange synchronization signals via the SPI interface to achieve initial alignment of the cycle timer. After initialization, the first processor 101 establishes or updates the cycle timer based on the scan results. Figure 3 The Uniform Resource Mapping table shown.

[0053] S402: Instruction reception and parsing. The first processor 101 receives a motion control instruction from the host computer 109 through the auxiliary communication module 108, such as linear interpolation, linkage of logic axis 1 and axis 2, moving from position (0,0) to (100,200) at a speed of 50mm / s.

[0054] S403: Instruction Processing and Data Distribution. The first processor 101 parses the instruction and, at the beginning of each 1ms interpolation cycle, calls the linear interpolation algorithm to calculate the displacement increment of each logical axis within that cycle. According to the logical axis mapping table 301, if logical axis 1 is mapped to a local pulse axis, the first processor 101 directly generates the corresponding pulse sequence and sends it to the pulse output module 104; if logical axis 2 is mapped to an EtherCAT extended axis, the calculated displacement increment data is processed according to... Figure 2 The format is encapsulated into an SPI data frame and sent to the designated data buffer of the second processor 102 via the high-speed SPI interface 103 before the end of the current interpolation cycle.

[0055] The processing and execution flow of multi-axis interpolation commands in step S403 above can be further refined; see [link to details]. Figure 5 The entire process is led by the first processor 101, realizing closed-loop control of the entire process of multi-axis interpolation commands from reception and parsing to data distribution. It is suitable for mixed linkage scenarios of pulse axis and EtherCAT axis. The steps are as follows: S4031: Receive a multi-axis interpolation instruction. The first processor 101 receives a multi-axis interpolation instruction from the host computer through the auxiliary communication module 108. This instruction may include key information such as single-axis motion, multi-axis linkage, speed parameters, acceleration parameters, and target position. The instruction format supports standard industrial G-code or custom motion instructions to ensure compatibility with mainstream industrial host computer programming specifications.

[0056] S4032: Parse instructions to obtain information such as target point, velocity, and axis group. The first processor 101 starts the instruction parsing unit to perform syntax parsing and semantic recognition on the received multi-axis interpolation instructions, extracting core parameters such as the axis group involved in the motion, the target position of each axis, the motion velocity, acceleration, and interpolation method. At the same time, it verifies the legality of the instructions. If an illegal instruction is detected, an alarm feedback is immediately triggered to avoid malfunctions.

[0057] S4033: Based on the logical axis mapping table, determine the axes participating in interpolation and their physical types. The first processor 101 calls the logical axis mapping table 301 in memory, matches the parsed logical axis number with the actual axis in the physical resource pool 303, clarifies the physical type corresponding to each logical axis participating in interpolation, and records information such as the physical address and communication channel of each axis to provide a basis for subsequent data distribution.

[0058] S4034: Invoke the interpolation algorithm to calculate the displacement increment of each axis in the next interpolation cycle. The first processor 101 calls the corresponding interpolation algorithm library according to the parsed interpolation method, and calculates the displacement increment and velocity increment of each participating axis in the cycle in combination with the preset 1ms interpolation cycle, to ensure smooth and synchronized multi-axis motion trajectory. The displacement increment calculation accuracy can reach the micrometer level, which is suitable for high-precision motion control scenarios. At the same time, it performs velocity smoothing processing based on the motion state of the previous cycle to avoid motion impact.

[0059] S4035: Determine the logical axis type and branch the processing of data for the pulse axis and EtherCAT axis. Based on the axis physical type determined in S4033, the first processor 101 performs branch processing on the displacement increment data of each axis, realizing differentiated data encapsulation and distribution for the pulse axis and EtherCAT axis, ensuring that the data adapts to the transmission specifications of the corresponding physical channel.

[0060] S4036: For the pulse axis, the displacement increment is converted into the number of pulses and written to the comparison register of the pulse generator. If the logical axis is a local pulse axis, the first processor 101 converts the calculated displacement increment into the corresponding number of pulses and generates a direction signal, which is written to the comparison register of the pulse generator in the pulse output module 104. The pulse generator outputs the corresponding pulse / direction signal at a 1ms cycle to drive the traditional pulse servo drive.

[0061] S4037: For EtherCAT axes, the displacement increment is encapsulated as an SPI data frame. If the logical axis is an EtherCAT extended axis, the first processor 101 will process the calculated displacement increment or target position data according to... Figure 2 The SPI communication data frame format shown is encapsulated, and the frame header, instruction type, axis identifier, data area and checksum are filled in sequentially to ensure the integrity and reliability of data transmission; at the same time, a double buffering mechanism is enabled to avoid conflicts with data from other cycles during the data encapsulation process.

[0062] S4038: The data frame encapsulated in S4037 is sent to the designated buffer of the second processor via the high-speed SPI interface. The first processor 101 sends the encapsulated SPI data frame to the preset data buffer of the second processor 102 via the high-speed SPI interface 103, and at the same time sends a synchronization signal to inform the second processor 102 that the data is ready and can be prepared for subsequent EtherCAT bus transmission operations; after the data transmission is completed, the first processor 101 records the transmission status for subsequent data retransmission verification.

[0063] S4039: Wait for the interpolation cycle timer interrupt to trigger the calculation of the next cycle until the interpolation is completed. The first processor 101 waits for the 1ms interpolation cycle timer interrupt signal. After the interrupt is triggered, it repeats steps S4034 to S4038, continuously calculates the displacement increment of each axis and completes data distribution until the motion trajectory corresponding to the entire multi-axis interpolation command is completed. After the motion is completed, the first processor 101 generates a completion feedback signal and sends it back to the host computer. At the same time, it updates the system status image to prepare for the reception of the next command.

[0064] Figure 5 The processes shown are closely linked. Figure 4 The overall control flow has the core advantage of realizing refined and periodic processing of multi-axis interpolation instructions. Through logical axis mapping and branch processing mechanisms, it takes into account the mixed linkage requirements of local pulse axes and EtherCAT extended axes. At the same time, relying on a fixed interpolation period of 1ms and high-speed SPI data transmission, it ensures the synchronization and real-time performance of multi-axis motion. This is highly consistent with the core concept of dual-processor heterogeneous division of labor and unified resource management of this invention, further improving the high-precision control capability of the system.

[0065] S404: EtherCAT instruction execution. At a predetermined phase point in its next fixed EtherCAT communication cycle, the second processor 102 reads data from the buffer from the first processor 101 and writes it into the designated register of the corresponding EtherCAT servo driver with established PDO mapping, thereby driving the motor to move.

[0066] S405: Status Feedback and Synchronization. In each EtherCAT cycle, the second processor 102 also reads data such as actual position, speed, and alarm status from each slave device. Simultaneously, the first processor 101 reads the local pulse axis encoder feedback and local I / O status. The second processor 102 sends the read EtherCAT device status data back to the first processor 101 via the SPI interface. The first processor 101 summarizes all statuses and updates its internal unified system status image.

[0067] S406: Loop Execution. The system continuously repeats steps S402 to S405, forming a closed-loop control until the motion command is completed. Throughout the process, the user program consistently perceives responsive and uniformly stated logical axes and logical I / O.

[0068] Variations of the Implementation Examples Those skilled in the art will understand that, based on the core concept of this invention, the specific implementation can be adjusted. For example, the high-speed serial communication interface is not limited to SPI; QSPI, a high-speed parallel bus, or a PCIe interface can also be used, provided that real-time requirements are met.

[0069] The specific models of the first processor 101 and the second processor 102 are not limited to STM32H743. Other ARM Cortex-M7 / M4 core microcontrollers with comparable performance can be used, or a combination of ARM processor and FPGA can be used.

[0070] The unified resource management, in addition to virtual mapping tables, can also be implemented using software architectures such as object dictionaries and tag-based access.

[0071] The EtherCAT master protocol stack can adopt different implementation schemes or support more advanced EtherCAT functions, such as distributed clock synchronization.

[0072] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A dual-processor EtherCAT motion control all-in-one machine, characterized in that, include: The system includes a first processor, a second processor, a high-speed serial communication interface, a pulse output module, a local I / O module, and an EtherCAT communication module. The first processor and the second processor communicate bidirectionally via the high-speed serial communication interface; The first processor is configured to execute user program logic, run a multi-axis interpolation algorithm, and generate a pulse control signal based on the interpolation algorithm, the pulse control signal being output through the pulse output module; The second processor is configured to run the EtherCAT master protocol stack and connect to and manage at least one EtherCAT slave device through the EtherCAT communication module; The first processor sends motion control commands to the second processor through the high-speed serial communication interface, and the second processor sends the commands to the corresponding EtherCAT slave devices through the EtherCAT communication module. The second processor also transmits feedback data collected from the EtherCAT slave device back to the first processor via the high-speed serial communication interface.

2. The dual-processor EtherCAT motion control integrated machine according to claim 1, characterized in that, The high-speed serial communication interface is an SPI interface with a communication rate of not less than 100MHz, and the data transmission delay between the first processor and the second processor is less than 1 microsecond.

3. The dual-processor EtherCAT motion control integrated machine according to claim 1, characterized in that, The first processor is also configured to: uniformly manage local axes from the pulse output module, extended axes from the EtherCAT slave device, the local I / O module, and remote I / O modules extended through the EtherCAT slave device, and establish a unified logical address mapping for all managed resources; the first processor maintains a logical address mapping table for dynamically mapping physical axes and physical I / O points to logical axes and logical I / O addresses; the logical address mapping table supports online configuration and adaptive updates when the network topology changes.

4. The dual-processor EtherCAT motion control integrated machine according to claim 1, characterized in that, The calculation cycle of the interpolation algorithm executed by the first processor is no more than 1 millisecond, and the interpolation calculation cycle of the first processor and the EtherCAT communication cycle of the second processor are clock-aligned and synchronized through the high-speed serial communication interface.

5. The dual-processor EtherCAT motion control integrated machine according to claim 1, characterized in that, Both the first processor and the second processor use microcontrollers with ARM Cortex-M7 or higher performance cores; specifically, the first processor and the second processor use STM32H743 series microcontrollers.

6. The dual-processor EtherCAT motion control integrated machine according to claim 1, characterized in that, The EtherCAT communication module has a communication rate of 100Mbps and supports expansion to at least 64 EtherCAT slave devices.

7. The dual-processor EtherCAT motion control integrated machine according to claim 1, characterized in that, It also includes an auxiliary communication module, which includes an RS485 interface and an Ethernet interface, supporting the Modbus RTU protocol and the TCP / IP protocol respectively.

8. The dual-processor EtherCAT motion control integrated machine according to claim 2, characterized in that, The high-speed serial communication interface adopts a DMA triggering mechanism, supports double-buffered data transmission, and the data frame format includes a command header, axis identifier, position / speed data, I / O status, and a check field.

9. A dual-processor EtherCAT motion control method, applied to the dual-processor EtherCAT motion control all-in-one machine according to any one of claims 1 to 8, characterized in that, Includes the following steps: Step S1: The first processor receives motion control commands from the host computer; Step S2: The first processor parses the motion control command and runs an interpolation algorithm to generate target control data; Step S3: The first processor sends the target control data to the second processor through a high-speed serial communication interface; Step S4: The second processor sends the target control data to the corresponding EtherCAT slave device through the EtherCAT communication module; Step S5: The second processor collects the real-time status data of the EtherCAT slave device and transmits it back to the first processor through the high-speed serial communication interface.

10. The dual-processor EtherCAT motion control method according to claim 9, characterized in that, In step S2, the first processor maintains a unified logical address mapping table to map the local pulse axis and the EtherCAT extended axis as logical axes for unified trajectory planning. In steps S3 and S5, the timing of data transmission and feedback between the first processor and the second processor is matched with the interpolation calculation cycle of the first processor and the EtherCAT communication cycle of the second processor, forming a cycle-bound closed-loop control pipeline.

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