A dual-channel parallel data caching and shunting storage system and method based on FPGA
By using DDR3 caching and synchronous FIFO processing within the FPGA module, combined with the parallel storage of two NVMe SSDs, the problem that a single NVMe SSD cannot meet the high-throughput data stream storage requirement is solved, thereby improving data storage speed and system reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HARBIN INST OF TECH
- Filing Date
- 2026-03-04
- Publication Date
- 2026-06-09
AI Technical Summary
A single NVMe SSD cannot meet the storage requirements of the high-throughput data streams output by FPGAs, especially in the field of radar testing, where the speed, capacity, and power consumption requirements of high-speed storage devices are not fully met.
A dual-channel parallel data caching and offloading storage system based on FPGA is adopted. Data is processed through DDR3 cache and synchronous FIFO in the FPGA module, and two independent NVMe SSDs are used for data storage. Combined with NVMe controller and PCIe bus connection, parallel writing and reading of data are realized. A DDR virtual FIFO controller is used for polling detection and priority scheduling.
It improves data storage rate, breaks through the bandwidth bottleneck of a single NVMe SSD, realizes efficient data transmission between FPGA and NVMe SSD, meets the storage requirements of high-throughput data streams, and leaves room for design upgrades, thereby improving system reliability and reducing development difficulty.
Smart Images
Figure CN122173025A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of data storage technology, specifically relating to an FPGA-based dual-channel parallel data caching and split-flow storage system and method. Background Technology
[0002] As the performance of phased array radar continues to improve, the amount of data it generates is also increasing. In the field of radar testing, high-speed storage devices are needed to store the raw echo signals received by the radar for subsequent data analysis and overall system functionality verification. High-performance radar poses challenges to the speed and capacity of storage devices, while field and airborne applications also place demands on the size and power consumption of these devices.
[0003] NVMe SSDs are a new generation of storage devices that have emerged in recent years. Leveraging the high transmission speed of the PCIe bus, they can achieve data storage speeds in the GB / s range. However, due to the limitations of NVMe SSDs' sustained write bandwidth and write fluctuations, a single NVMe SSD cannot meet the storage requirements of the high-throughput data streams output by FPGAs. Summary of the Invention
[0004] The purpose of this invention is to solve the problem that a single NVMe SSD cannot meet the storage requirements of the high-throughput data stream output by an FPGA, and to propose an FPGA-based dual-channel parallel data caching and split storage system and method.
[0005] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows:
[0006] According to one aspect of the present invention, a dual-channel parallel data caching and offloading storage system based on FPGA is provided, the system comprising an FPGA module, a first NVMe SSD, and a second NVMe SSD, wherein:
[0007] The FPGA module includes DDR3, a first channel, and a second channel;
[0008] The DDR3 memory within the FPGA module is used to cache the data written to the first and second channels.
[0009] The first NVMe SSD and the second NVMe SSD are used to store data read from the first channel and the second channel, respectively.
[0010] Furthermore, the interface of the FPGA module is connected to the interface of the Aurora data source.
[0011] Furthermore, the FPGA module also includes a synchronous FIFO and a data channel decomposition unit;
[0012] The synchronization FIFO is used to synchronize the clock of the incoming data;
[0013] The data channel decomposition unit is used to divide the clock-synchronized data into two parts according to the high and low bits. The two parts of data are written into the first channel and the second channel respectively, and finally stored in the first NVMe SSD and the second NVMe SSD.
[0014] Furthermore, the FPGA module also includes an NVMe controller, which controls the connection between the FPGA module and each NVMe SSD via the PCIe bus.
[0015] Furthermore, both the first channel and the second channel include a write operation data bit width conversion unit and a write operation buffer unit;
[0016] The write operation data bit width conversion unit is used to convert the data after being divided by the data channel decomposition unit into the input bit width of DDR3;
[0017] The write operation buffer unit is used to buffer the data after the bit width conversion, and the buffered data of the write operation buffer unit is stored in DDR3.
[0018] Furthermore, both the first channel and the second channel include a read operation buffer unit, a read operation data bit width conversion unit, and an output buffer unit;
[0019] The read operation buffer unit is used to buffer the data read from DDR3;
[0020] The read operation data bit width conversion unit is used to convert the buffered data of the read operation buffer unit into the input bit width of the NVMeSSD;
[0021] The output buffer unit is used to buffer the data after bit width conversion, and the buffered data of the output buffer unit is stored in the NVMe SSD.
[0022] Furthermore, the FPGA module also includes a DDR virtual FIFO controller;
[0023] The DDR virtual FIFO controller is used to poll and detect the read and write signals of the first and second channels.
[0024] Furthermore, the DDR virtual FIFO controller performs polling detection of the read / write signals of the first and second channels through a polling scheduling state machine. The priority order of read / write operations for the first and second channels is defined as: first channel read operation, second channel read operation, first channel write operation, and second channel write operation. The specific polling detection process is as follows:
[0025] Step 1: Check if the triggering conditions for the first channel read operation are met;
[0026] If the triggering condition for the first channel read operation is met, then after completing the processing of the first channel read operation, step 2 will be executed.
[0027] If the triggering condition for the first channel read operation is not met, proceed directly to step 2;
[0028] Step 2: Check if the triggering conditions for the second channel read operation are met;
[0029] If the triggering conditions for the second channel read operation are met, then after completing the second channel read operation, proceed to step 3.
[0030] If the triggering conditions for the second channel read operation are not met, proceed directly to step 3;
[0031] Step 3: Check if the triggering conditions for the first channel write operation are met;
[0032] If the triggering condition for the first channel write operation is met, then after completing the processing of the first channel write operation, proceed to step 4.
[0033] If the triggering condition for the first channel write operation is not met, proceed directly to step 4;
[0034] Step 4: Check if the triggering conditions for the second channel write operation are met;
[0035] If the triggering condition for the second channel write operation is met, then after completing the second channel write operation, return to step 1.
[0036] If the triggering conditions for the second channel write operation are not met, then return directly to step 1.
[0037] According to another aspect of the present invention, a dual-channel parallel data caching and split-flow storage method based on FPGA is provided, the method specifically including the following steps:
[0038] The Aurora data input to the FPGA is divided into two parts according to the high and low bits, and then the two parts of data are written into the first channel and the second channel respectively.
[0039] In the first channel, data undergoes write operation bit width conversion and write operation buffering sequentially; in the second channel, data undergoes write operation bit width conversion and write operation buffering sequentially; the data processed by the write operation buffer is cached in DDR3.
[0040] The data written from the first channel is obtained from DDR3, and the data written from the first channel is sequentially processed by read operation buffering, read operation bit width conversion and output buffering.
[0041] The data written from the second channel is obtained from DDR3, and the data written from the second channel is sequentially processed by read operation buffering, read operation bit width conversion and output buffering.
[0042] The output buffer data of the first channel is stored in the first NVMe SSD, and the output buffer data of the second channel is stored in the second NVMe SSD.
[0043] Furthermore, the processing order of write operations on the first channel, write operations on the second channel, read operations on the first channel, and read operations on the second channel is determined through polling detection, specifically as follows:
[0044] Step 1: Check if the triggering conditions for the first channel read operation are met;
[0045] If the triggering condition for the first channel read operation is met, then after completing the processing of the first channel read operation, step 2 will be executed.
[0046] If the triggering condition for the first channel read operation is not met, proceed directly to step 2;
[0047] Step 2: Check if the triggering conditions for the second channel read operation are met;
[0048] If the triggering conditions for the second channel read operation are met, then after completing the second channel read operation, proceed to step 3.
[0049] If the triggering conditions for the second channel read operation are not met, proceed directly to step 3;
[0050] Step 3: Check if the triggering conditions for the first channel write operation are met;
[0051] If the triggering condition for the first channel write operation is met, then after completing the processing of the first channel write operation, proceed to step 4.
[0052] If the triggering condition for the first channel write operation is not met, proceed directly to step 4;
[0053] Step 4: Check if the triggering conditions for the second channel write operation are met;
[0054] If the triggering condition for the second channel write operation is met, then after completing the second channel write operation, return to step 1.
[0055] If the triggering conditions for the second channel write operation are not met, then return directly to step 1.
[0056] The beneficial effects of this invention are:
[0057] This invention divides data into two parts and caches them through dual channels to achieve parallel data writing, improve data storage speed, and break through the bandwidth bottleneck of a single NVMe SSD. This invention allocates independent DDR3 buffer areas to the two channels, utilizes DDR3 address space partitioning and a multi-channel polling scheduling mechanism to achieve parallel caching of two independent data channels on a single DDR3 interface, and employs a four-stage polling state machine to dynamically adjust the read and write priorities of each channel, fairly scheduling read and write requests for both channels. Parallel storage of the NVMe SSD is implemented using FPGA logic, improving the data transfer speed between the FPGA and the NVMe SSD, meeting the storage requirements of the high-throughput data stream output by the FPGA, and leaving sufficient speed margin for future device upgrades, thus improving design reliability and reducing development difficulty. Attached Figure Description
[0058] Figure 1 This is a flowchart of a dual-channel parallel data caching and split-flow storage method based on FPGA according to the present invention;
[0059] s_axis_t is the data format for FPGA input, ch0 represents the first channel, ch1 represents the second channel, and m_axis is the data protocol;
[0060] Figure 2 This is a schematic diagram of state polling scheduling;
[0061] Figure 3 This is a data processing state transition diagram;
[0062] Figure 4 This is a diagram illustrating the data storage rate of a non-independent channel.
[0063] Figure 5 This is a diagram illustrating the independent channel data storage rate. Detailed Implementation
[0064] Specific implementation method one: Combining Figure 1 This embodiment describes a dual-channel parallel data caching and offloading storage system based on an FPGA. The system includes an FPGA module, a first NVMe SSD (Non-Volatile Memory Host Controller Interface Standard Solid State Drive), and a second NVMe SSD, wherein:
[0065] The FPGA module includes DDR3 (third-generation double data rate synchronous dynamic random access memory), a first channel, and a second channel.
[0066] The DDR3 memory within the FPGA module is used to cache the data written to the first and second channels.
[0067] The first NVMe SSD and the second NVMe SSD are used to store data read from the first channel and the second channel, respectively.
[0068] This invention utilizes an FPGA module to enable the coordinated use of two NVMe SSD devices, which can build a high-speed data storage device suitable for solid-state drives. Through the logical coordination and bandwidth allocation of the two NVMe SSD array storage devices, the bandwidth of the NVMe SSD storage device can be effectively improved.
[0069] Specific Implementation Method Two: This implementation method is a further limitation of Specific Implementation Method One, wherein the interface of the FPGA module is connected to the interface of the Aurora data source.
[0070] The other steps and parameters are the same as in Specific Implementation Method 1.
[0071] Specific Implementation Method 3: This implementation method is a further limitation of Specific Implementation Method 2. The FPGA module also includes a synchronous FIFO (synchronous first-in-first-out memory) and a data channel decomposition unit.
[0072] The synchronous FIFO (synchronous first-in-first-out memory) is used to synchronize the clock of the incoming data;
[0073] The data channel decomposition unit is used to divide the clock-synchronized data into two parts according to the high and low bits. The two parts of data are written into the first channel and the second channel respectively, and finally stored in the first NVMe SSD and the second NVMe SSD.
[0074] The other steps and parameters are the same as in Specific Implementation Method Two.
[0075] Specific Implementation Method Four: This implementation method is a further limitation of Specific Implementation Method Three. The FPGA module also includes an NVMe controller, which is used to control the connection between the FPGA module and each NVMe SSD via the PCIe bus.
[0076] The other steps and parameters are the same as in Specific Implementation Method 3.
[0077] Specific Implementation Method 5: This implementation method is a further limitation of Specific Implementation Method 4. Both the first channel and the second channel include a write operation data bit width conversion unit and a write operation buffer unit.
[0078] The write operation data bit width conversion unit is used to convert the data after being divided by the data channel decomposition unit into the input bit width of DDR3;
[0079] The write operation buffer unit is used to buffer the data after the bit width conversion, and the buffered data of the write operation buffer unit is stored in DDR3.
[0080] The other steps and parameters are the same as in Specific Implementation Method Four.
[0081] Specific Implementation Method Six: This implementation method is a further limitation of Specific Implementation Method Four. Both the first channel and the second channel include a read operation buffer unit, a read operation data bit width conversion unit, and an output buffer unit.
[0082] The read operation buffer unit is used to buffer the data read from DDR3;
[0083] The read operation data bit width conversion unit is used to convert the buffered data of the read operation buffer unit into the input bit width of the NVMeSSD;
[0084] The output buffer unit is used to buffer the data after bit width conversion, and the buffered data of the output buffer unit is stored in the NVMe SSD.
[0085] The other steps and parameters are the same as in Specific Implementation Method Four.
[0086] Specific Implementation Method Seven: This implementation method is a further limitation of Specific Implementation Method Five or Six, and the FPGA module also includes a DDR virtual FIFO controller;
[0087] The DDR virtual FIFO controller is used to poll and detect the read and write signals of the first and second channels.
[0088] The other steps and parameters are the same as in specific implementation methods five or six.
[0089] Specific Implementation Method Eight: This implementation method further defines Specific Implementation Method Seven. The DDR virtual FIFO controller performs polling detection on the read / write signals of the first and second channels through a polling scheduling state machine. The priority order of read / write operations on the first and second channels is defined as first channel read operation, second channel read operation, first channel write operation, and second channel write operation, respectively. The specific polling detection process is as follows:
[0090] Step 1: Check if the triggering conditions for the first channel read operation are met;
[0091] If the triggering condition for the first channel read operation is met, then after completing the processing of the first channel read operation, step 2 will be executed.
[0092] If the triggering condition for the first channel read operation is not met, proceed directly to step 2;
[0093] Step 2: Check if the triggering conditions for the second channel read operation are met;
[0094] If the triggering conditions for the second channel read operation are met, then after completing the second channel read operation, proceed to step 3.
[0095] If the triggering conditions for the second channel read operation are not met, proceed directly to step 3;
[0096] Step 3: Check if the triggering conditions for the first channel write operation are met;
[0097] If the triggering condition for the first channel write operation is met, then after completing the processing of the first channel write operation, proceed to step 4.
[0098] If the triggering condition for the first channel write operation is not met, proceed directly to step 4;
[0099] Step 4: Check if the triggering conditions for the second channel write operation are met;
[0100] If the triggering condition for the second channel write operation is met, then after completing the second channel write operation, return to step 1.
[0101] If the triggering conditions for the second channel write operation are not met, then return directly to step 1.
[0102] The other steps and parameters are the same as in Specific Implementation Method Seven.
[0103] Specific Implementation Method Nine: The dual-channel parallel data caching and split-flow storage method based on FPGA described in this implementation method specifically includes the following steps:
[0104] The Aurora data input to the FPGA is divided into two parts according to the high and low bits, and then the two parts of data are written into the first channel and the second channel respectively.
[0105] In the first channel, data undergoes write operation bit width conversion and write operation buffering sequentially; in the second channel, data undergoes write operation bit width conversion and write operation buffering sequentially; the data processed by the write operation buffer is cached in DDR3.
[0106] The data written from the first channel is obtained from DDR3, and the data written from the first channel is sequentially processed by read operation buffering, read operation bit width conversion and output buffering.
[0107] The data written from the second channel is obtained from DDR3, and the data written from the second channel is sequentially processed by read operation buffering, read operation bit width conversion and output buffering.
[0108] The output buffer data of the first channel is stored in the first NVMe SSD, and the output buffer data of the second channel is stored in the second NVMe SSD.
[0109] Specific Implementation Method Ten: This implementation method further defines Specific Implementation Method Nine. The processing order of the write operation of the first channel, the write operation of the second channel, the read operation of the first channel, and the read operation of the second channel is determined by polling detection, specifically as follows:
[0110] Step 1: Check if the triggering conditions for the first channel read operation are met;
[0111] If the triggering condition for the first channel read operation is met, then after completing the processing of the first channel read operation, step 2 will be executed.
[0112] If the triggering condition for the first channel read operation is not met, proceed directly to step 2;
[0113] Step 2: Check if the triggering conditions for the second channel read operation are met;
[0114] If the triggering conditions for the second channel read operation are met, then after completing the second channel read operation, proceed to step 3.
[0115] If the triggering conditions for the second channel read operation are not met, proceed directly to step 3;
[0116] Step 3: Check if the triggering conditions for the first channel write operation are met;
[0117] If the triggering condition for the first channel write operation is met, then after completing the processing of the first channel write operation, proceed to step 4.
[0118] If the triggering condition for the first channel write operation is not met, proceed directly to step 4;
[0119] Step 4: Check if the triggering conditions for the second channel write operation are met;
[0120] If the triggering condition for the second channel write operation is met, then after completing the second channel write operation, return to step 1.
[0121] If the triggering conditions for the second channel write operation are not met, then return directly to step 1.
[0122] The other steps and parameters are the same as in Specific Implementation Method Nine.
[0123] Example
[0124] This invention improves NVMe SSD bandwidth through dual-channel parallel storage. The high-speed data parallel storage process is as follows:
[0125] (1) High-speed data enters the FPGA module through the Aurora interface of the data source. After receiving the high-speed data from the data source, the FPGA module needs to split the data according to the high and low bits, that is, to divide the input 64-bit Aurora data into two parts, the high 32 bits and the low 32 bits, to achieve natural load balancing.
[0126] (2) After the two parts of data pass through the write operation data bit width conversion unit, they enter the DDR3 cache;
[0127] When writing to DDR3, a single address bit is set as the channel selection bit, so that the data for the two channels is stored in separate DDR3 caches. This ensures that the data from the two channels do not interfere with each other, and that the overall write operation is not affected by the rate fluctuation of one channel.
[0128] (3) High-speed data cached by DDR3 is stored in NVMe SSD through NVMe controller and PCIe hard core.
[0129] In this invention, read and write operations between data and the DDR3 cache are implemented through a DDR virtual FIFO controller. The DDR virtual FIFO controller is controlled by a polling scheduling state machine. This polling state machine has four scheduling phases, each assigning the highest priority to different channels and operations to ensure long-term fairness and low latency for read and write operations. After completing a burst processing step, it jumps to the next phase to achieve fair service.
[0130] The state transition process of the polling scheduling state machine is as follows: Figure 2 As shown:
[0131] State 1: Idle state.
[0132] Once the polling state machine enters the idle state, it directly jumps to the first polling state.
[0133] State 2: Polling scheduling loop state.
[0134] Four polling judgment modules detect the read and write enable of the two channels, and each polling judgment module has a different priority, biased towards four different triggering conditions;
[0135] It should be noted that the specific triggering conditions are as follows:
[0136] Based on the relationship between the amount of data cached in the synchronous FIFO and the preset burst length, for example, when the amount of data cached in the synchronous FIFO is greater than or equal to the preset burst length and the DDR3 is not full, the trigger condition for a write operation is met; when the amount of data in the DDR3 is greater than or equal to the preset burst length and there is enough space on the NVMe SSD side, the trigger condition for a read operation is met.
[0137] The DDR3 AXI interface can only handle one burst transaction at a time, but after the data from each channel is read out, it enters an independent DMA queue and is written to different NVMe SSDs, allowing the two NVMe SSDs to work in parallel, thus making the overall write bandwidth the sum of the bandwidth of the two disks.
[0138] State 3: When a certain path meets the initiation conditions, it enters the corresponding emergency phase, exits the polling scheduling loop, and enters the operation state group.
[0139] Status 4: Data transmission status.
[0140] In the operation state group, the AXI interface signals m_axi_awvalid (write address valid) or m_axi_arvalid (read address valid) will be issued to wait for the DDR3 handshake, and then the data transmission state will be entered. After the operation state is completed, it will return to the polling scheduling ring.
[0141] This invention sets the priority order of read and write operations for each channel as follows: first channel read operation, second channel read operation, first channel write operation, and second channel write operation. After a burst processing is completed, the process proceeds to the next judgment, ensuring fair polling of operations across channels. For example, after the second channel read operation is completed, the system prioritizes checking whether the first channel write operation meets the trigger condition. The data read / write processing state machine flow during FPGA module data transmission is as follows: Figure 3 As shown:
[0142] State 1: Round-robin scheduling state.
[0143] The polling scheduling state consists of the read / write priority judgment of two channels. If the corresponding read / write enable signal is detected in the polling scheduling ring, the polling operation will be exited and the process will switch to the channel read / write processing state.
[0144] State 2: Read / Write Burst Processing State.
[0145] The system performs read and write operations on the channel data. When the DDR3 returns a write / read completion signal, it jumps to the next polling state.
[0146] State 3: Return to polling state ring.
[0147] After the read / write operation of a channel is completed, it returns to the polling scheduling loop and then to the next priority polling state. For example, after the first channel read burst is completed, the second channel read operation in the polling scheduling will take priority, and the channel read / write signals will be polled to ensure that the state machine can process the next highest priority data. And so on.
[0148] Status 4: All polling has ended.
[0149] When the last priority of the polling schedule ends or the lowest priority burst processing (second channel write burst processing) ends, the state machine returns to the first state of the polling schedule loop to start a new round of data processing.
[0150] The system of this invention uses only one AXI4 port to communicate with DDR3, but the system has two channels, and both channels simultaneously receive read and write requests. Under normal circumstances, only one request from one channel can be satisfied, which leads to significant data loss, idle reads, and overwriting. Furthermore, this invention requires complete data isolation between the two DDR3 channels to ensure data parallelism. Therefore, this invention employs the following three methods to avoid conflicts between multi-channel read and write operations:
[0151] (1) Ensure that the read and write processes of the two channels can be fairly scheduled;
[0152] (2) Assign independent read and write pointers to the two channels.
[0153] (3) Use burst transmission for read and write processes to avoid long-term occupation of the channel.
[0154] This invention constructs a circular storage space using read and write pointers. It displays the remaining data amount in the DDR3 circular region using predefined variables. During write bursts, the data amount corresponding to the write burst increases with each clock cycle; during read bursts, the data amount corresponding to the read burst decreases with each clock cycle. The remaining data amount in the DDR3 circular region is limited, maintaining a safe distance between the read and write pointers. This prevents the write pointer from catching up with the read pointer, thus avoiding data overwriting, and conversely, prevents the read pointer from catching up with the write pointer, thus avoiding empty read areas. The circular pointer structure monitors the remaining DDR3 space in real time and automatically adjusts the channel's read / write balance.
[0155] like Figure 4 As shown, when the two data channels are not stored independently, the speed fluctuations of the two NVMe SSDs will affect each other. That is, the two NVMe SSDs will encounter the problem of overlapping speed fluctuations, resulting in a very small improvement in the final average write speed, and the data speed is almost the same as that of single-channel storage.
[0156] like Figure 5 As shown, the method of this invention divides data into two independent channels. One data channel is not affected by the rate fluctuations of the other. Using this independent channel data storage method can minimize the impact of NVMe SSD write fluctuations, theoretically achieving the effect of superimposed data write rates from both channels. Using dual-channel independent caching can smooth out rate fluctuations, enabling the average write rate to achieve a superimposed effect.
[0157] Because the two NVMe SSDs have independent PCIe lanes and internal parallel write structures, the back-end write process is completely parallel, enabling linear aggregation of total bandwidth and stable writing. Although DDR3 outputs in a polling manner, as long as its burst supply rate exceeds the minimum rate requirement of each NVMe SSD, the two NVMe SSDs can continuously write in parallel in the back-end, thereby increasing the total bandwidth.
[0158] The above examples of the present invention are merely illustrative of the computational model and process of the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is impossible to exhaustively list all possible implementations here. Any obvious variations or modifications derived from the technical solutions of the present invention are still within the scope of protection of the present invention.
Claims
1. A dual-channel parallel data caching and offloading storage system based on FPGA, characterized in that, The system includes an FPGA module, a first NVMe SSD, and a second NVMe SSD, wherein: The FPGA module includes DDR3, a first channel, and a second channel; The DDR3 memory within the FPGA module is used to cache the data written to the first and second channels. The first NVMe SSD and the second NVMe SSD are used to store data read from the first channel and the second channel, respectively.
2. The FPGA-based dual-channel parallel data caching and offloading storage system according to claim 1, characterized in that, The interface of the FPGA module is connected to the interface of the Aurora data source.
3. The FPGA-based dual-channel parallel data caching and offloading storage system according to claim 2, characterized in that, The FPGA module also includes a synchronous FIFO and a data channel decomposition unit; The synchronization FIFO is used to synchronize the clock of the incoming data; The data channel decomposition unit is used to divide the clock-synchronized data into two parts according to the high and low bits. The two parts of data are written into the first channel and the second channel respectively, and finally stored in the first NVMe SSD and the second NVMe SSD.
4. The FPGA-based dual-channel parallel data caching and offloading storage system according to claim 3, characterized in that, The FPGA module also includes an NVMe controller, which controls the connection between the FPGA module and each NVMeSSD via the PCIe bus.
5. The FPGA-based dual-channel parallel data caching and offloading storage system according to claim 4, characterized in that, Both the first channel and the second channel include a write operation data bit width conversion unit and a write operation buffer unit; The write operation data bit width conversion unit is used to convert the data after being divided by the data channel decomposition unit into the input bit width of DDR3; The write operation buffer unit is used to buffer the data after the bit width conversion, and the buffered data of the write operation buffer unit is stored in DDR3.
6. The FPGA-based dual-channel parallel data caching and offloading storage system according to claim 4, characterized in that, Both the first channel and the second channel include a read operation buffer unit, a read operation data bit width conversion unit, and an output buffer unit; The read operation buffer unit is used to buffer the data read from DDR3; The read operation data bit width conversion unit is used to convert the buffered data of the read operation buffer unit into the input bit width of the NVMe SSD; The output buffer unit is used to buffer the data after bit width conversion, and the buffered data of the output buffer unit is stored in the NVMe SSD.
7. A dual-channel parallel data caching and offloading storage system based on FPGA according to claim 5 or 6, characterized in that, The FPGA module also includes a DDR virtual FIFO controller; The DDR virtual FIFO controller is used to poll and detect the read and write signals of the first and second channels.
8. The FPGA-based dual-channel parallel data caching and offloading storage system according to claim 7, characterized in that, The DDR virtual FIFO controller polls the read / write signals of the first and second channels using a polling scheduling state machine. The priority order of read / write operations for the first and second channels is defined as: first channel read operation, second channel read operation, first channel write operation, and second channel write operation. The specific polling process is as follows: Step 1: Check if the triggering conditions for the first channel read operation are met; If the triggering condition for the first channel read operation is met, then after completing the processing of the first channel read operation, step 2 will be executed. If the triggering condition for the first channel read operation is not met, proceed directly to step 2; Step 2: Check if the triggering conditions for the second channel read operation are met; If the triggering conditions for the second channel read operation are met, then after completing the second channel read operation, proceed to step 3. If the triggering conditions for the second channel read operation are not met, proceed directly to step 3; Step 3: Check if the triggering conditions for the first channel write operation are met; If the triggering condition for the first channel write operation is met, then after completing the processing of the first channel write operation, proceed to step 4. If the triggering condition for the first channel write operation is not met, proceed directly to step 4; Step 4: Check if the triggering conditions for the second channel write operation are met; If the triggering condition for the second channel write operation is met, then after completing the second channel write operation, return to step 1. If the triggering conditions for the second channel write operation are not met, then return directly to step 1.
9. A dual-channel parallel data caching and split-flow storage method based on FPGA, characterized in that, The method specifically includes the following steps: The Aurora data input to the FPGA is divided into two parts according to the high and low bits, and then the two parts of data are written into the first channel and the second channel respectively. In the first channel, data undergoes write operation bit width conversion and write operation buffering sequentially; in the second channel, data undergoes write operation bit width conversion and write operation buffering sequentially; the data processed by the write operation buffer is cached in DDR3. The data written from the first channel is obtained from DDR3, and the data written from the first channel is sequentially processed by read operation buffering, read operation bit width conversion and output buffering. The data written from the second channel is obtained from DDR3, and the data written from the second channel is sequentially processed by read operation buffering, read operation bit width conversion and output buffering. The output buffer data of the first channel is stored in the first NVMe SSD, and the output buffer data of the second channel is stored in the second NVMe SSD.
10. The FPGA-based dual-channel parallel data caching and split-flow storage method according to claim 9, characterized in that, The processing order of write operations on the first channel, write operations on the second channel, read operations on the first channel, and read operations on the second channel is determined by polling, specifically as follows: Step 1: Check if the triggering conditions for the first channel read operation are met; If the triggering condition for the first channel read operation is met, then after completing the processing of the first channel read operation, step 2 will be executed. If the triggering condition for the first channel read operation is not met, proceed directly to step 2; Step 2: Check if the triggering conditions for the second channel read operation are met; If the triggering conditions for the second channel read operation are met, then after completing the second channel read operation, proceed to step 3. If the triggering conditions for the second channel read operation are not met, proceed directly to step 3; Step 3: Check if the triggering conditions for the first channel write operation are met; If the triggering condition for the first channel write operation is met, then after completing the processing of the first channel write operation, proceed to step 4. If the triggering condition for the first channel write operation is not met, proceed directly to step 4; Step 4: Check if the triggering conditions for the second channel write operation are met; If the triggering condition for the second channel write operation is met, then after completing the second channel write operation, return to step 1. If the triggering conditions for the second channel write operation are not met, then return directly to step 1.